diff options
author | Saurav Kashyap <saurav.kashyap@qlogic.com> | 2014-02-26 04:15:11 -0500 |
---|---|---|
committer | James Bottomley <JBottomley@Parallels.com> | 2014-03-15 13:18:51 -0400 |
commit | fbe9c54b1da7c1f5795bc516676544b2ced58535 (patch) | |
tree | 1803f74fb6b9707dda1f9c98ef1496b25090c591 | |
parent | 6ac1f3b5ecfe12c56b90a0cbd654ea1ac8c81c0d (diff) |
[SCSI] qla2xxx: Simplify the ISPFX00 interrupt handler code for ISPFX00.
Signed-off-by: Giridhar Malavali <giridhar.malavali@qlogic.com>
Signed-off-by: Saurav Kashyap <saurav.kashyap@qlogic.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
-rw-r--r-- | drivers/scsi/qla2xxx/qla_mr.c | 25 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_mr.h | 4 |
2 files changed, 9 insertions, 20 deletions
diff --git a/drivers/scsi/qla2xxx/qla_mr.c b/drivers/scsi/qla2xxx/qla_mr.c index 290322f0a8d7..046a1699cb79 100644 --- a/drivers/scsi/qla2xxx/qla_mr.c +++ b/drivers/scsi/qla2xxx/qla_mr.c | |||
@@ -3014,6 +3014,7 @@ qlafx00_intr_handler(int irq, void *dev_id) | |||
3014 | struct rsp_que *rsp; | 3014 | struct rsp_que *rsp; |
3015 | unsigned long flags; | 3015 | unsigned long flags; |
3016 | uint32_t clr_intr = 0; | 3016 | uint32_t clr_intr = 0; |
3017 | uint32_t intr_stat = 0; | ||
3017 | 3018 | ||
3018 | rsp = (struct rsp_que *) dev_id; | 3019 | rsp = (struct rsp_que *) dev_id; |
3019 | if (!rsp) { | 3020 | if (!rsp) { |
@@ -3035,34 +3036,26 @@ qlafx00_intr_handler(int irq, void *dev_id) | |||
3035 | stat = QLAFX00_RD_INTR_REG(ha); | 3036 | stat = QLAFX00_RD_INTR_REG(ha); |
3036 | if (qla2x00_check_reg_for_disconnect(vha, stat)) | 3037 | if (qla2x00_check_reg_for_disconnect(vha, stat)) |
3037 | break; | 3038 | break; |
3038 | if ((stat & QLAFX00_HST_INT_STS_BITS) == 0) | 3039 | intr_stat = stat & QLAFX00_HST_INT_STS_BITS; |
3040 | if (!intr_stat) | ||
3039 | break; | 3041 | break; |
3040 | 3042 | ||
3041 | switch (stat & QLAFX00_HST_INT_STS_BITS) { | 3043 | if (stat & QLAFX00_INTR_MB_CMPLT) { |
3042 | case QLAFX00_INTR_MB_CMPLT: | ||
3043 | case QLAFX00_INTR_MB_RSP_CMPLT: | ||
3044 | case QLAFX00_INTR_MB_ASYNC_CMPLT: | ||
3045 | case QLAFX00_INTR_ALL_CMPLT: | ||
3046 | mb[0] = RD_REG_WORD(®->mailbox16); | 3044 | mb[0] = RD_REG_WORD(®->mailbox16); |
3047 | qlafx00_mbx_completion(vha, mb[0]); | 3045 | qlafx00_mbx_completion(vha, mb[0]); |
3048 | status |= MBX_INTERRUPT; | 3046 | status |= MBX_INTERRUPT; |
3049 | clr_intr |= QLAFX00_INTR_MB_CMPLT; | 3047 | clr_intr |= QLAFX00_INTR_MB_CMPLT; |
3050 | break; | 3048 | } |
3051 | case QLAFX00_INTR_ASYNC_CMPLT: | 3049 | if (intr_stat & QLAFX00_INTR_ASYNC_CMPLT) { |
3052 | case QLAFX00_INTR_RSP_ASYNC_CMPLT: | ||
3053 | ha->aenmb[0] = RD_REG_WORD(®->aenmailbox0); | 3050 | ha->aenmb[0] = RD_REG_WORD(®->aenmailbox0); |
3054 | qlafx00_async_event(vha); | 3051 | qlafx00_async_event(vha); |
3055 | clr_intr |= QLAFX00_INTR_ASYNC_CMPLT; | 3052 | clr_intr |= QLAFX00_INTR_ASYNC_CMPLT; |
3056 | break; | 3053 | } |
3057 | case QLAFX00_INTR_RSP_CMPLT: | 3054 | if (intr_stat & QLAFX00_INTR_RSP_CMPLT) { |
3058 | qlafx00_process_response_queue(vha, rsp); | 3055 | qlafx00_process_response_queue(vha, rsp); |
3059 | clr_intr |= QLAFX00_INTR_RSP_CMPLT; | 3056 | clr_intr |= QLAFX00_INTR_RSP_CMPLT; |
3060 | break; | ||
3061 | default: | ||
3062 | ql_dbg(ql_dbg_async, vha, 0x507a, | ||
3063 | "Unrecognized interrupt type (%d).\n", stat); | ||
3064 | break; | ||
3065 | } | 3057 | } |
3058 | |||
3066 | QLAFX00_CLR_INTR_REG(ha, clr_intr); | 3059 | QLAFX00_CLR_INTR_REG(ha, clr_intr); |
3067 | QLAFX00_RD_INTR_REG(ha); | 3060 | QLAFX00_RD_INTR_REG(ha); |
3068 | } | 3061 | } |
diff --git a/drivers/scsi/qla2xxx/qla_mr.h b/drivers/scsi/qla2xxx/qla_mr.h index 3cf5ddc244a5..e529dfaeb854 100644 --- a/drivers/scsi/qla2xxx/qla_mr.h +++ b/drivers/scsi/qla2xxx/qla_mr.h | |||
@@ -336,11 +336,7 @@ struct config_info_data { | |||
336 | 336 | ||
337 | #define QLAFX00_INTR_MB_CMPLT 0x1 | 337 | #define QLAFX00_INTR_MB_CMPLT 0x1 |
338 | #define QLAFX00_INTR_RSP_CMPLT 0x2 | 338 | #define QLAFX00_INTR_RSP_CMPLT 0x2 |
339 | #define QLAFX00_INTR_MB_RSP_CMPLT 0x3 | ||
340 | #define QLAFX00_INTR_ASYNC_CMPLT 0x4 | 339 | #define QLAFX00_INTR_ASYNC_CMPLT 0x4 |
341 | #define QLAFX00_INTR_MB_ASYNC_CMPLT 0x5 | ||
342 | #define QLAFX00_INTR_RSP_ASYNC_CMPLT 0x6 | ||
343 | #define QLAFX00_INTR_ALL_CMPLT 0x7 | ||
344 | 340 | ||
345 | #define QLAFX00_MBA_SYSTEM_ERR 0x8002 | 341 | #define QLAFX00_MBA_SYSTEM_ERR 0x8002 |
346 | #define QLAFX00_MBA_TEMP_OVER 0x8005 | 342 | #define QLAFX00_MBA_TEMP_OVER 0x8005 |