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authorKevin Cernekee <cernekee@gmail.com>2014-11-25 19:49:51 -0500
committerFlorian Fainelli <f.fainelli@gmail.com>2014-11-28 18:44:43 -0500
commitf80835875d3d1a4764711a90f6cc2669f037f527 (patch)
tree7b5cfaf8ac02554e5fda1b0b5e09c02d90108978
parent2b53eadcea05b680278f8d078b166e1e295e2a4f (diff)
bus: brcmstb_gisb: Look up register offsets in a table
There are at least 4 incompatible variations of this hardware block, so let's use the ARB_* constants as a table index instead of hardcoding specific register offsets. Also, allow for the possibility of adding old devices that are missing some of the registers. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
-rw-r--r--drivers/bus/brcmstb_gisb.c42
1 files changed, 34 insertions, 8 deletions
diff --git a/drivers/bus/brcmstb_gisb.c b/drivers/bus/brcmstb_gisb.c
index 8ff403da5d74..ef1e4238ef5f 100644
--- a/drivers/bus/brcmstb_gisb.c
+++ b/drivers/bus/brcmstb_gisb.c
@@ -29,23 +29,37 @@
29#include <asm/signal.h> 29#include <asm/signal.h>
30#endif 30#endif
31 31
32#define ARB_TIMER 0x008
33#define ARB_ERR_CAP_CLR 0x7e4
34#define ARB_ERR_CAP_CLEAR (1 << 0) 32#define ARB_ERR_CAP_CLEAR (1 << 0)
35#define ARB_ERR_CAP_HI_ADDR 0x7e8
36#define ARB_ERR_CAP_ADDR 0x7ec
37#define ARB_ERR_CAP_DATA 0x7f0
38#define ARB_ERR_CAP_STATUS 0x7f4
39#define ARB_ERR_CAP_STATUS_TIMEOUT (1 << 12) 33#define ARB_ERR_CAP_STATUS_TIMEOUT (1 << 12)
40#define ARB_ERR_CAP_STATUS_TEA (1 << 11) 34#define ARB_ERR_CAP_STATUS_TEA (1 << 11)
41#define ARB_ERR_CAP_STATUS_BS_SHIFT (1 << 2) 35#define ARB_ERR_CAP_STATUS_BS_SHIFT (1 << 2)
42#define ARB_ERR_CAP_STATUS_BS_MASK 0x3c 36#define ARB_ERR_CAP_STATUS_BS_MASK 0x3c
43#define ARB_ERR_CAP_STATUS_WRITE (1 << 1) 37#define ARB_ERR_CAP_STATUS_WRITE (1 << 1)
44#define ARB_ERR_CAP_STATUS_VALID (1 << 0) 38#define ARB_ERR_CAP_STATUS_VALID (1 << 0)
45#define ARB_ERR_CAP_MASTER 0x7f8 39
40enum {
41 ARB_TIMER,
42 ARB_ERR_CAP_CLR,
43 ARB_ERR_CAP_HI_ADDR,
44 ARB_ERR_CAP_ADDR,
45 ARB_ERR_CAP_DATA,
46 ARB_ERR_CAP_STATUS,
47 ARB_ERR_CAP_MASTER,
48};
49
50static const int gisb_offsets_bcm7445[] = {
51 [ARB_TIMER] = 0x008,
52 [ARB_ERR_CAP_CLR] = 0x7e4,
53 [ARB_ERR_CAP_HI_ADDR] = 0x7e8,
54 [ARB_ERR_CAP_ADDR] = 0x7ec,
55 [ARB_ERR_CAP_DATA] = 0x7f0,
56 [ARB_ERR_CAP_STATUS] = 0x7f4,
57 [ARB_ERR_CAP_MASTER] = 0x7f8,
58};
46 59
47struct brcmstb_gisb_arb_device { 60struct brcmstb_gisb_arb_device {
48 void __iomem *base; 61 void __iomem *base;
62 const int *gisb_offsets;
49 struct mutex lock; 63 struct mutex lock;
50 struct list_head next; 64 struct list_head next;
51 u32 valid_mask; 65 u32 valid_mask;
@@ -56,11 +70,21 @@ static LIST_HEAD(brcmstb_gisb_arb_device_list);
56 70
57static u32 gisb_read(struct brcmstb_gisb_arb_device *gdev, int reg) 71static u32 gisb_read(struct brcmstb_gisb_arb_device *gdev, int reg)
58{ 72{
59 return ioread32(gdev->base + reg); 73 int offset = gdev->gisb_offsets[reg];
74
75 /* return 1 if the hardware doesn't have ARB_ERR_CAP_MASTER */
76 if (offset == -1)
77 return 1;
78
79 return ioread32(gdev->base + offset);
60} 80}
61 81
62static void gisb_write(struct brcmstb_gisb_arb_device *gdev, u32 val, int reg) 82static void gisb_write(struct brcmstb_gisb_arb_device *gdev, u32 val, int reg)
63{ 83{
84 int offset = gdev->gisb_offsets[reg];
85
86 if (offset == -1)
87 return;
64 iowrite32(val, gdev->base + reg); 88 iowrite32(val, gdev->base + reg);
65} 89}
66 90
@@ -230,6 +254,8 @@ static int brcmstb_gisb_arb_probe(struct platform_device *pdev)
230 if (IS_ERR(gdev->base)) 254 if (IS_ERR(gdev->base))
231 return PTR_ERR(gdev->base); 255 return PTR_ERR(gdev->base);
232 256
257 gdev->gisb_offsets = gisb_offsets_bcm7445;
258
233 err = devm_request_irq(&pdev->dev, timeout_irq, 259 err = devm_request_irq(&pdev->dev, timeout_irq,
234 brcmstb_gisb_timeout_handler, 0, pdev->name, 260 brcmstb_gisb_timeout_handler, 0, pdev->name,
235 gdev); 261 gdev);