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authorPranavkumar Sawargaonkar <pranavkumar@linaro.org>2014-07-31 02:53:23 -0400
committerChristoffer Dall <christoffer.dall@linaro.org>2014-08-29 05:53:26 -0400
commitf6edbbf36da3a27b298b66c7955fc84e1dcca305 (patch)
treeb139fa1469a73dd1e7082aba203d08509101ca2c
parent30d1e0e806e5b2fadc297ba78f2d7afd6ba309cf (diff)
ARM/ARM64: KVM: Nuke Hyp-mode tlbs before enabling MMU
X-Gene u-boot runs in EL2 mode with MMU enabled hence we might have stale EL2 tlb enteris when we enable EL2 MMU on each host CPU. This can happen on any ARM/ARM64 board running bootloader in Hyp-mode (or EL2-mode) with MMU enabled. This patch ensures that we flush all Hyp-mode (or EL2-mode) TLBs on each host CPU before enabling Hyp-mode (or EL2-mode) MMU. Cc: <stable@vger.kernel.org> Tested-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org> Signed-off-by: Anup Patel <anup.patel@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
-rw-r--r--arch/arm/kvm/init.S4
-rw-r--r--arch/arm64/kvm/hyp-init.S4
2 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/kvm/init.S b/arch/arm/kvm/init.S
index 991415d978b6..3988e72d16ff 100644
--- a/arch/arm/kvm/init.S
+++ b/arch/arm/kvm/init.S
@@ -99,6 +99,10 @@ __do_hyp_init:
99 mrc p15, 0, r0, c10, c2, 1 99 mrc p15, 0, r0, c10, c2, 1
100 mcr p15, 4, r0, c10, c2, 1 100 mcr p15, 4, r0, c10, c2, 1
101 101
102 @ Invalidate the stale TLBs from Bootloader
103 mcr p15, 4, r0, c8, c7, 0 @ TLBIALLH
104 dsb ish
105
102 @ Set the HSCTLR to: 106 @ Set the HSCTLR to:
103 @ - ARM/THUMB exceptions: Kernel config (Thumb-2 kernel) 107 @ - ARM/THUMB exceptions: Kernel config (Thumb-2 kernel)
104 @ - Endianness: Kernel config 108 @ - Endianness: Kernel config
diff --git a/arch/arm64/kvm/hyp-init.S b/arch/arm64/kvm/hyp-init.S
index d968796f4b2d..c3191168a994 100644
--- a/arch/arm64/kvm/hyp-init.S
+++ b/arch/arm64/kvm/hyp-init.S
@@ -80,6 +80,10 @@ __do_hyp_init:
80 msr mair_el2, x4 80 msr mair_el2, x4
81 isb 81 isb
82 82
83 /* Invalidate the stale TLBs from Bootloader */
84 tlbi alle2
85 dsb sy
86
83 mrs x4, sctlr_el2 87 mrs x4, sctlr_el2
84 and x4, x4, #SCTLR_EL2_EE // preserve endianness of EL2 88 and x4, x4, #SCTLR_EL2_EE // preserve endianness of EL2
85 ldr x5, =SCTLR_EL2_FLAGS 89 ldr x5, =SCTLR_EL2_FLAGS