diff options
author | Arnd Bergmann <arnd@arndb.de> | 2016-09-15 11:45:57 -0400 |
---|---|---|
committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-09-16 19:18:19 -0400 |
commit | f00d2db7c4739af8a2496273175e0939e1047813 (patch) | |
tree | 1a139e15f84b5c28235e2620dae5e571c4aaf813 | |
parent | 0637a4c7810a6b09ec6b1bf3dc88830cb64ce08b (diff) |
clk: zx: fix pointer case warnings
The zx296718 clock driver has a creative way of assigning the register
values for each clock, by initializing an __iomem pointer to an
offset and then later adding the base (from ioremap) on top
with a cast to u64. This fail on all 32-bit architectures during
compile testing:
drivers/clk/zte/clk-zx296718.c: In function 'top_clocks_init':
drivers/clk/zte/clk-zx296718.c:554:35: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
zx296718_pll_clk[i].reg_base += (u64)reg_base;
drivers/clk/zte/clk-zx296718.c:579:29: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
drivers/clk/zte/clk-zx296718.c:592:31: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
It would be nice to avoid all the casts, but I decided to simply
shut up the warnings by changing the type from u64 to uintptr_t,
which does the right thing in practice.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fixes: ca0233285a93 ("clk: zx: register ZX296718 clocks")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
-rw-r--r-- | drivers/clk/zte/clk-zx296718.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/clk/zte/clk-zx296718.c b/drivers/clk/zte/clk-zx296718.c index b4fe8ddd7373..c7716c17f302 100644 --- a/drivers/clk/zte/clk-zx296718.c +++ b/drivers/clk/zte/clk-zx296718.c | |||
@@ -551,7 +551,7 @@ static int __init top_clocks_init(struct device_node *np) | |||
551 | } | 551 | } |
552 | 552 | ||
553 | for (i = 0; i < ARRAY_SIZE(zx296718_pll_clk); i++) { | 553 | for (i = 0; i < ARRAY_SIZE(zx296718_pll_clk); i++) { |
554 | zx296718_pll_clk[i].reg_base += (u64)reg_base; | 554 | zx296718_pll_clk[i].reg_base += (uintptr_t)reg_base; |
555 | ret = clk_hw_register(NULL, &zx296718_pll_clk[i].hw); | 555 | ret = clk_hw_register(NULL, &zx296718_pll_clk[i].hw); |
556 | if (ret) { | 556 | if (ret) { |
557 | pr_warn("top clk %s init error!\n", | 557 | pr_warn("top clk %s init error!\n", |
@@ -576,7 +576,7 @@ static int __init top_clocks_init(struct device_node *np) | |||
576 | top_hw_onecell_data.hws[top_mux_clk[i].id] = | 576 | top_hw_onecell_data.hws[top_mux_clk[i].id] = |
577 | &top_mux_clk[i].mux.hw; | 577 | &top_mux_clk[i].mux.hw; |
578 | 578 | ||
579 | top_mux_clk[i].mux.reg += (u64)reg_base; | 579 | top_mux_clk[i].mux.reg += (uintptr_t)reg_base; |
580 | ret = clk_hw_register(NULL, &top_mux_clk[i].mux.hw); | 580 | ret = clk_hw_register(NULL, &top_mux_clk[i].mux.hw); |
581 | if (ret) { | 581 | if (ret) { |
582 | pr_warn("top clk %s init error!\n", | 582 | pr_warn("top clk %s init error!\n", |
@@ -589,7 +589,7 @@ static int __init top_clocks_init(struct device_node *np) | |||
589 | top_hw_onecell_data.hws[top_gate_clk[i].id] = | 589 | top_hw_onecell_data.hws[top_gate_clk[i].id] = |
590 | &top_gate_clk[i].gate.hw; | 590 | &top_gate_clk[i].gate.hw; |
591 | 591 | ||
592 | top_gate_clk[i].gate.reg += (u64)reg_base; | 592 | top_gate_clk[i].gate.reg += (uintptr_t)reg_base; |
593 | ret = clk_hw_register(NULL, &top_gate_clk[i].gate.hw); | 593 | ret = clk_hw_register(NULL, &top_gate_clk[i].gate.hw); |
594 | if (ret) { | 594 | if (ret) { |
595 | pr_warn("top clk %s init error!\n", | 595 | pr_warn("top clk %s init error!\n", |
@@ -602,7 +602,7 @@ static int __init top_clocks_init(struct device_node *np) | |||
602 | top_hw_onecell_data.hws[top_div_clk[i].id] = | 602 | top_hw_onecell_data.hws[top_div_clk[i].id] = |
603 | &top_div_clk[i].div.hw; | 603 | &top_div_clk[i].div.hw; |
604 | 604 | ||
605 | top_div_clk[i].div.reg += (u64)reg_base; | 605 | top_div_clk[i].div.reg += (uintptr_t)reg_base; |
606 | ret = clk_hw_register(NULL, &top_div_clk[i].div.hw); | 606 | ret = clk_hw_register(NULL, &top_div_clk[i].div.hw); |
607 | if (ret) { | 607 | if (ret) { |
608 | pr_warn("top clk %s init error!\n", | 608 | pr_warn("top clk %s init error!\n", |
@@ -742,7 +742,7 @@ static int __init lsp0_clocks_init(struct device_node *np) | |||
742 | lsp0_hw_onecell_data.hws[lsp0_mux_clk[i].id] = | 742 | lsp0_hw_onecell_data.hws[lsp0_mux_clk[i].id] = |
743 | &lsp0_mux_clk[i].mux.hw; | 743 | &lsp0_mux_clk[i].mux.hw; |
744 | 744 | ||
745 | lsp0_mux_clk[i].mux.reg += (u64)reg_base; | 745 | lsp0_mux_clk[i].mux.reg += (uintptr_t)reg_base; |
746 | ret = clk_hw_register(NULL, &lsp0_mux_clk[i].mux.hw); | 746 | ret = clk_hw_register(NULL, &lsp0_mux_clk[i].mux.hw); |
747 | if (ret) { | 747 | if (ret) { |
748 | pr_warn("lsp0 clk %s init error!\n", | 748 | pr_warn("lsp0 clk %s init error!\n", |
@@ -755,7 +755,7 @@ static int __init lsp0_clocks_init(struct device_node *np) | |||
755 | lsp0_hw_onecell_data.hws[lsp0_gate_clk[i].id] = | 755 | lsp0_hw_onecell_data.hws[lsp0_gate_clk[i].id] = |
756 | &lsp0_gate_clk[i].gate.hw; | 756 | &lsp0_gate_clk[i].gate.hw; |
757 | 757 | ||
758 | lsp0_gate_clk[i].gate.reg += (u64)reg_base; | 758 | lsp0_gate_clk[i].gate.reg += (uintptr_t)reg_base; |
759 | ret = clk_hw_register(NULL, &lsp0_gate_clk[i].gate.hw); | 759 | ret = clk_hw_register(NULL, &lsp0_gate_clk[i].gate.hw); |
760 | if (ret) { | 760 | if (ret) { |
761 | pr_warn("lsp0 clk %s init error!\n", | 761 | pr_warn("lsp0 clk %s init error!\n", |
@@ -768,7 +768,7 @@ static int __init lsp0_clocks_init(struct device_node *np) | |||
768 | lsp0_hw_onecell_data.hws[lsp0_div_clk[i].id] = | 768 | lsp0_hw_onecell_data.hws[lsp0_div_clk[i].id] = |
769 | &lsp0_div_clk[i].div.hw; | 769 | &lsp0_div_clk[i].div.hw; |
770 | 770 | ||
771 | lsp0_div_clk[i].div.reg += (u64)reg_base; | 771 | lsp0_div_clk[i].div.reg += (uintptr_t)reg_base; |
772 | ret = clk_hw_register(NULL, &lsp0_div_clk[i].div.hw); | 772 | ret = clk_hw_register(NULL, &lsp0_div_clk[i].div.hw); |
773 | if (ret) { | 773 | if (ret) { |
774 | pr_warn("lsp0 clk %s init error!\n", | 774 | pr_warn("lsp0 clk %s init error!\n", |
@@ -847,7 +847,7 @@ static int __init lsp1_clocks_init(struct device_node *np) | |||
847 | lsp1_hw_onecell_data.hws[lsp1_mux_clk[i].id] = | 847 | lsp1_hw_onecell_data.hws[lsp1_mux_clk[i].id] = |
848 | &lsp0_mux_clk[i].mux.hw; | 848 | &lsp0_mux_clk[i].mux.hw; |
849 | 849 | ||
850 | lsp1_mux_clk[i].mux.reg += (u64)reg_base; | 850 | lsp1_mux_clk[i].mux.reg += (uintptr_t)reg_base; |
851 | ret = clk_hw_register(NULL, &lsp1_mux_clk[i].mux.hw); | 851 | ret = clk_hw_register(NULL, &lsp1_mux_clk[i].mux.hw); |
852 | if (ret) { | 852 | if (ret) { |
853 | pr_warn("lsp1 clk %s init error!\n", | 853 | pr_warn("lsp1 clk %s init error!\n", |
@@ -860,7 +860,7 @@ static int __init lsp1_clocks_init(struct device_node *np) | |||
860 | lsp1_hw_onecell_data.hws[lsp1_gate_clk[i].id] = | 860 | lsp1_hw_onecell_data.hws[lsp1_gate_clk[i].id] = |
861 | &lsp1_gate_clk[i].gate.hw; | 861 | &lsp1_gate_clk[i].gate.hw; |
862 | 862 | ||
863 | lsp1_gate_clk[i].gate.reg += (u64)reg_base; | 863 | lsp1_gate_clk[i].gate.reg += (uintptr_t)reg_base; |
864 | ret = clk_hw_register(NULL, &lsp1_gate_clk[i].gate.hw); | 864 | ret = clk_hw_register(NULL, &lsp1_gate_clk[i].gate.hw); |
865 | if (ret) { | 865 | if (ret) { |
866 | pr_warn("lsp1 clk %s init error!\n", | 866 | pr_warn("lsp1 clk %s init error!\n", |
@@ -873,7 +873,7 @@ static int __init lsp1_clocks_init(struct device_node *np) | |||
873 | lsp1_hw_onecell_data.hws[lsp1_div_clk[i].id] = | 873 | lsp1_hw_onecell_data.hws[lsp1_div_clk[i].id] = |
874 | &lsp1_div_clk[i].div.hw; | 874 | &lsp1_div_clk[i].div.hw; |
875 | 875 | ||
876 | lsp1_div_clk[i].div.reg += (u64)reg_base; | 876 | lsp1_div_clk[i].div.reg += (uintptr_t)reg_base; |
877 | ret = clk_hw_register(NULL, &lsp1_div_clk[i].div.hw); | 877 | ret = clk_hw_register(NULL, &lsp1_div_clk[i].div.hw); |
878 | if (ret) { | 878 | if (ret) { |
879 | pr_warn("lsp1 clk %s init error!\n", | 879 | pr_warn("lsp1 clk %s init error!\n", |