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authorMika Westerberg <mika.westerberg@linux.intel.com>2015-10-21 06:08:45 -0400
committerLinus Walleij <linus.walleij@linaro.org>2015-10-27 08:32:13 -0400
commitee1a6ca43dba07465c71f6ab661702d703f5eb06 (patch)
tree104f600471e5864c2574e133ce745f44a7a39448
parent4341e8a5458f10cb7265167061fa06ebf3a3a903 (diff)
pinctrl: intel: Add Intel Broxton pin controller support
This driver adds pinctrl/GPIO support for Intel Broxton. The GPIO controller is based on the same hardware design that is already used in Intel Sunrisepoint so we leverage the core driver here. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat
-rw-r--r--drivers/pinctrl/intel/Kconfig8
-rw-r--r--drivers/pinctrl/intel/Makefile1
-rw-r--r--drivers/pinctrl/intel/pinctrl-broxton.c1065
3 files changed, 1074 insertions, 0 deletions
diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig
index fe5e07db0a95..4d2efad6553c 100644
--- a/drivers/pinctrl/intel/Kconfig
+++ b/drivers/pinctrl/intel/Kconfig
@@ -34,6 +34,14 @@ config PINCTRL_INTEL
34 select GPIOLIB 34 select GPIOLIB
35 select GPIOLIB_IRQCHIP 35 select GPIOLIB_IRQCHIP
36 36
37config PINCTRL_BROXTON
38 tristate "Intel Broxton pinctrl and GPIO driver"
39 depends on ACPI
40 select PINCTRL_INTEL
41 help
42 Broxton pinctrl driver provides an interface that allows
43 configuring of SoC pins and using them as GPIOs.
44
37config PINCTRL_SUNRISEPOINT 45config PINCTRL_SUNRISEPOINT
38 tristate "Intel Sunrisepoint pinctrl and GPIO driver" 46 tristate "Intel Sunrisepoint pinctrl and GPIO driver"
39 depends on ACPI 47 depends on ACPI
diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile
index fee756e1255b..03bc68e3546c 100644
--- a/drivers/pinctrl/intel/Makefile
+++ b/drivers/pinctrl/intel/Makefile
@@ -3,4 +3,5 @@
3obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o 3obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
4obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o 4obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o
5obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o 5obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o
6obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o
6obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o 7obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o
diff --git a/drivers/pinctrl/intel/pinctrl-broxton.c b/drivers/pinctrl/intel/pinctrl-broxton.c
new file mode 100644
index 000000000000..e42d5d4183f5
--- /dev/null
+++ b/drivers/pinctrl/intel/pinctrl-broxton.c
@@ -0,0 +1,1065 @@
1/*
2 * Intel Broxton SoC pinctrl/GPIO driver
3 *
4 * Copyright (C) 2015, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/acpi.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/pm.h>
16#include <linux/pinctrl/pinctrl.h>
17
18#include "pinctrl-intel.h"
19
20#define BXT_PAD_OWN 0x020
21#define BXT_HOSTSW_OWN 0x080
22#define BXT_PADCFGLOCK 0x090
23#define BXT_GPI_IE 0x110
24
25#define BXT_COMMUNITY(s, e) \
26 { \
27 .padown_offset = BXT_PAD_OWN, \
28 .padcfglock_offset = BXT_PADCFGLOCK, \
29 .hostown_offset = BXT_HOSTSW_OWN, \
30 .ie_offset = BXT_GPI_IE, \
31 .pin_base = (s), \
32 .npins = ((e) - (s) + 1), \
33 }
34
35/* BXT */
36static const struct pinctrl_pin_desc bxt_north_pins[] = {
37 PINCTRL_PIN(0, "GPIO_0"),
38 PINCTRL_PIN(1, "GPIO_1"),
39 PINCTRL_PIN(2, "GPIO_2"),
40 PINCTRL_PIN(3, "GPIO_3"),
41 PINCTRL_PIN(4, "GPIO_4"),
42 PINCTRL_PIN(5, "GPIO_5"),
43 PINCTRL_PIN(6, "GPIO_6"),
44 PINCTRL_PIN(7, "GPIO_7"),
45 PINCTRL_PIN(8, "GPIO_8"),
46 PINCTRL_PIN(9, "GPIO_9"),
47 PINCTRL_PIN(10, "GPIO_10"),
48 PINCTRL_PIN(11, "GPIO_11"),
49 PINCTRL_PIN(12, "GPIO_12"),
50 PINCTRL_PIN(13, "GPIO_13"),
51 PINCTRL_PIN(14, "GPIO_14"),
52 PINCTRL_PIN(15, "GPIO_15"),
53 PINCTRL_PIN(16, "GPIO_16"),
54 PINCTRL_PIN(17, "GPIO_17"),
55 PINCTRL_PIN(18, "GPIO_18"),
56 PINCTRL_PIN(19, "GPIO_19"),
57 PINCTRL_PIN(20, "GPIO_20"),
58 PINCTRL_PIN(21, "GPIO_21"),
59 PINCTRL_PIN(22, "GPIO_22"),
60 PINCTRL_PIN(23, "GPIO_23"),
61 PINCTRL_PIN(24, "GPIO_24"),
62 PINCTRL_PIN(25, "GPIO_25"),
63 PINCTRL_PIN(26, "GPIO_26"),
64 PINCTRL_PIN(27, "GPIO_27"),
65 PINCTRL_PIN(28, "GPIO_28"),
66 PINCTRL_PIN(29, "GPIO_29"),
67 PINCTRL_PIN(30, "GPIO_30"),
68 PINCTRL_PIN(31, "GPIO_31"),
69 PINCTRL_PIN(32, "GPIO_32"),
70 PINCTRL_PIN(33, "GPIO_33"),
71 PINCTRL_PIN(34, "PWM0"),
72 PINCTRL_PIN(35, "PWM1"),
73 PINCTRL_PIN(36, "PWM2"),
74 PINCTRL_PIN(37, "PWM3"),
75 PINCTRL_PIN(38, "LPSS_UART0_RXD"),
76 PINCTRL_PIN(39, "LPSS_UART0_TXD"),
77 PINCTRL_PIN(40, "LPSS_UART0_RTS_B"),
78 PINCTRL_PIN(41, "LPSS_UART0_CTS_B"),
79 PINCTRL_PIN(42, "LPSS_UART1_RXD"),
80 PINCTRL_PIN(43, "LPSS_UART1_TXD"),
81 PINCTRL_PIN(44, "LPSS_UART1_RTS_B"),
82 PINCTRL_PIN(45, "LPSS_UART1_CTS_B"),
83 PINCTRL_PIN(46, "LPSS_UART2_RXD"),
84 PINCTRL_PIN(47, "LPSS_UART2_TXD"),
85 PINCTRL_PIN(48, "LPSS_UART2_RTS_B"),
86 PINCTRL_PIN(49, "LPSS_UART2_CTS_B"),
87 PINCTRL_PIN(50, "ISH_UART0_RXD"),
88 PINCTRL_PIN(51, "ISH_UART0_TXT"),
89 PINCTRL_PIN(52, "ISH_UART0_RTS_B"),
90 PINCTRL_PIN(53, "ISH_UART0_CTS_B"),
91 PINCTRL_PIN(54, "ISH_UART1_RXD"),
92 PINCTRL_PIN(55, "ISH_UART1_TXT"),
93 PINCTRL_PIN(56, "ISH_UART1_RTS_B"),
94 PINCTRL_PIN(57, "ISH_UART1_CTS_B"),
95 PINCTRL_PIN(58, "ISH_UART2_RXD"),
96 PINCTRL_PIN(59, "ISH_UART2_TXD"),
97 PINCTRL_PIN(60, "ISH_UART2_RTS_B"),
98 PINCTRL_PIN(61, "ISH_UART2_CTS_B"),
99 PINCTRL_PIN(62, "GP_CAMERASB00"),
100 PINCTRL_PIN(63, "GP_CAMERASB01"),
101 PINCTRL_PIN(64, "GP_CAMERASB02"),
102 PINCTRL_PIN(65, "GP_CAMERASB03"),
103 PINCTRL_PIN(66, "GP_CAMERASB04"),
104 PINCTRL_PIN(67, "GP_CAMERASB05"),
105 PINCTRL_PIN(68, "GP_CAMERASB06"),
106 PINCTRL_PIN(69, "GP_CAMERASB07"),
107 PINCTRL_PIN(70, "GP_CAMERASB08"),
108 PINCTRL_PIN(71, "GP_CAMERASB09"),
109 PINCTRL_PIN(72, "GP_CAMERASB10"),
110 PINCTRL_PIN(73, "GP_CAMERASB11"),
111 PINCTRL_PIN(74, "TCK"),
112 PINCTRL_PIN(75, "TRST_B"),
113 PINCTRL_PIN(76, "TMS"),
114 PINCTRL_PIN(77, "TDI"),
115 PINCTRL_PIN(78, "CX_PMODE"),
116 PINCTRL_PIN(79, "CX_PREQ_B"),
117 PINCTRL_PIN(80, "JTAGX"),
118 PINCTRL_PIN(81, "CX_PRDY_B"),
119 PINCTRL_PIN(82, "TDO"),
120};
121
122static const unsigned bxt_north_pwm0_pins[] = { 34 };
123static const unsigned bxt_north_pwm1_pins[] = { 35 };
124static const unsigned bxt_north_pwm2_pins[] = { 36 };
125static const unsigned bxt_north_pwm3_pins[] = { 37 };
126static const unsigned bxt_north_uart0_pins[] = { 38, 39, 40, 41 };
127static const unsigned bxt_north_uart1_pins[] = { 42, 43, 44, 45 };
128static const unsigned bxt_north_uart2_pins[] = { 46, 47, 48, 49 };
129static const unsigned bxt_north_uart0b_pins[] = { 50, 51, 52, 53 };
130static const unsigned bxt_north_uart1b_pins[] = { 54, 55, 56, 57 };
131static const unsigned bxt_north_uart2b_pins[] = { 58, 59, 60, 61 };
132static const unsigned bxt_north_uart3_pins[] = { 58, 59, 60, 61 };
133
134static const struct intel_pingroup bxt_north_groups[] = {
135 PIN_GROUP("pwm0_grp", bxt_north_pwm0_pins, 1),
136 PIN_GROUP("pwm1_grp", bxt_north_pwm1_pins, 1),
137 PIN_GROUP("pwm2_grp", bxt_north_pwm2_pins, 1),
138 PIN_GROUP("pwm3_grp", bxt_north_pwm3_pins, 1),
139 PIN_GROUP("uart0_grp", bxt_north_uart0_pins, 1),
140 PIN_GROUP("uart1_grp", bxt_north_uart1_pins, 1),
141 PIN_GROUP("uart2_grp", bxt_north_uart2_pins, 1),
142 PIN_GROUP("uart0b_grp", bxt_north_uart0b_pins, 2),
143 PIN_GROUP("uart1b_grp", bxt_north_uart1b_pins, 2),
144 PIN_GROUP("uart2b_grp", bxt_north_uart2b_pins, 2),
145 PIN_GROUP("uart3_grp", bxt_north_uart3_pins, 3),
146};
147
148static const char * const bxt_north_pwm0_groups[] = { "pwm0_grp" };
149static const char * const bxt_north_pwm1_groups[] = { "pwm1_grp" };
150static const char * const bxt_north_pwm2_groups[] = { "pwm2_grp" };
151static const char * const bxt_north_pwm3_groups[] = { "pwm3_grp" };
152static const char * const bxt_north_uart0_groups[] = {
153 "uart0_grp", "uart0b_grp",
154};
155static const char * const bxt_north_uart1_groups[] = {
156 "uart1_grp", "uart1b_grp",
157};
158static const char * const bxt_north_uart2_groups[] = {
159 "uart2_grp", "uart2b_grp",
160};
161static const char * const bxt_north_uart3_groups[] = { "uart3_grp" };
162
163static const struct intel_function bxt_north_functions[] = {
164 FUNCTION("pwm0", bxt_north_pwm0_groups),
165 FUNCTION("pwm1", bxt_north_pwm1_groups),
166 FUNCTION("pwm2", bxt_north_pwm2_groups),
167 FUNCTION("pwm3", bxt_north_pwm3_groups),
168 FUNCTION("uart0", bxt_north_uart0_groups),
169 FUNCTION("uart1", bxt_north_uart1_groups),
170 FUNCTION("uart2", bxt_north_uart2_groups),
171 FUNCTION("uart3", bxt_north_uart3_groups),
172};
173
174static const struct intel_community bxt_north_communities[] = {
175 BXT_COMMUNITY(0, 82),
176};
177
178static const struct intel_pinctrl_soc_data bxt_north_soc_data = {
179 .uid = "1",
180 .pins = bxt_north_pins,
181 .npins = ARRAY_SIZE(bxt_north_pins),
182 .groups = bxt_north_groups,
183 .ngroups = ARRAY_SIZE(bxt_north_groups),
184 .functions = bxt_north_functions,
185 .nfunctions = ARRAY_SIZE(bxt_north_functions),
186 .communities = bxt_north_communities,
187 .ncommunities = ARRAY_SIZE(bxt_north_communities),
188};
189
190static const struct pinctrl_pin_desc bxt_northwest_pins[] = {
191 PINCTRL_PIN(0, "PMC_SPI_FS0"),
192 PINCTRL_PIN(1, "PMC_SPI_FS1"),
193 PINCTRL_PIN(2, "PMC_SPI_FS2"),
194 PINCTRL_PIN(3, "PMC_SPI_RXD"),
195 PINCTRL_PIN(4, "PMC_SPI_TXD"),
196 PINCTRL_PIN(5, "PMC_SPI_CLK"),
197 PINCTRL_PIN(6, "PMC_UART_RXD"),
198 PINCTRL_PIN(7, "PMC_UART_TXD"),
199 PINCTRL_PIN(8, "PMIC_PWRGOOD"),
200 PINCTRL_PIN(9, "PMIC_RESET_B"),
201 PINCTRL_PIN(10, "RTC_CLK"),
202 PINCTRL_PIN(11, "PMIC_SDWN_B"),
203 PINCTRL_PIN(12, "PMIC_BCUDISW2"),
204 PINCTRL_PIN(13, "PMIC_BCUDISCRIT"),
205 PINCTRL_PIN(14, "PMIC_THERMTRIP_B"),
206 PINCTRL_PIN(15, "PMIC_STDBY"),
207 PINCTRL_PIN(16, "SVID0_ALERT_B"),
208 PINCTRL_PIN(17, "SVID0_DATA"),
209 PINCTRL_PIN(18, "SVID0_CLK"),
210 PINCTRL_PIN(19, "PMIC_I2C_SCL"),
211 PINCTRL_PIN(20, "PMIC_I2C_SDA"),
212 PINCTRL_PIN(21, "AVS_I2S1_MCLK"),
213 PINCTRL_PIN(22, "AVS_I2S1_BCLK"),
214 PINCTRL_PIN(23, "AVS_I2S1_WS_SYNC"),
215 PINCTRL_PIN(24, "AVS_I2S1_SDI"),
216 PINCTRL_PIN(25, "AVS_I2S1_SDO"),
217 PINCTRL_PIN(26, "AVS_M_CLK_A1"),
218 PINCTRL_PIN(27, "AVS_M_CLK_B1"),
219 PINCTRL_PIN(28, "AVS_M_DATA_1"),
220 PINCTRL_PIN(29, "AVS_M_CLK_AB2"),
221 PINCTRL_PIN(30, "AVS_M_DATA_2"),
222 PINCTRL_PIN(31, "AVS_I2S2_MCLK"),
223 PINCTRL_PIN(32, "AVS_I2S2_BCLK"),
224 PINCTRL_PIN(33, "AVS_I2S2_WS_SYNC"),
225 PINCTRL_PIN(34, "AVS_I2S2_SDI"),
226 PINCTRL_PIN(35, "AVS_I2S2_SDOK"),
227 PINCTRL_PIN(36, "AVS_I2S3_BCLK"),
228 PINCTRL_PIN(37, "AVS_I2S3_WS_SYNC"),
229 PINCTRL_PIN(38, "AVS_I2S3_SDI"),
230 PINCTRL_PIN(39, "AVS_I2S3_SDO"),
231 PINCTRL_PIN(40, "AVS_I2S4_BCLK"),
232 PINCTRL_PIN(41, "AVS_I2S4_WS_SYNC"),
233 PINCTRL_PIN(42, "AVS_I2S4_SDI"),
234 PINCTRL_PIN(43, "AVS_I2S4_SDO"),
235 PINCTRL_PIN(44, "PROCHOT_B"),
236 PINCTRL_PIN(45, "FST_SPI_CS0_B"),
237 PINCTRL_PIN(46, "FST_SPI_CS1_B"),
238 PINCTRL_PIN(47, "FST_SPI_MOSI_IO0"),
239 PINCTRL_PIN(48, "FST_SPI_MISO_IO1"),
240 PINCTRL_PIN(49, "FST_SPI_IO2"),
241 PINCTRL_PIN(50, "FST_SPI_IO3"),
242 PINCTRL_PIN(51, "FST_SPI_CLK"),
243 PINCTRL_PIN(52, "FST_SPI_CLK_FB"),
244 PINCTRL_PIN(53, "GP_SSP_0_CLK"),
245 PINCTRL_PIN(54, "GP_SSP_0_FS0"),
246 PINCTRL_PIN(55, "GP_SSP_0_FS1"),
247 PINCTRL_PIN(56, "GP_SSP_0_FS2"),
248 PINCTRL_PIN(57, "GP_SSP_0_RXD"),
249 PINCTRL_PIN(58, "GP_SSP_0_TXD"),
250 PINCTRL_PIN(59, "GP_SSP_1_CLK"),
251 PINCTRL_PIN(60, "GP_SSP_1_FS0"),
252 PINCTRL_PIN(61, "GP_SSP_1_FS1"),
253 PINCTRL_PIN(62, "GP_SSP_1_FS2"),
254 PINCTRL_PIN(63, "GP_SSP_1_FS3"),
255 PINCTRL_PIN(64, "GP_SSP_1_RXD"),
256 PINCTRL_PIN(65, "GP_SSP_1_TXD"),
257 PINCTRL_PIN(66, "GP_SSP_2_CLK"),
258 PINCTRL_PIN(67, "GP_SSP_2_FS0"),
259 PINCTRL_PIN(68, "GP_SSP_2_FS1"),
260 PINCTRL_PIN(69, "GP_SSP_2_FS2"),
261 PINCTRL_PIN(70, "GP_SSP_2_RXD"),
262 PINCTRL_PIN(71, "GP_SSP_2_TXD"),
263};
264
265static const unsigned bxt_northwest_ssp0_pins[] = { 53, 54, 55, 56, 57, 58 };
266static const unsigned bxt_northwest_ssp1_pins[] = {
267 59, 60, 61, 62, 63, 64, 65
268};
269static const unsigned bxt_northwest_ssp2_pins[] = { 66, 67, 68, 69, 70, 71 };
270static const unsigned bxt_northwest_uart3_pins[] = { 67, 68, 69, 70 };
271
272static const struct intel_pingroup bxt_northwest_groups[] = {
273 PIN_GROUP("ssp0_grp", bxt_northwest_ssp0_pins, 1),
274 PIN_GROUP("ssp1_grp", bxt_northwest_ssp1_pins, 1),
275 PIN_GROUP("ssp2_grp", bxt_northwest_ssp2_pins, 1),
276 PIN_GROUP("uart3_grp", bxt_northwest_uart3_pins, 2),
277};
278
279static const char * const bxt_northwest_ssp0_groups[] = { "ssp0_grp" };
280static const char * const bxt_northwest_ssp1_groups[] = { "ssp1_grp" };
281static const char * const bxt_northwest_ssp2_groups[] = { "ssp2_grp" };
282static const char * const bxt_northwest_uart3_groups[] = { "uart3_grp" };
283
284static const struct intel_function bxt_northwest_functions[] = {
285 FUNCTION("ssp0", bxt_northwest_ssp0_groups),
286 FUNCTION("ssp1", bxt_northwest_ssp1_groups),
287 FUNCTION("ssp2", bxt_northwest_ssp2_groups),
288 FUNCTION("uart3", bxt_northwest_uart3_groups),
289};
290
291static const struct intel_community bxt_northwest_communities[] = {
292 BXT_COMMUNITY(0, 71),
293};
294
295static const struct intel_pinctrl_soc_data bxt_northwest_soc_data = {
296 .uid = "2",
297 .pins = bxt_northwest_pins,
298 .npins = ARRAY_SIZE(bxt_northwest_pins),
299 .groups = bxt_northwest_groups,
300 .ngroups = ARRAY_SIZE(bxt_northwest_groups),
301 .functions = bxt_northwest_functions,
302 .nfunctions = ARRAY_SIZE(bxt_northwest_functions),
303 .communities = bxt_northwest_communities,
304 .ncommunities = ARRAY_SIZE(bxt_northwest_communities),
305};
306
307static const struct pinctrl_pin_desc bxt_west_pins[] = {
308 PINCTRL_PIN(0, "LPSS_I2C0_SDA"),
309 PINCTRL_PIN(1, "LPSS_I2C0_SCL"),
310 PINCTRL_PIN(2, "LPSS_I2C1_SDA"),
311 PINCTRL_PIN(3, "LPSS_I2C1_SCL"),
312 PINCTRL_PIN(4, "LPSS_I2C2_SDA"),
313 PINCTRL_PIN(5, "LPSS_I2C2_SCL"),
314 PINCTRL_PIN(6, "LPSS_I2C3_SDA"),
315 PINCTRL_PIN(7, "LPSS_I2C3_SCL"),
316 PINCTRL_PIN(8, "LPSS_I2C4_SDA"),
317 PINCTRL_PIN(9, "LPSS_I2C4_SCL"),
318 PINCTRL_PIN(10, "LPSS_I2C5_SDA"),
319 PINCTRL_PIN(11, "LPSS_I2C5_SCL"),
320 PINCTRL_PIN(12, "LPSS_I2C6_SDA"),
321 PINCTRL_PIN(13, "LPSS_I2C6_SCL"),
322 PINCTRL_PIN(14, "LPSS_I2C7_SDA"),
323 PINCTRL_PIN(15, "LPSS_I2C7_SCL"),
324 PINCTRL_PIN(16, "ISH_I2C0_SDA"),
325 PINCTRL_PIN(17, "ISH_I2C0_SCL"),
326 PINCTRL_PIN(18, "ISH_I2C1_SDA"),
327 PINCTRL_PIN(19, "ISH_I2C1_SCL"),
328 PINCTRL_PIN(20, "ISH_I2C2_SDA"),
329 PINCTRL_PIN(21, "ISH_I2C2_SCL"),
330 PINCTRL_PIN(22, "ISH_GPIO_0"),
331 PINCTRL_PIN(23, "ISH_GPIO_1"),
332 PINCTRL_PIN(24, "ISH_GPIO_2"),
333 PINCTRL_PIN(25, "ISH_GPIO_3"),
334 PINCTRL_PIN(26, "ISH_GPIO_4"),
335 PINCTRL_PIN(27, "ISH_GPIO_5"),
336 PINCTRL_PIN(28, "ISH_GPIO_6"),
337 PINCTRL_PIN(29, "ISH_GPIO_7"),
338 PINCTRL_PIN(30, "ISH_GPIO_8"),
339 PINCTRL_PIN(31, "ISH_GPIO_9"),
340 PINCTRL_PIN(32, "MODEM_CLKREQ"),
341 PINCTRL_PIN(33, "DGCLKDBG_PMC_0"),
342 PINCTRL_PIN(34, "DGCLKDBG_PMC_1"),
343 PINCTRL_PIN(35, "DGCLKDBG_PMC_2"),
344 PINCTRL_PIN(36, "DGCLKDBG_ICLK_0"),
345 PINCTRL_PIN(37, "DGCLKDBG_ICLK_1"),
346 PINCTRL_PIN(38, "OSC_CLK_OUT_0"),
347 PINCTRL_PIN(39, "OSC_CLK_OUT_1"),
348 PINCTRL_PIN(40, "OSC_CLK_OUT_2"),
349 PINCTRL_PIN(41, "OSC_CLK_OUT_3"),
350};
351
352static const unsigned bxt_west_i2c0_pins[] = { 0, 1 };
353static const unsigned bxt_west_i2c1_pins[] = { 2, 3 };
354static const unsigned bxt_west_i2c2_pins[] = { 4, 5 };
355static const unsigned bxt_west_i2c3_pins[] = { 6, 7 };
356static const unsigned bxt_west_i2c4_pins[] = { 8, 9 };
357static const unsigned bxt_west_i2c5_pins[] = { 10, 11 };
358static const unsigned bxt_west_i2c6_pins[] = { 12, 13 };
359static const unsigned bxt_west_i2c7_pins[] = { 14, 15 };
360static const unsigned bxt_west_i2c5b_pins[] = { 16, 17 };
361static const unsigned bxt_west_i2c6b_pins[] = { 18, 19 };
362static const unsigned bxt_west_i2c7b_pins[] = { 20, 21 };
363
364static const struct intel_pingroup bxt_west_groups[] = {
365 PIN_GROUP("i2c0_grp", bxt_west_i2c0_pins, 1),
366 PIN_GROUP("i2c1_grp", bxt_west_i2c1_pins, 1),
367 PIN_GROUP("i2c2_grp", bxt_west_i2c2_pins, 1),
368 PIN_GROUP("i2c3_grp", bxt_west_i2c3_pins, 1),
369 PIN_GROUP("i2c4_grp", bxt_west_i2c4_pins, 1),
370 PIN_GROUP("i2c5_grp", bxt_west_i2c5_pins, 1),
371 PIN_GROUP("i2c6_grp", bxt_west_i2c6_pins, 1),
372 PIN_GROUP("i2c7_grp", bxt_west_i2c7_pins, 1),
373 PIN_GROUP("i2c5b_grp", bxt_west_i2c5b_pins, 2),
374 PIN_GROUP("i2c6b_grp", bxt_west_i2c6b_pins, 2),
375 PIN_GROUP("i2c7b_grp", bxt_west_i2c7b_pins, 2),
376};
377
378static const char * const bxt_west_i2c0_groups[] = { "i2c0_grp" };
379static const char * const bxt_west_i2c1_groups[] = { "i2c1_grp" };
380static const char * const bxt_west_i2c2_groups[] = { "i2c2_grp" };
381static const char * const bxt_west_i2c3_groups[] = { "i2c3_grp" };
382static const char * const bxt_west_i2c4_groups[] = { "i2c4_grp" };
383static const char * const bxt_west_i2c5_groups[] = { "i2c5_grp", "i2c5b_grp" };
384static const char * const bxt_west_i2c6_groups[] = { "i2c6_grp", "i2c6b_grp" };
385static const char * const bxt_west_i2c7_groups[] = { "i2c7_grp", "i2c7b_grp" };
386
387static const struct intel_function bxt_west_functions[] = {
388 FUNCTION("i2c0", bxt_west_i2c0_groups),
389 FUNCTION("i2c1", bxt_west_i2c1_groups),
390 FUNCTION("i2c2", bxt_west_i2c2_groups),
391 FUNCTION("i2c3", bxt_west_i2c3_groups),
392 FUNCTION("i2c4", bxt_west_i2c4_groups),
393 FUNCTION("i2c5", bxt_west_i2c5_groups),
394 FUNCTION("i2c6", bxt_west_i2c6_groups),
395 FUNCTION("i2c7", bxt_west_i2c7_groups),
396};
397
398static const struct intel_community bxt_west_communities[] = {
399 BXT_COMMUNITY(0, 41),
400};
401
402static const struct intel_pinctrl_soc_data bxt_west_soc_data = {
403 .uid = "3",
404 .pins = bxt_west_pins,
405 .npins = ARRAY_SIZE(bxt_west_pins),
406 .groups = bxt_west_groups,
407 .ngroups = ARRAY_SIZE(bxt_west_groups),
408 .functions = bxt_west_functions,
409 .nfunctions = ARRAY_SIZE(bxt_west_functions),
410 .communities = bxt_west_communities,
411 .ncommunities = ARRAY_SIZE(bxt_west_communities),
412};
413
414static const struct pinctrl_pin_desc bxt_southwest_pins[] = {
415 PINCTRL_PIN(0, "EMMC0_CLK"),
416 PINCTRL_PIN(1, "EMMC0_D0"),
417 PINCTRL_PIN(2, "EMMC0_D1"),
418 PINCTRL_PIN(3, "EMMC0_D2"),
419 PINCTRL_PIN(4, "EMMC0_D3"),
420 PINCTRL_PIN(5, "EMMC0_D4"),
421 PINCTRL_PIN(6, "EMMC0_D5"),
422 PINCTRL_PIN(7, "EMMC0_D6"),
423 PINCTRL_PIN(8, "EMMC0_D7"),
424 PINCTRL_PIN(9, "EMMC0_CMD"),
425 PINCTRL_PIN(10, "SDIO_CLK"),
426 PINCTRL_PIN(11, "SDIO_D0"),
427 PINCTRL_PIN(12, "SDIO_D1"),
428 PINCTRL_PIN(13, "SDIO_D2"),
429 PINCTRL_PIN(14, "SDIO_D3"),
430 PINCTRL_PIN(15, "SDIO_CMD"),
431 PINCTRL_PIN(16, "SDCARD_CLK"),
432 PINCTRL_PIN(17, "SDCARD_D0"),
433 PINCTRL_PIN(18, "SDCARD_D1"),
434 PINCTRL_PIN(19, "SDCARD_D2"),
435 PINCTRL_PIN(20, "SDCARD_D3"),
436 PINCTRL_PIN(21, "SDCARD_CD_B"),
437 PINCTRL_PIN(22, "SDCARD_CMD"),
438 PINCTRL_PIN(23, "SDCARD_LVL_CLK_FB"),
439 PINCTRL_PIN(24, "SDCARD_LVL_CMD_DIR"),
440 PINCTRL_PIN(25, "SDCARD_LVL_DAT_DIR"),
441 PINCTRL_PIN(26, "EMMC0_STROBE"),
442 PINCTRL_PIN(27, "SDIO_PWR_DOWN_B"),
443 PINCTRL_PIN(28, "SDCARD_PWR_DOWN_B"),
444 PINCTRL_PIN(29, "SDCARD_LVL_SEL"),
445 PINCTRL_PIN(30, "SDCARD_LVL_WP"),
446};
447
448static const unsigned bxt_southwest_emmc0_pins[] = {
449 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 26,
450};
451static const unsigned bxt_southwest_sdio_pins[] = {
452 10, 11, 12, 13, 14, 15, 27,
453};
454static const unsigned bxt_southwest_sdcard_pins[] = {
455 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 28, 29, 30,
456};
457
458static const struct intel_pingroup bxt_southwest_groups[] = {
459 PIN_GROUP("emmc0_grp", bxt_southwest_emmc0_pins, 1),
460 PIN_GROUP("sdio_grp", bxt_southwest_sdio_pins, 1),
461 PIN_GROUP("sdcard_grp", bxt_southwest_sdcard_pins, 1),
462};
463
464static const char * const bxt_southwest_emmc0_groups[] = { "emmc0_grp" };
465static const char * const bxt_southwest_sdio_groups[] = { "sdio_grp" };
466static const char * const bxt_southwest_sdcard_groups[] = { "sdcard_grp" };
467
468static const struct intel_function bxt_southwest_functions[] = {
469 FUNCTION("emmc0", bxt_southwest_emmc0_groups),
470 FUNCTION("sdio", bxt_southwest_sdio_groups),
471 FUNCTION("sdcard", bxt_southwest_sdcard_groups),
472};
473
474static const struct intel_community bxt_southwest_communities[] = {
475 BXT_COMMUNITY(0, 30),
476};
477
478static const struct intel_pinctrl_soc_data bxt_southwest_soc_data = {
479 .uid = "4",
480 .pins = bxt_southwest_pins,
481 .npins = ARRAY_SIZE(bxt_southwest_pins),
482 .groups = bxt_southwest_groups,
483 .ngroups = ARRAY_SIZE(bxt_southwest_groups),
484 .functions = bxt_southwest_functions,
485 .nfunctions = ARRAY_SIZE(bxt_southwest_functions),
486 .communities = bxt_southwest_communities,
487 .ncommunities = ARRAY_SIZE(bxt_southwest_communities),
488};
489
490static const struct pinctrl_pin_desc bxt_south_pins[] = {
491 PINCTRL_PIN(0, "HV_DDI0_DDC_SDA"),
492 PINCTRL_PIN(1, "HV_DDI0_DDC_SCL"),
493 PINCTRL_PIN(2, "HV_DDI1_DDC_SDA"),
494 PINCTRL_PIN(3, "HV_DDI1_DDC_SCL"),
495 PINCTRL_PIN(4, "DBI_SDA"),
496 PINCTRL_PIN(5, "DBI_SCL"),
497 PINCTRL_PIN(6, "PANEL0_VDDEN"),
498 PINCTRL_PIN(7, "PANEL0_BKLTEN"),
499 PINCTRL_PIN(8, "PANEL0_BKLTCTL"),
500 PINCTRL_PIN(9, "PANEL1_VDDEN"),
501 PINCTRL_PIN(10, "PANEL1_BKLTEN"),
502 PINCTRL_PIN(11, "PANEL1_BKLTCTL"),
503 PINCTRL_PIN(12, "DBI_CSX"),
504 PINCTRL_PIN(13, "DBI_RESX"),
505 PINCTRL_PIN(14, "GP_INTD_DSI_TE1"),
506 PINCTRL_PIN(15, "GP_INTD_DSI_TE2"),
507 PINCTRL_PIN(16, "USB_OC0_B"),
508 PINCTRL_PIN(17, "USB_OC1_B"),
509 PINCTRL_PIN(18, "MEX_WAKE0_B"),
510 PINCTRL_PIN(19, "MEX_WAKE1_B"),
511};
512
513static const struct intel_community bxt_south_communities[] = {
514 BXT_COMMUNITY(0, 19),
515};
516
517static const struct intel_pinctrl_soc_data bxt_south_soc_data = {
518 .uid = "5",
519 .pins = bxt_south_pins,
520 .npins = ARRAY_SIZE(bxt_south_pins),
521 .communities = bxt_south_communities,
522 .ncommunities = ARRAY_SIZE(bxt_south_communities),
523};
524
525static const struct intel_pinctrl_soc_data *bxt_pinctrl_soc_data[] = {
526 &bxt_north_soc_data,
527 &bxt_northwest_soc_data,
528 &bxt_west_soc_data,
529 &bxt_southwest_soc_data,
530 &bxt_south_soc_data,
531 NULL,
532};
533
534/* APL */
535static const struct pinctrl_pin_desc apl_north_pins[] = {
536 PINCTRL_PIN(0, "GPIO_0"),
537 PINCTRL_PIN(1, "GPIO_1"),
538 PINCTRL_PIN(2, "GPIO_2"),
539 PINCTRL_PIN(3, "GPIO_3"),
540 PINCTRL_PIN(4, "GPIO_4"),
541 PINCTRL_PIN(5, "GPIO_5"),
542 PINCTRL_PIN(6, "GPIO_6"),
543 PINCTRL_PIN(7, "GPIO_7"),
544 PINCTRL_PIN(8, "GPIO_8"),
545 PINCTRL_PIN(9, "GPIO_9"),
546 PINCTRL_PIN(10, "GPIO_10"),
547 PINCTRL_PIN(11, "GPIO_11"),
548 PINCTRL_PIN(12, "GPIO_12"),
549 PINCTRL_PIN(13, "GPIO_13"),
550 PINCTRL_PIN(14, "GPIO_14"),
551 PINCTRL_PIN(15, "GPIO_15"),
552 PINCTRL_PIN(16, "GPIO_16"),
553 PINCTRL_PIN(17, "GPIO_17"),
554 PINCTRL_PIN(18, "GPIO_18"),
555 PINCTRL_PIN(19, "GPIO_19"),
556 PINCTRL_PIN(20, "GPIO_20"),
557 PINCTRL_PIN(21, "GPIO_21"),
558 PINCTRL_PIN(22, "GPIO_22"),
559 PINCTRL_PIN(23, "GPIO_23"),
560 PINCTRL_PIN(24, "GPIO_24"),
561 PINCTRL_PIN(25, "GPIO_25"),
562 PINCTRL_PIN(26, "GPIO_26"),
563 PINCTRL_PIN(27, "GPIO_27"),
564 PINCTRL_PIN(28, "GPIO_28"),
565 PINCTRL_PIN(29, "GPIO_29"),
566 PINCTRL_PIN(30, "GPIO_30"),
567 PINCTRL_PIN(31, "GPIO_31"),
568 PINCTRL_PIN(32, "GPIO_32"),
569 PINCTRL_PIN(33, "GPIO_33"),
570 PINCTRL_PIN(34, "PWM0"),
571 PINCTRL_PIN(35, "PWM1"),
572 PINCTRL_PIN(36, "PWM2"),
573 PINCTRL_PIN(37, "PWM3"),
574 PINCTRL_PIN(38, "LPSS_UART0_RXD"),
575 PINCTRL_PIN(39, "LPSS_UART0_TXD"),
576 PINCTRL_PIN(40, "LPSS_UART0_RTS_B"),
577 PINCTRL_PIN(41, "LPSS_UART0_CTS_B"),
578 PINCTRL_PIN(42, "LPSS_UART1_RXD"),
579 PINCTRL_PIN(43, "LPSS_UART1_TXD"),
580 PINCTRL_PIN(44, "LPSS_UART1_RTS_B"),
581 PINCTRL_PIN(45, "LPSS_UART1_CTS_B"),
582 PINCTRL_PIN(46, "LPSS_UART2_RXD"),
583 PINCTRL_PIN(47, "LPSS_UART2_TXD"),
584 PINCTRL_PIN(48, "LPSS_UART2_RTS_B"),
585 PINCTRL_PIN(49, "LPSS_UART2_CTS_B"),
586 PINCTRL_PIN(50, "GP_CAMERASB00"),
587 PINCTRL_PIN(51, "GP_CAMERASB01"),
588 PINCTRL_PIN(52, "GP_CAMERASB02"),
589 PINCTRL_PIN(53, "GP_CAMERASB03"),
590 PINCTRL_PIN(54, "GP_CAMERASB04"),
591 PINCTRL_PIN(55, "GP_CAMERASB05"),
592 PINCTRL_PIN(56, "GP_CAMERASB06"),
593 PINCTRL_PIN(57, "GP_CAMERASB07"),
594 PINCTRL_PIN(58, "GP_CAMERASB08"),
595 PINCTRL_PIN(59, "GP_CAMERASB09"),
596 PINCTRL_PIN(60, "GP_CAMERASB10"),
597 PINCTRL_PIN(61, "GP_CAMERASB11"),
598 PINCTRL_PIN(62, "TCK"),
599 PINCTRL_PIN(63, "TRST_B"),
600 PINCTRL_PIN(64, "TMS"),
601 PINCTRL_PIN(65, "TDI"),
602 PINCTRL_PIN(66, "CX_PMODE"),
603 PINCTRL_PIN(67, "CX_PREQ_B"),
604 PINCTRL_PIN(68, "JTAGX"),
605 PINCTRL_PIN(69, "CX_PRDY_B"),
606 PINCTRL_PIN(70, "TDO"),
607 PINCTRL_PIN(71, "CNV_BRI_DT"),
608 PINCTRL_PIN(72, "CNV_BRI_RSP"),
609 PINCTRL_PIN(73, "CNV_RGI_DT"),
610 PINCTRL_PIN(74, "CNV_RGI_RSP"),
611 PINCTRL_PIN(75, "SVID0_ALERT_B"),
612 PINCTRL_PIN(76, "SVID0_DATA"),
613 PINCTRL_PIN(77, "SVID0_CLK"),
614};
615
616static const unsigned apl_north_pwm0_pins[] = { 34 };
617static const unsigned apl_north_pwm1_pins[] = { 35 };
618static const unsigned apl_north_pwm2_pins[] = { 36 };
619static const unsigned apl_north_pwm3_pins[] = { 37 };
620static const unsigned apl_north_uart0_pins[] = { 38, 39, 40, 41 };
621static const unsigned apl_north_uart1_pins[] = { 42, 43, 44, 45 };
622static const unsigned apl_north_uart2_pins[] = { 46, 47, 48, 49 };
623
624static const struct intel_pingroup apl_north_groups[] = {
625 PIN_GROUP("pwm0_grp", apl_north_pwm0_pins, 1),
626 PIN_GROUP("pwm1_grp", apl_north_pwm1_pins, 1),
627 PIN_GROUP("pwm2_grp", apl_north_pwm2_pins, 1),
628 PIN_GROUP("pwm3_grp", apl_north_pwm3_pins, 1),
629 PIN_GROUP("uart0_grp", apl_north_uart0_pins, 1),
630 PIN_GROUP("uart1_grp", apl_north_uart1_pins, 1),
631 PIN_GROUP("uart2_grp", apl_north_uart2_pins, 1),
632};
633
634static const char * const apl_north_pwm0_groups[] = { "pwm0_grp" };
635static const char * const apl_north_pwm1_groups[] = { "pwm1_grp" };
636static const char * const apl_north_pwm2_groups[] = { "pwm2_grp" };
637static const char * const apl_north_pwm3_groups[] = { "pwm3_grp" };
638static const char * const apl_north_uart0_groups[] = { "uart0_grp" };
639static const char * const apl_north_uart1_groups[] = { "uart1_grp" };
640static const char * const apl_north_uart2_groups[] = { "uart2_grp" };
641
642static const struct intel_function apl_north_functions[] = {
643 FUNCTION("pwm0", apl_north_pwm0_groups),
644 FUNCTION("pwm1", apl_north_pwm1_groups),
645 FUNCTION("pwm2", apl_north_pwm2_groups),
646 FUNCTION("pwm3", apl_north_pwm3_groups),
647 FUNCTION("uart0", apl_north_uart0_groups),
648 FUNCTION("uart1", apl_north_uart1_groups),
649 FUNCTION("uart2", apl_north_uart2_groups),
650};
651
652static const struct intel_community apl_north_communities[] = {
653 BXT_COMMUNITY(0, 77),
654};
655
656static const struct intel_pinctrl_soc_data apl_north_soc_data = {
657 .uid = "1",
658 .pins = apl_north_pins,
659 .npins = ARRAY_SIZE(apl_north_pins),
660 .groups = apl_north_groups,
661 .ngroups = ARRAY_SIZE(apl_north_groups),
662 .functions = apl_north_functions,
663 .nfunctions = ARRAY_SIZE(apl_north_functions),
664 .communities = apl_north_communities,
665 .ncommunities = ARRAY_SIZE(apl_north_communities),
666};
667
668static const struct pinctrl_pin_desc apl_northwest_pins[] = {
669 PINCTRL_PIN(0, "HV_DDI0_DDC_SDA"),
670 PINCTRL_PIN(1, "HV_DDI0_DDC_SCL"),
671 PINCTRL_PIN(2, "HV_DDI1_DDC_SDA"),
672 PINCTRL_PIN(3, "HV_DDI1_DDC_SCL"),
673 PINCTRL_PIN(4, "DBI_SDA"),
674 PINCTRL_PIN(5, "DBI_SCL"),
675 PINCTRL_PIN(6, "PANEL0_VDDEN"),
676 PINCTRL_PIN(7, "PANEL0_BKLTEN"),
677 PINCTRL_PIN(8, "PANEL0_BKLTCTL"),
678 PINCTRL_PIN(9, "PANEL1_VDDEN"),
679 PINCTRL_PIN(10, "PANEL1_BKLTEN"),
680 PINCTRL_PIN(11, "PANEL1_BKLTCTL"),
681 PINCTRL_PIN(12, "DBI_CSX"),
682 PINCTRL_PIN(13, "DBI_RESX"),
683 PINCTRL_PIN(14, "GP_INTD_DSI_TE1"),
684 PINCTRL_PIN(15, "GP_INTD_DSI_TE2"),
685 PINCTRL_PIN(16, "USB_OC0_B"),
686 PINCTRL_PIN(17, "USB_OC1_B"),
687 PINCTRL_PIN(18, "PMC_SPI_FS0"),
688 PINCTRL_PIN(19, "PMC_SPI_FS1"),
689 PINCTRL_PIN(20, "PMC_SPI_FS2"),
690 PINCTRL_PIN(21, "PMC_SPI_RXD"),
691 PINCTRL_PIN(22, "PMC_SPI_TXD"),
692 PINCTRL_PIN(23, "PMC_SPI_CLK"),
693 PINCTRL_PIN(24, "PMIC_PWRGOOD"),
694 PINCTRL_PIN(25, "PMIC_RESET_B"),
695 PINCTRL_PIN(26, "PMIC_SDWN_B"),
696 PINCTRL_PIN(27, "PMIC_BCUDISW2"),
697 PINCTRL_PIN(28, "PMIC_BCUDISCRIT"),
698 PINCTRL_PIN(29, "PMIC_THERMTRIP_B"),
699 PINCTRL_PIN(30, "PMIC_STDBY"),
700 PINCTRL_PIN(31, "PROCHOT_B"),
701 PINCTRL_PIN(32, "PMIC_I2C_SCL"),
702 PINCTRL_PIN(33, "PMIC_I2C_SDA"),
703 PINCTRL_PIN(34, "AVS_I2S1_MCLK"),
704 PINCTRL_PIN(35, "AVS_I2S1_BCLK"),
705 PINCTRL_PIN(36, "AVS_I2S1_WS_SYNC"),
706 PINCTRL_PIN(37, "AVS_I2S1_SDI"),
707 PINCTRL_PIN(38, "AVS_I2S1_SDO"),
708 PINCTRL_PIN(39, "AVS_M_CLK_A1"),
709 PINCTRL_PIN(40, "AVS_M_CLK_B1"),
710 PINCTRL_PIN(41, "AVS_M_DATA_1"),
711 PINCTRL_PIN(42, "AVS_M_CLK_AB2"),
712 PINCTRL_PIN(43, "AVS_M_DATA_2"),
713 PINCTRL_PIN(44, "AVS_I2S2_MCLK"),
714 PINCTRL_PIN(45, "AVS_I2S2_BCLK"),
715 PINCTRL_PIN(46, "AVS_I2S2_WS_SYNC"),
716 PINCTRL_PIN(47, "AVS_I2S2_SDI"),
717 PINCTRL_PIN(48, "AVS_I2S2_SDO"),
718 PINCTRL_PIN(49, "AVS_I2S3_BCLK"),
719 PINCTRL_PIN(50, "AVS_I2S3_WS_SYNC"),
720 PINCTRL_PIN(51, "AVS_I2S3_SDI"),
721 PINCTRL_PIN(52, "AVS_I2S3_SDO"),
722 PINCTRL_PIN(53, "FST_SPI_CS0_B"),
723 PINCTRL_PIN(54, "FST_SPI_CS1_B"),
724 PINCTRL_PIN(55, "FST_SPI_MOSI_IO0"),
725 PINCTRL_PIN(56, "FST_SPI_MISO_IO1"),
726 PINCTRL_PIN(57, "FST_SPI_IO2"),
727 PINCTRL_PIN(58, "FST_SPI_IO3"),
728 PINCTRL_PIN(59, "FST_SPI_CLK"),
729 PINCTRL_PIN(60, "FST_SPI_CLK_FB"),
730 PINCTRL_PIN(61, "GP_SSP_0_CLK"),
731 PINCTRL_PIN(62, "GP_SSP_0_FS0"),
732 PINCTRL_PIN(63, "GP_SSP_0_FS1"),
733 PINCTRL_PIN(64, "GP_SSP_0_RXD"),
734 PINCTRL_PIN(65, "GP_SSP_0_TXD"),
735 PINCTRL_PIN(66, "GP_SSP_1_CLK"),
736 PINCTRL_PIN(67, "GP_SSP_1_FS0"),
737 PINCTRL_PIN(68, "GP_SSP_1_FS1"),
738 PINCTRL_PIN(69, "GP_SSP_1_RXD"),
739 PINCTRL_PIN(70, "GP_SSP_1_TXD"),
740 PINCTRL_PIN(71, "GP_SSP_2_CLK"),
741 PINCTRL_PIN(72, "GP_SSP_2_FS0"),
742 PINCTRL_PIN(73, "GP_SSP_2_FS1"),
743 PINCTRL_PIN(74, "GP_SSP_2_FS2"),
744 PINCTRL_PIN(75, "GP_SSP_2_RXD"),
745 PINCTRL_PIN(76, "GP_SSP_2_TXD"),
746};
747
748static const unsigned apl_northwest_ssp0_pins[] = { 61, 62, 63, 64, 65 };
749static const unsigned apl_northwest_ssp1_pins[] = { 66, 67, 68, 69, 70 };
750static const unsigned apl_northwest_ssp2_pins[] = { 71, 72, 73, 74, 75, 76 };
751static const unsigned apl_northwest_uart3_pins[] = { 67, 68, 69, 70 };
752
753static const struct intel_pingroup apl_northwest_groups[] = {
754 PIN_GROUP("ssp0_grp", apl_northwest_ssp0_pins, 1),
755 PIN_GROUP("ssp1_grp", apl_northwest_ssp1_pins, 1),
756 PIN_GROUP("ssp2_grp", apl_northwest_ssp2_pins, 1),
757 PIN_GROUP("uart3_grp", apl_northwest_uart3_pins, 2),
758};
759
760static const char * const apl_northwest_ssp0_groups[] = { "ssp0_grp" };
761static const char * const apl_northwest_ssp1_groups[] = { "ssp1_grp" };
762static const char * const apl_northwest_ssp2_groups[] = { "ssp2_grp" };
763static const char * const apl_northwest_uart3_groups[] = { "uart3_grp" };
764
765static const struct intel_function apl_northwest_functions[] = {
766 FUNCTION("ssp0", apl_northwest_ssp0_groups),
767 FUNCTION("ssp1", apl_northwest_ssp1_groups),
768 FUNCTION("ssp2", apl_northwest_ssp2_groups),
769 FUNCTION("uart3", apl_northwest_uart3_groups),
770};
771
772static const struct intel_community apl_northwest_communities[] = {
773 BXT_COMMUNITY(0, 76),
774};
775
776static const struct intel_pinctrl_soc_data apl_northwest_soc_data = {
777 .uid = "2",
778 .pins = apl_northwest_pins,
779 .npins = ARRAY_SIZE(apl_northwest_pins),
780 .groups = apl_northwest_groups,
781 .ngroups = ARRAY_SIZE(apl_northwest_groups),
782 .functions = apl_northwest_functions,
783 .nfunctions = ARRAY_SIZE(apl_northwest_functions),
784 .communities = apl_northwest_communities,
785 .ncommunities = ARRAY_SIZE(apl_northwest_communities),
786};
787
788static const struct pinctrl_pin_desc apl_west_pins[] = {
789 PINCTRL_PIN(0, "LPSS_I2C0_SDA"),
790 PINCTRL_PIN(1, "LPSS_I2C0_SCL"),
791 PINCTRL_PIN(2, "LPSS_I2C1_SDA"),
792 PINCTRL_PIN(3, "LPSS_I2C1_SCL"),
793 PINCTRL_PIN(4, "LPSS_I2C2_SDA"),
794 PINCTRL_PIN(5, "LPSS_I2C2_SCL"),
795 PINCTRL_PIN(6, "LPSS_I2C3_SDA"),
796 PINCTRL_PIN(7, "LPSS_I2C3_SCL"),
797 PINCTRL_PIN(8, "LPSS_I2C4_SDA"),
798 PINCTRL_PIN(9, "LPSS_I2C4_SCL"),
799 PINCTRL_PIN(10, "LPSS_I2C5_SDA"),
800 PINCTRL_PIN(11, "LPSS_I2C5_SCL"),
801 PINCTRL_PIN(12, "LPSS_I2C6_SDA"),
802 PINCTRL_PIN(13, "LPSS_I2C6_SCL"),
803 PINCTRL_PIN(14, "LPSS_I2C7_SDA"),
804 PINCTRL_PIN(15, "LPSS_I2C7_SCL"),
805 PINCTRL_PIN(16, "ISH_GPIO_0"),
806 PINCTRL_PIN(17, "ISH_GPIO_1"),
807 PINCTRL_PIN(18, "ISH_GPIO_2"),
808 PINCTRL_PIN(19, "ISH_GPIO_3"),
809 PINCTRL_PIN(20, "ISH_GPIO_4"),
810 PINCTRL_PIN(21, "ISH_GPIO_5"),
811 PINCTRL_PIN(22, "ISH_GPIO_6"),
812 PINCTRL_PIN(23, "ISH_GPIO_7"),
813 PINCTRL_PIN(24, "ISH_GPIO_8"),
814 PINCTRL_PIN(25, "ISH_GPIO_9"),
815 PINCTRL_PIN(26, "PCIE_CLKREQ0_B"),
816 PINCTRL_PIN(27, "PCIE_CLKREQ1_B"),
817 PINCTRL_PIN(28, "PCIE_CLKREQ2_B"),
818 PINCTRL_PIN(29, "PCIE_CLKREQ3_B"),
819 PINCTRL_PIN(30, "OSC_CLK_OUT_0"),
820 PINCTRL_PIN(31, "OSC_CLK_OUT_1"),
821 PINCTRL_PIN(32, "OSC_CLK_OUT_2"),
822 PINCTRL_PIN(33, "OSC_CLK_OUT_3"),
823 PINCTRL_PIN(34, "OSC_CLK_OUT_4"),
824 PINCTRL_PIN(35, "PMU_AC_PRESENT"),
825 PINCTRL_PIN(36, "PMU_BATLOW_B"),
826 PINCTRL_PIN(37, "PMU_PLTRST_B"),
827 PINCTRL_PIN(38, "PMU_PWRBTN_B"),
828 PINCTRL_PIN(39, "PMU_RESETBUTTON_B"),
829 PINCTRL_PIN(40, "PMU_SLP_S0_B"),
830 PINCTRL_PIN(41, "PMU_SLP_S3_B"),
831 PINCTRL_PIN(42, "PMU_SLP_S4_B"),
832 PINCTRL_PIN(43, "PMU_SUSCLK"),
833 PINCTRL_PIN(44, "PMU_WAKE_B"),
834 PINCTRL_PIN(45, "SUS_STAT_B"),
835 PINCTRL_PIN(46, "SUSPWRDNACK"),
836};
837
838static const unsigned apl_west_i2c0_pins[] = { 0, 1 };
839static const unsigned apl_west_i2c1_pins[] = { 2, 3 };
840static const unsigned apl_west_i2c2_pins[] = { 4, 5 };
841static const unsigned apl_west_i2c3_pins[] = { 6, 7 };
842static const unsigned apl_west_i2c4_pins[] = { 8, 9 };
843static const unsigned apl_west_i2c5_pins[] = { 10, 11 };
844static const unsigned apl_west_i2c6_pins[] = { 12, 13 };
845static const unsigned apl_west_i2c7_pins[] = { 14, 15 };
846static const unsigned apl_west_uart2_pins[] = { 20, 21, 22, 34 };
847
848static const struct intel_pingroup apl_west_groups[] = {
849 PIN_GROUP("i2c0_grp", apl_west_i2c0_pins, 1),
850 PIN_GROUP("i2c1_grp", apl_west_i2c1_pins, 1),
851 PIN_GROUP("i2c2_grp", apl_west_i2c2_pins, 1),
852 PIN_GROUP("i2c3_grp", apl_west_i2c3_pins, 1),
853 PIN_GROUP("i2c4_grp", apl_west_i2c4_pins, 1),
854 PIN_GROUP("i2c5_grp", apl_west_i2c5_pins, 1),
855 PIN_GROUP("i2c6_grp", apl_west_i2c6_pins, 1),
856 PIN_GROUP("i2c7_grp", apl_west_i2c7_pins, 1),
857 PIN_GROUP("uart2_grp", apl_west_uart2_pins, 3),
858};
859
860static const char * const apl_west_i2c0_groups[] = { "i2c0_grp" };
861static const char * const apl_west_i2c1_groups[] = { "i2c1_grp" };
862static const char * const apl_west_i2c2_groups[] = { "i2c2_grp" };
863static const char * const apl_west_i2c3_groups[] = { "i2c3_grp" };
864static const char * const apl_west_i2c4_groups[] = { "i2c4_grp" };
865static const char * const apl_west_i2c5_groups[] = { "i2c5_grp" };
866static const char * const apl_west_i2c6_groups[] = { "i2c6_grp" };
867static const char * const apl_west_i2c7_groups[] = { "i2c7_grp" };
868static const char * const apl_west_uart2_groups[] = { "uart2_grp" };
869
870static const struct intel_function apl_west_functions[] = {
871 FUNCTION("i2c0", apl_west_i2c0_groups),
872 FUNCTION("i2c1", apl_west_i2c1_groups),
873 FUNCTION("i2c2", apl_west_i2c2_groups),
874 FUNCTION("i2c3", apl_west_i2c3_groups),
875 FUNCTION("i2c4", apl_west_i2c4_groups),
876 FUNCTION("i2c5", apl_west_i2c5_groups),
877 FUNCTION("i2c6", apl_west_i2c6_groups),
878 FUNCTION("i2c7", apl_west_i2c7_groups),
879 FUNCTION("uart2", apl_west_uart2_groups),
880};
881
882static const struct intel_community apl_west_communities[] = {
883 BXT_COMMUNITY(0, 46),
884};
885
886static const struct intel_pinctrl_soc_data apl_west_soc_data = {
887 .uid = "3",
888 .pins = apl_west_pins,
889 .npins = ARRAY_SIZE(apl_west_pins),
890 .groups = apl_west_groups,
891 .ngroups = ARRAY_SIZE(apl_west_groups),
892 .functions = apl_west_functions,
893 .nfunctions = ARRAY_SIZE(apl_west_functions),
894 .communities = apl_west_communities,
895 .ncommunities = ARRAY_SIZE(apl_west_communities),
896};
897
898static const struct pinctrl_pin_desc apl_southwest_pins[] = {
899 PINCTRL_PIN(0, "PCIE_WAKE0_B"),
900 PINCTRL_PIN(1, "PCIE_WAKE1_B"),
901 PINCTRL_PIN(2, "PCIE_WAKE2_B"),
902 PINCTRL_PIN(3, "PCIE_WAKE3_B"),
903 PINCTRL_PIN(4, "EMMC0_CLK"),
904 PINCTRL_PIN(5, "EMMC0_D0"),
905 PINCTRL_PIN(6, "EMMC0_D1"),
906 PINCTRL_PIN(7, "EMMC0_D2"),
907 PINCTRL_PIN(8, "EMMC0_D3"),
908 PINCTRL_PIN(9, "EMMC0_D4"),
909 PINCTRL_PIN(10, "EMMC0_D5"),
910 PINCTRL_PIN(11, "EMMC0_D6"),
911 PINCTRL_PIN(12, "EMMC0_D7"),
912 PINCTRL_PIN(13, "EMMC0_CMD"),
913 PINCTRL_PIN(14, "SDIO_CLK"),
914 PINCTRL_PIN(15, "SDIO_D0"),
915 PINCTRL_PIN(16, "SDIO_D1"),
916 PINCTRL_PIN(17, "SDIO_D2"),
917 PINCTRL_PIN(18, "SDIO_D3"),
918 PINCTRL_PIN(19, "SDIO_CMD"),
919 PINCTRL_PIN(20, "SDCARD_CLK"),
920 PINCTRL_PIN(21, "SDCARD_CLK_FB"),
921 PINCTRL_PIN(22, "SDCARD_D0"),
922 PINCTRL_PIN(23, "SDCARD_D1"),
923 PINCTRL_PIN(24, "SDCARD_D2"),
924 PINCTRL_PIN(25, "SDCARD_D3"),
925 PINCTRL_PIN(26, "SDCARD_CD_B"),
926 PINCTRL_PIN(27, "SDCARD_CMD"),
927 PINCTRL_PIN(28, "SDCARD_LVL_WP"),
928 PINCTRL_PIN(29, "EMMC0_STROBE"),
929 PINCTRL_PIN(30, "SDIO_PWR_DOWN_B"),
930 PINCTRL_PIN(31, "SMB_ALERTB"),
931 PINCTRL_PIN(32, "SMB_CLK"),
932 PINCTRL_PIN(33, "SMB_DATA"),
933 PINCTRL_PIN(34, "LPC_ILB_SERIRQ"),
934 PINCTRL_PIN(35, "LPC_CLKOUT0"),
935 PINCTRL_PIN(36, "LPC_CLKOUT1"),
936 PINCTRL_PIN(37, "LPC_AD0"),
937 PINCTRL_PIN(38, "LPC_AD1"),
938 PINCTRL_PIN(39, "LPC_AD2"),
939 PINCTRL_PIN(40, "LPC_AD3"),
940 PINCTRL_PIN(41, "LPC_CLKRUNB"),
941 PINCTRL_PIN(42, "LPC_FRAMEB"),
942};
943
944static const unsigned apl_southwest_emmc0_pins[] = {
945 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 29,
946};
947static const unsigned apl_southwest_sdio_pins[] = {
948 14, 15, 16, 17, 18, 19, 30,
949};
950static const unsigned apl_southwest_sdcard_pins[] = {
951 20, 21, 22, 23, 24, 25, 26, 27, 28,
952};
953static const unsigned apl_southwest_i2c7_pins[] = { 32, 33 };
954
955static const struct intel_pingroup apl_southwest_groups[] = {
956 PIN_GROUP("emmc0_grp", apl_southwest_emmc0_pins, 1),
957 PIN_GROUP("sdio_grp", apl_southwest_sdio_pins, 1),
958 PIN_GROUP("sdcard_grp", apl_southwest_sdcard_pins, 1),
959 PIN_GROUP("i2c7_grp", apl_southwest_i2c7_pins, 2),
960};
961
962static const char * const apl_southwest_emmc0_groups[] = { "emmc0_grp" };
963static const char * const apl_southwest_sdio_groups[] = { "sdio_grp" };
964static const char * const apl_southwest_sdcard_groups[] = { "sdcard_grp" };
965static const char * const apl_southwest_i2c7_groups[] = { "i2c7_grp" };
966
967static const struct intel_function apl_southwest_functions[] = {
968 FUNCTION("emmc0", apl_southwest_emmc0_groups),
969 FUNCTION("sdio", apl_southwest_sdio_groups),
970 FUNCTION("sdcard", apl_southwest_sdcard_groups),
971 FUNCTION("i2c7", apl_southwest_i2c7_groups),
972};
973
974static const struct intel_community apl_southwest_communities[] = {
975 BXT_COMMUNITY(0, 42),
976};
977
978static const struct intel_pinctrl_soc_data apl_southwest_soc_data = {
979 .uid = "4",
980 .pins = apl_southwest_pins,
981 .npins = ARRAY_SIZE(apl_southwest_pins),
982 .groups = apl_southwest_groups,
983 .ngroups = ARRAY_SIZE(apl_southwest_groups),
984 .functions = apl_southwest_functions,
985 .nfunctions = ARRAY_SIZE(apl_southwest_functions),
986 .communities = apl_southwest_communities,
987 .ncommunities = ARRAY_SIZE(apl_southwest_communities),
988};
989
990static const struct intel_pinctrl_soc_data *apl_pinctrl_soc_data[] = {
991 &apl_north_soc_data,
992 &apl_northwest_soc_data,
993 &apl_west_soc_data,
994 &apl_southwest_soc_data,
995 NULL,
996};
997
998static const struct acpi_device_id bxt_pinctrl_acpi_match[] = {
999 { "INT3452", (kernel_ulong_t)apl_pinctrl_soc_data },
1000 { "INT34D1", (kernel_ulong_t)bxt_pinctrl_soc_data },
1001 { }
1002};
1003MODULE_DEVICE_TABLE(acpi, bxt_pinctrl_acpi_match);
1004
1005static int bxt_pinctrl_probe(struct platform_device *pdev)
1006{
1007 const struct intel_pinctrl_soc_data *soc_data = NULL;
1008 const struct intel_pinctrl_soc_data **soc_table;
1009 const struct acpi_device_id *id;
1010 struct acpi_device *adev;
1011 int i;
1012
1013 adev = ACPI_COMPANION(&pdev->dev);
1014 if (!adev)
1015 return -ENODEV;
1016
1017 id = acpi_match_device(bxt_pinctrl_acpi_match, &pdev->dev);
1018 if (!id)
1019 return -ENODEV;
1020
1021 soc_table = (const struct intel_pinctrl_soc_data **)id->driver_data;
1022
1023 for (i = 0; soc_table[i]; i++) {
1024 if (!strcmp(adev->pnp.unique_id, soc_table[i]->uid)) {
1025 soc_data = soc_table[i];
1026 break;
1027 }
1028 }
1029
1030 if (!soc_data)
1031 return -ENODEV;
1032
1033 return intel_pinctrl_probe(pdev, soc_data);
1034}
1035
1036static const struct dev_pm_ops bxt_pinctrl_pm_ops = {
1037 SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
1038 intel_pinctrl_resume)
1039};
1040
1041static struct platform_driver bxt_pinctrl_driver = {
1042 .probe = bxt_pinctrl_probe,
1043 .remove = intel_pinctrl_remove,
1044 .driver = {
1045 .name = "broxton-pinctrl",
1046 .acpi_match_table = bxt_pinctrl_acpi_match,
1047 .pm = &bxt_pinctrl_pm_ops,
1048 },
1049};
1050
1051static int __init bxt_pinctrl_init(void)
1052{
1053 return platform_driver_register(&bxt_pinctrl_driver);
1054}
1055subsys_initcall(bxt_pinctrl_init);
1056
1057static void __exit bxt_pinctrl_exit(void)
1058{
1059 platform_driver_unregister(&bxt_pinctrl_driver);
1060}
1061module_exit(bxt_pinctrl_exit);
1062
1063MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1064MODULE_DESCRIPTION("Intel Broxton SoC pinctrl/GPIO driver");
1065MODULE_LICENSE("GPL v2");
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-11 10:17:57 -0400