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authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>2016-09-08 05:30:22 -0400
committerStephen Boyd <sboyd@codeaurora.org>2016-09-14 14:28:04 -0400
commitece59749c3e4c0f75a114424e1e6059c4002b4a9 (patch)
tree436d96a782c09a087537239c2b37572f789894a1
parentfcff03813a7c612873303037cef5ba0329850c35 (diff)
ARM: clk-imx35: annotate clk enum with number values
This helps to decode error messages like: [ 0.000000] i.MX clk 82: register failed with -17 Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
-rw-r--r--drivers/clk/imx/clk-imx35.c30
1 files changed, 16 insertions, 14 deletions
diff --git a/drivers/clk/imx/clk-imx35.c b/drivers/clk/imx/clk-imx35.c
index d302ed3b8225..203cad6c9aab 100644
--- a/drivers/clk/imx/clk-imx35.c
+++ b/drivers/clk/imx/clk-imx35.c
@@ -66,20 +66,22 @@ static const char *std_sel[] = {"ppll", "arm"};
66static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"}; 66static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"};
67 67
68enum mx35_clks { 68enum mx35_clks {
69 ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg, 69 /* 0 */ ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb,
70 arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, esdhc_sel, 70 /* 9 */ ipg, arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div,
71 esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel, spdif_div_pre, 71 /* 15 */ esdhc_sel, esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel,
72 spdif_div_post, ssi_sel, ssi1_div_pre, ssi1_div_post, ssi2_div_pre, 72 /* 20 */ spdif_div_pre, spdif_div_post, ssi_sel, ssi1_div_pre,
73 ssi2_div_post, usb_sel, usb_div, nfc_div, asrc_gate, pata_gate, 73 /* 24 */ ssi1_div_post, ssi2_div_pre, ssi2_div_post, usb_sel, usb_div,
74 audmux_gate, can1_gate, can2_gate, cspi1_gate, cspi2_gate, ect_gate, 74 /* 29 */ nfc_div, asrc_gate, pata_gate, audmux_gate, can1_gate,
75 edio_gate, emi_gate, epit1_gate, epit2_gate, esai_gate, esdhc1_gate, 75 /* 34 */ can2_gate, cspi1_gate, cspi2_gate, ect_gate, edio_gate,
76 esdhc2_gate, esdhc3_gate, fec_gate, gpio1_gate, gpio2_gate, gpio3_gate, 76 /* 39 */ emi_gate, epit1_gate, epit2_gate, esai_gate, esdhc1_gate,
77 gpt_gate, i2c1_gate, i2c2_gate, i2c3_gate, iomuxc_gate, ipu_gate, 77 /* 44 */ esdhc2_gate, esdhc3_gate, fec_gate, gpio1_gate, gpio2_gate,
78 kpp_gate, mlb_gate, mshc_gate, owire_gate, pwm_gate, rngc_gate, 78 /* 49 */ gpio3_gate, gpt_gate, i2c1_gate, i2c2_gate, i2c3_gate,
79 rtc_gate, rtic_gate, scc_gate, sdma_gate, spba_gate, spdif_gate, 79 /* 54 */ iomuxc_gate, ipu_gate, kpp_gate, mlb_gate, mshc_gate,
80 ssi1_gate, ssi2_gate, uart1_gate, uart2_gate, uart3_gate, usbotg_gate, 80 /* 59 */ owire_gate, pwm_gate, rngc_gate, rtc_gate, rtic_gate, scc_gate,
81 wdog_gate, max_gate, admux_gate, csi_gate, csi_div, csi_sel, iim_gate, 81 /* 65 */ sdma_gate, spba_gate, spdif_gate, ssi1_gate, ssi2_gate,
82 gpu2d_gate, ckil, clk_max 82 /* 70 */ uart1_gate, uart2_gate, uart3_gate, usbotg_gate, wdog_gate,
83 /* 75 */ max_gate, admux_gate, csi_gate, csi_div, csi_sel, iim_gate,
84 /* 81 */ gpu2d_gate, ckil, clk_max
83}; 85};
84 86
85static struct clk *clk[clk_max]; 87static struct clk *clk[clk_max];