iommu: add ARM LPAE page table allocator

A number of IOMMUs found in ARM SoCs can walk architecture-compatible
page tables.

This patch adds a generic allocator for Stage-1 and Stage-2 v7/v8
long-descriptor page tables. 4k, 16k and 64k pages are supported, with
up to 4-levels of walk to cover a 48-bit address space.

Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

6 files changed, 817 insertions, 0 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index 3589d67437f8..00b27863384e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1589,6 +1589,7 @@ M:	Will Deacon <will.deacon@arm.com>
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:      Maintained
 F:      drivers/iommu/arm-smmu.c
+F:      drivers/iommu/io-pgtable-arm.c
 
 ARM64 PORT (AARCH64 ARCHITECTURE)
 M:      Catalin Marinas <catalin.marinas@arm.com>
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index 3faaa41db8ff..306454fbc52d 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -19,6 +19,15 @@ menu "Generic IOMMU Pagetable Support"
 config IOMMU_IO_PGTABLE
         bool
 
+config IOMMU_IO_PGTABLE_LPAE
+        bool "ARMv7/v8 Long Descriptor Format"
+        select IOMMU_IO_PGTABLE
+        help
+          Enable support for the ARM long descriptor pagetable format.
+          This allocator supports 4K/2M/1G, 16K/32M and 64K/512M page
+          sizes at both stage-1 and stage-2, as well as address spaces
+          up to 48-bits in size.
+
 endmenu
 
 config OF_IOMMU
diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile
index 701c9516e2ae..d6889b487d55 100644
--- a/drivers/iommu/Makefile
+++ b/drivers/iommu/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_IOMMU_API) += iommu.o
 obj-$(CONFIG_IOMMU_API) += iommu-traces.o
 obj-$(CONFIG_IOMMU_API) += iommu-sysfs.o
 obj-$(CONFIG_IOMMU_IO_PGTABLE) += io-pgtable.o
+obj-$(CONFIG_IOMMU_IO_PGTABLE_LPAE) += io-pgtable-arm.o
 obj-$(CONFIG_OF_IOMMU)  += of_iommu.o
 obj-$(CONFIG_MSM_IOMMU) += msm_iommu.o msm_iommu_dev.o
 obj-$(CONFIG_AMD_IOMMU) += amd_iommu.o amd_iommu_init.o
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
new file mode 100644
index 000000000000..dbe6178a53e9
--- /dev/null
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -0,0 +1,781 @@
+/*
+ * CPU-agnostic ARM page table allocator.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Copyright (C) 2014 ARM Limited
+ *
+ * Author: Will Deacon <will.deacon@arm.com>
+ */
+
+#define pr_fmt(fmt)     "arm-lpae io-pgtable: " fmt
+
+#include <linux/iommu.h>
+#include <linux/kernel.h>
+#include <linux/sizes.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+#include "io-pgtable.h"
+
+#define ARM_LPAE_MAX_ADDR_BITS          48
+#define ARM_LPAE_S2_MAX_CONCAT_PAGES    16
+#define ARM_LPAE_MAX_LEVELS             4
+
+/* Struct accessors */
+#define io_pgtable_to_data(x)                                           \
+        container_of((x), struct arm_lpae_io_pgtable, iop)
+
+#define io_pgtable_ops_to_pgtable(x)                                    \
+        container_of((x), struct io_pgtable, ops)
+
+#define io_pgtable_ops_to_data(x)                                       \
+        io_pgtable_to_data(io_pgtable_ops_to_pgtable(x))
+
+/*
+ * For consistency with the architecture, we always consider
+ * ARM_LPAE_MAX_LEVELS levels, with the walk starting at level n >=0
+ */
+#define ARM_LPAE_START_LVL(d)           (ARM_LPAE_MAX_LEVELS - (d)->levels)
+
+/*
+ * Calculate the right shift amount to get to the portion describing level l
+ * in a virtual address mapped by the pagetable in d.
+ */
+#define ARM_LPAE_LVL_SHIFT(l,d)                                         \
+        ((((d)->levels - ((l) - ARM_LPAE_START_LVL(d) + 1))             \
+          * (d)->bits_per_level) + (d)->pg_shift)
+
+#define ARM_LPAE_PAGES_PER_PGD(d)       ((d)->pgd_size >> (d)->pg_shift)
+
+/*
+ * Calculate the index at level l used to map virtual address a using the
+ * pagetable in d.
+ */
+#define ARM_LPAE_PGD_IDX(l,d)                                           \
+        ((l) == ARM_LPAE_START_LVL(d) ? ilog2(ARM_LPAE_PAGES_PER_PGD(d)) : 0)
+
+#define ARM_LPAE_LVL_IDX(a,l,d)                                         \
+        (((a) >> ARM_LPAE_LVL_SHIFT(l,d)) &                             \
+         ((1 << ((d)->bits_per_level + ARM_LPAE_PGD_IDX(l,d))) - 1))
+
+/* Calculate the block/page mapping size at level l for pagetable in d. */
+#define ARM_LPAE_BLOCK_SIZE(l,d)                                        \
+        (1 << (ilog2(sizeof(arm_lpae_iopte)) +                          \
+                ((ARM_LPAE_MAX_LEVELS - (l)) * (d)->bits_per_level)))
+
+/* Page table bits */
+#define ARM_LPAE_PTE_TYPE_SHIFT         0
+#define ARM_LPAE_PTE_TYPE_MASK          0x3
+
+#define ARM_LPAE_PTE_TYPE_BLOCK         1
+#define ARM_LPAE_PTE_TYPE_TABLE         3
+#define ARM_LPAE_PTE_TYPE_PAGE          3
+
+#define ARM_LPAE_PTE_XN                 (((arm_lpae_iopte)3) << 53)
+#define ARM_LPAE_PTE_AF                 (((arm_lpae_iopte)1) << 10)
+#define ARM_LPAE_PTE_SH_NS              (((arm_lpae_iopte)0) << 8)
+#define ARM_LPAE_PTE_SH_OS              (((arm_lpae_iopte)2) << 8)
+#define ARM_LPAE_PTE_SH_IS              (((arm_lpae_iopte)3) << 8)
+#define ARM_LPAE_PTE_VALID              (((arm_lpae_iopte)1) << 0)
+
+#define ARM_LPAE_PTE_ATTR_LO_MASK       (((arm_lpae_iopte)0x3ff) << 2)
+/* Ignore the contiguous bit for block splitting */
+#define ARM_LPAE_PTE_ATTR_HI_MASK       (((arm_lpae_iopte)6) << 52)
+#define ARM_LPAE_PTE_ATTR_MASK          (ARM_LPAE_PTE_ATTR_LO_MASK |    \
+                                         ARM_LPAE_PTE_ATTR_HI_MASK)
+
+/* Stage-1 PTE */
+#define ARM_LPAE_PTE_AP_UNPRIV          (((arm_lpae_iopte)1) << 6)
+#define ARM_LPAE_PTE_AP_RDONLY          (((arm_lpae_iopte)2) << 6)
+#define ARM_LPAE_PTE_ATTRINDX_SHIFT     2
+#define ARM_LPAE_PTE_nG                 (((arm_lpae_iopte)1) << 11)
+
+/* Stage-2 PTE */
+#define ARM_LPAE_PTE_HAP_FAULT          (((arm_lpae_iopte)0) << 6)
+#define ARM_LPAE_PTE_HAP_READ           (((arm_lpae_iopte)1) << 6)
+#define ARM_LPAE_PTE_HAP_WRITE          (((arm_lpae_iopte)2) << 6)
+#define ARM_LPAE_PTE_MEMATTR_OIWB       (((arm_lpae_iopte)0xf) << 2)
+#define ARM_LPAE_PTE_MEMATTR_NC         (((arm_lpae_iopte)0x5) << 2)
+#define ARM_LPAE_PTE_MEMATTR_DEV        (((arm_lpae_iopte)0x1) << 2)
+
+/* Register bits */
+#define ARM_32_LPAE_TCR_EAE             (1 << 31)
+#define ARM_64_LPAE_S2_TCR_RES1         (1 << 31)
+
+#define ARM_LPAE_TCR_TG0_4K             (0 << 14)
+#define ARM_LPAE_TCR_TG0_64K            (1 << 14)
+#define ARM_LPAE_TCR_TG0_16K            (2 << 14)
+
+#define ARM_LPAE_TCR_SH0_SHIFT          12
+#define ARM_LPAE_TCR_SH0_MASK           0x3
+#define ARM_LPAE_TCR_SH_NS              0
+#define ARM_LPAE_TCR_SH_OS              2
+#define ARM_LPAE_TCR_SH_IS              3
+
+#define ARM_LPAE_TCR_ORGN0_SHIFT        10
+#define ARM_LPAE_TCR_IRGN0_SHIFT        8
+#define ARM_LPAE_TCR_RGN_MASK           0x3
+#define ARM_LPAE_TCR_RGN_NC             0
+#define ARM_LPAE_TCR_RGN_WBWA           1
+#define ARM_LPAE_TCR_RGN_WT             2
+#define ARM_LPAE_TCR_RGN_WB             3
+
+#define ARM_LPAE_TCR_SL0_SHIFT          6
+#define ARM_LPAE_TCR_SL0_MASK           0x3
+
+#define ARM_LPAE_TCR_T0SZ_SHIFT         0
+#define ARM_LPAE_TCR_SZ_MASK            0xf
+
+#define ARM_LPAE_TCR_PS_SHIFT           16
+#define ARM_LPAE_TCR_PS_MASK            0x7
+
+#define ARM_LPAE_TCR_IPS_SHIFT          32
+#define ARM_LPAE_TCR_IPS_MASK           0x7
+
+#define ARM_LPAE_TCR_PS_32_BIT          0x0ULL
+#define ARM_LPAE_TCR_PS_36_BIT          0x1ULL
+#define ARM_LPAE_TCR_PS_40_BIT          0x2ULL
+#define ARM_LPAE_TCR_PS_42_BIT          0x3ULL
+#define ARM_LPAE_TCR_PS_44_BIT          0x4ULL
+#define ARM_LPAE_TCR_PS_48_BIT          0x5ULL
+
+#define ARM_LPAE_MAIR_ATTR_SHIFT(n)     ((n) << 3)
+#define ARM_LPAE_MAIR_ATTR_MASK         0xff
+#define ARM_LPAE_MAIR_ATTR_DEVICE