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authorAlexander Shiyan <shc_work@mail.ru>2016-08-06 00:56:25 -0400
committerShawn Guo <shawnguo@kernel.org>2016-08-09 10:47:26 -0400
commite1291cffcc509e790f46f1af6fec13eb8d44d5bb (patch)
tree13d12223291c14d0758223ddedc60cd72d48e50d
parentde2d6662ece073b1b02e94678f77c47646920f17 (diff)
ARM: i.MX: Remove i.MX1 non-DT support
This patch removes registration helpers and support files, used for non-DT i.MX1 targets. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat
-rw-r--r--arch/arm/mach-imx/Kconfig1
-rw-r--r--arch/arm/mach-imx/Makefile1
-rw-r--r--arch/arm/mach-imx/common.h5
-rw-r--r--arch/arm/mach-imx/devices-imx1.h30
-rw-r--r--arch/arm/mach-imx/devices/devices-common.h12
-rw-r--r--arch/arm/mach-imx/devices/platform-imx-fb.c5
-rw-r--r--arch/arm/mach-imx/devices/platform-imx-i2c.c5
-rw-r--r--arch/arm/mach-imx/devices/platform-imx-uart.c37
-rw-r--r--arch/arm/mach-imx/devices/platform-spi_imx.c9
-rw-r--r--arch/arm/mach-imx/hardware.h1
-rw-r--r--arch/arm/mach-imx/imx1-dt.c23
-rw-r--r--arch/arm/mach-imx/iomux-mx1.h155
-rw-r--r--arch/arm/mach-imx/mm-imx1.c67
-rw-r--r--arch/arm/mach-imx/mx1.h172
-rw-r--r--drivers/clk/imx/clk-imx1.c46
15 files changed, 26 insertions, 543 deletions
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 7aa8f814d226..ca7db3293a4f 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -67,7 +67,6 @@ config ARCH_MXC_IOMUX_V3
67config SOC_IMX1 67config SOC_IMX1
68 bool 68 bool
69 select CPU_ARM920T 69 select CPU_ARM920T
70 select IMX_HAVE_IOMUX_V1
71 select MXC_AVIC 70 select MXC_AVIC
72 select PINCTRL_IMX1 71 select PINCTRL_IMX1
73 72
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 5e33873d0160..3fa087d5edf1 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,6 +1,5 @@
1obj-y := cpu.o system.o irq-common.o 1obj-y := cpu.o system.o irq-common.o
2 2
3obj-$(CONFIG_SOC_IMX1) += mm-imx1.o
4obj-$(CONFIG_SOC_IMX21) += mm-imx21.o 3obj-$(CONFIG_SOC_IMX21) += mm-imx21.o
5 4
6obj-$(CONFIG_SOC_IMX25) += cpu-imx25.o mach-imx25.o pm-imx25.o 5obj-$(CONFIG_SOC_IMX25) += cpu-imx25.o mach-imx25.o pm-imx25.o
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index a8f469333027..bcca48138933 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -21,29 +21,24 @@ struct device_node;
21enum mxc_cpu_pwr_mode; 21enum mxc_cpu_pwr_mode;
22struct of_device_id; 22struct of_device_id;
23 23
24void mx1_map_io(void);
25void mx21_map_io(void); 24void mx21_map_io(void);
26void mx27_map_io(void); 25void mx27_map_io(void);
27void mx31_map_io(void); 26void mx31_map_io(void);
28void mx35_map_io(void); 27void mx35_map_io(void);
29void imx1_init_early(void);
30void imx21_init_early(void); 28void imx21_init_early(void);
31void imx27_init_early(void); 29void imx27_init_early(void);
32void imx31_init_early(void); 30void imx31_init_early(void);
33void imx35_init_early(void); 31void imx35_init_early(void);
34void mxc_init_irq(void __iomem *); 32void mxc_init_irq(void __iomem *);
35void mx1_init_irq(void);
36void mx21_init_irq(void); 33void mx21_init_irq(void);
37void mx27_init_irq(void); 34void mx27_init_irq(void);
38void mx31_init_irq(void); 35void mx31_init_irq(void);
39void mx35_init_irq(void); 36void mx35_init_irq(void);
40void imx1_soc_init(void);
41void imx21_soc_init(void); 37void imx21_soc_init(void);
42void imx27_soc_init(void); 38void imx27_soc_init(void);
43void imx31_soc_init(void); 39void imx31_soc_init(void);
44void imx35_soc_init(void); 40void imx35_soc_init(void);
45void epit_timer_init(void __iomem *base, int irq); 41void epit_timer_init(void __iomem *base, int irq);
46int mx1_clocks_init(unsigned long fref);
47int mx21_clocks_init(unsigned long lref, unsigned long fref); 42int mx21_clocks_init(unsigned long lref, unsigned long fref);
48int mx27_clocks_init(unsigned long fref); 43int mx27_clocks_init(unsigned long fref);
49int mx31_clocks_init(unsigned long fref); 44int mx31_clocks_init(unsigned long fref);
diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h
deleted file mode 100644
index f9b5afc6bcd1..000000000000
--- a/arch/arm/mach-imx/devices-imx1.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include "devices/devices-common.h"
10
11extern const struct imx_imx_fb_data imx1_imx_fb_data;
12#define imx1_add_imx_fb(pdata) \
13 imx_add_imx_fb(&imx1_imx_fb_data, pdata)
14
15extern const struct imx_imx_i2c_data imx1_imx_i2c_data;
16#define imx1_add_imx_i2c(pdata) \
17 imx_add_imx_i2c(&imx1_imx_i2c_data, pdata)
18
19extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[];
20#define imx1_add_imx_uart(id, pdata) \
21 imx_add_imx_uart_3irq(&imx1_imx_uart_data[id], pdata)
22#define imx1_add_imx_uart0(pdata) imx1_add_imx_uart(0, pdata)
23#define imx1_add_imx_uart1(pdata) imx1_add_imx_uart(1, pdata)
24
25extern const struct imx_spi_imx_data imx1_cspi_data[];
26#define imx1_add_cspi(id, pdata) \
27 imx_add_spi_imx(&imx1_cspi_data[id], pdata)
28
29#define imx1_add_spi_imx0(pdata) imx1_add_cspi(0, pdata)
30#define imx1_add_spi_imx1(pdata) imx1_add_cspi(1, pdata)
diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h
index 09cebd8cef2b..6920e356f4e5 100644
--- a/arch/arm/mach-imx/devices/devices-common.h
+++ b/arch/arm/mach-imx/devices/devices-common.h
@@ -154,18 +154,6 @@ struct platform_device *__init imx_add_imx_ssi(
154 const struct imx_ssi_platform_data *pdata); 154 const struct imx_ssi_platform_data *pdata);
155 155
156#include <linux/platform_data/serial-imx.h> 156#include <linux/platform_data/serial-imx.h>
157struct imx_imx_uart_3irq_data {
158 int id;
159 resource_size_t iobase;
160 resource_size_t iosize;
161 resource_size_t irqrx;
162 resource_size_t irqtx;
163 resource_size_t irqrts;
164};
165struct platform_device *__init imx_add_imx_uart_3irq(
166 const struct imx_imx_uart_3irq_data *data,
167 const struct imxuart_platform_data *pdata);
168
169struct imx_imx_uart_1irq_data { 157struct imx_imx_uart_1irq_data {
170 int id; 158 int id;
171 resource_size_t iobase; 159 resource_size_t iobase;
diff --git a/arch/arm/mach-imx/devices/platform-imx-fb.c b/arch/arm/mach-imx/devices/platform-imx-fb.c
index 7df6328306f9..aa00272252e0 100644
--- a/arch/arm/mach-imx/devices/platform-imx-fb.c
+++ b/arch/arm/mach-imx/devices/platform-imx-fb.c
@@ -19,11 +19,6 @@
19 .irq = soc ## _INT_LCDC, \ 19 .irq = soc ## _INT_LCDC, \
20 } 20 }
21 21
22#ifdef CONFIG_SOC_IMX1
23const struct imx_imx_fb_data imx1_imx_fb_data __initconst =
24 imx_imx_fb_data_entry_single(MX1, "imx1-fb", SZ_4K);
25#endif /* ifdef CONFIG_SOC_IMX1 */
26
27#ifdef CONFIG_SOC_IMX21 22#ifdef CONFIG_SOC_IMX21
28const struct imx_imx_fb_data imx21_imx_fb_data __initconst = 23const struct imx_imx_fb_data imx21_imx_fb_data __initconst =
29 imx_imx_fb_data_entry_single(MX21, "imx21-fb", SZ_4K); 24 imx_imx_fb_data_entry_single(MX21, "imx21-fb", SZ_4K);
diff --git a/arch/arm/mach-imx/devices/platform-imx-i2c.c b/arch/arm/mach-imx/devices/platform-imx-i2c.c
index ae9791522fc8..9822bedb5d09 100644
--- a/arch/arm/mach-imx/devices/platform-imx-i2c.c
+++ b/arch/arm/mach-imx/devices/platform-imx-i2c.c
@@ -21,11 +21,6 @@
21#define imx_imx_i2c_data_entry(soc, _devid, _id, _hwid, _size) \ 21#define imx_imx_i2c_data_entry(soc, _devid, _id, _hwid, _size) \
22 [_id] = imx_imx_i2c_data_entry_single(soc, _devid, _id, _hwid, _size) 22 [_id] = imx_imx_i2c_data_entry_single(soc, _devid, _id, _hwid, _size)
23 23
24#ifdef CONFIG_SOC_IMX1
25const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst =
26 imx_imx_i2c_data_entry_single(MX1, "imx1-i2c", 0, , SZ_4K);
27#endif /* ifdef CONFIG_SOC_IMX1 */
28
29#ifdef CONFIG_SOC_IMX21 24#ifdef CONFIG_SOC_IMX21
30const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst = 25const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst =
31 imx_imx_i2c_data_entry_single(MX21, "imx21-i2c", 0, , SZ_4K); 26 imx_imx_i2c_data_entry_single(MX21, "imx21-i2c", 0, , SZ_4K);
diff --git a/arch/arm/mach-imx/devices/platform-imx-uart.c b/arch/arm/mach-imx/devices/platform-imx-uart.c
index 6962cff4a950..e3c89e9caf93 100644
--- a/arch/arm/mach-imx/devices/platform-imx-uart.c
+++ b/arch/arm/mach-imx/devices/platform-imx-uart.c
@@ -27,15 +27,6 @@
27 .irq = soc ## _INT_UART ## _hwid, \ 27 .irq = soc ## _INT_UART ## _hwid, \
28 } 28 }
29 29
30#ifdef CONFIG_SOC_IMX1
31const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst = {
32#define imx1_imx_uart_data_entry(_id, _hwid) \
33 imx_imx_uart_3irq_data_entry(MX1, _id, _hwid, 0xd0)
34 imx1_imx_uart_data_entry(0, 1),
35 imx1_imx_uart_data_entry(1, 2),
36};
37#endif /* ifdef CONFIG_SOC_IMX1 */
38
39#ifdef CONFIG_SOC_IMX21 30#ifdef CONFIG_SOC_IMX21
40const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = { 31const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = {
41#define imx21_imx_uart_data_entry(_id, _hwid) \ 32#define imx21_imx_uart_data_entry(_id, _hwid) \
@@ -82,34 +73,6 @@ const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
82}; 73};
83#endif /* ifdef CONFIG_SOC_IMX35 */ 74#endif /* ifdef CONFIG_SOC_IMX35 */
84 75
85struct platform_device *__init imx_add_imx_uart_3irq(
86 const struct imx_imx_uart_3irq_data *data,
87 const struct imxuart_platform_data *pdata)
88{
89 struct resource res[] = {
90 {
91 .start = data->iobase,
92 .end = data->iobase + data->iosize - 1,
93 .flags = IORESOURCE_MEM,
94 }, {
95 .start = data->irqrx,
96 .end = data->irqrx,
97 .flags = IORESOURCE_IRQ,
98 }, {
99 .start = data->irqtx,
100 .end = data->irqtx,
101 .flags = IORESOURCE_IRQ,
102 }, {
103 .start = data->irqrts,
104 .end = data->irqrx,
105 .flags = IORESOURCE_IRQ,
106 },
107 };
108
109 return imx_add_platform_device("imx1-uart", data->id, res,
110 ARRAY_SIZE(res), pdata, sizeof(*pdata));
111}
112
113struct platform_device *__init imx_add_imx_uart_1irq( 76struct platform_device *__init imx_add_imx_uart_1irq(
114 const struct imx_imx_uart_1irq_data *data, 77 const struct imx_imx_uart_1irq_data *data,
115 const struct imxuart_platform_data *pdata) 78 const struct imxuart_platform_data *pdata)
diff --git a/arch/arm/mach-imx/devices/platform-spi_imx.c b/arch/arm/mach-imx/devices/platform-spi_imx.c
index 5e9707b47f92..d93c446c9c02 100644
--- a/arch/arm/mach-imx/devices/platform-spi_imx.c
+++ b/arch/arm/mach-imx/devices/platform-spi_imx.c
@@ -21,15 +21,6 @@
21#define imx_spi_imx_data_entry(soc, type, devid, id, hwid, size) \ 21#define imx_spi_imx_data_entry(soc, type, devid, id, hwid, size) \
22 [id] = imx_spi_imx_data_entry_single(soc, type, devid, id, hwid, size) 22 [id] = imx_spi_imx_data_entry_single(soc, type, devid, id, hwid, size)
23 23
24#ifdef CONFIG_SOC_IMX1
25const struct imx_spi_imx_data imx1_cspi_data[] __initconst = {
26#define imx1_cspi_data_entry(_id, _hwid) \
27 imx_spi_imx_data_entry(MX1, CSPI, "imx1-cspi", _id, _hwid, SZ_4K)
28 imx1_cspi_data_entry(0, 1),
29 imx1_cspi_data_entry(1, 2),
30};
31#endif
32
33#ifdef CONFIG_SOC_IMX21 24#ifdef CONFIG_SOC_IMX21
34const struct imx_spi_imx_data imx21_cspi_data[] __initconst = { 25const struct imx_spi_imx_data imx21_cspi_data[] __initconst = {
35#define imx21_cspi_data_entry(_id, _hwid) \ 26#define imx21_cspi_data_entry(_id, _hwid) \
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
index d737f95ebb07..a42a6dfcbd6a 100644
--- a/arch/arm/mach-imx/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -112,7 +112,6 @@
112#include "mx2x.h" 112#include "mx2x.h"
113#include "mx21.h" 113#include "mx21.h"
114#include "mx27.h" 114#include "mx27.h"
115#include "mx1.h"
116 115
117#define imx_map_entry(soc, name, _type) { \ 116#define imx_map_entry(soc, name, _type) { \
118 .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ 117 .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
diff --git a/arch/arm/mach-imx/imx1-dt.c b/arch/arm/mach-imx/imx1-dt.c
index 6f915b0961c4..de5ab8d88549 100644
--- a/arch/arm/mach-imx/imx1-dt.c
+++ b/arch/arm/mach-imx/imx1-dt.c
@@ -9,8 +9,27 @@
9 9
10#include <linux/of_platform.h> 10#include <linux/of_platform.h>
11#include <asm/mach/arch.h> 11#include <asm/mach/arch.h>
12#include <asm/mach/map.h>
12 13
13#include "common.h" 14#include "common.h"
15#include "hardware.h"
16
17#define MX1_AVIC_ADDR 0x00223000
18
19static void __init imx1_init_early(void)
20{
21 mxc_set_cpu_type(MXC_CPU_MX1);
22}
23
24static void __init imx1_init_irq(void)
25{
26 void __iomem *avic_addr;
27
28 avic_addr = ioremap(MX1_AVIC_ADDR, SZ_4K);
29 WARN_ON(!avic_addr);
30
31 mxc_init_irq(avic_addr);
32}
14 33
15static const char * const imx1_dt_board_compat[] __initconst = { 34static const char * const imx1_dt_board_compat[] __initconst = {
16 "fsl,imx1", 35 "fsl,imx1",
@@ -18,9 +37,9 @@ static const char * const imx1_dt_board_compat[] __initconst = {
18}; 37};
19 38
20DT_MACHINE_START(IMX1_DT, "Freescale i.MX1 (Device Tree Support)") 39DT_MACHINE_START(IMX1_DT, "Freescale i.MX1 (Device Tree Support)")
21 .map_io = mx1_map_io, 40 .map_io = debug_ll_io_init,
22 .init_early = imx1_init_early, 41 .init_early = imx1_init_early,
23 .init_irq = mx1_init_irq, 42 .init_irq = imx1_init_irq,
24 .dt_compat = imx1_dt_board_compat, 43 .dt_compat = imx1_dt_board_compat,
25 .restart = mxc_restart, 44 .restart = mxc_restart,
26MACHINE_END 45MACHINE_END
diff --git a/arch/arm/mach-imx/iomux-mx1.h b/arch/arm/mach-imx/iomux-mx1.h
deleted file mode 100644
index 95f4681d85d7..000000000000
--- a/arch/arm/mach-imx/iomux-mx1.h
+++ /dev/null
@@ -1,155 +0,0 @@
1/*
2 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18#ifndef __MACH_IOMUX_MX1_H__
19#define __MACH_IOMUX_MX1_H__
20
21#include "iomux-v1.h"
22
23#define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0)
24#define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0)
25#define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 1)
26#define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1)
27#define PA2_PF_PWM0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 2)
28#define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3)
29#define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4)
30#define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5)
31#define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6)
32#define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7)
33#define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8)
34#define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9)
35#define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10)
36#define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11)
37#define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12)
38#define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13)
39#define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14)
40#define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15)
41#define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16)
42#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17)
43#define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17)
44#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18)
45#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19)
46#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20)
47#define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21)
48#define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22)
49#define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23)
50#define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24)
51#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24)
52#define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25)
53#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25)
54#define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26)
55#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26)
56#define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27)
57#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27)
58#define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28)
59#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28)
60#define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29)
61#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29)
62#define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30)
63#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30)
64#define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31)
65#define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31)
66#define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8)
67#define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8)
68#define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9)
69#define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9)
70#define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10)
71#define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10)
72#define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11)
73#define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11)
74#define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12)
75#define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12)
76#define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13)
77#define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13)
78#define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14)
79#define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15)
80#define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_AF | GPIO_IN | 16)
81#define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_AF | GPIO_OUT | 17)
82#define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18)
83#define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19)
84#define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20)
85#define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21)
86#define PB22_PF_USBD_RCV (GPIO_PORTB | GPIO_PF | 22)
87#define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23)
88#define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24)
89#define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25)
90#define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26)
91#define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27)
92#define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_PF | GPIO_OUT | 28)
93#define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_PF | GPIO_IN | 29)
94#define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_PF | GPIO_OUT | 30)
95#define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_PF | GPIO_IN | 31)
96#define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3)
97#define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4)
98#define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_PF | GPIO_IN | 5)
99#define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_PF | GPIO_OUT | 6)
100#define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7)
101#define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8)
102#define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9)
103#define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_PF | GPIO_IN | 10)
104#define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11)
105#define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 12)
106#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13)
107#define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14)
108#define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15)
109#define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16)
110#define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17)
111#define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 24)
112#define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 25)
113#define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 26)
114#define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 27)
115#define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 28)
116#define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 29)
117#define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30)
118#define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 31)
119#define PD6_PF_LSCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 6)
120#define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7)
121#define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_AF | GPIO_IN | 7)
122#define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7)
123#define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8)
124#define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_AF | GPIO_OUT | 8)
125#define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8)
126#define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9)
127#define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_AF | GPIO_OUT | 9)
128#define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 9)
129#define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_PF | GPIO_OUT | 10)
130#define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_AF | GPIO_OUT | 10)
131#define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 10)
132#define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_PF | GPIO_OUT | 11)
133#define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_PF | GPIO_OUT | 12)
134#define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 13)
135#define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 14)
136#define PD15_PF_LD0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 15)
137#define PD16_PF_LD1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 16)
138#define PD17_PF_LD2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17)
139#define PD18_PF_LD3 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18)
140#define PD19_PF_LD4 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19)
141#define PD20_PF_LD5 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20)
142#define PD21_PF_LD6 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21)
143#define PD22_PF_LD7 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22)
144#define PD23_PF_LD8 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 23)
145#define PD24_PF_LD9 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24)
146#define PD25_PF_LD10 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25)
147#define PD26_PF_LD11 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26)
148#define PD27_PF_LD12 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27)
149#define PD28_PF_LD13 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28)
150#define PD29_PF_LD14 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29)
151#define PD30_PF_LD15 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 30)
152#define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31)
153#define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31)
154
155#endif /* ifndef __MACH_IOMUX_MX1_H__ */
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
deleted file mode 100644
index 9a42f19be81e..000000000000
--- a/arch/arm/mach-imx/mm-imx1.c
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * author: Sascha Hauer
3 * Created: april 20th, 2004
4 * Copyright: Synertronixx GmbH
5 *
6 * Common code for i.MX1 machines
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/io.h>
21#include <linux/pinctrl/machine.h>
22
23#include <asm/mach/map.h>
24
25#include "common.h"
26#include "devices/devices-common.h"
27#include "hardware.h"
28#include "iomux-v1.h"
29
30static struct map_desc imx_io_desc[] __initdata = {
31 imx_map_entry(MX1, IO, MT_DEVICE),
32};
33
34void __init mx1_map_io(void)
35{
36 iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
37}
38
39void __init imx1_init_early(void)
40{
41 mxc_set_cpu_type(MXC_CPU_MX1);
42 imx_iomuxv1_init(MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
43 MX1_NUM_GPIO_PORT);
44}
45
46void __init mx1_init_irq(void)
47{
48 mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR));
49}
50
51void __init imx1_soc_init(void)
52{
53 imx1_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
54 mxc_device_init();
55
56 mxc_register_gpio("imx1-gpio", 0, MX1_GPIO1_BASE_ADDR, SZ_256,
57 MX1_GPIO_INT_PORTA, 0);
58 mxc_register_gpio("imx1-gpio", 1, MX1_GPIO2_BASE_ADDR, SZ_256,
59 MX1_GPIO_INT_PORTB, 0);
60 mxc_register_gpio("imx1-gpio", 2, MX1_GPIO3_BASE_ADDR, SZ_256,
61 MX1_GPIO_INT_PORTC, 0);
62 mxc_register_gpio("imx1-gpio", 3, MX1_GPIO4_BASE_ADDR, SZ_256,
63 MX1_GPIO_INT_PORTD, 0);
64 imx_add_imx_dma("imx1-dma", MX1_DMA_BASE_ADDR,
65 MX1_DMA_INT, MX1_DMA_ERR);
66 pinctrl_provide_dummies();
67}
diff --git a/arch/arm/mach-imx/mx1.h b/arch/arm/mach-imx/mx1.h
deleted file mode 100644
index 45bd31cc34d6..000000000000
--- a/arch/arm/mach-imx/mx1.h
+++ /dev/null
@@ -1,172 +0,0 @@
1/*
2 * Copyright (C) 1997,1998 Russell King
3 * Copyright (C) 1999 ARM Limited
4 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __MACH_MX1_H__
13#define __MACH_MX1_H__
14
15/*
16 * Memory map
17 */
18#define MX1_IO_BASE_ADDR 0x00200000
19#define MX1_IO_SIZE SZ_1M
20
21#define MX1_CS0_PHYS 0x10000000
22#define MX1_CS0_SIZE 0x02000000
23
24#define MX1_CS1_PHYS 0x12000000
25#define MX1_CS1_SIZE 0x01000000
26
27#define MX1_CS2_PHYS 0x13000000
28#define MX1_CS2_SIZE 0x01000000
29
30#define MX1_CS3_PHYS 0x14000000
31#define MX1_CS3_SIZE 0x01000000
32
33#define MX1_CS4_PHYS 0x15000000
34#define MX1_CS4_SIZE 0x01000000
35
36#define MX1_CS5_PHYS 0x16000000
37#define MX1_CS5_SIZE 0x01000000
38
39/*
40 * Register BASEs, based on OFFSETs
41 */
42#define MX1_AIPI1_BASE_ADDR (0x00000 + MX1_IO_BASE_ADDR)
43#define MX1_WDT_BASE_ADDR (0x01000 + MX1_IO_BASE_ADDR)
44#define MX1_TIM1_BASE_ADDR (0x02000 + MX1_IO_BASE_ADDR)
45#define MX1_TIM2_BASE_ADDR (0x03000 + MX1_IO_BASE_ADDR)
46#define MX1_RTC_BASE_ADDR (0x04000 + MX1_IO_BASE_ADDR)
47#define MX1_LCDC_BASE_ADDR (0x05000 + MX1_IO_BASE_ADDR)
48#define MX1_UART1_BASE_ADDR (0x06000 + MX1_IO_BASE_ADDR)
49#define MX1_UART2_BASE_ADDR (0x07000 + MX1_IO_BASE_ADDR)
50#define MX1_PWM_BASE_ADDR (0x08000 + MX1_IO_BASE_ADDR)
51#define MX1_DMA_BASE_ADDR (0x09000 + MX1_IO_BASE_ADDR)
52#define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR)
53#define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR)
54#define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR)
55#define MX1_CSPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR)
56#define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR)
57#define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR)
58#define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR)
59#define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR)
60#define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR)
61#define MX1_CSPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR)
62#define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR)
63#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR)
64#define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR)
65#define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
66#define MX1_GPIO1_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
67#define MX1_GPIO2_BASE_ADDR (0x1C100 + MX1_IO_BASE_ADDR)
68#define MX1_GPIO3_BASE_ADDR (0x1C200 + MX1_IO_BASE_ADDR)
69#define MX1_GPIO4_BASE_ADDR (0x1C300 + MX1_IO_BASE_ADDR)
70#define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR)
71#define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR)
72#define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR)
73#define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR)
74#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR)
75
76/* macro to get at IO space when running virtually */
77#define MX1_IO_P2V(x) IMX_IO_P2V(x)
78#define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x))
79
80/* fixed interrput numbers */
81#include <asm/irq.h>
82#define MX1_INT_SOFTINT (NR_IRQS_LEGACY + 0)
83#define MX1_INT_CSI (NR_IRQS_LEGACY + 6)
84#define MX1_DSPA_MAC_INT (NR_IRQS_LEGACY + 7)
85#define MX1_DSPA_INT (NR_IRQS_LEGACY + 8)
86#define MX1_COMP_INT (NR_IRQS_LEGACY + 9)
87#define MX1_MSHC_XINT (NR_IRQS_LEGACY + 10)
88#define MX1_GPIO_INT_PORTA (NR_IRQS_LEGACY + 11)
89#define MX1_GPIO_INT_PORTB (NR_IRQS_LEGACY + 12)
90#define MX1_GPIO_INT_PORTC (NR_IRQS_LEGACY + 13)
91#define MX1_INT_LCDC (NR_IRQS_LEGACY + 14)
92#define MX1_SIM_INT (NR_IRQS_LEGACY + 15)
93#define MX1_SIM_DATA_INT (NR_IRQS_LEGACY + 16)
94#define MX1_RTC_INT (NR_IRQS_LEGACY + 17)
95#define MX1_RTC_SAMINT (NR_IRQS_LEGACY + 18)
96#define MX1_INT_UART2PFERR (NR_IRQS_LEGACY + 19)
97#define MX1_INT_UART2RTS (NR_IRQS_LEGACY + 20)
98#define MX1_INT_UART2DTR (NR_IRQS_LEGACY + 21)
99#define MX1_INT_UART2UARTC (NR_IRQS_LEGACY + 22)
100#define MX1_INT_UART2TX (NR_IRQS_LEGACY + 23)
101#define MX1_INT_UART2RX (NR_IRQS_LEGACY + 24)
102#define MX1_INT_UART1PFERR (NR_IRQS_LEGACY + 25)
103#define MX1_INT_UART1RTS (NR_IRQS_LEGACY + 26)
104#define MX1_INT_UART1DTR (NR_IRQS_LEGACY + 27)
105#define MX1_INT_UART1UARTC (NR_IRQS_LEGACY + 28)
106#define MX1_INT_UART1TX (NR_IRQS_LEGACY + 29)
107#define MX1_INT_UART1RX (NR_IRQS_LEGACY + 30)
108#define MX1_VOICE_DAC_INT (NR_IRQS_LEGACY + 31)
109#define MX1_VOICE_ADC_INT (NR_IRQS_LEGACY + 32)
110#define MX1_PEN_DATA_INT (NR_IRQS_LEGACY + 33)
111#define MX1_PWM_INT (NR_IRQS_LEGACY + 34)
112#define MX1_SDHC_INT (NR_IRQS_LEGACY + 35)
113#define MX1_INT_I2C (NR_IRQS_LEGACY + 39)
114#define MX1_INT_CSPI2 (NR_IRQS_LEGACY + 40)
115#define MX1_INT_CSPI1 (NR_IRQS_LEGACY + 41)
116#define MX1_SSI_TX_INT (NR_IRQS_LEGACY + 42)
117#define MX1_SSI_TX_ERR_INT (NR_IRQS_LEGACY + 43)
118#define MX1_SSI_RX_INT (NR_IRQS_LEGACY + 44)
119#define MX1_SSI_RX_ERR_INT (NR_IRQS_LEGACY + 45)
120#define MX1_TOUCH_INT (NR_IRQS_LEGACY + 46)
121#define MX1_INT_USBD0 (NR_IRQS_LEGACY + 47)
122#define MX1_INT_USBD1 (NR_IRQS_LEGACY + 48)
123#define MX1_INT_USBD2 (NR_IRQS_LEGACY + 49)
124#define MX1_INT_USBD3 (NR_IRQS_LEGACY + 50)
125#define MX1_INT_USBD4 (NR_IRQS_LEGACY + 51)
126#define MX1_INT_USBD5 (NR_IRQS_LEGACY + 52)
127#define MX1_INT_USBD6 (NR_IRQS_LEGACY + 53)
128#define MX1_BTSYS_INT (NR_IRQS_LEGACY + 55)
129#define MX1_BTTIM_INT (NR_IRQS_LEGACY + 56)
130#define MX1_BTWUI_INT (NR_IRQS_LEGACY + 57)
131#define MX1_TIM2_INT (NR_IRQS_LEGACY + 58)
132#define MX1_TIM1_INT (NR_IRQS_LEGACY + 59)
133#define MX1_DMA_ERR (NR_IRQS_LEGACY + 60)
134#define MX1_DMA_INT (NR_IRQS_LEGACY + 61)
135#define MX1_GPIO_INT_PORTD (NR_IRQS_LEGACY + 62)
136#define MX1_WDT_INT (NR_IRQS_LEGACY + 63)
137
138/* DMA */
139#define MX1_DMA_REQ_UART3_T 2
140#define MX1_DMA_REQ_UART3_R 3
141#define MX1_DMA_REQ_SSI2_T 4
142#define MX1_DMA_REQ_SSI2_R 5
143#define MX1_DMA_REQ_CSI_STAT 6
144#define MX1_DMA_REQ_CSI_R 7
145#define MX1_DMA_REQ_MSHC 8
146#define MX1_DMA_REQ_DSPA_DCT_DOUT 9
147#define MX1_DMA_REQ_DSPA_DCT_DIN 10
148#define MX1_DMA_REQ_DSPA_MAC 11
149#define MX1_DMA_REQ_EXT 12
150#define MX1_DMA_REQ_SDHC 13
151#define MX1_DMA_REQ_SPI1_R 14
152#define MX1_DMA_REQ_SPI1_T 15
153#define MX1_DMA_REQ_SSI_T 16
154#define MX1_DMA_REQ_SSI_R 17
155#define MX1_DMA_REQ_ASP_DAC 18
156#define MX1_DMA_REQ_ASP_ADC 19
157#define MX1_DMA_REQ_USP_EP(x) (20 + (x))
158#define MX1_DMA_REQ_SPI2_R 26
159#define MX1_DMA_REQ_SPI2_T 27
160#define MX1_DMA_REQ_UART2_T 28
161#define MX1_DMA_REQ_UART2_R 29
162#define MX1_DMA_REQ_UART1_T 30
163#define MX1_DMA_REQ_UART1_R 31
164
165/*
166 * This doesn't depend on IMX_NEEDS_DEPRECATED_SYMBOLS
167 * to not break drivers/usb/gadget/imx_udc. Should go
168 * away after this driver uses the new name.
169 */
170#define USBD_INT0 MX1_INT_USBD0
171
172#endif /* ifndef __MACH_MX1_H__ */
diff --git a/drivers/clk/imx/clk-imx1.c b/drivers/clk/imx/clk-imx1.c
index 99cf802fa51f..eaa462ad09e8 100644
--- a/drivers/clk/imx/clk-imx1.c
+++ b/drivers/clk/imx/clk-imx1.c
@@ -45,10 +45,13 @@ static void __iomem *ccm __initdata;
45#define CCM_PCDR (ccm + 0x0020) 45#define CCM_PCDR (ccm + 0x0020)
46#define SCM_GCCR (ccm + 0x0810) 46#define SCM_GCCR (ccm + 0x0810)
47 47
48static void __init _mx1_clocks_init(unsigned long fref) 48static void __init mx1_clocks_init_dt(struct device_node *np)
49{ 49{
50 ccm = of_iomap(np, 0);
51 BUG_ON(!ccm);
52
50 clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0); 53 clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
51 clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", fref); 54 clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", 32768);
52 clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000); 55 clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000);
53 clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17); 56 clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);
54 clk[IMX1_CLK_CLK32_PREMULT] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1); 57 clk[IMX1_CLK_CLK32_PREMULT] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
@@ -74,45 +77,6 @@ static void __init _mx1_clocks_init(unsigned long fref)
74 clk[IMX1_CLK_USBD_GATE] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0); 77 clk[IMX1_CLK_USBD_GATE] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
75 78
76 imx_check_clocks(clk, ARRAY_SIZE(clk)); 79 imx_check_clocks(clk, ARRAY_SIZE(clk));
77}
78
79int __init mx1_clocks_init(unsigned long fref)
80{
81 ccm = ioremap(MX1_CCM_BASE_ADDR, SZ_4K);
82 BUG_ON(!ccm);
83
84 _mx1_clocks_init(fref);
85
86 clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx-gpt.0");
87 clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx-gpt.0");
88 clk_register_clkdev(clk[IMX1_CLK_DMA_GATE], "ahb", "imx1-dma");
89 clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-dma");
90 clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.0");
91 clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.0");
92 clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.1");
93 clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.1");
94 clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.2");
95 clk_register_clkdev(clk[IMX1_CLK_UART3_GATE], "ipg", "imx1-uart.2");
96 clk_register_clkdev(clk[IMX1_CLK_HCLK], NULL, "imx1-i2c.0");
97 clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.0");
98 clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.0");
99 clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.1");
100 clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.1");
101 clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-fb.0");
102 clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-fb.0");
103 clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ahb", "imx1-fb.0");
104
105 mxc_timer_init(MX1_TIM1_BASE_ADDR, MX1_TIM1_INT, GPT_TYPE_IMX1);
106
107 return 0;
108}
109
110static void __init mx1_clocks_init_dt(struct device_node *np)
111{
112 ccm = of_iomap(np, 0);
113 BUG_ON(!ccm);
114
115 _mx1_clocks_init(32768);
116 80
117 clk_data.clks = clk; 81 clk_data.clks = clk;
118 clk_data.clk_num = ARRAY_SIZE(clk); 82 clk_data.clk_num = ARRAY_SIZE(clk);
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-11 17:06:37 -0400