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authorMike Turquette <mturquette@linaro.org>2014-05-23 17:30:35 -0400
committerMike Turquette <mturquette@linaro.org>2014-05-23 17:30:35 -0400
commitdedca6abaf42fb596645e60a20f677a6a4692c22 (patch)
tree0498ed626ed7f6ae056b6fc8d4b75afc06cbbc17
parent4b660a7f5c8099d88d1a43d8ae138965112592c7 (diff)
parentfb8abb7aefe8454e3b478ef11da78ea25b891ad4 (diff)
Merge remote-tracking branch 'linaro/clk-next' into clk-next
Diffstat
-rw-r--r--Documentation/clk.txt16
-rw-r--r--Documentation/devicetree/bindings/clock/bcm-kona-clock.txt116
-rw-r--r--Documentation/devicetree/bindings/clock/clock-bindings.txt9
-rw-r--r--Documentation/devicetree/bindings/clock/fixed-clock.txt1
-rw-r--r--Documentation/devicetree/bindings/clock/hix5hd2-clock.txt31
-rw-r--r--Documentation/devicetree/bindings/clock/lsi,axm5516-clks.txt29
-rw-r--r--Documentation/devicetree/bindings/clock/mvebu-core-clock.txt8
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc.txt1
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt1
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt41
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt27
-rw-r--r--arch/arm/boot/dts/bcm21664.dtsi164
-rw-r--r--drivers/clk/Makefile2
-rw-r--r--drivers/clk/bcm/Kconfig2
-rw-r--r--drivers/clk/bcm/Makefile1
-rw-r--r--drivers/clk/bcm/clk-bcm21664.c290
-rw-r--r--drivers/clk/bcm/clk-bcm281xx.c231
-rw-r--r--drivers/clk/bcm/clk-kona-setup.c229
-rw-r--r--drivers/clk/bcm/clk-kona.c212
-rw-r--r--drivers/clk/bcm/clk-kona.h160
-rw-r--r--drivers/clk/clk-axm5516.c615
-rw-r--r--drivers/clk/clk-divider.c93
-rw-r--r--drivers/clk/clk-si570.c2
-rw-r--r--drivers/clk/clk.c46
-rw-r--r--drivers/clk/clk.h1
-rw-r--r--drivers/clk/clkdev.c34
-rw-r--r--drivers/clk/hisilicon/Makefile1
-rw-r--r--drivers/clk/hisilicon/clk-hix5hd2.c101
-rw-r--r--drivers/clk/hisilicon/clk.c41
-rw-r--r--drivers/clk/hisilicon/clk.h3
-rw-r--r--drivers/clk/mvebu/Kconfig4
-rw-r--r--drivers/clk/mvebu/Makefile1
-rw-r--r--drivers/clk/mvebu/orion.c210
-rw-r--r--drivers/clk/qcom/Kconfig4
-rw-r--r--drivers/clk/qcom/Makefile1
-rw-r--r--drivers/clk/qcom/common.c99
-rw-r--r--drivers/clk/qcom/common.h34
-rw-r--r--drivers/clk/qcom/gcc-msm8660.c77
-rw-r--r--drivers/clk/qcom/gcc-msm8960.c109
-rw-r--r--drivers/clk/qcom/gcc-msm8974.c77
-rw-r--r--drivers/clk/qcom/mmcc-msm8960.c78
-rw-r--r--drivers/clk/qcom/mmcc-msm8974.c80
-rw-r--r--drivers/clk/shmobile/Makefile2
-rw-r--r--drivers/clk/shmobile/clk-mstp.c2
-rw-r--r--drivers/clk/shmobile/clk-r8a7740.c199
-rw-r--r--drivers/clk/shmobile/clk-r8a7779.c180
-rw-r--r--drivers/clk/socfpga/clk-gate.c1
-rw-r--r--drivers/clk/socfpga/clk-periph.c22
-rw-r--r--drivers/clk/socfpga/clk.h4
-rw-r--r--drivers/clk/sunxi/clk-factors.c36
-rw-r--r--drivers/clk/sunxi/clk-sunxi.c37
-rw-r--r--drivers/clk/tegra/clk-id.h1
-rw-r--r--drivers/clk/tegra/clk-pll.c33
-rw-r--r--drivers/clk/tegra/clk-tegra-periph.c10
-rw-r--r--drivers/clk/tegra/clk-tegra114.c22
-rw-r--r--drivers/clk/tegra/clk-tegra124.c21
-rw-r--r--drivers/clk/versatile/clk-icst.c1
-rw-r--r--drivers/clk/versatile/clk-impd1.c38
-rw-r--r--drivers/clk/zynq/clkc.c12
-rw-r--r--include/dt-bindings/clock/bcm21664.h62
-rw-r--r--include/dt-bindings/clock/bcm281xx.h12
-rw-r--r--include/dt-bindings/clock/hix5hd2-clock.h58
-rw-r--r--include/dt-bindings/clock/qcom,gcc-msm8960.h7
-rw-r--r--include/dt-bindings/clock/tegra114-car.h3
-rw-r--r--include/dt-bindings/clock/tegra124-car.h3
-rw-r--r--include/dt-bindings/reset/qcom,gcc-msm8960.h2
-rw-r--r--include/linux/clk-provider.h127
-rw-r--r--include/linux/clk/shmobile.h3
-rw-r--r--include/linux/clk/sunxi.h22
69 files changed, 3389 insertions, 813 deletions
diff --git a/Documentation/clk.txt b/Documentation/clk.txt
index c9c399af7c08..1fee72f4d331 100644
--- a/Documentation/clk.txt
+++ b/Documentation/clk.txt
@@ -68,21 +68,27 @@ the operations defined in clk.h:
68 int (*is_enabled)(struct clk_hw *hw); 68 int (*is_enabled)(struct clk_hw *hw);
69 unsigned long (*recalc_rate)(struct clk_hw *hw, 69 unsigned long (*recalc_rate)(struct clk_hw *hw,
70 unsigned long parent_rate); 70 unsigned long parent_rate);
71 long (*round_rate)(struct clk_hw *hw, unsigned long, 71 long (*round_rate)(struct clk_hw *hw,
72 unsigned long *); 72 unsigned long rate,
73 unsigned long *parent_rate);
73 long (*determine_rate)(struct clk_hw *hw, 74 long (*determine_rate)(struct clk_hw *hw,
74 unsigned long rate, 75 unsigned long rate,
75 unsigned long *best_parent_rate, 76 unsigned long *best_parent_rate,
76 struct clk **best_parent_clk); 77 struct clk **best_parent_clk);
77 int (*set_parent)(struct clk_hw *hw, u8 index); 78 int (*set_parent)(struct clk_hw *hw, u8 index);
78 u8 (*get_parent)(struct clk_hw *hw); 79 u8 (*get_parent)(struct clk_hw *hw);
79 int (*set_rate)(struct clk_hw *hw, unsigned long); 80 int (*set_rate)(struct clk_hw *hw,
81 unsigned long rate,
82 unsigned long parent_rate);
80 int (*set_rate_and_parent)(struct clk_hw *hw, 83 int (*set_rate_and_parent)(struct clk_hw *hw,
81 unsigned long rate, 84 unsigned long rate,
82 unsigned long parent_rate, u8 index); 85 unsigned long parent_rate,
86 u8 index);
83 unsigned long (*recalc_accuracy)(struct clk_hw *hw, 87 unsigned long (*recalc_accuracy)(struct clk_hw *hw,
84 unsigned long parent_accuracy); 88 unsigned long parent_accuracy);
85 void (*init)(struct clk_hw *hw); 89 void (*init)(struct clk_hw *hw);
90 int (*debug_init)(struct clk_hw *hw,
91 struct dentry *dentry);
86 }; 92 };
87 93
88 Part 3 - hardware clk implementations 94 Part 3 - hardware clk implementations
diff --git a/Documentation/devicetree/bindings/clock/bcm-kona-clock.txt b/Documentation/devicetree/bindings/clock/bcm-kona-clock.txt
index 56d1f4961075..5286e260fcae 100644
--- a/Documentation/devicetree/bindings/clock/bcm-kona-clock.txt
+++ b/Documentation/devicetree/bindings/clock/bcm-kona-clock.txt
@@ -10,12 +10,12 @@ This binding uses the common clock binding:
10 10
11Required properties: 11Required properties:
12- compatible 12- compatible
13 Shall have one of the following values: 13 Shall have a value of the form "brcm,<model>-<which>-ccu",
14 - "brcm,bcm11351-root-ccu" 14 where <model> is a Broadcom SoC model number and <which> is
15 - "brcm,bcm11351-aon-ccu" 15 the name of a defined CCU. For example:
16 - "brcm,bcm11351-hub-ccu" 16 "brcm,bcm11351-root-ccu"
17 - "brcm,bcm11351-master-ccu" 17 The compatible strings used for each supported SoC family
18 - "brcm,bcm11351-slave-ccu" 18 are defined below.
19- reg 19- reg
20 Shall define the base and range of the address space 20 Shall define the base and range of the address space
21 containing clock control registers 21 containing clock control registers
@@ -26,12 +26,48 @@ Required properties:
26 Shall be an ordered list of strings defining the names of 26 Shall be an ordered list of strings defining the names of
27 the clocks provided by the CCU. 27 the clocks provided by the CCU.
28 28
29Device tree example:
30
31 slave_ccu: slave_ccu {
32 compatible = "brcm,bcm11351-slave-ccu";
33 reg = <0x3e011000 0x0f00>;
34 #clock-cells = <1>;
35 clock-output-names = "uartb",
36 "uartb2",
37 "uartb3",
38 "uartb4";
39 };
40
41 ref_crystal_clk: ref_crystal {
42 #clock-cells = <0>;
43 compatible = "fixed-clock";
44 clock-frequency = <26000000>;
45 };
46
47 uart@3e002000 {
48 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
49 status = "disabled";
50 reg = <0x3e002000 0x1000>;
51 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
52 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
53 reg-shift = <2>;
54 reg-io-width = <4>;
55 };
56
57BCM281XX family
58---------------
59CCU compatible string values for SoCs in the BCM281XX family are:
60 "brcm,bcm11351-root-ccu"
61 "brcm,bcm11351-aon-ccu"
62 "brcm,bcm11351-hub-ccu"
63 "brcm,bcm11351-master-ccu"
64 "brcm,bcm11351-slave-ccu"
29 65
30BCM281XX family SoCs use Kona CCUs. The following table defines 66The following table defines the set of CCUs and clock specifiers for
31the set of CCUs and clock specifiers for BCM281XX clocks. When 67BCM281XX family clocks. When a clock consumer references a clocks,
32a clock consumer references a clocks, its symbolic specifier 68its symbolic specifier (rather than its numeric index value) should
33(rather than its numeric index value) should be used. These 69be used. These specifiers are defined in:
34specifiers are defined in "include/dt-bindings/clock/bcm281xx.h". 70 "include/dt-bindings/clock/bcm281xx.h"
35 71
36 CCU Clock Type Index Specifier 72 CCU Clock Type Index Specifier
37 --- ----- ---- ----- --------- 73 --- ----- ---- ----- ---------
@@ -64,30 +100,40 @@ specifiers are defined in "include/dt-bindings/clock/bcm281xx.h".
64 slave pwm peri 9 BCM281XX_SLAVE_CCU_PWM 100 slave pwm peri 9 BCM281XX_SLAVE_CCU_PWM
65 101
66 102
67Device tree example: 103BCM21664 family
104---------------
105CCU compatible string values for SoCs in the BCM21664 family are:
106 "brcm,bcm21664-root-ccu"
107 "brcm,bcm21664-aon-ccu"
108 "brcm,bcm21664-master-ccu"
109 "brcm,bcm21664-slave-ccu"
68 110
69 slave_ccu: slave_ccu { 111The following table defines the set of CCUs and clock specifiers for
70 compatible = "brcm,bcm11351-slave-ccu"; 112BCM21664 family clocks. When a clock consumer references a clocks,
71 reg = <0x3e011000 0x0f00>; 113its symbolic specifier (rather than its numeric index value) should
72 #clock-cells = <1>; 114be used. These specifiers are defined in:
73 clock-output-names = "uartb", 115 "include/dt-bindings/clock/bcm21664.h"
74 "uartb2",
75 "uartb3",
76 "uartb4";
77 };
78 116
79 ref_crystal_clk: ref_crystal { 117 CCU Clock Type Index Specifier
80 #clock-cells = <0>; 118 --- ----- ---- ----- ---------
81 compatible = "fixed-clock"; 119 root frac_1m peri 0 BCM21664_ROOT_CCU_FRAC_1M
82 clock-frequency = <26000000>;
83 };
84 120
85 uart@3e002000 { 121 aon hub_timer peri 0 BCM21664_AON_CCU_HUB_TIMER
86 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; 122
87 status = "disabled"; 123 master sdio1 peri 0 BCM21664_MASTER_CCU_SDIO1
88 reg = <0x3e002000 0x1000>; 124 master sdio2 peri 1 BCM21664_MASTER_CCU_SDIO2
89 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>; 125 master sdio3 peri 2 BCM21664_MASTER_CCU_SDIO3
90 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 126 master sdio4 peri 3 BCM21664_MASTER_CCU_SDIO4
91 reg-shift = <2>; 127 master sdio1_sleep peri 4 BCM21664_MASTER_CCU_SDIO1_SLEEP
92 reg-io-width = <4>; 128 master sdio2_sleep peri 5 BCM21664_MASTER_CCU_SDIO2_SLEEP
93 }; 129 master sdio3_sleep peri 6 BCM21664_MASTER_CCU_SDIO3_SLEEP
130 master sdio4_sleep peri 7 BCM21664_MASTER_CCU_SDIO4_SLEEP
131
132 slave uartb peri 0 BCM21664_SLAVE_CCU_UARTB
133 slave uartb2 peri 1 BCM21664_SLAVE_CCU_UARTB2
134 slave uartb3 peri 2 BCM21664_SLAVE_CCU_UARTB3
135 slave uartb4 peri 3 BCM21664_SLAVE_CCU_UARTB4
136 slave bsc1 peri 4 BCM21664_SLAVE_CCU_BSC1
137 slave bsc2 peri 5 BCM21664_SLAVE_CCU_BSC2
138 slave bsc3 peri 6 BCM21664_SLAVE_CCU_BSC3
139 slave bsc4 peri 7 BCM21664_SLAVE_CCU_BSC4
diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt b/Documentation/devicetree/bindings/clock/clock-bindings.txt
index 700e7aac3717..f15787817d6b 100644
--- a/Documentation/devicetree/bindings/clock/clock-bindings.txt
+++ b/Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -44,10 +44,9 @@ For example:
44 clocks by index. The names should reflect the clock output signal 44 clocks by index. The names should reflect the clock output signal
45 names for the device. 45 names for the device.
46 46
47clock-indices: If the identifyng number for the clocks in the node 47clock-indices: If the identifying number for the clocks in the node
48 is not linear from zero, then the this mapping allows 48 is not linear from zero, then this allows the mapping of
49 the mapping of identifiers into the clock-output-names 49 identifiers into the clock-output-names array.
50 array.
51 50
52For example, if we have two clocks <&oscillator 1> and <&oscillator 3>: 51For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
53 52
@@ -58,7 +57,7 @@ For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
58 clock-output-names = "clka", "clkb"; 57 clock-output-names = "clka", "clkb";
59 } 58 }
60 59
61 This ensures we do not have any empty nodes in clock-output-names 60 This ensures we do not have any empty strings in clock-output-names
62 61
63 62
64==Clock consumers== 63==Clock consumers==
diff --git a/Documentation/devicetree/bindings/clock/fixed-clock.txt b/Documentation/devicetree/bindings/clock/fixed-clock.txt
index 48ea0ad8ad46..0641a663ad69 100644
--- a/Documentation/devicetree/bindings/clock/fixed-clock.txt
+++ b/Documentation/devicetree/bindings/clock/fixed-clock.txt
@@ -12,7 +12,6 @@ Required properties:
12Optional properties: 12Optional properties:
13- clock-accuracy : accuracy of clock in ppb (parts per billion). 13- clock-accuracy : accuracy of clock in ppb (parts per billion).
14 Should be a single cell. 14 Should be a single cell.
15- gpios : From common gpio binding; gpio connection to clock enable pin.
16- clock-output-names : From common clock binding. 15- clock-output-names : From common clock binding.
17 16
18Example: 17Example:
diff --git a/Documentation/devicetree/bindings/clock/hix5hd2-clock.txt b/Documentation/devicetree/bindings/clock/hix5hd2-clock.txt
new file mode 100644
index 000000000000..7894a64887cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/hix5hd2-clock.txt
@@ -0,0 +1,31 @@
1* Hisilicon Hix5hd2 Clock Controller
2
3The hix5hd2 clock controller generates and supplies clock to various
4controllers within the hix5hd2 SoC.
5
6Required Properties:
7
8- compatible: should be "hisilicon,hix5hd2-clock"
9- reg: Address and length of the register set
10- #clock-cells: Should be <1>
11
12Each clock is assigned an identifier and client nodes use this identifier
13to specify the clock which they consume.
14
15All these identifier could be found in <dt-bindings/clock/hix5hd2-clock.h>.
16
17Examples:
18 clock: clock@f8a22000 {
19 compatible = "hisilicon,hix5hd2-clock";
20 reg = <0xf8a22000 0x1000>;
21 #clock-cells = <1>;
22 };
23
24 uart0: uart@f8b00000 {
25 compatible = "arm,pl011", "arm,primecell";
26 reg = <0xf8b00000 0x1000>;
27 interrupts = <0 49 4>;
28 clocks = <&clock HIX5HD2_FIXED_83M>;
29 clock-names = "apb_pclk";
30 status = "disabled";
31 };
diff --git a/Documentation/devicetree/bindings/clock/lsi,axm5516-clks.txt b/Documentation/devicetree/bindings/clock/lsi,axm5516-clks.txt
new file mode 100644
index 000000000000..3ce97cfe999b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/lsi,axm5516-clks.txt
@@ -0,0 +1,29 @@
1AXM5516 clock driver bindings
2-----------------------------
3
4Required properties :
5- compatible : shall contain "lsi,axm5516-clks"
6- reg : shall contain base register location and length
7- #clock-cells : shall contain 1
8
9The consumer specifies the desired clock by having the clock ID in its "clocks"
10phandle cell. See <dt-bindings/clock/lsi,axxia-clock.h> for the list of
11supported clock IDs.
12
13Example:
14
15 clks: clock-controller@2010020000 {
16 compatible = "lsi,axm5516-clks";
17 #clock-cells = <1>;
18 reg = <0x20 0x10020000 0 0x20000>;
19 };
20
21 serial0: uart@2010080000 {
22 compatible = "arm,pl011", "arm,primecell";
23 reg = <0x20 0x10080000 0 0x1000>;
24 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
25 clocks = <&clks AXXIA_CLK_PER>;
26 clock-names = "apb_pclk";
27 };
28 };
29
diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
index 307a503c5db8..dc5ea5b22da9 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
@@ -29,6 +29,11 @@ The following is a list of provided IDs and clock names on Kirkwood and Dove:
29 2 = l2clk (L2 Cache clock derived from CPU0 clock) 29 2 = l2clk (L2 Cache clock derived from CPU0 clock)
30 3 = ddrclk (DDR controller clock derived from CPU0 clock) 30 3 = ddrclk (DDR controller clock derived from CPU0 clock)
31 31
32The following is a list of provided IDs and clock names on Orion5x:
33 0 = tclk (Internal Bus clock)
34 1 = cpuclk (CPU0 clock)
35 2 = ddrclk (DDR controller clock derived from CPU0 clock)
36
32Required properties: 37Required properties:
33- compatible : shall be one of the following: 38- compatible : shall be one of the following:
34 "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks 39 "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
@@ -38,6 +43,9 @@ Required properties:
38 "marvell,dove-core-clock" - for Dove SoC core clocks 43 "marvell,dove-core-clock" - for Dove SoC core clocks
39 "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180) 44 "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
40 "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC 45 "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
46 "marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
47 "marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
48 "marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
41- reg : shall be the register address of the Sample-At-Reset (SAR) register 49- reg : shall be the register address of the Sample-At-Reset (SAR) register
42- #clock-cells : from common clock binding; shall be set to 1 50- #clock-cells : from common clock binding; shall be set to 1
43 51
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 767401f42871..7b7104e8cb1e 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -4,6 +4,7 @@ Qualcomm Global Clock & Reset Controller Binding
4Required properties : 4Required properties :
5- compatible : shall contain only one of the following: 5- compatible : shall contain only one of the following:
6 6
7 "qcom,gcc-apq8064"
7 "qcom,gcc-msm8660" 8 "qcom,gcc-msm8660"
8 "qcom,gcc-msm8960" 9 "qcom,gcc-msm8960"
9 "qcom,gcc-msm8974" 10 "qcom,gcc-msm8974"
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
index 02a25d99ca61..30df825d72ef 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -10,6 +10,7 @@ index in the group, from 0 to 31.
10Required Properties: 10Required Properties:
11 11
12 - compatible: Must be one of the following 12 - compatible: Must be one of the following
13 - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
13 - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks 14 - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
14 - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks 15 - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
15 - "renesas,cpg-mstp-clock" for generic MSTP gate clocks 16 - "renesas,cpg-mstp-clock" for generic MSTP gate clocks
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt
new file mode 100644
index 000000000000..2c03302f86ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt
@@ -0,0 +1,41 @@
1These bindings should be considered EXPERIMENTAL for now.
2
3* Renesas R8A7740 Clock Pulse Generator (CPG)
4
5The CPG generates core clocks for the R8A7740 SoC. It includes three PLLs
6and several fixed ratio and variable ratio dividers.
7
8Required Properties:
9
10 - compatible: Must be "renesas,r8a7740-cpg-clocks"
11
12 - reg: Base address and length of the memory resource used by the CPG
13
14 - clocks: Reference to the three parent clocks
15 - #clock-cells: Must be 1
16 - clock-output-names: The names of the clocks. Supported clocks are
17 "system", "pllc0", "pllc1", "pllc2", "r", "usb24s", "i", "zg", "b",
18 "m1", "hp", "hpp", "usbp", "s", "zb", "m3", and "cp".
19
20 - renesas,mode: board-specific settings of the MD_CK* bits
21
22
23Example
24-------
25
26cpg_clocks: cpg_clocks@e6150000 {
27 compatible = "renesas,r8a7740-cpg-clocks";
28 reg = <0xe6150000 0x10000>;
29 clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
30 #clock-cells = <1>;
31 clock-output-names = "system", "pllc0", "pllc1",
32 "pllc2", "r",
33 "usb24s",
34 "i", "zg", "b", "m1", "hp",
35 "hpp", "usbp", "s", "zb", "m3",
36 "cp";
37};
38
39&cpg_clocks {
40 renesas,mode = <0x05>;
41};
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
new file mode 100644
index 000000000000..ed3c8cb12f4e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
@@ -0,0 +1,27 @@
1* Renesas R8A7779 Clock Pulse Generator (CPG)
2
3The CPG generates core clocks for the R8A7779. It includes one PLL and
4several fixed ratio dividers
5
6Required Properties:
7
8 - compatible: Must be "renesas,r8a7779-cpg-clocks"
9 - reg: Base address and length of the memory resource used by the CPG
10
11 - clocks: Reference to the parent clock
12 - #clock-cells: Must be 1
13 - clock-output-names: The names of the clocks. Supported clocks are "plla",
14 "z", "zs", "s", "s1", "p", "b", "out".
15
16
17Example
18-------
19
20 cpg_clocks: cpg_clocks@ffc80000 {
21 compatible = "renesas,r8a7779-cpg-clocks";
22 reg = <0 0xffc80000 0 0x30>;
23 clocks = <&extal_clk>;
24 #clock-cells = <1>;
25 clock-output-names = "plla", "z", "zs", "s", "s1", "p",
26 "b", "out";
27 };
diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi
index 08a44d41b672..8b366822bb43 100644
--- a/arch/arm/boot/dts/bcm21664.dtsi
+++ b/arch/arm/boot/dts/bcm21664.dtsi
@@ -14,6 +14,8 @@
14#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/interrupt-controller/irq.h>
16 16
17#include "dt-bindings/clock/bcm21664.h"
18
17#include "skeleton.dtsi" 19#include "skeleton.dtsi"
18 20
19/ { 21/ {
@@ -43,7 +45,7 @@
43 compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; 45 compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
44 status = "disabled"; 46 status = "disabled";
45 reg = <0x3e000000 0x118>; 47 reg = <0x3e000000 0x118>;
46 clocks = <&uartb_clk>; 48 clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>;
47 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 49 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
48 reg-shift = <2>; 50 reg-shift = <2>;
49 reg-io-width = <4>; 51 reg-io-width = <4>;
@@ -53,7 +55,7 @@
53 compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; 55 compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
54 status = "disabled"; 56 status = "disabled";
55 reg = <0x3e001000 0x118>; 57 reg = <0x3e001000 0x118>;
56 clocks = <&uartb2_clk>; 58 clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>;
57 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 59 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
58 reg-shift = <2>; 60 reg-shift = <2>;
59 reg-io-width = <4>; 61 reg-io-width = <4>;
@@ -63,7 +65,7 @@
63 compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; 65 compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
64 status = "disabled"; 66 status = "disabled";
65 reg = <0x3e002000 0x118>; 67 reg = <0x3e002000 0x118>;
66 clocks = <&uartb3_clk>; 68 clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>;
67 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 69 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
68 reg-shift = <2>; 70 reg-shift = <2>;
69 reg-io-width = <4>; 71 reg-io-width = <4>;
@@ -85,7 +87,7 @@
85 compatible = "brcm,kona-timer"; 87 compatible = "brcm,kona-timer";
86 reg = <0x35006000 0x1c>; 88 reg = <0x35006000 0x1c>;
87 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 89 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
88 clocks = <&hub_timer_clk>; 90 clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>;
89 }; 91 };
90 92
91 gpio: gpio@35003000 { 93 gpio: gpio@35003000 {
@@ -106,7 +108,7 @@
106 compatible = "brcm,kona-sdhci"; 108 compatible = "brcm,kona-sdhci";
107 reg = <0x3f180000 0x801c>; 109 reg = <0x3f180000 0x801c>;
108 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 110 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
109 clocks = <&sdio1_clk>; 111 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>;
110 status = "disabled"; 112 status = "disabled";
111 }; 113 };
112 114
@@ -114,7 +116,7 @@
114 compatible = "brcm,kona-sdhci"; 116 compatible = "brcm,kona-sdhci";
115 reg = <0x3f190000 0x801c>; 117 reg = <0x3f190000 0x801c>;
116 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 118 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
117 clocks = <&sdio2_clk>; 119 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>;
118 status = "disabled"; 120 status = "disabled";
119 }; 121 };
120 122
@@ -122,7 +124,7 @@
122 compatible = "brcm,kona-sdhci"; 124 compatible = "brcm,kona-sdhci";
123 reg = <0x3f1a0000 0x801c>; 125 reg = <0x3f1a0000 0x801c>;
124 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 126 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
125 clocks = <&sdio3_clk>; 127 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>;
126 status = "disabled"; 128 status = "disabled";
127 }; 129 };
128 130
@@ -130,7 +132,7 @@
130 compatible = "brcm,kona-sdhci"; 132 compatible = "brcm,kona-sdhci";
131 reg = <0x3f1b0000 0x801c>; 133 reg = <0x3f1b0000 0x801c>;
132 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 134 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
133 clocks = <&sdio4_clk>; 135 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>;
134 status = "disabled"; 136 status = "disabled";
135 }; 137 };
136 138
@@ -140,7 +142,7 @@
140 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 142 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
141 #address-cells = <1>; 143 #address-cells = <1>;
142 #size-cells = <0>; 144 #size-cells = <0>;
143 clocks = <&bsc1_clk>; 145 clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>;
144 status = "disabled"; 146 status = "disabled";
145 }; 147 };
146 148
@@ -150,7 +152,7 @@
150 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 152 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
151 #address-cells = <1>; 153 #address-cells = <1>;
152 #size-cells = <0>; 154 #size-cells = <0>;
153 clocks = <&bsc2_clk>; 155 clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>;
154 status = "disabled"; 156 status = "disabled";
155 }; 157 };
156 158
@@ -160,7 +162,7 @@
160 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 162 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
161 #address-cells = <1>; 163 #address-cells = <1>;
162 #size-cells = <0>; 164 #size-cells = <0>;
163 clocks = <&bsc3_clk>; 165 clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>;
164 status = "disabled"; 166 status = "disabled";
165 }; 167 };
166 168
@@ -170,105 +172,149 @@
170 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 172 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
171 #address-cells = <1>; 173 #address-cells = <1>;
172 #size-cells = <0>; 174 #size-cells = <0>;
173 clocks = <&bsc4_clk>; 175 clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>;
174 status = "disabled"; 176 status = "disabled";
175 }; 177 };
176 178
177 clocks { 179 clocks {
178 bsc1_clk: bsc1 { 180 #address-cells = <1>;
179 compatible = "fixed-clock"; 181 #size-cells = <1>;
180 clock-frequency = <13000000>; 182 ranges;
181 #clock-cells = <0>;
182 };
183 183
184 bsc2_clk: bsc2 { 184 /*
185 compatible = "fixed-clock"; 185 * Fixed clocks are defined before CCUs whose
186 clock-frequency = <13000000>; 186 * clocks may depend on them.
187 */
188
189 ref_32k_clk: ref_32k {
187 #clock-cells = <0>; 190 #clock-cells = <0>;
191 compatible = "fixed-clock";
192 clock-frequency = <32768>;
188 }; 193 };
189 194
190 bsc3_clk: bsc3 { 195 bbl_32k_clk: bbl_32k {
191 compatible = "fixed-clock";
192 clock-frequency = <13000000>;
193 #clock-cells = <0>; 196 #clock-cells = <0>;
197 compatible = "fixed-clock";
198 clock-frequency = <32768>;
194 }; 199 };
195 200
196 bsc4_clk: bsc4 { 201 ref_13m_clk: ref_13m {
202 #clock-cells = <0>;
197 compatible = "fixed-clock"; 203 compatible = "fixed-clock";
198 clock-frequency = <13000000>; 204 clock-frequency = <13000000>;
199 #clock-cells = <0>;
200 }; 205 };
201 206
202 pmu_bsc_clk: pmu_bsc { 207 var_13m_clk: var_13m {
208 #clock-cells = <0>;
203 compatible = "fixed-clock"; 209 compatible = "fixed-clock";
204 clock-frequency = <13000000>; 210 clock-frequency = <13000000>;
205 #clock-cells = <0>;
206 }; 211 };
207 212
208 hub_timer_clk: hub_timer { 213 dft_19_5m_clk: dft_19_5m {
209 compatible = "fixed-clock";
210 clock-frequency = <32768>;
211 #clock-cells = <0>; 214 #clock-cells = <0>;
215 compatible = "fixed-clock";
216 clock-frequency = <19500000>;
212 }; 217 };
213 218
214 pwm_clk: pwm { 219 ref_crystal_clk: ref_crystal {
220 #clock-cells = <0>;
215 compatible = "fixed-clock"; 221 compatible = "fixed-clock";
216 clock-frequency = <26000000>; 222 clock-frequency = <26000000>;
217 #clock-cells = <0>;
218 }; 223 };
219 224
220 sdio1_clk: sdio1 { 225 ref_52m_clk: ref_52m {
221 compatible = "fixed-clock";
222 clock-frequency = <48000000>;
223 #clock-cells = <0>; 226 #clock-cells = <0>;
227 compatible = "fixed-clock";
228 clock-frequency = <52000000>;
224 }; 229 };
225 230
226 sdio2_clk: sdio2 { 231 var_52m_clk: var_52m {
227 compatible = "fixed-clock";
228 clock-frequency = <48000000>;
229 #clock-cells = <0>; 232 #clock-cells = <0>;
233 compatible = "fixed-clock";
234 clock-frequency = <52000000>;
230 }; 235 };
231 236
232 sdio3_clk: sdio3 { 237 usb_otg_ahb_clk: usb_otg_ahb {
233 compatible = "fixed-clock";
234 clock-frequency = <48000000>;
235 #clock-cells = <0>; 238 #clock-cells = <0>;
239 compatible = "fixed-clock";
240 clock-frequency = <52000000>;
236 }; 241 };
237 242
238 sdio4_clk: sdio4 { 243 ref_96m_clk: ref_96m {
239 compatible = "fixed-clock";
240 clock-frequency = <48000000>;
241 #clock-cells = <0>; 244 #clock-cells = <0>;
245 compatible = "fixed-clock";
246 clock-frequency = <96000000>;
242 }; 247 };
243 248
244 tmon_1m_clk: tmon_1m { 249 var_96m_clk: var_96m {
245 compatible = "fixed-clock";
246 clock-frequency = <1000000>;
247 #clock-cells = <0>; 250 #clock-cells = <0>;
251 compatible = "fixed-clock";
252 clock-frequency = <96000000>;
248 }; 253 };
249 254
250 uartb_clk: uartb { 255 ref_104m_clk: ref_104m {
251 compatible = "fixed-clock";
252 clock-frequency = <13000000>;
253 #clock-cells = <0>; 256 #clock-cells = <0>;
257 compatible = "fixed-clock";
258 clock-frequency = <104000000>;
254 }; 259 };
255 260
256 uartb2_clk: uartb2 { 261 var_104m_clk: var_104m {
257 compatible = "fixed-clock";
258 clock-frequency = <13000000>;
259 #clock-cells = <0>; 262 #clock-cells = <0>;
263 compatible = "fixed-clock";
264 clock-frequency = <104000000>;
260 }; 265 };
261 266
262 uartb3_clk: uartb3 { 267 ref_156m_clk: ref_156m {
263 compatible = "fixed-clock";
264 clock-frequency = <13000000>;
265 #clock-cells = <0>; 268 #clock-cells = <0>;
269 compatible = "fixed-clock";
270 clock-frequency = <156000000>;
266 }; 271 };
267 272
268 usb_otg_ahb_clk: usb_otg_ahb { 273 var_156m_clk: var_156m {
269 compatible = "fixed-clock";
270 clock-frequency = <52000000>;
271 #clock-cells = <0>; 274 #clock-cells = <0>;
275 compatible = "fixed-clock";
276 clock-frequency = <156000000>;
277 };
278
279 root_ccu: root_ccu {
280 compatible = BCM21664_DT_ROOT_CCU_COMPAT;
281 reg = <0x35001000 0x0f00>;
282 #clock-cells = <1>;
283 clock-output-names = "frac_1m";
284 };
285
286 aon_ccu: aon_ccu {
287 compatible = BCM21664_DT_AON_CCU_COMPAT;
288 reg = <0x35002000 0x0f00>;
289 #clock-cells = <1>;
290 clock-output-names = "hub_timer";
291 };
292
293 master_ccu: master_ccu {
294 compatible = BCM21664_DT_MASTER_CCU_COMPAT;
295 reg = <0x3f001000 0x0f00>;
296 #clock-cells = <1>;
297 clock-output-names = "sdio1",
298 "sdio2",
299 "sdio3",
300 "sdio4",
301 "sdio1_sleep",
302 "sdio2_sleep",
303 "sdio3_sleep",
304 "sdio4_sleep";
305 };
306
307 slave_ccu: slave_ccu {
308 compatible = BCM21664_DT_SLAVE_CCU_COMPAT;
309 reg = <0x3e011000 0x0f00>;
310 #clock-cells = <1>;
311 clock-output-names = "uartb",
312 "uartb2",
313 "uartb3",
314 "bsc1",
315 "bsc2",
316 "bsc3",
317 "bsc4";
272 }; 318 };
273 }; 319 };
274 320
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5f8a28735c96..f30357aa5471 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_COMMON_CLK) += clk-composite.o
12# hardware specific clock types 12# hardware specific clock types
13# please keep this section sorted lexicographically by file/directory path name 13# please keep this section sorted lexicographically by file/directory path name
14obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o 14obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o
15obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o
15obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o 16obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
16obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o 17obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
17obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o 18obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
@@ -33,6 +34,7 @@ obj-$(CONFIG_COMMON_CLK_AT91) += at91/
33obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm/ 34obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm/
34obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/ 35obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
35obj-$(CONFIG_ARCH_HIP04) += hisilicon/ 36obj-$(CONFIG_ARCH_HIP04) += hisilicon/
37obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
36obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/ 38obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
37ifeq ($(CONFIG_COMMON_CLK), y) 39ifeq ($(CONFIG_COMMON_CLK), y)
38obj-$(CONFIG_ARCH_MMP) += mmp/ 40obj-$(CONFIG_ARCH_MMP) += mmp/
diff --git a/drivers/clk/bcm/Kconfig b/drivers/clk/bcm/Kconfig
index a7262fb8ce55..75506e53075b 100644
--- a/drivers/clk/bcm/Kconfig
+++ b/drivers/clk/bcm/Kconfig
@@ -6,4 +6,4 @@ config CLK_BCM_KONA
6 help 6 help
7 Enable common clock framework support for Broadcom SoCs 7 Enable common clock framework support for Broadcom SoCs
8 using "Kona" style clock control units, including those 8 using "Kona" style clock control units, including those
9 in the BCM281xx family. 9 in the BCM281xx and BCM21664 families.
diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
index cf93359aa862..6297d05a9a10 100644
--- a/drivers/clk/bcm/Makefile
+++ b/drivers/clk/bcm/Makefile
@@ -1,3 +1,4 @@
1obj-$(CONFIG_CLK_BCM_KONA) += clk-kona.o 1obj-$(CONFIG_CLK_BCM_KONA) += clk-kona.o
2obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o 2obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
3obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o 3obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
4obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o
diff --git a/drivers/clk/bcm/clk-bcm21664.c b/drivers/clk/bcm/clk-bcm21664.c
new file mode 100644
index 000000000000..eeae4cad2281
--- /dev/null
+++ b/drivers/clk/bcm/clk-bcm21664.c
@@ -0,0 +1,290 @@
1/*
2 * Copyright (C) 2014 Broadcom Corporation
3 * Copyright 2014 Linaro Limited
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation version 2.
8 *
9 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
10 * kind, whether express or implied; without even the implied warranty
11 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include "clk-kona.h"
16#include "dt-bindings/clock/bcm21664.h"
17
18#define BCM21664_CCU_COMMON(_name, _capname) \
19 KONA_CCU_COMMON(BCM21664, _name, _capname)
20
21/* Root CCU */
22
23static struct peri_clk_data frac_1m_data = {
24 .gate = HW_SW_GATE(0x214, 16, 0, 1),
25 .clocks = CLOCKS("ref_crystal"),
26};
27
28static struct ccu_data root_ccu_data = {
29 BCM21664_CCU_COMMON(root, ROOT),
30 /* no policy control */
31 .kona_clks = {
32 [BCM21664_ROOT_CCU_FRAC_1M] =
33 KONA_CLK(root, frac_1m, peri),
34 [BCM21664_ROOT_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
35 },
36};
37
38/* AON CCU */
39
40static struct peri_clk_data hub_timer_data = {
41 .gate = HW_SW_GATE(0x0414, 16, 0, 1),
42 .hyst = HYST(0x0414, 8, 9),
43 .clocks = CLOCKS("bbl_32k",
44 "frac_1m",
45 "dft_19_5m"),
46 .sel = SELECTOR(0x0a10, 0, 2),
47 .trig = TRIGGER(0x0a40, 4),
48};
49
50static struct ccu_data aon_ccu_data = {
51 BCM21664_CCU_COMMON(aon, AON),
52 .policy = {
53 .enable = CCU_LVM_EN(0x0034, 0),
54 .control = CCU_POLICY_CTL(0x000c, 0, 1, 2),
55 },
56 .kona_clks = {
57 [BCM21664_AON_CCU_HUB_TIMER] =
58 KONA_CLK(aon, hub_timer, peri),
59 [BCM21664_AON_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
60 },
61};
62
63/* Master CCU */
64
65static struct peri_clk_data sdio1_data = {
66 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
67 .clocks = CLOCKS("ref_crystal",
68 "var_52m",
69 "ref_52m",
70 "var_96m",
71 "ref_96m"),
72 .sel = SELECTOR(0x0a28, 0, 3),
73 .div = DIVIDER(0x0a28, 4, 14),
74 .trig = TRIGGER(0x0afc, 9),
75};
76
77static struct peri_clk_data sdio2_data = {
78 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
79 .clocks = CLOCKS("ref_crystal",
80 "var_52m",
81 "ref_52m",
82 "var_96m",
83 "ref_96m"),
84 .sel = SELECTOR(0x0a2c, 0, 3),
85 .div = DIVIDER(0x0a2c, 4, 14),
86 .trig = TRIGGER(0x0afc, 10),
87};
88
89static struct peri_clk_data sdio3_data = {
90 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
91 .clocks = CLOCKS("ref_crystal",
92 "var_52m",
93 "ref_52m",
94 "var_96m",
95 "ref_96m"),
96 .sel = SELECTOR(0x0a34, 0, 3),
97 .div = DIVIDER(0x0a34, 4, 14),
98 .trig = TRIGGER(0x0afc, 12),
99};
100
101static struct peri_clk_data sdio4_data = {
102 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
103 .clocks = CLOCKS("ref_crystal",
104 "var_52m",
105 "ref_52m",
106 "var_96m",
107 "ref_96m"),
108 .sel = SELECTOR(0x0a30, 0, 3),
109 .div = DIVIDER(0x0a30, 4, 14),
110 .trig = TRIGGER(0x0afc, 11),
111};
112
113static struct peri_clk_data sdio1_sleep_data = {
114 .clocks = CLOCKS("ref_32k"), /* Verify */
115 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
116};
117
118static struct peri_clk_data sdio2_sleep_data = {
119 .clocks = CLOCKS("ref_32k"), /* Verify */
120 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
121};
122
123static struct peri_clk_data sdio3_sleep_data = {
124 .clocks = CLOCKS("ref_32k"), /* Verify */
125 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
126};
127
128static struct peri_clk_data sdio4_sleep_data = {
129 .clocks = CLOCKS("ref_32k"), /* Verify */
130 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
131};
132
133static struct ccu_data master_ccu_data = {
134 BCM21664_CCU_COMMON(master, MASTER),
135 .policy = {
136 .enable = CCU_LVM_EN(0x0034, 0),
137 .control = CCU_POLICY_CTL(0x000c, 0, 1, 2),
138 },
139 .kona_clks = {
140 [BCM21664_MASTER_CCU_SDIO1] =
141 KONA_CLK(master, sdio1, peri),
142 [BCM21664_MASTER_CCU_SDIO2] =
143 KONA_CLK(master, sdio2, peri),
144 [BCM21664_MASTER_CCU_SDIO3] =
145 KONA_CLK(master, sdio3, peri),
146 [BCM21664_MASTER_CCU_SDIO4] =
147 KONA_CLK(master, sdio4, peri),
148 [BCM21664_MASTER_CCU_SDIO1_SLEEP] =
149 KONA_CLK(master, sdio1_sleep, peri),
150 [BCM21664_MASTER_CCU_SDIO2_SLEEP] =
151 KONA_CLK(master, sdio2_sleep, peri),
152 [BCM21664_MASTER_CCU_SDIO3_SLEEP] =
153 KONA_CLK(master, sdio3_sleep, peri),
154 [BCM21664_MASTER_CCU_SDIO4_SLEEP] =
155 KONA_CLK(master, sdio4_sleep, peri),
156 [BCM21664_MASTER_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
157 },
158};
159
160/* Slave CCU */
161
162static struct peri_clk_data uartb_data = {
163 .gate = HW_SW_GATE(0x0400, 18, 2, 3),
164 .clocks = CLOCKS("ref_crystal",
165 "var_156m",
166 "ref_156m"),
167 .sel = SELECTOR(0x0a10, 0, 2),
168 .div = FRAC_DIVIDER(0x0a10, 4, 12, 8),
169 .trig = TRIGGER(0x0afc, 2),
170};
171
172static struct peri_clk_data uartb2_data = {
173 .gate = HW_SW_GATE(0x0404, 18, 2, 3),
174 .clocks = CLOCKS("ref_crystal",
175 "var_156m",
176 "ref_156m"),
177 .sel = SELECTOR(0x0a14, 0, 2),
178 .div = FRAC_DIVIDER(0x0a14, 4, 12, 8),
179 .trig = TRIGGER(0x0afc, 3),
180};
181
182static struct peri_clk_data uartb3_data = {
183 .gate = HW_SW_GATE(0x0408, 18, 2, 3),
184 .clocks = CLOCKS("ref_crystal",
185 "var_156m",
186 "ref_156m"),
187 .sel = SELECTOR(0x0a18, 0, 2),
188 .div = FRAC_DIVIDER(0x0a18, 4, 12, 8),
189 .trig = TRIGGER(0x0afc, 4),
190};
191
192static struct peri_clk_data bsc1_data = {
193 .gate = HW_SW_GATE(0x0458, 18, 2, 3),
194 .clocks = CLOCKS("ref_crystal",
195 "var_104m",
196 "ref_104m",
197 "var_13m",
198 "ref_13m"),
199 .sel = SELECTOR(0x0a64, 0, 3),
200 .trig = TRIGGER(0x0afc, 23),
201};
202
203static struct peri_clk_data bsc2_data = {
204 .gate = HW_SW_GATE(0x045c, 18, 2, 3),
205 .clocks = CLOCKS("ref_crystal",
206 "var_104m",
207 "ref_104m",
208 "var_13m",
209 "ref_13m"),
210 .sel = SELECTOR(0x0a68, 0, 3),
211 .trig = TRIGGER(0x0afc, 24),
212};
213
214static struct peri_clk_data bsc3_data = {
215 .gate = HW_SW_GATE(0x0470, 18, 2, 3),
216 .clocks = CLOCKS("ref_crystal",
217 "var_104m",
218 "ref_104m",
219 "var_13m",
220 "ref_13m"),
221 .sel = SELECTOR(0x0a7c, 0, 3),
222 .trig = TRIGGER(0x0afc, 18),
223};
224
225static struct peri_clk_data bsc4_data = {
226 .gate = HW_SW_GATE(0x0474, 18, 2, 3),
227 .clocks = CLOCKS("ref_crystal",
228 "var_104m",
229 "ref_104m",
230 "var_13m",
231 "ref_13m"),
232 .sel = SELECTOR(0x0a80, 0, 3),
233 .trig = TRIGGER(0x0afc, 19),
234};
235
236static struct ccu_data slave_ccu_data = {
237 BCM21664_CCU_COMMON(slave, SLAVE),
238 .policy = {
239 .enable = CCU_LVM_EN(0x0034, 0),
240 .control = CCU_POLICY_CTL(0x000c, 0, 1, 2),
241 },
242 .kona_clks = {
243 [BCM21664_SLAVE_CCU_UARTB] =
244 KONA_CLK(slave, uartb, peri),
245 [BCM21664_SLAVE_CCU_UARTB2] =
246 KONA_CLK(slave, uartb2, peri),
247 [BCM21664_SLAVE_CCU_UARTB3] =
248 KONA_CLK(slave, uartb3, peri),
249 [BCM21664_SLAVE_CCU_BSC1] =
250 KONA_CLK(slave, bsc1, peri),
251 [BCM21664_SLAVE_CCU_BSC2] =
252 KONA_CLK(slave, bsc2, peri),
253 [BCM21664_SLAVE_CCU_BSC3] =
254 KONA_CLK(slave, bsc3, peri),
255 [BCM21664_SLAVE_CCU_BSC4] =
256 KONA_CLK(slave, bsc4, peri),
257 [BCM21664_SLAVE_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
258 },
259};
260
261/* Device tree match table callback functions */
262
263static void __init kona_dt_root_ccu_setup(struct device_node *node)
264{
265 kona_dt_ccu_setup(&root_ccu_data, node);
266}
267
268static void __init kona_dt_aon_ccu_setup(struct device_node *node)
269{
270 kona_dt_ccu_setup(&aon_ccu_data, node);
271}
272
273static void __init kona_dt_master_ccu_setup(struct device_node *node)
274{
275 kona_dt_ccu_setup(&master_ccu_data, node);
276}
277
278static void __init kona_dt_slave_ccu_setup(struct device_node *node)
279{
280 kona_dt_ccu_setup(&slave_ccu_data, node);
281}
282
283CLK_OF_DECLARE(bcm21664_root_ccu, BCM21664_DT_ROOT_CCU_COMPAT,
284 kona_dt_root_ccu_setup);
285CLK_OF_DECLARE(bcm21664_aon_ccu, BCM21664_DT_AON_CCU_COMPAT,
286 kona_dt_aon_ccu_setup);
287CLK_OF_DECLARE(bcm21664_master_ccu, BCM21664_DT_MASTER_CCU_COMPAT,
288 kona_dt_master_ccu_setup);
289CLK_OF_DECLARE(bcm21664_slave_ccu, BCM21664_DT_SLAVE_CCU_COMPAT,
290 kona_dt_slave_ccu_setup);
diff --git a/drivers/clk/bcm/clk-bcm281xx.c b/drivers/clk/bcm/clk-bcm281xx.c
index 3c66de696aeb..502a487d62c5 100644
--- a/drivers/clk/bcm/clk-bcm281xx.c
+++ b/drivers/clk/bcm/clk-bcm281xx.c
@@ -15,14 +15,10 @@
15#include "clk-kona.h" 15#include "clk-kona.h"
16#include "dt-bindings/clock/bcm281xx.h" 16#include "dt-bindings/clock/bcm281xx.h"
17 17
18/* bcm11351 CCU device tree "compatible" strings */ 18#define BCM281XX_CCU_COMMON(_name, _ucase_name) \
19#define BCM11351_DT_ROOT_CCU_COMPAT "brcm,bcm11351-root-ccu" 19 KONA_CCU_COMMON(BCM281XX, _name, _ucase_name)
20#define BCM11351_DT_AON_CCU_COMPAT "brcm,bcm11351-aon-ccu"
21#define BCM11351_DT_HUB_CCU_COMPAT "brcm,bcm11351-hub-ccu"
22#define BCM11351_DT_MASTER_CCU_COMPAT "brcm,bcm11351-master-ccu"
23#define BCM11351_DT_SLAVE_CCU_COMPAT "brcm,bcm11351-slave-ccu"
24 20
25/* Root CCU clocks */ 21/* Root CCU */
26 22
27static struct peri_clk_data frac_1m_data = { 23static struct peri_clk_data frac_1m_data = {
28 .gate = HW_SW_GATE(0x214, 16, 0, 1), 24 .gate = HW_SW_GATE(0x214, 16, 0, 1),
@@ -31,7 +27,16 @@ static struct peri_clk_data frac_1m_data = {
31 .clocks = CLOCKS("ref_crystal"), 27 .clocks = CLOCKS("ref_crystal"),
32}; 28};
33 29
34/* AON CCU clocks */ 30static struct ccu_data root_ccu_data = {
31 BCM281XX_CCU_COMMON(root, ROOT),
32 .kona_clks = {
33 [BCM281XX_ROOT_CCU_FRAC_1M] =
34 KONA_CLK(root, frac_1m, peri),
35 [BCM281XX_ROOT_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
36 },
37};
38
39/* AON CCU */
35 40
36static struct peri_clk_data hub_timer_data = { 41static struct peri_clk_data hub_timer_data = {
37 .gate = HW_SW_GATE(0x0414, 16, 0, 1), 42 .gate = HW_SW_GATE(0x0414, 16, 0, 1),
@@ -60,7 +65,20 @@ static struct peri_clk_data pmu_bsc_var_data = {
60 .trig = TRIGGER(0x0a40, 2), 65 .trig = TRIGGER(0x0a40, 2),
61}; 66};
62 67
63/* Hub CCU clocks */ 68static struct ccu_data aon_ccu_data = {
69 BCM281XX_CCU_COMMON(aon, AON),
70 .kona_clks = {
71 [BCM281XX_AON_CCU_HUB_TIMER] =
72 KONA_CLK(aon, hub_timer, peri),
73 [BCM281XX_AON_CCU_PMU_BSC] =
74 KONA_CLK(aon, pmu_bsc, peri),
75 [BCM281XX_AON_CCU_PMU_BSC_VAR] =
76 KONA_CLK(aon, pmu_bsc_var, peri),
77 [BCM281XX_AON_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
78 },
79};
80
81/* Hub CCU */
64 82
65static struct peri_clk_data tmon_1m_data = { 83static struct peri_clk_data tmon_1m_data = {
66 .gate = HW_SW_GATE(0x04a4, 18, 2, 3), 84 .gate = HW_SW_GATE(0x04a4, 18, 2, 3),
@@ -70,7 +88,16 @@ static struct peri_clk_data tmon_1m_data = {
70 .trig = TRIGGER(0x0e84, 1), 88 .trig = TRIGGER(0x0e84, 1),
71}; 89};
72 90
73/* Master CCU clocks */ 91static struct ccu_data hub_ccu_data = {
92 BCM281XX_CCU_COMMON(hub, HUB),
93 .kona_clks = {
94 [BCM281XX_HUB_CCU_TMON_1M] =
95 KONA_CLK(hub, tmon_1m, peri),
96 [BCM281XX_HUB_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
97 },
98};
99
100/* Master CCU */
74 101
75static struct peri_clk_data sdio1_data = { 102static struct peri_clk_data sdio1_data = {
76 .gate = HW_SW_GATE(0x0358, 18, 2, 3), 103 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
@@ -153,7 +180,28 @@ static struct peri_clk_data hsic2_12m_data = {
153 .trig = TRIGGER(0x0afc, 5), 180 .trig = TRIGGER(0x0afc, 5),
154}; 181};
155 182
156/* Slave CCU clocks */ 183static struct ccu_data master_ccu_data = {
184 BCM281XX_CCU_COMMON(master, MASTER),
185 .kona_clks = {
186 [BCM281XX_MASTER_CCU_SDIO1] =
187 KONA_CLK(master, sdio1, peri),
188 [BCM281XX_MASTER_CCU_SDIO2] =
189 KONA_CLK(master, sdio2, peri),
190 [BCM281XX_MASTER_CCU_SDIO3] =
191 KONA_CLK(master, sdio3, peri),
192 [BCM281XX_MASTER_CCU_SDIO4] =
193 KONA_CLK(master, sdio4, peri),
194 [BCM281XX_MASTER_CCU_USB_IC] =
195 KONA_CLK(master, usb_ic, peri),
196 [BCM281XX_MASTER_CCU_HSIC2_48M] =
197 KONA_CLK(master, hsic2_48m, peri),
198 [BCM281XX_MASTER_CCU_HSIC2_12M] =
199 KONA_CLK(master, hsic2_12m, peri),
200 [BCM281XX_MASTER_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
201 },
202};
203
204/* Slave CCU */
157 205
158static struct peri_clk_data uartb_data = { 206static struct peri_clk_data uartb_data = {
159 .gate = HW_SW_GATE(0x0400, 18, 2, 3), 207 .gate = HW_SW_GATE(0x0400, 18, 2, 3),
@@ -261,156 +309,67 @@ static struct peri_clk_data pwm_data = {
261 .trig = TRIGGER(0x0afc, 15), 309 .trig = TRIGGER(0x0afc, 15),
262}; 310};
263 311
264/* 312static struct ccu_data slave_ccu_data = {
265 * CCU setup routines 313 BCM281XX_CCU_COMMON(slave, SLAVE),
266 * 314 .kona_clks = {
267 * These are called from kona_dt_ccu_setup() to initialize the array 315 [BCM281XX_SLAVE_CCU_UARTB] =
268 * of clocks provided by the CCU. Once allocated, the entries in 316 KONA_CLK(slave, uartb, peri),
269 * the array are initialized by calling kona_clk_setup() with the 317 [BCM281XX_SLAVE_CCU_UARTB2] =
270 * initialization data for each clock. They return 0 if successful 318 KONA_CLK(slave, uartb2, peri),
271 * or an error code otherwise. 319 [BCM281XX_SLAVE_CCU_UARTB3] =
272 */ 320 KONA_CLK(slave, uartb3, peri),
273static int __init bcm281xx_root_ccu_clks_setup(struct ccu_data *ccu) 321 [BCM281XX_SLAVE_CCU_UARTB4] =
274{ 322 KONA_CLK(slave, uartb4, peri),
275 struct clk **clks; 323 [BCM281XX_SLAVE_CCU_SSP0] =
276 size_t count = BCM281XX_ROOT_CCU_CLOCK_COUNT; 324 KONA_CLK(slave, ssp0, peri),
277 325 [BCM281XX_SLAVE_CCU_SSP2] =
278 clks = kzalloc(count * sizeof(*clks), GFP_KERNEL); 326 KONA_CLK(slave, ssp2, peri),
279 if (!clks) { 327 [BCM281XX_SLAVE_CCU_BSC1] =
280 pr_err("%s: failed to allocate root clocks\n", __func__); 328 KONA_CLK(slave, bsc1, peri),
281 return -ENOMEM; 329 [BCM281XX_SLAVE_CCU_BSC2] =
282 } 330 KONA_CLK(slave, bsc2, peri),
283 ccu->data.clks = clks; 331 [BCM281XX_SLAVE_CCU_BSC3] =
284 ccu->data.clk_num = count; 332 KONA_CLK(slave, bsc3, peri),
285 333 [BCM281XX_SLAVE_CCU_PWM] =
286 PERI_CLK_SETUP(clks, ccu, BCM281XX_ROOT_CCU_FRAC_1M, frac_1m); 334 KONA_CLK(slave, pwm, peri),
287 335 [BCM281XX_SLAVE_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
288 return 0; 336 },
289} 337};
290
291static int __init bcm281xx_aon_ccu_clks_setup(struct ccu_data *ccu)
292{
293 struct clk **clks;
294 size_t count = BCM281XX_AON_CCU_CLOCK_COUNT;
295
296 clks = kzalloc(count * sizeof(*clks), GFP_KERNEL);
297 if (!clks) {
298 pr_err("%s: failed to allocate aon clocks\n", __func__);
299 return -ENOMEM;
300 }
301 ccu->data.clks = clks;
302 ccu->data.clk_num = count;
303
304 PERI_CLK_SETUP(clks, ccu, BCM281XX_AON_CCU_HUB_TIMER, hub_timer);
305 PERI_CLK_SETUP(clks, ccu, BCM281XX_AON_CCU_PMU_BSC, pmu_bsc);
306 PERI_CLK_SETUP(clks, ccu, BCM281XX_AON_CCU_PMU_BSC_VAR, pmu_bsc_var);
307
308 return 0;
309}
310
311static int __init bcm281xx_hub_ccu_clks_setup(struct ccu_data *ccu)
312{
313 struct clk **clks;
314 size_t count = BCM281XX_HUB_CCU_CLOCK_COUNT;
315
316 clks = kzalloc(count * sizeof(*clks), GFP_KERNEL);
317 if (!clks) {
318 pr_err("%s: failed to allocate hub clocks\n", __func__);
319 return -ENOMEM;
320 }
321 ccu->data.clks = clks;
322 ccu->data.clk_num = count;
323
324 PERI_CLK_SETUP(clks, ccu, BCM281XX_HUB_CCU_TMON_1M, tmon_1m);
325
326 return 0;
327}
328
329static int __init bcm281xx_master_ccu_clks_setup(struct ccu_data *ccu)
330{
331 struct clk **clks;
332 size_t count = BCM281XX_MASTER_CCU_CLOCK_COUNT;
333
334 clks = kzalloc(count * sizeof(*clks), GFP_KERNEL);
335 if (!clks) {
336 pr_err("%s: failed to allocate master clocks\n", __func__);
337 return -ENOMEM;
338 }
339 ccu->data.clks = clks;
340 ccu->data.clk_num = count;
341
342 PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_SDIO1, sdio1);
343 PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_SDIO2, sdio2);
344 PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_SDIO3, sdio3);
345 PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_SDIO4, sdio4);
346 PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_USB_IC, usb_ic);
347 PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_HSIC2_48M, hsic2_48m);
348 PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_HSIC2_12M, hsic2_12m);
349
350 return 0;
351}
352
353static int __init bcm281xx_slave_ccu_clks_setup(struct ccu_data *ccu)
354{
355 struct clk **clks;
356 size_t count = BCM281XX_SLAVE_CCU_CLOCK_COUNT;
357
358 clks = kzalloc(count * sizeof(*clks), GFP_KERNEL);
359 if (!clks) {
360 pr_err("%s: failed to allocate slave clocks\n", __func__);
361 return -ENOMEM;
362 }
363 ccu->data.clks = clks;
364 ccu->data.clk_num = count;
365
366 PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_UARTB, uartb);
367 PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_UARTB2, uartb2);
368 PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_UARTB3, uartb3);
369 PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_UARTB4, uartb4);
370 PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_SSP0, ssp0);
371 PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_SSP2, ssp2);
372 PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_BSC1, bsc1);
373 PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_BSC2, bsc2);
374 PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_BSC3, bsc3);
375 PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_PWM, pwm);
376
377 return 0;
378}
379 338
380/* Device tree match table callback functions */ 339/* Device tree match table callback functions */
381 340
382static void __init kona_dt_root_ccu_setup(struct device_node *node) 341static void __init kona_dt_root_ccu_setup(struct device_node *node)
383{ 342{
384 kona_dt_ccu_setup(node, bcm281xx_root_ccu_clks_setup); 343 kona_dt_ccu_setup(&root_ccu_data, node);
385} 344}
386 345
387static void __init kona_dt_aon_ccu_setup(struct device_node *node) 346static void __init kona_dt_aon_ccu_setup(struct device_node *node)
388{ 347{
389 kona_dt_ccu_setup(node, bcm281xx_aon_ccu_clks_setup); 348 kona_dt_ccu_setup(&aon_ccu_data, node);
390} 349}
391 350
392static void __init kona_dt_hub_ccu_setup(struct device_node *node) 351static void __init kona_dt_hub_ccu_setup(struct device_node *node)
393{ 352{
394 kona_dt_ccu_setup(node, bcm281xx_hub_ccu_clks_setup); 353 kona_dt_ccu_setup(&hub_ccu_data, node);
395} 354}
396 355
397static void __init kona_dt_master_ccu_setup(struct device_node *node) 356static void __init kona_dt_master_ccu_setup(struct device_node *node)
398{ 357{
399 kona_dt_ccu_setup(node, bcm281xx_master_ccu_clks_setup); 358 kona_dt_ccu_setup(&master_ccu_data, node);
400} 359}
401 360
402static void __init kona_dt_slave_ccu_setup(struct device_node *node) 361static void __init kona_dt_slave_ccu_setup(struct device_node *node)
403{ 362{
404 kona_dt_ccu_setup(node, bcm281xx_slave_ccu_clks_setup); 363 kona_dt_ccu_setup(&slave_ccu_data, node);
405} 364}
406 365
407CLK_OF_DECLARE(bcm11351_root_ccu, BCM11351_DT_ROOT_CCU_COMPAT, 366CLK_OF_DECLARE(bcm281xx_root_ccu, BCM281XX_DT_ROOT_CCU_COMPAT,
408 kona_dt_root_ccu_setup); 367 kona_dt_root_ccu_setup);
409CLK_OF_DECLARE(bcm11351_aon_ccu, BCM11351_DT_AON_CCU_COMPAT, 368CLK_OF_DECLARE(bcm281xx_aon_ccu, BCM281XX_DT_AON_CCU_COMPAT,
410 kona_dt_aon_ccu_setup); 369 kona_dt_aon_ccu_setup);
411CLK_OF_DECLARE(bcm11351_hub_ccu, BCM11351_DT_HUB_CCU_COMPAT, 370CLK_OF_DECLARE(bcm281xx_hub_ccu, BCM281XX_DT_HUB_CCU_COMPAT,
412 kona_dt_hub_ccu_setup); 371 kona_dt_hub_ccu_setup);
413CLK_OF_DECLARE(bcm11351_master_ccu, BCM11351_DT_MASTER_CCU_COMPAT, 372CLK_OF_DECLARE(bcm281xx_master_ccu, BCM281XX_DT_MASTER_CCU_COMPAT,
414 kona_dt_master_ccu_setup); 373 kona_dt_master_ccu_setup);
415CLK_OF_DECLARE(bcm11351_slave_ccu, BCM11351_DT_SLAVE_CCU_COMPAT, 374CLK_OF_DECLARE(bcm281xx_slave_ccu, BCM281XX_DT_SLAVE_CCU_COMPAT,
416 kona_dt_slave_ccu_setup); 375 kona_dt_slave_ccu_setup);
diff --git a/drivers/clk/bcm/clk-kona-setup.c b/drivers/clk/bcm/clk-kona-setup.c
index 54a06526f64f..e5aededdd322 100644
--- a/drivers/clk/bcm/clk-kona-setup.c
+++ b/drivers/clk/bcm/clk-kona-setup.c
@@ -25,6 +25,31 @@ LIST_HEAD(ccu_list); /* The list of set up CCUs */
25 25
26/* Validity checking */ 26/* Validity checking */
27 27
28static bool ccu_data_offsets_valid(struct ccu_data *ccu)
29{
30 struct ccu_policy *ccu_policy = &ccu->policy;
31 u32 limit;
32
33 limit = ccu->range - sizeof(u32);
34 limit = round_down(limit, sizeof(u32));
35 if (ccu_policy_exists(ccu_policy)) {
36 if (ccu_policy->enable.offset > limit) {
37 pr_err("%s: bad policy enable offset for %s "
38 "(%u > %u)\n", __func__,
39 ccu->name, ccu_policy->enable.offset, limit);
40 return false;
41 }
42 if (ccu_policy->control.offset > limit) {
43 pr_err("%s: bad policy control offset for %s "
44 "(%u > %u)\n", __func__,
45 ccu->name, ccu_policy->control.offset, limit);
46 return false;
47 }
48 }
49
50 return true;
51}
52
28static bool clk_requires_trigger(struct kona_clk *bcm_clk) 53static bool clk_requires_trigger(struct kona_clk *bcm_clk)
29{ 54{
30 struct peri_clk_data *peri = bcm_clk->u.peri; 55 struct peri_clk_data *peri = bcm_clk->u.peri;
@@ -54,7 +79,9 @@ static bool clk_requires_trigger(struct kona_clk *bcm_clk)
54static bool peri_clk_data_offsets_valid(struct kona_clk *bcm_clk) 79static bool peri_clk_data_offsets_valid(struct kona_clk *bcm_clk)
55{ 80{
56 struct peri_clk_data *peri; 81 struct peri_clk_data *peri;
82 struct bcm_clk_policy *policy;
57 struct bcm_clk_gate *gate; 83 struct bcm_clk_gate *gate;
84 struct bcm_clk_hyst *hyst;
58 struct bcm_clk_div *div; 85 struct bcm_clk_div *div;
59 struct bcm_clk_sel *sel; 86 struct bcm_clk_sel *sel;
60 struct bcm_clk_trig *trig; 87 struct bcm_clk_trig *trig;
@@ -64,19 +91,41 @@ static bool peri_clk_data_offsets_valid(struct kona_clk *bcm_clk)
64 91
65 BUG_ON(bcm_clk->type != bcm_clk_peri); 92 BUG_ON(bcm_clk->type != bcm_clk_peri);
66 peri = bcm_clk->u.peri; 93 peri = bcm_clk->u.peri;
67 name = bcm_clk->name; 94 name = bcm_clk->init_data.name;
68 range = bcm_clk->ccu->range; 95 range = bcm_clk->ccu->range;
69 96
70 limit = range - sizeof(u32); 97 limit = range - sizeof(u32);
71 limit = round_down(limit, sizeof(u32)); 98 limit = round_down(limit, sizeof(u32));
72 99
100 policy = &peri->policy;
101 if (policy_exists(policy)) {
102 if (policy->offset > limit) {
103 pr_err("%s: bad policy offset for %s (%u > %u)\n",
104 __func__, name, policy->offset, limit);
105 return false;
106 }
107 }
108
73 gate = &peri->gate; 109 gate = &peri->gate;
110 hyst = &peri->hyst;
74 if (gate_exists(gate)) { 111 if (gate_exists(gate)) {
75 if (gate->offset > limit) { 112 if (gate->offset > limit) {
76 pr_err("%s: bad gate offset for %s (%u > %u)\n", 113 pr_err("%s: bad gate offset for %s (%u > %u)\n",
77 __func__, name, gate->offset, limit); 114 __func__, name, gate->offset, limit);
78 return false; 115 return false;
79 } 116 }
117
118 if (hyst_exists(hyst)) {
119 if (hyst->offset > limit) {
120 pr_err("%s: bad hysteresis offset for %s "
121 "(%u > %u)\n", __func__,
122 name, hyst->offset, limit);
123 return false;
124 }
125 }
126 } else if (hyst_exists(hyst)) {
127 pr_err("%s: hysteresis but no gate for %s\n", __func__, name);
128 return false;
80 } 129 }
81 130
82 div = &peri->div; 131 div = &peri->div;
@@ -167,6 +216,36 @@ static bool bitfield_valid(u32 shift, u32 width, const char *field_name,
167 return true; 216 return true;
168} 217}
169 218
219static bool
220ccu_policy_valid(struct ccu_policy *ccu_policy, const char *ccu_name)
221{
222 struct bcm_lvm_en *enable = &ccu_policy->enable;
223 struct bcm_policy_ctl *control;
224
225 if (!bit_posn_valid(enable->bit, "policy enable", ccu_name))
226 return false;
227
228 control = &ccu_policy->control;
229 if (!bit_posn_valid(control->go_bit, "policy control GO", ccu_name))
230 return false;
231
232 if (!bit_posn_valid(control->atl_bit, "policy control ATL", ccu_name))
233 return false;
234
235 if (!bit_posn_valid(control->ac_bit, "policy control AC", ccu_name))
236 return false;
237
238 return true;
239}
240
241static bool policy_valid(struct bcm_clk_policy *policy, const char *clock_name)
242{
243 if (!bit_posn_valid(policy->bit, "policy", clock_name))
244 return false;
245
246 return true;
247}
248
170/* 249/*
171 * All gates, if defined, have a status bit, and for hardware-only 250 * All gates, if defined, have a status bit, and for hardware-only
172 * gates, that's it. Gates that can be software controlled also 251 * gates, that's it. Gates that can be software controlled also
@@ -196,6 +275,17 @@ static bool gate_valid(struct bcm_clk_gate *gate, const char *field_name,
196 return true; 275 return true;
197} 276}
198 277
278static bool hyst_valid(struct bcm_clk_hyst *hyst, const char *clock_name)
279{
280 if (!bit_posn_valid(hyst->en_bit, "hysteresis enable", clock_name))
281 return false;
282
283 if (!bit_posn_valid(hyst->val_bit, "hysteresis value", clock_name))
284 return false;
285
286 return true;
287}
288
199/* 289/*
200 * A selector bitfield must be valid. Its parent_sel array must 290 * A selector bitfield must be valid. Its parent_sel array must
201 * also be reasonable for the field. 291 * also be reasonable for the field.
@@ -312,7 +402,9 @@ static bool
312peri_clk_data_valid(struct kona_clk *bcm_clk) 402peri_clk_data_valid(struct kona_clk *bcm_clk)
313{ 403{
314 struct peri_clk_data *peri; 404 struct peri_clk_data *peri;
405 struct bcm_clk_policy *policy;
315 struct bcm_clk_gate *gate; 406 struct bcm_clk_gate *gate;
407 struct bcm_clk_hyst *hyst;
316 struct bcm_clk_sel *sel; 408 struct bcm_clk_sel *sel;
317 struct bcm_clk_div *div; 409 struct bcm_clk_div *div;
318 struct bcm_clk_div *pre_div; 410 struct bcm_clk_div *pre_div;
@@ -330,11 +422,20 @@ peri_clk_data_valid(struct kona_clk *bcm_clk)
330 return false; 422 return false;
331 423
332 peri = bcm_clk->u.peri; 424 peri = bcm_clk->u.peri;
333 name = bcm_clk->name; 425 name = bcm_clk->init_data.name;
426
427 policy = &peri->policy;
428 if (policy_exists(policy) && !policy_valid(policy, name))
429 return false;
430
334 gate = &peri->gate; 431 gate = &peri->gate;
335 if (gate_exists(gate) && !gate_valid(gate, "gate", name)) 432 if (gate_exists(gate) && !gate_valid(gate, "gate", name))
336 return false; 433 return false;
337 434
435 hyst = &peri->hyst;
436 if (hyst_exists(hyst) && !hyst_valid(hyst, name))
437 return false;
438
338 sel = &peri->sel; 439 sel = &peri->sel;
339 if (selector_exists(sel)) { 440 if (selector_exists(sel)) {
340 if (!sel_valid(sel, "selector", name)) 441 if (!sel_valid(sel, "selector", name))
@@ -567,7 +668,6 @@ static void peri_clk_teardown(struct peri_clk_data *data,
567 struct clk_init_data *init_data) 668 struct clk_init_data *init_data)
568{ 669{
569 clk_sel_teardown(&data->sel, init_data); 670 clk_sel_teardown(&data->sel, init_data);
570 init_data->ops = NULL;
571} 671}
572 672
573/* 673/*
@@ -576,10 +676,9 @@ static void peri_clk_teardown(struct peri_clk_data *data,
576 * that can be assigned if the clock has one or more parent clocks 676 * that can be assigned if the clock has one or more parent clocks
577 * associated with it. 677 * associated with it.
578 */ 678 */
579static int peri_clk_setup(struct ccu_data *ccu, struct peri_clk_data *data, 679static int
580 struct clk_init_data *init_data) 680peri_clk_setup(struct peri_clk_data *data, struct clk_init_data *init_data)
581{ 681{
582 init_data->ops = &kona_peri_clk_ops;
583 init_data->flags = CLK_IGNORE_UNUSED; 682 init_data->flags = CLK_IGNORE_UNUSED;
584 683
585 return clk_sel_setup(data->clocks, &data->sel, init_data); 684 return clk_sel_setup(data->clocks, &data->sel, init_data);
@@ -617,39 +716,26 @@ static void kona_clk_teardown(struct clk *clk)
617 bcm_clk_teardown(bcm_clk); 716 bcm_clk_teardown(bcm_clk);
618} 717}
619 718
620struct clk *kona_clk_setup(struct ccu_data *ccu, const char *name, 719struct clk *kona_clk_setup(struct kona_clk *bcm_clk)
621 enum bcm_clk_type type, void *data)
622{ 720{
623 struct kona_clk *bcm_clk; 721 struct clk_init_data *init_data = &bcm_clk->init_data;
624 struct clk_init_data *init_data;
625 struct clk *clk = NULL; 722 struct clk *clk = NULL;
626 723
627 bcm_clk = kzalloc(sizeof(*bcm_clk), GFP_KERNEL); 724 switch (bcm_clk->type) {
628 if (!bcm_clk) {
629 pr_err("%s: failed to allocate bcm_clk for %s\n", __func__,
630 name);
631 return NULL;
632 }
633 bcm_clk->ccu = ccu;
634 bcm_clk->name = name;
635
636 init_data = &bcm_clk->init_data;
637 init_data->name = name;
638 switch (type) {
639 case bcm_clk_peri: 725 case bcm_clk_peri:
640 if (peri_clk_setup(ccu, data, init_data)) 726 if (peri_clk_setup(bcm_clk->u.data, init_data))
641 goto out_free; 727 return NULL;
642 break; 728 break;
643 default: 729 default:
644 data = NULL; 730 pr_err("%s: clock type %d invalid for %s\n", __func__,
645 break; 731 (int)bcm_clk->type, init_data->name);
732 return NULL;
646 } 733 }
647 bcm_clk->type = type;
648 bcm_clk->u.data = data;
649 734
650 /* Make sure everything makes sense before we set it up */ 735 /* Make sure everything makes sense before we set it up */
651 if (!kona_clk_valid(bcm_clk)) { 736 if (!kona_clk_valid(bcm_clk)) {
652 pr_err("%s: clock data invalid for %s\n", __func__, name); 737 pr_err("%s: clock data invalid for %s\n", __func__,
738 init_data->name);
653 goto out_teardown; 739 goto out_teardown;
654 } 740 }
655 741
@@ -657,7 +743,7 @@ struct clk *kona_clk_setup(struct ccu_data *ccu, const char *name,
657 clk = clk_register(NULL, &bcm_clk->hw); 743 clk = clk_register(NULL, &bcm_clk->hw);
658 if (IS_ERR(clk)) { 744 if (IS_ERR(clk)) {
659 pr_err("%s: error registering clock %s (%ld)\n", __func__, 745 pr_err("%s: error registering clock %s (%ld)\n", __func__,
660 name, PTR_ERR(clk)); 746 init_data->name, PTR_ERR(clk));
661 goto out_teardown; 747 goto out_teardown;
662 } 748 }
663 BUG_ON(!clk); 749 BUG_ON(!clk);
@@ -665,8 +751,6 @@ struct clk *kona_clk_setup(struct ccu_data *ccu, const char *name,
665 return clk; 751 return clk;
666out_teardown: 752out_teardown:
667 bcm_clk_teardown(bcm_clk); 753 bcm_clk_teardown(bcm_clk);
668out_free:
669 kfree(bcm_clk);
670 754
671 return NULL; 755 return NULL;
672} 756}
@@ -675,50 +759,64 @@ static void ccu_clks_teardown(struct ccu_data *ccu)
675{ 759{
676 u32 i; 760 u32 i;
677 761
678 for (i = 0; i < ccu->data.clk_num; i++) 762 for (i = 0; i < ccu->clk_data.clk_num; i++)
679 kona_clk_teardown(ccu->data.clks[i]); 763 kona_clk_teardown(ccu->clk_data.clks[i]);
680 kfree(ccu->data.clks); 764 kfree(ccu->clk_data.clks);
681} 765}
682 766
683static void kona_ccu_teardown(struct ccu_data *ccu) 767static void kona_ccu_teardown(struct ccu_data *ccu)
684{ 768{
685 if (!ccu) 769 kfree(ccu->clk_data.clks);
686 return; 770 ccu->clk_data.clks = NULL;
687
688 if (!ccu->base) 771 if (!ccu->base)
689 goto done; 772 return;
690 773
691 of_clk_del_provider(ccu->node); /* safe if never added */ 774 of_clk_del_provider(ccu->node); /* safe if never added */
692 ccu_clks_teardown(ccu); 775 ccu_clks_teardown(ccu);
693 list_del(&ccu->links); 776 list_del(&ccu->links);
694 of_node_put(ccu->node); 777 of_node_put(ccu->node);
778 ccu->node = NULL;
695 iounmap(ccu->base); 779 iounmap(ccu->base);
696done: 780 ccu->base = NULL;
697 kfree(ccu->name); 781}
698 kfree(ccu); 782
783static bool ccu_data_valid(struct ccu_data *ccu)
784{
785 struct ccu_policy *ccu_policy;
786
787 if (!ccu_data_offsets_valid(ccu))
788 return false;
789
790 ccu_policy = &ccu->policy;
791 if (ccu_policy_exists(ccu_policy))
792 if (!ccu_policy_valid(ccu_policy, ccu->name))
793 return false;
794
795 return true;
699} 796}
700 797
701/* 798/*
702 * Set up a CCU. Call the provided ccu_clks_setup callback to 799 * Set up a CCU. Call the provided ccu_clks_setup callback to
703 * initialize the array of clocks provided by the CCU. 800 * initialize the array of clocks provided by the CCU.
704 */ 801 */
705void __init kona_dt_ccu_setup(struct device_node *node, 802void __init kona_dt_ccu_setup(struct ccu_data *ccu,
706 int (*ccu_clks_setup)(struct ccu_data *)) 803 struct device_node *node)
707{ 804{
708 struct ccu_data *ccu;
709 struct resource res = { 0 }; 805 struct resource res = { 0 };
710 resource_size_t range; 806 resource_size_t range;
807 unsigned int i;
711 int ret; 808 int ret;
712 809
713 ccu = kzalloc(sizeof(*ccu), GFP_KERNEL); 810 if (ccu->clk_data.clk_num) {
714 if (ccu) 811 size_t size;
715 ccu->name = kstrdup(node->name, GFP_KERNEL);
716 if (!ccu || !ccu->name) {
717 pr_err("%s: unable to allocate CCU struct for %s\n",
718 __func__, node->name);
719 kfree(ccu);
720 812
721 return; 813 size = ccu->clk_data.clk_num * sizeof(*ccu->clk_data.clks);
814 ccu->clk_data.clks = kzalloc(size, GFP_KERNEL);
815 if (!ccu->clk_data.clks) {
816 pr_err("%s: unable to allocate %u clocks for %s\n",
817 __func__, ccu->clk_data.clk_num, node->name);
818 return;
819 }
722 } 820 }
723 821
724 ret = of_address_to_resource(node, 0, &res); 822 ret = of_address_to_resource(node, 0, &res);
@@ -736,24 +834,33 @@ void __init kona_dt_ccu_setup(struct device_node *node,
736 } 834 }
737 835
738 ccu->range = (u32)range; 836 ccu->range = (u32)range;
837
838 if (!ccu_data_valid(ccu)) {
839 pr_err("%s: ccu data not valid for %s\n", __func__, node->name);
840 goto out_err;
841 }
842
739 ccu->base = ioremap(res.start, ccu->range); 843 ccu->base = ioremap(res.start, ccu->range);
740 if (!ccu->base) { 844 if (!ccu->base) {
741 pr_err("%s: unable to map CCU registers for %s\n", __func__, 845 pr_err("%s: unable to map CCU registers for %s\n", __func__,
742 node->name); 846 node->name);
743 goto out_err; 847 goto out_err;
744 } 848 }
745
746 spin_lock_init(&ccu->lock);
747 INIT_LIST_HEAD(&ccu->links);
748 ccu->node = of_node_get(node); 849 ccu->node = of_node_get(node);
749
750 list_add_tail(&ccu->links, &ccu_list); 850 list_add_tail(&ccu->links, &ccu_list);
751 851
752 /* Set up clocks array (in ccu->data) */ 852 /*
753 if (ccu_clks_setup(ccu)) 853 * Set up each defined kona clock and save the result in
754 goto out_err; 854 * the clock framework clock array (in ccu->data). Then
855 * register as a provider for these clocks.
856 */
857 for (i = 0; i < ccu->clk_data.clk_num; i++) {
858 if (!ccu->kona_clks[i].ccu)
859 continue;
860 ccu->clk_data.clks[i] = kona_clk_setup(&ccu->kona_clks[i]);
861 }
755 862
756 ret = of_clk_add_provider(node, of_clk_src_onecell_get, &ccu->data); 863 ret = of_clk_add_provider(node, of_clk_src_onecell_get, &ccu->clk_data);
757 if (ret) { 864 if (ret) {
758 pr_err("%s: error adding ccu %s as provider (%d)\n", __func__, 865 pr_err("%s: error adding ccu %s as provider (%d)\n", __func__,
759 node->name, ret); 866 node->name, ret);
diff --git a/drivers/clk/bcm/clk-kona.c b/drivers/clk/bcm/clk-kona.c
index db11a87449f2..d603c4e22fca 100644
--- a/drivers/clk/bcm/clk-kona.c
+++ b/drivers/clk/bcm/clk-kona.c
@@ -16,6 +16,14 @@
16 16
17#include <linux/delay.h> 17#include <linux/delay.h>
18 18
19/*
20 * "Policies" affect the frequencies of bus clocks provided by a
21 * CCU. (I believe these polices are named "Deep Sleep", "Economy",
22 * "Normal", and "Turbo".) A lower policy number has lower power
23 * consumption, and policy 2 is the default.
24 */
25#define CCU_POLICY_COUNT 4
26
19#define CCU_ACCESS_PASSWORD 0xA5A500 27#define CCU_ACCESS_PASSWORD 0xA5A500
20#define CLK_GATE_DELAY_LOOP 2000 28#define CLK_GATE_DELAY_LOOP 2000
21 29
@@ -207,9 +215,154 @@ __ccu_wait_bit(struct ccu_data *ccu, u32 reg_offset, u32 bit, bool want)
207 return true; 215 return true;
208 udelay(1); 216 udelay(1);
209 } 217 }
218 pr_warn("%s: %s/0x%04x bit %u was never %s\n", __func__,
219 ccu->name, reg_offset, bit, want ? "set" : "clear");
220
210 return false; 221 return false;
211} 222}
212 223
224/* Policy operations */
225
226static bool __ccu_policy_engine_start(struct ccu_data *ccu, bool sync)
227{
228 struct bcm_policy_ctl *control = &ccu->policy.control;
229 u32 offset;
230 u32 go_bit;
231 u32 mask;
232 bool ret;
233
234 /* If we don't need to control policy for this CCU, we're done. */
235 if (!policy_ctl_exists(control))
236 return true;
237
238 offset = control->offset;
239 go_bit = control->go_bit;
240
241 /* Ensure we're not busy before we start */
242 ret = __ccu_wait_bit(ccu, offset, go_bit, false);
243 if (!ret) {
244 pr_err("%s: ccu %s policy engine wouldn't go idle\n",
245 __func__, ccu->name);
246 return false;
247 }
248
249 /*
250 * If it's a synchronous request, we'll wait for the voltage
251 * and frequency of the active load to stabilize before
252 * returning. To do this we select the active load by
253 * setting the ATL bit.
254 *
255 * An asynchronous request instead ramps the voltage in the
256 * background, and when that process stabilizes, the target
257 * load is copied to the active load and the CCU frequency
258 * is switched. We do this by selecting the target load
259 * (ATL bit clear) and setting the request auto-copy (AC bit
260 * set).
261 *
262 * Note, we do NOT read-modify-write this register.
263 */
264 mask = (u32)1 << go_bit;
265 if (sync)
266 mask |= 1 << control->atl_bit;
267 else
268 mask |= 1 << control->ac_bit;
269 __ccu_write(ccu, offset, mask);
270
271 /* Wait for indication that operation is complete. */
272 ret = __ccu_wait_bit(ccu, offset, go_bit, false);
273 if (!ret)
274 pr_err("%s: ccu %s policy engine never started\n",
275 __func__, ccu->name);
276
277 return ret;
278}
279
280static bool __ccu_policy_engine_stop(struct ccu_data *ccu)
281{
282 struct bcm_lvm_en *enable = &ccu->policy.enable;
283 u32 offset;
284 u32 enable_bit;
285 bool ret;
286
287 /* If we don't need to control policy for this CCU, we're done. */
288 if (!policy_lvm_en_exists(enable))
289 return true;
290
291 /* Ensure we're not busy before we start */
292 offset = enable->offset;
293 enable_bit = enable->bit;
294 ret = __ccu_wait_bit(ccu, offset, enable_bit, false);
295 if (!ret) {
296 pr_err("%s: ccu %s policy engine already stopped\n",
297 __func__, ccu->name);
298 return false;
299 }
300
301 /* Now set the bit to stop the engine (NO read-modify-write) */
302 __ccu_write(ccu, offset, (u32)1 << enable_bit);
303
304 /* Wait for indication that it has stopped. */
305 ret = __ccu_wait_bit(ccu, offset, enable_bit, false);
306 if (!ret)
307 pr_err("%s: ccu %s policy engine never stopped\n",
308 __func__, ccu->name);
309
310 return ret;
311}
312
313/*
314 * A CCU has four operating conditions ("policies"), and some clocks
315 * can be disabled or enabled based on which policy is currently in
316 * effect. Such clocks have a bit in a "policy mask" register for
317 * each policy indicating whether the clock is enabled for that
318 * policy or not. The bit position for a clock is the same for all
319 * four registers, and the 32-bit registers are at consecutive
320 * addresses.
321 */
322static bool policy_init(struct ccu_data *ccu, struct bcm_clk_policy *policy)
323{
324 u32 offset;
325 u32 mask;
326 int i;
327 bool ret;
328
329 if (!policy_exists(policy))
330 return true;
331
332 /*
333 * We need to stop the CCU policy engine to allow update
334 * of our policy bits.
335 */
336 if (!__ccu_policy_engine_stop(ccu)) {
337 pr_err("%s: unable to stop CCU %s policy engine\n",
338 __func__, ccu->name);
339 return false;
340 }
341
342 /*
343 * For now, if a clock defines its policy bit we just mark
344 * it "enabled" for all four policies.
345 */
346 offset = policy->offset;
347 mask = (u32)1 << policy->bit;
348 for (i = 0; i < CCU_POLICY_COUNT; i++) {
349 u32 reg_val;
350
351 reg_val = __ccu_read(ccu, offset);
352 reg_val |= mask;
353 __ccu_write(ccu, offset, reg_val);
354 offset += sizeof(u32);
355 }
356
357 /* We're done updating; fire up the policy engine again. */
358 ret = __ccu_policy_engine_start(ccu, true);
359 if (!ret)
360 pr_err("%s: unable to restart CCU %s policy engine\n",
361 __func__, ccu->name);
362
363 return ret;
364}
365
213/* Gate operations */ 366/* Gate operations */
214 367
215/* Determine whether a clock is gated. CCU lock must be held. */ 368/* Determine whether a clock is gated. CCU lock must be held. */
@@ -374,6 +527,35 @@ static int clk_gate(struct ccu_data *ccu, const char *name,
374 return -EIO; 527 return -EIO;
375} 528}
376 529
530/* Hysteresis operations */
531
532/*
533 * If a clock gate requires a turn-off delay it will have
534 * "hysteresis" register bits defined. The first, if set, enables
535 * the delay; and if enabled, the second bit determines whether the
536 * delay is "low" or "high" (1 means high). For now, if it's
537 * defined for a clock, we set it.
538 */
539static bool hyst_init(struct ccu_data *ccu, struct bcm_clk_hyst *hyst)
540{
541 u32 offset;
542 u32 reg_val;
543 u32 mask;
544
545 if (!hyst_exists(hyst))
546 return true;
547
548 offset = hyst->offset;
549 mask = (u32)1 << hyst->en_bit;
550 mask |= (u32)1 << hyst->val_bit;
551
552 reg_val = __ccu_read(ccu, offset);
553 reg_val |= mask;
554 __ccu_write(ccu, offset, reg_val);
555
556 return true;
557}
558
377/* Trigger operations */ 559/* Trigger operations */
378 560
379/* 561/*
@@ -806,7 +988,7 @@ static int kona_peri_clk_enable(struct clk_hw *hw)
806 struct kona_clk *bcm_clk = to_kona_clk(hw); 988 struct kona_clk *bcm_clk = to_kona_clk(hw);
807 struct bcm_clk_gate *gate = &bcm_clk->u.peri->gate; 989 struct bcm_clk_gate *gate = &bcm_clk->u.peri->gate;
808 990
809 return clk_gate(bcm_clk->ccu, bcm_clk->name, gate, true); 991 return clk_gate(bcm_clk->ccu, bcm_clk->init_data.name, gate, true);
810} 992}
811 993
812static void kona_peri_clk_disable(struct clk_hw *hw) 994static void kona_peri_clk_disable(struct clk_hw *hw)
@@ -814,7 +996,7 @@ static void kona_peri_clk_disable(struct clk_hw *hw)
814 struct kona_clk *bcm_clk = to_kona_clk(hw); 996 struct kona_clk *bcm_clk = to_kona_clk(hw);
815 struct bcm_clk_gate *gate = &bcm_clk->u.peri->gate; 997 struct bcm_clk_gate *gate = &bcm_clk->u.peri->gate;
816 998
817 (void)clk_gate(bcm_clk->ccu, bcm_clk->name, gate, false); 999 (void)clk_gate(bcm_clk->ccu, bcm_clk->init_data.name, gate, false);
818} 1000}
819 1001
820static int kona_peri_clk_is_enabled(struct clk_hw *hw) 1002static int kona_peri_clk_is_enabled(struct clk_hw *hw)
@@ -872,12 +1054,13 @@ static int kona_peri_clk_set_parent(struct clk_hw *hw, u8 index)
872 1054
873 ret = selector_write(bcm_clk->ccu, &data->gate, sel, trig, index); 1055 ret = selector_write(bcm_clk->ccu, &data->gate, sel, trig, index);
874 if (ret == -ENXIO) { 1056 if (ret == -ENXIO) {
875 pr_err("%s: gating failure for %s\n", __func__, bcm_clk->name); 1057 pr_err("%s: gating failure for %s\n", __func__,
1058 bcm_clk->init_data.name);
876 ret = -EIO; /* Don't proliferate weird errors */ 1059 ret = -EIO; /* Don't proliferate weird errors */
877 } else if (ret == -EIO) { 1060 } else if (ret == -EIO) {
878 pr_err("%s: %strigger failed for %s\n", __func__, 1061 pr_err("%s: %strigger failed for %s\n", __func__,
879 trig == &data->pre_trig ? "pre-" : "", 1062 trig == &data->pre_trig ? "pre-" : "",
880 bcm_clk->name); 1063 bcm_clk->init_data.name);
881 } 1064 }
882 1065
883 return ret; 1066 return ret;
@@ -936,10 +1119,12 @@ static int kona_peri_clk_set_rate(struct clk_hw *hw, unsigned long rate,
936 ret = divider_write(bcm_clk->ccu, &data->gate, &data->div, 1119 ret = divider_write(bcm_clk->ccu, &data->gate, &data->div,
937 &data->trig, scaled_div); 1120 &data->trig, scaled_div);
938 if (ret == -ENXIO) { 1121 if (ret == -ENXIO) {
939 pr_err("%s: gating failure for %s\n", __func__, bcm_clk->name); 1122 pr_err("%s: gating failure for %s\n", __func__,
1123 bcm_clk->init_data.name);
940 ret = -EIO; /* Don't proliferate weird errors */ 1124 ret = -EIO; /* Don't proliferate weird errors */
941 } else if (ret == -EIO) { 1125 } else if (ret == -EIO) {
942 pr_err("%s: trigger failed for %s\n", __func__, bcm_clk->name); 1126 pr_err("%s: trigger failed for %s\n", __func__,
1127 bcm_clk->init_data.name);
943 } 1128 }
944 1129
945 return ret; 1130 return ret;
@@ -961,15 +1146,24 @@ static bool __peri_clk_init(struct kona_clk *bcm_clk)
961{ 1146{
962 struct ccu_data *ccu = bcm_clk->ccu; 1147 struct ccu_data *ccu = bcm_clk->ccu;
963 struct peri_clk_data *peri = bcm_clk->u.peri; 1148 struct peri_clk_data *peri = bcm_clk->u.peri;
964 const char *name = bcm_clk->name; 1149 const char *name = bcm_clk->init_data.name;
965 struct bcm_clk_trig *trig; 1150 struct bcm_clk_trig *trig;
966 1151
967 BUG_ON(bcm_clk->type != bcm_clk_peri); 1152 BUG_ON(bcm_clk->type != bcm_clk_peri);
968 1153
1154 if (!policy_init(ccu, &peri->policy)) {
1155 pr_err("%s: error initializing policy for %s\n",
1156 __func__, name);
1157 return false;
1158 }
969 if (!gate_init(ccu, &peri->gate)) { 1159 if (!gate_init(ccu, &peri->gate)) {
970 pr_err("%s: error initializing gate for %s\n", __func__, name); 1160 pr_err("%s: error initializing gate for %s\n", __func__, name);
971 return false; 1161 return false;
972 } 1162 }
1163 if (!hyst_init(ccu, &peri->hyst)) {
1164 pr_err("%s: error initializing hyst for %s\n", __func__, name);
1165 return false;
1166 }
973 if (!div_init(ccu, &peri->gate, &peri->div, &peri->trig)) { 1167 if (!div_init(ccu, &peri->gate, &peri->div, &peri->trig)) {
974 pr_err("%s: error initializing divider for %s\n", __func__, 1168 pr_err("%s: error initializing divider for %s\n", __func__,
975 name); 1169 name);
@@ -1014,13 +1208,13 @@ bool __init kona_ccu_init(struct ccu_data *ccu)
1014{ 1208{
1015 unsigned long flags; 1209 unsigned long flags;
1016 unsigned int which; 1210 unsigned int which;
1017 struct clk **clks = ccu->data.clks; 1211 struct clk **clks = ccu->clk_data.clks;
1018 bool success = true; 1212 bool success = true;
1019 1213
1020 flags = ccu_lock(ccu); 1214 flags = ccu_lock(ccu);
1021 __ccu_write_enable(ccu); 1215 __ccu_write_enable(ccu);
1022 1216
1023 for (which = 0; which < ccu->data.clk_num; which++) { 1217 for (which = 0; which < ccu->clk_data.clk_num; which++) {
1024 struct kona_clk *bcm_clk; 1218 struct kona_clk *bcm_clk;
1025 1219
1026 if (!clks[which]) 1220 if (!clks[which])
diff --git a/drivers/clk/bcm/clk-kona.h b/drivers/clk/bcm/clk-kona.h
index dee690951bb6..2537b3072910 100644
--- a/drivers/clk/bcm/clk-kona.h
+++ b/drivers/clk/bcm/clk-kona.h
@@ -43,8 +43,14 @@
43#define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag)) 43#define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
44#define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag))) 44#define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
45 45
46/* CCU field state tests */
47
48#define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0)
49
46/* Clock field state tests */ 50/* Clock field state tests */
47 51
52#define policy_exists(policy) ((policy)->offset != 0)
53
48#define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS) 54#define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS)
49#define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED) 55#define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED)
50#define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW) 56#define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW)
@@ -54,6 +60,8 @@
54 60
55#define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED) 61#define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED)
56 62
63#define hyst_exists(hyst) ((hyst)->offset != 0)
64
57#define divider_exists(div) FLAG_TEST(div, DIV, EXISTS) 65#define divider_exists(div) FLAG_TEST(div, DIV, EXISTS)
58#define divider_is_fixed(div) FLAG_TEST(div, DIV, FIXED) 66#define divider_is_fixed(div) FLAG_TEST(div, DIV, FIXED)
59#define divider_has_fraction(div) (!divider_is_fixed(div) && \ 67#define divider_has_fraction(div) (!divider_is_fixed(div) && \
@@ -62,6 +70,9 @@
62#define selector_exists(sel) ((sel)->width != 0) 70#define selector_exists(sel) ((sel)->width != 0)
63#define trigger_exists(trig) FLAG_TEST(trig, TRIG, EXISTS) 71#define trigger_exists(trig) FLAG_TEST(trig, TRIG, EXISTS)
64 72
73#define policy_lvm_en_exists(enable) ((enable)->offset != 0)
74#define policy_ctl_exists(control) ((control)->offset != 0)
75
65/* Clock type, used to tell common block what it's part of */ 76/* Clock type, used to tell common block what it's part of */
66enum bcm_clk_type { 77enum bcm_clk_type {
67 bcm_clk_none, /* undefined clock type */ 78 bcm_clk_none, /* undefined clock type */
@@ -71,25 +82,26 @@ enum bcm_clk_type {
71}; 82};
72 83
73/* 84/*
74 * Each CCU defines a mapped area of memory containing registers 85 * CCU policy control for clocks. Clocks can be enabled or disabled
75 * used to manage clocks implemented by the CCU. Access to memory 86 * based on the CCU policy in effect. One bit in each policy mask
76 * within the CCU's space is serialized by a spinlock. Before any 87 * register (one per CCU policy) represents whether the clock is
77 * (other) address can be written, a special access "password" value 88 * enabled when that policy is effect or not. The CCU policy engine
78 * must be written to its WR_ACCESS register (located at the base 89 * must be stopped to update these bits, and must be restarted again
79 * address of the range). We keep track of the name of each CCU as 90 * afterward.
80 * it is set up, and maintain them in a list.
81 */ 91 */
82struct ccu_data { 92struct bcm_clk_policy {
83 void __iomem *base; /* base of mapped address space */ 93 u32 offset; /* first policy mask register offset */
84 spinlock_t lock; /* serialization lock */ 94 u32 bit; /* bit used in all mask registers */
85 bool write_enabled; /* write access is currently enabled */
86 struct list_head links; /* for ccu_list */
87 struct device_node *node;
88 struct clk_onecell_data data;
89 const char *name;
90 u32 range; /* byte range of address space */
91}; 95};
92 96
97/* Policy initialization macro */
98
99#define POLICY(_offset, _bit) \
100 { \
101 .offset = (_offset), \
102 .bit = (_bit), \
103 }
104
93/* 105/*
94 * Gating control and status is managed by a 32-bit gate register. 106 * Gating control and status is managed by a 32-bit gate register.
95 * 107 *
@@ -195,6 +207,22 @@ struct bcm_clk_gate {
195 .flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \ 207 .flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \
196 } 208 }
197 209
210/* Gate hysteresis for clocks */
211struct bcm_clk_hyst {
212 u32 offset; /* hyst register offset (normally CLKGATE) */
213 u32 en_bit; /* bit used to enable hysteresis */
214 u32 val_bit; /* if enabled: 0 = low delay; 1 = high delay */
215};
216
217/* Hysteresis initialization macro */
218
219#define HYST(_offset, _en_bit, _val_bit) \
220 { \
221 .offset = (_offset), \
222 .en_bit = (_en_bit), \
223 .val_bit = (_val_bit), \
224 }
225
198/* 226/*
199 * Each clock can have zero, one, or two dividers which change the 227 * Each clock can have zero, one, or two dividers which change the
200 * output rate of the clock. Each divider can be either fixed or 228 * output rate of the clock. Each divider can be either fixed or
@@ -360,7 +388,9 @@ struct bcm_clk_trig {
360 } 388 }
361 389
362struct peri_clk_data { 390struct peri_clk_data {
391 struct bcm_clk_policy policy;
363 struct bcm_clk_gate gate; 392 struct bcm_clk_gate gate;
393 struct bcm_clk_hyst hyst;
364 struct bcm_clk_trig pre_trig; 394 struct bcm_clk_trig pre_trig;
365 struct bcm_clk_div pre_div; 395 struct bcm_clk_div pre_div;
366 struct bcm_clk_trig trig; 396 struct bcm_clk_trig trig;
@@ -373,8 +403,7 @@ struct peri_clk_data {
373 403
374struct kona_clk { 404struct kona_clk {
375 struct clk_hw hw; 405 struct clk_hw hw;
376 struct clk_init_data init_data; 406 struct clk_init_data init_data; /* includes name of this clock */
377 const char *name; /* name of this clock */
378 struct ccu_data *ccu; /* ccu this clock is associated with */ 407 struct ccu_data *ccu; /* ccu this clock is associated with */
379 enum bcm_clk_type type; 408 enum bcm_clk_type type;
380 union { 409 union {
@@ -385,14 +414,92 @@ struct kona_clk {
385#define to_kona_clk(_hw) \ 414#define to_kona_clk(_hw) \
386 container_of(_hw, struct kona_clk, hw) 415 container_of(_hw, struct kona_clk, hw)
387 416
388/* Exported globals */ 417/* Initialization macro for an entry in a CCU's kona_clks[] array. */
418#define KONA_CLK(_ccu_name, _clk_name, _type) \
419 { \
420 .init_data = { \
421 .name = #_clk_name, \
422 .ops = &kona_ ## _type ## _clk_ops, \
423 }, \
424 .ccu = &_ccu_name ## _ccu_data, \
425 .type = bcm_clk_ ## _type, \
426 .u.data = &_clk_name ## _data, \
427 }
428#define LAST_KONA_CLK { .type = bcm_clk_none }
389 429
390extern struct clk_ops kona_peri_clk_ops; 430/*
431 * CCU policy control. To enable software update of the policy
432 * tables the CCU policy engine must be stopped by setting the
433 * software update enable bit (LVM_EN). After an update the engine
434 * is restarted using the GO bit and either the GO_ATL or GO_AC bit.
435 */
436struct bcm_lvm_en {
437 u32 offset; /* LVM_EN register offset */
438 u32 bit; /* POLICY_CONFIG_EN bit in register */
439};
440
441/* Policy enable initialization macro */
442#define CCU_LVM_EN(_offset, _bit) \
443 { \
444 .offset = (_offset), \
445 .bit = (_bit), \
446 }
447
448struct bcm_policy_ctl {
449 u32 offset; /* POLICY_CTL register offset */
450 u32 go_bit;
451 u32 atl_bit; /* GO, GO_ATL, and GO_AC bits */
452 u32 ac_bit;
453};
454
455/* Policy control initialization macro */
456#define CCU_POLICY_CTL(_offset, _go_bit, _ac_bit, _atl_bit) \
457 { \
458 .offset = (_offset), \
459 .go_bit = (_go_bit), \
460 .ac_bit = (_ac_bit), \
461 .atl_bit = (_atl_bit), \
462 }
463
464struct ccu_policy {
465 struct bcm_lvm_en enable;
466 struct bcm_policy_ctl control;
467};
468
469/*
470 * Each CCU defines a mapped area of memory containing registers
471 * used to manage clocks implemented by the CCU. Access to memory
472 * within the CCU's space is serialized by a spinlock. Before any
473 * (other) address can be written, a special access "password" value
474 * must be written to its WR_ACCESS register (located at the base
475 * address of the range). We keep track of the name of each CCU as
476 * it is set up, and maintain them in a list.
477 */
478struct ccu_data {
479 void __iomem *base; /* base of mapped address space */
480 spinlock_t lock; /* serialization lock */
481 bool write_enabled; /* write access is currently enabled */
482 struct ccu_policy policy;
483 struct list_head links; /* for ccu_list */
484 struct device_node *node;
485 struct clk_onecell_data clk_data;
486 const char *name;
487 u32 range; /* byte range of address space */
488 struct kona_clk kona_clks[]; /* must be last */
489};
391 490
392/* Help functions */ 491/* Initialization for common fields in a Kona ccu_data structure */
492#define KONA_CCU_COMMON(_prefix, _name, _ccuname) \
493 .name = #_name "_ccu", \
494 .lock = __SPIN_LOCK_UNLOCKED(_name ## _ccu_data.lock), \
495 .links = LIST_HEAD_INIT(_name ## _ccu_data.links), \
496 .clk_data = { \
497 .clk_num = _prefix ## _ ## _ccuname ## _CCU_CLOCK_COUNT, \
498 }
499
500/* Exported globals */
393 501
394#define PERI_CLK_SETUP(clks, ccu, id, name) \ 502extern struct clk_ops kona_peri_clk_ops;
395 clks[id] = kona_clk_setup(ccu, #name, bcm_clk_peri, &name ## _data)
396 503
397/* Externally visible functions */ 504/* Externally visible functions */
398 505
@@ -401,10 +508,9 @@ extern u64 scaled_div_max(struct bcm_clk_div *div);
401extern u64 scaled_div_build(struct bcm_clk_div *div, u32 div_value, 508extern u64 scaled_div_build(struct bcm_clk_div *div, u32 div_value,
402 u32 billionths); 509 u32 billionths);
403 510
404extern struct clk *kona_clk_setup(struct ccu_data *ccu, const char *name, 511extern struct clk *kona_clk_setup(struct kona_clk *bcm_clk);
405 enum bcm_clk_type type, void *data); 512extern void __init kona_dt_ccu_setup(struct ccu_data *ccu,
406extern void __init kona_dt_ccu_setup(struct device_node *node, 513 struct device_node *node);
407 int (*ccu_clks_setup)(struct ccu_data *));
408extern bool __init kona_ccu_init(struct ccu_data *ccu); 514extern bool __init kona_ccu_init(struct ccu_data *ccu);
409 515
410#endif /* _CLK_KONA_H */ 516#endif /* _CLK_KONA_H */
diff --git a/drivers/clk/clk-axm5516.c b/drivers/clk/clk-axm5516.c
new file mode 100644
index 000000000000..d2f1e119b450
--- /dev/null
+++ b/drivers/clk/clk-axm5516.c
@@ -0,0 +1,615 @@
1/*
2 * drivers/clk/clk-axm5516.c
3 *
4 * Provides clock implementations for three different types of clock devices on
5 * the Axxia device: PLL clock, a clock divider and a clock mux.
6 *
7 * Copyright (C) 2014 LSI Corporation
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 */
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/slab.h>
16#include <linux/platform_device.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/clk-provider.h>
20#include <linux/regmap.h>
21#include <dt-bindings/clock/lsi,axm5516-clks.h>
22
23
24/**
25 * struct axxia_clk - Common struct to all Axxia clocks.
26 * @hw: clk_hw for the common clk framework
27 * @regmap: Regmap for the clock control registers
28 */
29struct axxia_clk {
30 struct clk_hw hw;
31 struct regmap *regmap;
32};
33#define to_axxia_clk(_hw) container_of(_hw, struct axxia_clk, hw)
34
35/**
36 * struct axxia_pllclk - Axxia PLL generated clock.
37 * @aclk: Common struct
38 * @reg: Offset into regmap for PLL control register
39 */
40struct axxia_pllclk {
41 struct axxia_clk aclk;
42 u32 reg;
43};
44#define to_axxia_pllclk(_aclk) container_of(_aclk, struct axxia_pllclk, aclk)
45
46/**
47 * axxia_pllclk_recalc - Calculate the PLL generated clock rate given the
48 * parent clock rate.
49 */
50static unsigned long
51axxia_pllclk_recalc(struct clk_hw *hw, unsigned long parent_rate)
52{
53 struct axxia_clk *aclk = to_axxia_clk(hw);
54 struct axxia_pllclk *pll = to_axxia_pllclk(aclk);
55 unsigned long rate, fbdiv, refdiv, postdiv;
56 u32 control;
57
58 regmap_read(aclk->regmap, pll->reg, &control);
59 postdiv = ((control >> 0) & 0xf) + 1;
60 fbdiv = ((control >> 4) & 0xfff) + 3;
61 refdiv = ((control >> 16) & 0x1f) + 1;
62 rate = (parent_rate / (refdiv * postdiv)) * fbdiv;
63
64 return rate;
65}
66
67static const struct clk_ops axxia_pllclk_ops = {
68 .recalc_rate = axxia_pllclk_recalc,
69};
70
71/**
72 * struct axxia_divclk - Axxia clock divider
73 * @aclk: Common struct
74 * @reg: Offset into regmap for PLL control register
75 * @shift: Bit position for divider value
76 * @width: Number of bits in divider value
77 */
78struct axxia_divclk {
79 struct axxia_clk aclk;
80 u32 reg;
81 u32 shift;
82 u32 width;
83};
84#define to_axxia_divclk(_aclk) container_of(_aclk, struct axxia_divclk, aclk)
85
86/**
87 * axxia_divclk_recalc_rate - Calculate clock divider output rage
88 */
89static unsigned long
90axxia_divclk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
91{
92 struct axxia_clk *aclk = to_axxia_clk(hw);
93 struct axxia_divclk *divclk = to_axxia_divclk(aclk);
94 u32 ctrl, div;
95
96 regmap_read(aclk->regmap, divclk->reg, &ctrl);
97 div = 1 + ((ctrl >> divclk->shift) & ((1 << divclk->width)-1));
98
99 return parent_rate / div;
100}
101
102static const struct clk_ops axxia_divclk_ops = {
103 .recalc_rate = axxia_divclk_recalc_rate,
104};
105
106/**
107 * struct axxia_clkmux - Axxia clock mux
108 * @aclk: Common struct
109 * @reg: Offset into regmap for PLL control register
110 * @shift: Bit position for selection value
111 * @width: Number of bits in selection value
112 */
113struct axxia_clkmux {
114 struct axxia_clk aclk;
115 u32 reg;
116 u32 shift;
117 u32 width;
118};
119#define to_axxia_clkmux(_aclk) container_of(_aclk, struct axxia_clkmux, aclk)
120
121/**
122 * axxia_clkmux_get_parent - Return the index of selected parent clock
123 */
124static u8 axxia_clkmux_get_parent(struct clk_hw *hw)
125{
126 struct axxia_clk *aclk = to_axxia_clk(hw);
127 struct axxia_clkmux *mux = to_axxia_clkmux(aclk);
128 u32 ctrl, parent;
129
130 regmap_read(aclk->regmap, mux->reg, &ctrl);
131 parent = (ctrl >> mux->shift) & ((1 << mux->width) - 1);
132
133 return (u8) parent;
134}
135
136static const struct clk_ops axxia_clkmux_ops = {
137 .get_parent = axxia_clkmux_get_parent,
138};
139
140
141/*
142 * PLLs
143 */
144
145static struct axxia_pllclk clk_fab_pll = {
146 .aclk.hw.init = &(struct clk_init_data){
147 .name = "clk_fab_pll",
148 .parent_names = (const char *[]){
149 "clk_ref0"
150 },
151 .num_parents = 1,
152 .ops = &axxia_pllclk_ops,
153 },
154 .reg = 0x01800,
155};
156
157static struct axxia_pllclk clk_cpu_pll = {
158 .aclk.hw.init = &(struct clk_init_data){
159 .name = "clk_cpu_pll",
160 .parent_names = (const char *[]){
161 "clk_ref0"
162 },
163 .num_parents = 1,
164 .ops = &axxia_pllclk_ops,
165 },
166 .reg = 0x02000,
167};
168
169static struct axxia_pllclk clk_sys_pll = {
170 .aclk.hw.init = &(struct clk_init_data){
171 .name = "clk_sys_pll",
172 .parent_names = (const char *[]){
173 "clk_ref0"
174 },
175 .num_parents = 1,
176 .ops = &axxia_pllclk_ops,
177 },
178 .reg = 0x02800,
179};
180
181static struct axxia_pllclk clk_sm0_pll = {
182 .aclk.hw.init = &(struct clk_init_data){
183 .name = "clk_sm0_pll",
184 .parent_names = (const char *[]){
185 "clk_ref2"
186 },
187 .num_parents = 1,
188 .ops = &axxia_pllclk_ops,
189 },
190 .reg = 0x03000,
191};
192
193static struct axxia_pllclk clk_sm1_pll = {
194 .aclk.hw.init = &(struct clk_init_data){
195 .name = "clk_sm1_pll",
196 .parent_names = (const char *[]){
197 "clk_ref1"
198 },
199 .num_parents = 1,
200 .ops = &axxia_pllclk_ops,
201 },
202 .reg = 0x03800,
203};
204
205/*
206 * Clock dividers
207 */
208
209static struct axxia_divclk clk_cpu0_div = {
210 .aclk.hw.init = &(struct clk_init_data){
211 .name = "clk_cpu0_div",
212 .parent_names = (const char *[]){
213 "clk_cpu_pll"
214 },
215 .num_parents = 1,
216 .ops = &axxia_divclk_ops,
217 },
218 .reg = 0x10008,
219 .shift = 0,
220 .width = 4,
221};
222
223static struct axxia_divclk clk_cpu1_div = {
224 .aclk.hw.init = &(struct clk_init_data){
225 .name = "clk_cpu1_div",
226 .parent_names = (const char *[]){
227 "clk_cpu_pll"
228 },
229 .num_parents = 1,
230 .ops = &axxia_divclk_ops,
231 },
232 .reg = 0x10008,
233 .shift = 4,
234 .width = 4,
235};
236
237static struct axxia_divclk clk_cpu2_div = {
238 .aclk.hw.init = &(struct clk_init_data){
239 .name = "clk_cpu2_div",
240 .parent_names = (const char *[]){
241 "clk_cpu_pll"
242 },
243 .num_parents = 1,
244 .ops = &axxia_divclk_ops,
245 },
246 .reg = 0x10008,
247 .shift = 8,
248 .width = 4,
249};
250
251static struct axxia_divclk clk_cpu3_div = {
252 .aclk.hw.init = &(struct clk_init_data){
253 .name = "clk_cpu3_div",
254 .parent_names = (const char *[]){
255 "clk_cpu_pll"
256 },
257 .num_parents = 1,
258 .ops = &axxia_divclk_ops,
259 },
260 .reg = 0x10008,
261 .shift = 12,
262 .width = 4,
263};
264
265static struct axxia_divclk clk_nrcp_div = {
266 .aclk.hw.init = &(struct clk_init_data){
267 .name = "clk_nrcp_div",
268 .parent_names = (const char *[]){
269 "clk_sys_pll"
270 },
271 .num_parents = 1,
272 .ops = &axxia_divclk_ops,
273 },
274 .reg = 0x1000c,
275 .shift = 0,
276 .width = 4,
277};
278
279static struct axxia_divclk clk_sys_div = {
280 .aclk.hw.init = &(struct clk_init_data){
281 .name = "clk_sys_div",
282 .parent_names = (const char *[]){
283 "clk_sys_pll"
284 },
285 .num_parents = 1,
286 .ops = &axxia_divclk_ops,
287 },
288 .reg = 0x1000c,
289 .shift = 4,
290 .width = 4,
291};
292
293static struct axxia_divclk clk_fab_div = {
294 .aclk.hw.init = &(struct clk_init_data){
295 .name = "clk_fab_div",
296 .parent_names = (const char *[]){
297 "clk_fab_pll"
298 },
299 .num_parents = 1,
300 .ops = &axxia_divclk_ops,
301 },
302 .reg = 0x1000c,
303 .shift = 8,
304 .width = 4,
305};
306
307static struct axxia_divclk clk_per_div = {
308 .aclk.hw.init = &(struct clk_init_data){
309 .name = "clk_per_div",
310 .parent_names = (const char *[]){
311 "clk_sm1_pll"
312 },
313 .num_parents = 1,
314 .flags = CLK_IS_BASIC,
315 .ops = &axxia_divclk_ops,
316 },
317 .reg = 0x1000c,
318 .shift = 12,
319 .width = 4,
320};
321
322static struct axxia_divclk clk_mmc_div = {
323 .aclk.hw.init = &(struct clk_init_data){
324 .name = "clk_mmc_div",
325 .parent_names = (const char *[]){
326 "clk_sm1_pll"
327 },
328 .num_parents = 1,
329 .flags = CLK_IS_BASIC,
330 .ops = &axxia_divclk_ops,
331 },
332 .reg = 0x1000c,
333 .shift = 16,
334 .width = 4,
335};
336
337/*
338 * Clock MUXes
339 */
340
341static struct axxia_clkmux clk_cpu0_mux = {
342 .aclk.hw.init = &(struct clk_init_data){
343 .name = "clk_cpu0",
344 .parent_names = (const char *[]){
345 "clk_ref0",
346 "clk_cpu_pll",
347 "clk_cpu0_div",
348 "clk_cpu0_div"
349 },
350 .num_parents = 4,
351 .ops = &axxia_clkmux_ops,
352 },
353 .reg = 0x10000,
354 .shift = 0,
355 .width = 2,
356};
357
358static struct axxia_clkmux clk_cpu1_mux = {
359 .aclk.hw.init = &(struct clk_init_data){
360 .name = "clk_cpu1",
361 .parent_names = (const char *[]){
362 "clk_ref0",
363 "clk_cpu_pll",
364 "clk_cpu1_div",
365 "clk_cpu1_div"
366 },
367 .num_parents = 4,
368 .ops = &axxia_clkmux_ops,
369 },
370 .reg = 0x10000,
371 .shift = 2,
372 .width = 2,
373};
374
375static struct axxia_clkmux clk_cpu2_mux = {
376 .aclk.hw.init = &(struct clk_init_data){
377 .name = "clk_cpu2",
378 .parent_names = (const char *[]){
379 "clk_ref0",
380 "clk_cpu_pll",
381 "clk_cpu2_div",
382 "clk_cpu2_div"
383 },
384 .num_parents = 4,
385 .ops = &axxia_clkmux_ops,
386 },
387 .reg = 0x10000,
388 .shift = 4,
389 .width = 2,
390};
391
392static struct axxia_clkmux clk_cpu3_mux = {
393 .aclk.hw.init = &(struct clk_init_data){
394 .name = "clk_cpu3",
395 .parent_names = (const char *[]){
396 "clk_ref0",
397 "clk_cpu_pll",
398 "clk_cpu3_div",
399 "clk_cpu3_div"
400 },
401 .num_parents = 4,
402 .ops = &axxia_clkmux_ops,
403 },
404 .reg = 0x10000,
405 .shift = 6,
406 .width = 2,
407};
408
409static struct axxia_clkmux clk_nrcp_mux = {
410 .aclk.hw.init = &(struct clk_init_data){
411 .name = "clk_nrcp",
412 .parent_names = (const char *[]){
413 "clk_ref0",
414 "clk_sys_pll",
415 "clk_nrcp_div",
416 "clk_nrcp_div"
417 },
418 .num_parents = 4,
419 .ops = &axxia_clkmux_ops,
420 },
421 .reg = 0x10004,
422 .shift = 0,
423 .width = 2,
424};
425
426static struct axxia_clkmux clk_sys_mux = {
427 .aclk.hw.init = &(struct clk_init_data){
428 .name = "clk_sys",
429 .parent_names = (const char *[]){
430 "clk_ref0",
431 "clk_sys_pll",
432 "clk_sys_div",
433 "clk_sys_div"
434 },
435 .num_parents = 4,
436 .ops = &axxia_clkmux_ops,
437 },
438 .reg = 0x10004,
439 .shift = 2,
440 .width = 2,
441};
442
443static struct axxia_clkmux clk_fab_mux = {
444 .aclk.hw.init = &(struct clk_init_data){
445 .name = "clk_fab",
446 .parent_names = (const char *[]){
447 "clk_ref0",
448 "clk_fab_pll",
449 "clk_fab_div",
450 "clk_fab_div"
451 },
452 .num_parents = 4,
453 .ops = &axxia_clkmux_ops,
454 },
455 .reg = 0x10004,
456 .shift = 4,
457 .width = 2,
458};
459
460static struct axxia_clkmux clk_per_mux = {
461 .aclk.hw.init = &(struct clk_init_data){
462 .name = "clk_per",
463 .parent_names = (const char *[]){
464 "clk_ref1",
465 "clk_per_div"
466 },
467 .num_parents = 2,
468 .ops = &axxia_clkmux_ops,
469 },
470 .reg = 0x10004,
471 .shift = 6,
472 .width = 1,
473};
474
475static struct axxia_clkmux clk_mmc_mux = {
476 .aclk.hw.init = &(struct clk_init_data){
477 .name = "clk_mmc",
478 .parent_names = (const char *[]){
479 "clk_ref1",
480 "clk_mmc_div"
481 },
482 .num_parents = 2,
483 .ops = &axxia_clkmux_ops,
484 },
485 .reg = 0x10004,
486 .shift = 9,
487 .width = 1,
488};
489
490/* Table of all supported clocks indexed by the clock identifiers from the
491 * device tree binding
492 */
493static struct axxia_clk *axmclk_clocks[] = {
494 [AXXIA_CLK_FAB_PLL] = &clk_fab_pll.aclk,
495 [AXXIA_CLK_CPU_PLL] = &clk_cpu_pll.aclk,
496 [AXXIA_CLK_SYS_PLL] = &clk_sys_pll.aclk,
497 [AXXIA_CLK_SM0_PLL] = &clk_sm0_pll.aclk,
498 [AXXIA_CLK_SM1_PLL] = &clk_sm1_pll.aclk,
499 [AXXIA_CLK_FAB_DIV] = &clk_fab_div.aclk,
500 [AXXIA_CLK_SYS_DIV] = &clk_sys_div.aclk,
501 [AXXIA_CLK_NRCP_DIV] = &clk_nrcp_div.aclk,
502 [AXXIA_CLK_CPU0_DIV] = &clk_cpu0_div.aclk,
503 [AXXIA_CLK_CPU1_DIV] = &clk_cpu1_div.aclk,
504 [AXXIA_CLK_CPU2_DIV] = &clk_cpu2_div.aclk,
505 [AXXIA_CLK_CPU3_DIV] = &clk_cpu3_div.aclk,
506 [AXXIA_CLK_PER_DIV] = &clk_per_div.aclk,
507 [AXXIA_CLK_MMC_DIV] = &clk_mmc_div.aclk,
508 [AXXIA_CLK_FAB] = &clk_fab_mux.aclk,
509 [AXXIA_CLK_SYS] = &clk_sys_mux.aclk,
510 [AXXIA_CLK_NRCP] = &clk_nrcp_mux.aclk,
511 [AXXIA_CLK_CPU0] = &clk_cpu0_mux.aclk,
512 [AXXIA_CLK_CPU1] = &clk_cpu1_mux.aclk,
513 [AXXIA_CLK_CPU2] = &clk_cpu2_mux.aclk,
514 [AXXIA_CLK_CPU3] = &clk_cpu3_mux.aclk,
515 [AXXIA_CLK_PER] = &clk_per_mux.aclk,
516 [AXXIA_CLK_MMC] = &clk_mmc_mux.aclk,
517};
518
519static const struct regmap_config axmclk_regmap_config = {
520 .reg_bits = 32,
521 .reg_stride = 4,
522 .val_bits = 32,
523 .max_register = 0x1fffc,
524 .fast_io = true,
525};
526
527static const struct of_device_id axmclk_match_table[] = {
528 { .compatible = "lsi,axm5516-clks" },
529 { }
530};
531MODULE_DEVICE_TABLE(of, axmclk_match_table);
532
533struct axmclk_priv {
534 struct clk_onecell_data onecell;
535 struct clk *clks[];
536};
537
538static int axmclk_probe(struct platform_device *pdev)
539{
540 void __iomem *base;
541 struct resource *res;
542 int i, ret;
543 struct device *dev = &pdev->dev;
544 struct clk *clk;
545 struct regmap *regmap;
546 size_t num_clks;
547 struct axmclk_priv *priv;
548
549 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
550 base = devm_ioremap_resource(dev, res);
551 if (IS_ERR(base))
552 return PTR_ERR(base);
553
554 regmap = devm_regmap_init_mmio(dev, base, &axmclk_regmap_config);
555 if (IS_ERR(regmap))
556 return PTR_ERR(regmap);
557
558 num_clks = ARRAY_SIZE(axmclk_clocks);
559 pr_info("axmclk: supporting %u clocks\n", num_clks);
560 priv = devm_kzalloc(dev, sizeof(*priv) + sizeof(*priv->clks) * num_clks,
561 GFP_KERNEL);
562 if (!priv)
563 return -ENOMEM;
564
565 priv->onecell.clks = priv->clks;
566 priv->onecell.clk_num = num_clks;
567
568 /* Update each entry with the allocated regmap and register the clock
569 * with the common clock framework
570 */
571 for (i = 0; i < num_clks; i++) {
572 axmclk_clocks[i]->regmap = regmap;
573 clk = devm_clk_register(dev, &axmclk_clocks[i]->hw);
574 if (IS_ERR(clk))
575 return PTR_ERR(clk);
576 priv->clks[i] = clk;
577 }
578
579 ret = of_clk_add_provider(dev->of_node,
580 of_clk_src_onecell_get, &priv->onecell);
581
582 return ret;
583}
584
585static int axmclk_remove(struct platform_device *pdev)
586{
587 of_clk_del_provider(pdev->dev.of_node);
588 return 0;
589}
590
591static struct platform_driver axmclk_driver = {
592 .probe = axmclk_probe,
593 .remove = axmclk_remove,
594 .driver = {
595 .name = "clk-axm5516",
596 .owner = THIS_MODULE,
597 .of_match_table = axmclk_match_table,
598 },
599};
600
601static int __init axmclk_init(void)
602{
603 return platform_driver_register(&axmclk_driver);
604}
605core_initcall(axmclk_init);
606
607static void __exit axmclk_exit(void)
608{
609 platform_driver_unregister(&axmclk_driver);
610}
611module_exit(axmclk_exit);
612
613MODULE_DESCRIPTION("AXM5516 clock driver");
614MODULE_LICENSE("GPL v2");
615MODULE_ALIAS("platform:clk-axm5516");
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 4637697c139f..c9343f5d9918 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -43,6 +43,17 @@ static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
43 return maxdiv; 43 return maxdiv;
44} 44}
45 45
46static unsigned int _get_table_mindiv(const struct clk_div_table *table)
47{
48 unsigned int mindiv = UINT_MAX;
49 const struct clk_div_table *clkt;
50
51 for (clkt = table; clkt->div; clkt++)
52 if (clkt->div < mindiv)
53 mindiv = clkt->div;
54 return mindiv;
55}
56
46static unsigned int _get_maxdiv(struct clk_divider *divider) 57static unsigned int _get_maxdiv(struct clk_divider *divider)
47{ 58{
48 if (divider->flags & CLK_DIVIDER_ONE_BASED) 59 if (divider->flags & CLK_DIVIDER_ONE_BASED)
@@ -162,6 +173,24 @@ static int _round_up_table(const struct clk_div_table *table, int div)
162 return up; 173 return up;
163} 174}
164 175
176static int _round_down_table(const struct clk_div_table *table, int div)
177{
178 const struct clk_div_table *clkt;
179 int down = _get_table_mindiv(table);
180
181 for (clkt = table; clkt->div; clkt++) {
182 if (clkt->div == div)
183 return clkt->div;
184 else if (clkt->div > div)
185 continue;
186
187 if ((div - clkt->div) < (div - down))
188 down = clkt->div;
189 }
190
191 return down;
192}
193
165static int _div_round_up(struct clk_divider *divider, 194static int _div_round_up(struct clk_divider *divider,
166 unsigned long parent_rate, unsigned long rate) 195 unsigned long parent_rate, unsigned long rate)
167{ 196{
@@ -175,6 +204,54 @@ static int _div_round_up(struct clk_divider *divider,
175 return div; 204 return div;
176} 205}
177 206
207static int _div_round_closest(struct clk_divider *divider,
208 unsigned long parent_rate, unsigned long rate)
209{
210 int up, down, div;
211
212 up = down = div = DIV_ROUND_CLOSEST(parent_rate, rate);
213
214 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) {
215 up = __roundup_pow_of_two(div);
216 down = __rounddown_pow_of_two(div);
217 } else if (divider->table) {
218 up = _round_up_table(divider->table, div);
219 down = _round_down_table(divider->table, div);
220 }
221
222 return (up - div) <= (div - down) ? up : down;
223}
224
225static int _div_round(struct clk_divider *divider, unsigned long parent_rate,
226 unsigned long rate)
227{
228 if (divider->flags & CLK_DIVIDER_ROUND_CLOSEST)
229 return _div_round_closest(divider, parent_rate, rate);
230
231 return _div_round_up(divider, parent_rate, rate);
232}
233
234static bool _is_best_div(struct clk_divider *divider,
235 int rate, int now, int best)
236{
237 if (divider->flags & CLK_DIVIDER_ROUND_CLOSEST)
238 return abs(rate - now) < abs(rate - best);
239
240 return now <= rate && now > best;
241}
242
243static int _next_div(struct clk_divider *divider, int div)
244{
245 div++;
246
247 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
248 return __roundup_pow_of_two(div);
249 if (divider->table)
250 return _round_up_table(divider->table, div);
251
252 return div;
253}
254
178static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate, 255static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
179 unsigned long *best_parent_rate) 256 unsigned long *best_parent_rate)
180{ 257{
@@ -190,7 +267,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
190 267
191 if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) { 268 if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
192 parent_rate = *best_parent_rate; 269 parent_rate = *best_parent_rate;
193 bestdiv = _div_round_up(divider, parent_rate, rate); 270 bestdiv = _div_round(divider, parent_rate, rate);
194 bestdiv = bestdiv == 0 ? 1 : bestdiv; 271 bestdiv = bestdiv == 0 ? 1 : bestdiv;
195 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv; 272 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
196 return bestdiv; 273 return bestdiv;
@@ -202,7 +279,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
202 */ 279 */
203 maxdiv = min(ULONG_MAX / rate, maxdiv); 280 maxdiv = min(ULONG_MAX / rate, maxdiv);
204 281
205 for (i = 1; i <= maxdiv; i++) { 282 for (i = 1; i <= maxdiv; i = _next_div(divider, i)) {
206 if (!_is_valid_div(divider, i)) 283 if (!_is_valid_div(divider, i))
207 continue; 284 continue;
208 if (rate * i == parent_rate_saved) { 285 if (rate * i == parent_rate_saved) {
@@ -217,7 +294,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
217 parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 294 parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
218 MULT_ROUND_UP(rate, i)); 295 MULT_ROUND_UP(rate, i));
219 now = DIV_ROUND_UP(parent_rate, i); 296 now = DIV_ROUND_UP(parent_rate, i);
220 if (now <= rate && now > best) { 297 if (_is_best_div(divider, rate, now, best)) {
221 bestdiv = i; 298 bestdiv = i;
222 best = now; 299 best = now;
223 *best_parent_rate = parent_rate; 300 *best_parent_rate = parent_rate;
@@ -284,6 +361,11 @@ const struct clk_ops clk_divider_ops = {
284}; 361};
285EXPORT_SYMBOL_GPL(clk_divider_ops); 362EXPORT_SYMBOL_GPL(clk_divider_ops);
286 363
364const struct clk_ops clk_divider_ro_ops = {
365 .recalc_rate = clk_divider_recalc_rate,
366};
367EXPORT_SYMBOL_GPL(clk_divider_ro_ops);
368
287static struct clk *_register_divider(struct device *dev, const char *name, 369static struct clk *_register_divider(struct device *dev, const char *name,
288 const char *parent_name, unsigned long flags, 370 const char *parent_name, unsigned long flags,
289 void __iomem *reg, u8 shift, u8 width, 371 void __iomem *reg, u8 shift, u8 width,
@@ -309,7 +391,10 @@ static struct clk *_register_divider(struct device *dev, const char *name,
309 } 391 }
310 392
311 init.name = name; 393 init.name = name;
312 init.ops = &clk_divider_ops; 394 if (clk_divider_flags & CLK_DIVIDER_READ_ONLY)
395 init.ops = &clk_divider_ro_ops;
396 else
397 init.ops = &clk_divider_ops;
313 init.flags = flags | CLK_IS_BASIC; 398 init.flags = flags | CLK_IS_BASIC;
314 init.parent_names = (parent_name ? &parent_name: NULL); 399 init.parent_names = (parent_name ? &parent_name: NULL);
315 init.num_parents = (parent_name ? 1 : 0); 400 init.num_parents = (parent_name ? 1 : 0);
diff --git a/drivers/clk/clk-si570.c b/drivers/clk/clk-si570.c
index 4bbbe32585ec..fc167b3f8919 100644
--- a/drivers/clk/clk-si570.c
+++ b/drivers/clk/clk-si570.c
@@ -526,6 +526,6 @@ static struct i2c_driver si570_driver = {
526module_i2c_driver(si570_driver); 526module_i2c_driver(si570_driver);
527 527
528MODULE_AUTHOR("Guenter Roeck <guenter.roeck@ericsson.com>"); 528MODULE_AUTHOR("Guenter Roeck <guenter.roeck@ericsson.com>");
529MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com"); 529MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
530MODULE_DESCRIPTION("Si570 driver"); 530MODULE_DESCRIPTION("Si570 driver");
531MODULE_LICENSE("GPL"); 531MODULE_LICENSE("GPL");
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 7cf2c093cc54..2df2b26297ce 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -106,12 +106,11 @@ static void clk_summary_show_one(struct seq_file *s, struct clk *c, int level)
106 if (!c) 106 if (!c)
107 return; 107 return;
108 108
109 seq_printf(s, "%*s%-*s %-11d %-12d %-10lu %-11lu", 109 seq_printf(s, "%*s%-*s %11d %12d %11lu %10lu\n",
110 level * 3 + 1, "", 110 level * 3 + 1, "",
111 30 - level * 3, c->name, 111 30 - level * 3, c->name,
112 c->enable_count, c->prepare_count, clk_get_rate(c), 112 c->enable_count, c->prepare_count, clk_get_rate(c),
113 clk_get_accuracy(c)); 113 clk_get_accuracy(c));
114 seq_printf(s, "\n");
115} 114}
116 115
117static void clk_summary_show_subtree(struct seq_file *s, struct clk *c, 116static void clk_summary_show_subtree(struct seq_file *s, struct clk *c,
@@ -132,8 +131,8 @@ static int clk_summary_show(struct seq_file *s, void *data)
132{ 131{
133 struct clk *c; 132 struct clk *c;
134 133
135 seq_printf(s, " clock enable_cnt prepare_cnt rate accuracy\n"); 134 seq_puts(s, " clock enable_cnt prepare_cnt rate accuracy\n");
136 seq_printf(s, "---------------------------------------------------------------------------------\n"); 135 seq_puts(s, "--------------------------------------------------------------------------------\n");
137 136
138 clk_prepare_lock(); 137 clk_prepare_lock();
139 138
@@ -822,6 +821,9 @@ void __clk_unprepare(struct clk *clk)
822 */ 821 */
823void clk_unprepare(struct clk *clk) 822void clk_unprepare(struct clk *clk)
824{ 823{
824 if (IS_ERR_OR_NULL(clk))
825 return;
826
825 clk_prepare_lock(); 827 clk_prepare_lock();
826 __clk_unprepare(clk); 828 __clk_unprepare(clk);
827 clk_prepare_unlock(); 829 clk_prepare_unlock();
@@ -883,9 +885,6 @@ static void __clk_disable(struct clk *clk)
883 if (!clk) 885 if (!clk)
884 return; 886 return;
885 887
886 if (WARN_ON(IS_ERR(clk)))
887 return;
888
889 if (WARN_ON(clk->enable_count == 0)) 888 if (WARN_ON(clk->enable_count == 0))
890 return; 889 return;
891 890
@@ -914,6 +913,9 @@ void clk_disable(struct clk *clk)
914{ 913{
915 unsigned long flags; 914 unsigned long flags;
916 915
916 if (IS_ERR_OR_NULL(clk))
917 return;
918
917 flags = clk_enable_lock(); 919 flags = clk_enable_lock();
918 __clk_disable(clk); 920 __clk_disable(clk);
919 clk_enable_unlock(flags); 921 clk_enable_unlock(flags);
@@ -1115,6 +1117,13 @@ long clk_get_accuracy(struct clk *clk)
1115} 1117}
1116EXPORT_SYMBOL_GPL(clk_get_accuracy); 1118EXPORT_SYMBOL_GPL(clk_get_accuracy);
1117 1119
1120static unsigned long clk_recalc(struct clk *clk, unsigned long parent_rate)
1121{
1122 if (clk->ops->recalc_rate)
1123 return clk->ops->recalc_rate(clk->hw, parent_rate);
1124 return parent_rate;
1125}
1126
1118/** 1127/**
1119 * __clk_recalc_rates 1128 * __clk_recalc_rates
1120 * @clk: first clk in the subtree 1129 * @clk: first clk in the subtree
@@ -1140,10 +1149,7 @@ static void __clk_recalc_rates(struct clk *clk, unsigned long msg)
1140 if (clk->parent) 1149 if (clk->parent)
1141 parent_rate = clk->parent->rate; 1150 parent_rate = clk->parent->rate;
1142 1151
1143 if (clk->ops->recalc_rate) 1152 clk->rate = clk_recalc(clk, parent_rate);
1144 clk->rate = clk->ops->recalc_rate(clk->hw, parent_rate);
1145 else
1146 clk->rate = parent_rate;
1147 1153
1148 /* 1154 /*
1149 * ignore NOTIFY_STOP and NOTIFY_BAD return values for POST_RATE_CHANGE 1155 * ignore NOTIFY_STOP and NOTIFY_BAD return values for POST_RATE_CHANGE
@@ -1334,10 +1340,7 @@ static int __clk_speculate_rates(struct clk *clk, unsigned long parent_rate)
1334 unsigned long new_rate; 1340 unsigned long new_rate;
1335 int ret = NOTIFY_DONE; 1341 int ret = NOTIFY_DONE;
1336 1342
1337 if (clk->ops->recalc_rate) 1343 new_rate = clk_recalc(clk, parent_rate);
1338 new_rate = clk->ops->recalc_rate(clk->hw, parent_rate);
1339 else
1340 new_rate = parent_rate;
1341 1344
1342 /* abort rate change if a driver returns NOTIFY_BAD or NOTIFY_STOP */ 1345 /* abort rate change if a driver returns NOTIFY_BAD or NOTIFY_STOP */
1343 if (clk->notifier_count) 1346 if (clk->notifier_count)
@@ -1373,10 +1376,7 @@ static void clk_calc_subtree(struct clk *clk, unsigned long new_rate,
1373 new_parent->new_child = clk; 1376 new_parent->new_child = clk;
1374 1377
1375 hlist_for_each_entry(child, &clk->children, child_node) { 1378 hlist_for_each_entry(child, &clk->children, child_node) {
1376 if (child->ops->recalc_rate) 1379 child->new_rate = clk_recalc(child, new_rate);
1377 child->new_rate = child->ops->recalc_rate(child->hw, new_rate);
1378 else
1379 child->new_rate = new_rate;
1380 clk_calc_subtree(child, child->new_rate, NULL, 0); 1380 clk_calc_subtree(child, child->new_rate, NULL, 0);
1381 } 1381 }
1382} 1382}
@@ -1524,10 +1524,7 @@ static void clk_change_rate(struct clk *clk)
1524 if (!skip_set_rate && clk->ops->set_rate) 1524 if (!skip_set_rate && clk->ops->set_rate)
1525 clk->ops->set_rate(clk->hw, clk->new_rate, best_parent_rate); 1525 clk->ops->set_rate(clk->hw, clk->new_rate, best_parent_rate);
1526 1526
1527 if (clk->ops->recalc_rate) 1527 clk->rate = clk_recalc(clk, best_parent_rate);
1528 clk->rate = clk->ops->recalc_rate(clk->hw, best_parent_rate);
1529 else
1530 clk->rate = best_parent_rate;
1531 1528
1532 if (clk->notifier_count && old_rate != clk->rate) 1529 if (clk->notifier_count && old_rate != clk->rate)
1533 __clk_notify(clk, POST_RATE_CHANGE, old_rate, clk->rate); 1530 __clk_notify(clk, POST_RATE_CHANGE, old_rate, clk->rate);
@@ -1716,9 +1713,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
1716 if (!clk) 1713 if (!clk)
1717 return 0; 1714 return 0;
1718 1715
1719 if (!clk->ops)
1720 return -EINVAL;
1721
1722 /* verify ops for for multi-parent clks */ 1716 /* verify ops for for multi-parent clks */
1723 if ((clk->num_parents > 1) && (!clk->ops->set_parent)) 1717 if ((clk->num_parents > 1) && (!clk->ops->set_parent))
1724 return -ENOSYS; 1718 return -ENOSYS;
diff --git a/drivers/clk/clk.h b/drivers/clk/clk.h
index 795cc9f0dac0..c798138f023f 100644
--- a/drivers/clk/clk.h
+++ b/drivers/clk/clk.h
@@ -10,6 +10,7 @@
10 */ 10 */
11 11
12#if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK) 12#if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK)
13struct clk *of_clk_get_by_clkspec(struct of_phandle_args *clkspec);
13struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec); 14struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec);
14void of_clk_lock(void); 15void of_clk_lock(void);
15void of_clk_unlock(void); 16void of_clk_unlock(void);
diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index a360b2eca5cb..f890b901c6bc 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -27,6 +27,32 @@ static LIST_HEAD(clocks);
27static DEFINE_MUTEX(clocks_mutex); 27static DEFINE_MUTEX(clocks_mutex);
28 28
29#if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK) 29#if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK)
30
31/**
32 * of_clk_get_by_clkspec() - Lookup a clock form a clock provider
33 * @clkspec: pointer to a clock specifier data structure
34 *
35 * This function looks up a struct clk from the registered list of clock
36 * providers, an input is a clock specifier data structure as returned
37 * from the of_parse_phandle_with_args() function call.
38 */
39struct clk *of_clk_get_by_clkspec(struct of_phandle_args *clkspec)
40{
41 struct clk *clk;
42
43 if (!clkspec)
44 return ERR_PTR(-EINVAL);
45
46 of_clk_lock();
47 clk = __of_clk_get_from_provider(clkspec);
48
49 if (!IS_ERR(clk) && !__clk_get(clk))
50 clk = ERR_PTR(-ENOENT);
51
52 of_clk_unlock();
53 return clk;
54}
55
30struct clk *of_clk_get(struct device_node *np, int index) 56struct clk *of_clk_get(struct device_node *np, int index)
31{ 57{
32 struct of_phandle_args clkspec; 58 struct of_phandle_args clkspec;
@@ -41,13 +67,7 @@ struct clk *of_clk_get(struct device_node *np, int index)
41 if (rc) 67 if (rc)
42 return ERR_PTR(rc); 68 return ERR_PTR(rc);
43 69
44 of_clk_lock(); 70 clk = of_clk_get_by_clkspec(&clkspec);
45 clk = __of_clk_get_from_provider(&clkspec);
46
47 if (!IS_ERR(clk) && !__clk_get(clk))
48 clk = ERR_PTR(-ENOENT);
49
50 of_clk_unlock();
51 of_node_put(clkspec.np); 71 of_node_put(clkspec.np);
52 return clk; 72 return clk;
53} 73}
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 40b33c6a8257..038c02f4d0e7 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -6,3 +6,4 @@ obj-y += clk.o clkgate-separated.o
6 6
7obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o 7obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
8obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o 8obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
9obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
diff --git a/drivers/clk/hisilicon/clk-hix5hd2.c b/drivers/clk/hisilicon/clk-hix5hd2.c
new file mode 100644
index 000000000000..e5fcfb4e32ef
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hix5hd2.c
@@ -0,0 +1,101 @@
1/*
2 * Copyright (c) 2014 Linaro Ltd.
3 * Copyright (c) 2014 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10#include <linux/of_address.h>
11#include <dt-bindings/clock/hix5hd2-clock.h>
12#include "clk.h"
13
14static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] __initdata = {
15 { HIX5HD2_FIXED_1200M, "1200m", NULL, CLK_IS_ROOT, 1200000000, },
16 { HIX5HD2_FIXED_400M, "400m", NULL, CLK_IS_ROOT, 400000000, },
17 { HIX5HD2_FIXED_48M, "48m", NULL, CLK_IS_ROOT, 48000000, },
18 { HIX5HD2_FIXED_24M, "24m", NULL, CLK_IS_ROOT, 24000000, },
19 { HIX5HD2_FIXED_600M, "600m", NULL, CLK_IS_ROOT, 600000000, },
20 { HIX5HD2_FIXED_300M, "300m", NULL, CLK_IS_ROOT, 300000000, },
21 { HIX5HD2_FIXED_75M, "75m", NULL, CLK_IS_ROOT, 75000000, },
22 { HIX5HD2_FIXED_200M, "200m", NULL, CLK_IS_ROOT, 200000000, },
23 { HIX5HD2_FIXED_100M, "100m", NULL, CLK_IS_ROOT, 100000000, },
24 { HIX5HD2_FIXED_40M, "40m", NULL, CLK_IS_ROOT, 40000000, },
25 { HIX5HD2_FIXED_150M, "150m", NULL, CLK_IS_ROOT, 150000000, },
26 { HIX5HD2_FIXED_1728M, "1728m", NULL, CLK_IS_ROOT, 1728000000, },
27 { HIX5HD2_FIXED_28P8M, "28p8m", NULL, CLK_IS_ROOT, 28000000, },
28 { HIX5HD2_FIXED_432M, "432m", NULL, CLK_IS_ROOT, 432000000, },
29 { HIX5HD2_FIXED_345P6M, "345p6m", NULL, CLK_IS_ROOT, 345000000, },
30 { HIX5HD2_FIXED_288M, "288m", NULL, CLK_IS_ROOT, 288000000, },
31 { HIX5HD2_FIXED_60M, "60m", NULL, CLK_IS_ROOT, 60000000, },
32 { HIX5HD2_FIXED_750M, "750m", NULL, CLK_IS_ROOT, 750000000, },
33 { HIX5HD2_FIXED_500M, "500m", NULL, CLK_IS_ROOT, 500000000, },
34 { HIX5HD2_FIXED_54M, "54m", NULL, CLK_IS_ROOT, 54000000, },
35 { HIX5HD2_FIXED_27M, "27m", NULL, CLK_IS_ROOT, 27000000, },
36 { HIX5HD2_FIXED_1500M, "1500m", NULL, CLK_IS_ROOT, 1500000000, },
37 { HIX5HD2_FIXED_375M, "375m", NULL, CLK_IS_ROOT, 375000000, },
38 { HIX5HD2_FIXED_187M, "187m", NULL, CLK_IS_ROOT, 187000000, },
39 { HIX5HD2_FIXED_250M, "250m", NULL, CLK_IS_ROOT, 250000000, },
40 { HIX5HD2_FIXED_125M, "125m", NULL, CLK_IS_ROOT, 125000000, },
41 { HIX5HD2_FIXED_2P02M, "2m", NULL, CLK_IS_ROOT, 2000000, },
42 { HIX5HD2_FIXED_50M, "50m", NULL, CLK_IS_ROOT, 50000000, },
43 { HIX5HD2_FIXED_25M, "25m", NULL, CLK_IS_ROOT, 25000000, },
44 { HIX5HD2_FIXED_83M, "83m", NULL, CLK_IS_ROOT, 83333333, },
45};
46
47static const char *sfc_mux_p[] __initconst = {
48 "24m", "150m", "200m", "100m", "75m", };
49static u32 sfc_mux_table[] = {0, 4, 5, 6, 7};
50
51static const char *sdio1_mux_p[] __initconst = {
52 "75m", "100m", "50m", "15m", };
53static u32 sdio1_mux_table[] = {0, 1, 2, 3};
54
55static const char *fephy_mux_p[] __initconst = { "25m", "125m"};
56static u32 fephy_mux_table[] = {0, 1};
57
58
59static struct hisi_mux_clock hix5hd2_mux_clks[] __initdata = {
60 { HIX5HD2_SFC_MUX, "sfc_mux", sfc_mux_p, ARRAY_SIZE(sfc_mux_p),
61 CLK_SET_RATE_PARENT, 0x5c, 8, 3, 0, sfc_mux_table, },
62 { HIX5HD2_MMC_MUX, "mmc_mux", sdio1_mux_p, ARRAY_SIZE(sdio1_mux_p),
63 CLK_SET_RATE_PARENT, 0xa0, 8, 2, 0, sdio1_mux_table, },
64 { HIX5HD2_FEPHY_MUX, "fephy_mux",
65 fephy_mux_p, ARRAY_SIZE(fephy_mux_p),
66 CLK_SET_RATE_PARENT, 0x120, 8, 2, 0, fephy_mux_table, },
67};
68
69static struct hisi_gate_clock hix5hd2_gate_clks[] __initdata = {
70 /*sfc*/
71 { HIX5HD2_SFC_CLK, "clk_sfc", "sfc_mux",
72 CLK_SET_RATE_PARENT, 0x5c, 0, 0, },
73 { HIX5HD2_SFC_RST, "rst_sfc", "clk_sfc",
74 CLK_SET_RATE_PARENT, 0x5c, 4, CLK_GATE_SET_TO_DISABLE, },
75 /*sdio1*/
76 { HIX5HD2_MMC_BIU_CLK, "clk_mmc_biu", "200m",
77 CLK_SET_RATE_PARENT, 0xa0, 0, 0, },
78 { HIX5HD2_MMC_CIU_CLK, "clk_mmc_ciu", "mmc_mux",
79 CLK_SET_RATE_PARENT, 0xa0, 1, 0, },
80 { HIX5HD2_MMC_CIU_RST, "rst_mmc_ciu", "clk_mmc_ciu",
81 CLK_SET_RATE_PARENT, 0xa0, 4, CLK_GATE_SET_TO_DISABLE, },
82};
83
84static void __init hix5hd2_clk_init(struct device_node *np)
85{
86 struct hisi_clock_data *clk_data;
87
88 clk_data = hisi_clk_init(np, HIX5HD2_NR_CLKS);
89 if (!clk_data)
90 return;
91
92 hisi_clk_register_fixed_rate(hix5hd2_fixed_rate_clks,
93 ARRAY_SIZE(hix5hd2_fixed_rate_clks),
94 clk_data);
95 hisi_clk_register_mux(hix5hd2_mux_clks, ARRAY_SIZE(hix5hd2_mux_clks),
96 clk_data);
97 hisi_clk_register_gate(hix5hd2_gate_clks,
98 ARRAY_SIZE(hix5hd2_gate_clks), clk_data);
99}
100
101CLK_OF_DECLARE(hix5hd2_clk, "hisilicon,hix5hd2-clock", hix5hd2_clk_init);
diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c
index 276f672e7b1a..a078e84f7b05 100644
--- a/drivers/clk/hisilicon/clk.c
+++ b/drivers/clk/hisilicon/clk.c
@@ -127,11 +127,14 @@ void __init hisi_clk_register_mux(struct hisi_mux_clock *clks,
127 int i; 127 int i;
128 128
129 for (i = 0; i < nums; i++) { 129 for (i = 0; i < nums; i++) {
130 clk = clk_register_mux(NULL, clks[i].name, clks[i].parent_names, 130 u32 mask = BIT(clks[i].width) - 1;
131 clks[i].num_parents, clks[i].flags, 131
132 base + clks[i].offset, clks[i].shift, 132 clk = clk_register_mux_table(NULL, clks[i].name,
133 clks[i].width, clks[i].mux_flags, 133 clks[i].parent_names,
134 &hisi_clk_lock); 134 clks[i].num_parents, clks[i].flags,
135 base + clks[i].offset, clks[i].shift,
136 mask, clks[i].mux_flags,
137 clks[i].table, &hisi_clk_lock);
135 if (IS_ERR(clk)) { 138 if (IS_ERR(clk)) {
136 pr_err("%s: failed to register clock %s\n", 139 pr_err("%s: failed to register clock %s\n",
137 __func__, clks[i].name); 140 __func__, clks[i].name);
@@ -174,6 +177,34 @@ void __init hisi_clk_register_divider(struct hisi_divider_clock *clks,
174 } 177 }
175} 178}
176 179
180void __init hisi_clk_register_gate(struct hisi_gate_clock *clks,
181 int nums, struct hisi_clock_data *data)
182{
183 struct clk *clk;
184 void __iomem *base = data->base;
185 int i;
186
187 for (i = 0; i < nums; i++) {
188 clk = clk_register_gate(NULL, clks[i].name,
189 clks[i].parent_name,
190 clks[i].flags,
191 base + clks[i].offset,
192 clks[i].bit_idx,
193 clks[i].gate_flags,
194 &hisi_clk_lock);
195 if (IS_ERR(clk)) {
196 pr_err("%s: failed to register clock %s\n",
197 __func__, clks[i].name);
198 continue;
199 }
200
201 if (clks[i].alias)
202 clk_register_clkdev(clk, clks[i].alias, NULL);
203
204 data->clk_data.clks[clks[i].id] = clk;
205 }
206}
207
177void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *clks, 208void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *clks,
178 int nums, struct hisi_clock_data *data) 209 int nums, struct hisi_clock_data *data)
179{ 210{
diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h
index 43fa5da88f02..31083ffc0650 100644
--- a/drivers/clk/hisilicon/clk.h
+++ b/drivers/clk/hisilicon/clk.h
@@ -62,6 +62,7 @@ struct hisi_mux_clock {
62 u8 shift; 62 u8 shift;
63 u8 width; 63 u8 width;
64 u8 mux_flags; 64 u8 mux_flags;
65 u32 *table;
65 const char *alias; 66 const char *alias;
66}; 67};
67 68
@@ -103,6 +104,8 @@ void __init hisi_clk_register_mux(struct hisi_mux_clock *, int,
103 struct hisi_clock_data *); 104 struct hisi_clock_data *);
104void __init hisi_clk_register_divider(struct hisi_divider_clock *, 105void __init hisi_clk_register_divider(struct hisi_divider_clock *,
105 int, struct hisi_clock_data *); 106 int, struct hisi_clock_data *);
107void __init hisi_clk_register_gate(struct hisi_gate_clock *,
108 int, struct hisi_clock_data *);
106void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *, 109void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *,
107 int, struct hisi_clock_data *); 110 int, struct hisi_clock_data *);
108#endif /* __HISI_CLK_H */ 111#endif /* __HISI_CLK_H */
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 693f7be129f1..3b34dba9178d 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -34,3 +34,7 @@ config DOVE_CLK
34config KIRKWOOD_CLK 34config KIRKWOOD_CLK
35 bool 35 bool
36 select MVEBU_CLK_COMMON 36 select MVEBU_CLK_COMMON
37
38config ORION_CLK
39 bool
40 select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 4c66162fb0b4..a9a56fc01901 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_ARMADA_38X_CLK) += armada-38x.o
8obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o 8obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o
9obj-$(CONFIG_DOVE_CLK) += dove.o 9obj-$(CONFIG_DOVE_CLK) += dove.o
10obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o 10obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o
11obj-$(CONFIG_ORION_CLK) += orion.o
diff --git a/drivers/clk/mvebu/orion.c b/drivers/clk/mvebu/orion.c
new file mode 100644
index 000000000000..fd129566c1ce
--- /dev/null
+++ b/drivers/clk/mvebu/orion.c
@@ -0,0 +1,210 @@
1/*
2 * Marvell Orion SoC clocks
3 *
4 * Copyright (C) 2014 Thomas Petazzoni
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/clk-provider.h>
15#include <linux/io.h>
16#include <linux/of.h>
17#include "common.h"
18
19static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = {
20 { .id = 0, .name = "ddrclk", }
21};
22
23/*
24 * Orion 5182
25 */
26
27#define SAR_MV88F5182_TCLK_FREQ 8
28#define SAR_MV88F5182_TCLK_FREQ_MASK 0x3
29
30static u32 __init mv88f5182_get_tclk_freq(void __iomem *sar)
31{
32 u32 opt = (readl(sar) >> SAR_MV88F5182_TCLK_FREQ) &
33 SAR_MV88F5182_TCLK_FREQ_MASK;
34 if (opt == 1)
35 return 150000000;
36 else if (opt == 2)
37 return 166666667;
38 else
39 return 0;
40}
41
42#define SAR_MV88F5182_CPU_FREQ 4
43#define SAR_MV88F5182_CPU_FREQ_MASK 0xf
44
45static u32 __init mv88f5182_get_cpu_freq(void __iomem *sar)
46{
47 u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) &
48 SAR_MV88F5182_CPU_FREQ_MASK;
49 if (opt == 0)
50 return 333333333;
51 else if (opt == 1 || opt == 2)
52 return 400000000;
53 else if (opt == 3)
54 return 500000000;
55 else
56 return 0;
57}
58
59static void __init mv88f5182_get_clk_ratio(void __iomem *sar, int id,
60 int *mult, int *div)
61{
62 u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) &
63 SAR_MV88F5182_CPU_FREQ_MASK;
64 if (opt == 0 || opt == 1) {
65 *mult = 1;
66 *div = 2;
67 } else if (opt == 2 || opt == 3) {
68 *mult = 1;
69 *div = 3;
70 } else {
71 *mult = 0;
72 *div = 1;
73 }
74}
75
76static const struct coreclk_soc_desc mv88f5182_coreclks = {
77 .get_tclk_freq = mv88f5182_get_tclk_freq,
78 .get_cpu_freq = mv88f5182_get_cpu_freq,
79 .get_clk_ratio = mv88f5182_get_clk_ratio,
80 .ratios = orion_coreclk_ratios,
81 .num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
82};
83
84static void __init mv88f5182_clk_init(struct device_node *np)
85{
86 return mvebu_coreclk_setup(np, &mv88f5182_coreclks);
87}
88
89CLK_OF_DECLARE(mv88f5182_clk, "marvell,mv88f5182-core-clock", mv88f5182_clk_init);
90
91/*
92 * Orion 5281
93 */
94
95static u32 __init mv88f5281_get_tclk_freq(void __iomem *sar)
96{
97 /* On 5281, tclk is always 166 Mhz */
98 return 166666667;
99}
100
101#define SAR_MV88F5281_CPU_FREQ 4
102#define SAR_MV88F5281_CPU_FREQ_MASK 0xf
103
104static u32 __init mv88f5281_get_cpu_freq(void __iomem *sar)
105{
106 u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) &
107 SAR_MV88F5281_CPU_FREQ_MASK;
108 if (opt == 1 || opt == 2)
109 return 400000000;
110 else if (opt == 3)
111 return 500000000;
112 else
113 return 0;
114}
115
116static void __init mv88f5281_get_clk_ratio(void __iomem *sar, int id,
117 int *mult, int *div)
118{
119 u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) &
120 SAR_MV88F5281_CPU_FREQ_MASK;
121 if (opt == 1) {
122 *mult = 1;
123 *div = 2;
124 } else if (opt == 2 || opt == 3) {
125 *mult = 1;
126 *div = 3;
127 } else {
128 *mult = 0;
129 *div = 1;
130 }
131}
132
133static const struct coreclk_soc_desc mv88f5281_coreclks = {
134 .get_tclk_freq = mv88f5281_get_tclk_freq,
135 .get_cpu_freq = mv88f5281_get_cpu_freq,
136 .get_clk_ratio = mv88f5281_get_clk_ratio,
137 .ratios = orion_coreclk_ratios,
138 .num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
139};
140
141static void __init mv88f5281_clk_init(struct device_node *np)
142{
143 return mvebu_coreclk_setup(np, &mv88f5281_coreclks);
144}
145
146CLK_OF_DECLARE(mv88f5281_clk, "marvell,mv88f5281-core-clock", mv88f5281_clk_init);
147
148/*
149 * Orion 6183
150 */
151
152#define SAR_MV88F6183_TCLK_FREQ 9
153#define SAR_MV88F6183_TCLK_FREQ_MASK 0x1
154
155static u32 __init mv88f6183_get_tclk_freq(void __iomem *sar)
156{
157 u32 opt = (readl(sar) >> SAR_MV88F6183_TCLK_FREQ) &
158 SAR_MV88F6183_TCLK_FREQ_MASK;
159 if (opt == 0)
160 return 133333333;
161 else if (opt == 1)
162 return 166666667;
163 else
164 return 0;
165}
166
167#define SAR_MV88F6183_CPU_FREQ 1
168#define SAR_MV88F6183_CPU_FREQ_MASK 0x3f
169
170static u32 __init mv88f6183_get_cpu_freq(void __iomem *sar)
171{
172 u32 opt = (readl(sar) >> SAR_MV88F6183_CPU_FREQ) &
173 SAR_MV88F6183_CPU_FREQ_MASK;
174 if (opt == 9)
175 return 333333333;
176 else if (opt == 17)
177 return 400000000;
178 else
179 return 0;
180}
181
182static void __init mv88f6183_get_clk_ratio(void __iomem *sar, int id,
183 int *mult, int *div)
184{
185 u32 opt = (readl(sar) >> SAR_MV88F6183_CPU_FREQ) &
186 SAR_MV88F6183_CPU_FREQ_MASK;
187 if (opt == 9 || opt == 17) {
188 *mult = 1;
189 *div = 2;
190 } else {
191 *mult = 0;
192 *div = 1;
193 }
194}
195
196static const struct coreclk_soc_desc mv88f6183_coreclks = {
197 .get_tclk_freq = mv88f6183_get_tclk_freq,
198 .get_cpu_freq = mv88f6183_get_cpu_freq,
199 .get_clk_ratio = mv88f6183_get_clk_ratio,
200 .ratios = orion_coreclk_ratios,
201 .num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
202};
203
204
205static void __init mv88f6183_clk_init(struct device_node *np)
206{
207 return mvebu_coreclk_setup(np, &mv88f6183_coreclks);
208}
209
210CLK_OF_DECLARE(mv88f6183_clk, "marvell,mv88f6183-core-clock", mv88f6183_clk_init);
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 995bcfa021a4..7f696b7d4422 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -13,10 +13,10 @@ config MSM_GCC_8660
13 i2c, USB, SD/eMMC, etc. 13 i2c, USB, SD/eMMC, etc.
14 14
15config MSM_GCC_8960 15config MSM_GCC_8960
16 tristate "MSM8960 Global Clock Controller" 16 tristate "APQ8064/MSM8960 Global Clock Controller"
17 depends on COMMON_CLK_QCOM 17 depends on COMMON_CLK_QCOM
18 help 18 help
19 Support for the global clock controller on msm8960 devices. 19 Support for the global clock controller on apq8064/msm8960 devices.
20 Say Y if you want to use peripheral devices such as UART, SPI, 20 Say Y if you want to use peripheral devices such as UART, SPI,
21 i2c, USB, SD/eMMC, SATA, PCIe, etc. 21 i2c, USB, SD/eMMC, SATA, PCIe, etc.
22 22
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index f60db2ef1aee..689e05bf4f95 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -1,5 +1,6 @@
1obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o 1obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
2 2
3clk-qcom-y += common.o
3clk-qcom-y += clk-regmap.o 4clk-qcom-y += clk-regmap.o
4clk-qcom-y += clk-pll.o 5clk-qcom-y += clk-pll.o
5clk-qcom-y += clk-rcg.o 6clk-qcom-y += clk-rcg.o
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
new file mode 100644
index 000000000000..86b45fba5f90
--- /dev/null
+++ b/drivers/clk/qcom/common.c
@@ -0,0 +1,99 @@
1/*
2 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/export.h>
15#include <linux/regmap.h>
16#include <linux/platform_device.h>
17#include <linux/clk-provider.h>
18#include <linux/reset-controller.h>
19
20#include "common.h"
21#include "clk-regmap.h"
22#include "reset.h"
23
24struct qcom_cc {
25 struct qcom_reset_controller reset;
26 struct clk_onecell_data data;
27 struct clk *clks[];
28};
29
30int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
31{
32 void __iomem *base;
33 struct resource *res;
34 int i, ret;
35 struct device *dev = &pdev->dev;
36 struct clk *clk;
37 struct clk_onecell_data *data;
38 struct clk **clks;
39 struct regmap *regmap;
40 struct qcom_reset_controller *reset;
41 struct qcom_cc *cc;
42 size_t num_clks = desc->num_clks;
43 struct clk_regmap **rclks = desc->clks;
44
45 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
46 base = devm_ioremap_resource(dev, res);
47 if (IS_ERR(base))
48 return PTR_ERR(base);
49
50 regmap = devm_regmap_init_mmio(dev, base, desc->config);
51 if (IS_ERR(regmap))
52 return PTR_ERR(regmap);
53
54 cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
55 GFP_KERNEL);
56 if (!cc)
57 return -ENOMEM;
58
59 clks = cc->clks;
60 data = &cc->data;
61 data->clks = clks;
62 data->clk_num = num_clks;
63
64 for (i = 0; i < num_clks; i++) {
65 if (!rclks[i])
66 continue;
67 clk = devm_clk_register_regmap(dev, rclks[i]);
68 if (IS_ERR(clk))
69 return PTR_ERR(clk);
70 clks[i] = clk;
71 }
72
73 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);
74 if (ret)
75 return ret;
76
77 reset = &cc->reset;
78 reset->rcdev.of_node = dev->of_node;
79 reset->rcdev.ops = &qcom_reset_ops;
80 reset->rcdev.owner = dev->driver->owner;
81 reset->rcdev.nr_resets = desc->num_resets;
82 reset->regmap = regmap;
83 reset->reset_map = desc->resets;
84 platform_set_drvdata(pdev, &reset->rcdev);
85
86 ret = reset_controller_register(&reset->rcdev);
87 if (ret)
88 of_clk_del_provider(dev->of_node);
89
90 return ret;
91}
92EXPORT_SYMBOL_GPL(qcom_cc_probe);
93
94void qcom_cc_remove(struct platform_device *pdev)
95{
96 of_clk_del_provider(pdev->dev.of_node);
97 reset_controller_unregister(platform_get_drvdata(pdev));
98}
99EXPORT_SYMBOL_GPL(qcom_cc_remove);
diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
new file mode 100644
index 000000000000..2c3cfc860348
--- /dev/null
+++ b/drivers/clk/qcom/common.h
@@ -0,0 +1,34 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13#ifndef __QCOM_CLK_COMMON_H__
14#define __QCOM_CLK_COMMON_H__
15
16struct platform_device;
17struct regmap_config;
18struct clk_regmap;
19struct qcom_reset_map;
20
21struct qcom_cc_desc {
22 const struct regmap_config *config;
23 struct clk_regmap **clks;
24 size_t num_clks;
25 const struct qcom_reset_map *resets;
26 size_t num_resets;
27};
28
29extern int qcom_cc_probe(struct platform_device *pdev,
30 const struct qcom_cc_desc *desc);
31
32extern void qcom_cc_remove(struct platform_device *pdev);
33
34#endif
diff --git a/drivers/clk/qcom/gcc-msm8660.c b/drivers/clk/qcom/gcc-msm8660.c
index bc0b7f1fcfbe..0c4b727ae429 100644
--- a/drivers/clk/qcom/gcc-msm8660.c
+++ b/drivers/clk/qcom/gcc-msm8660.c
@@ -25,6 +25,7 @@
25#include <dt-bindings/clock/qcom,gcc-msm8660.h> 25#include <dt-bindings/clock/qcom,gcc-msm8660.h>
26#include <dt-bindings/reset/qcom,gcc-msm8660.h> 26#include <dt-bindings/reset/qcom,gcc-msm8660.h>
27 27
28#include "common.h"
28#include "clk-regmap.h" 29#include "clk-regmap.h"
29#include "clk-pll.h" 30#include "clk-pll.h"
30#include "clk-rcg.h" 31#include "clk-rcg.h"
@@ -2701,51 +2702,24 @@ static const struct regmap_config gcc_msm8660_regmap_config = {
2701 .fast_io = true, 2702 .fast_io = true,
2702}; 2703};
2703 2704
2705static const struct qcom_cc_desc gcc_msm8660_desc = {
2706 .config = &gcc_msm8660_regmap_config,
2707 .clks = gcc_msm8660_clks,
2708 .num_clks = ARRAY_SIZE(gcc_msm8660_clks),
2709 .resets = gcc_msm8660_resets,
2710 .num_resets = ARRAY_SIZE(gcc_msm8660_resets),
2711};
2712
2704static const struct of_device_id gcc_msm8660_match_table[] = { 2713static const struct of_device_id gcc_msm8660_match_table[] = {
2705 { .compatible = "qcom,gcc-msm8660" }, 2714 { .compatible = "qcom,gcc-msm8660" },
2706 { } 2715 { }
2707}; 2716};
2708MODULE_DEVICE_TABLE(of, gcc_msm8660_match_table); 2717MODULE_DEVICE_TABLE(of, gcc_msm8660_match_table);
2709 2718
2710struct qcom_cc {
2711 struct qcom_reset_controller reset;
2712 struct clk_onecell_data data;
2713 struct clk *clks[];
2714};
2715
2716static int gcc_msm8660_probe(struct platform_device *pdev) 2719static int gcc_msm8660_probe(struct platform_device *pdev)
2717{ 2720{
2718 void __iomem *base;
2719 struct resource *res;
2720 int i, ret;
2721 struct device *dev = &pdev->dev;
2722 struct clk *clk; 2721 struct clk *clk;
2723 struct clk_onecell_data *data; 2722 struct device *dev = &pdev->dev;
2724 struct clk **clks;
2725 struct regmap *regmap;
2726 size_t num_clks;
2727 struct qcom_reset_controller *reset;
2728 struct qcom_cc *cc;
2729
2730 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2731 base = devm_ioremap_resource(dev, res);
2732 if (IS_ERR(base))
2733 return PTR_ERR(base);
2734
2735 regmap = devm_regmap_init_mmio(dev, base, &gcc_msm8660_regmap_config);
2736 if (IS_ERR(regmap))
2737 return PTR_ERR(regmap);
2738
2739 num_clks = ARRAY_SIZE(gcc_msm8660_clks);
2740 cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
2741 GFP_KERNEL);
2742 if (!cc)
2743 return -ENOMEM;
2744
2745 clks = cc->clks;
2746 data = &cc->data;
2747 data->clks = clks;
2748 data->clk_num = num_clks;
2749 2723
2750 /* Temporary until RPM clocks supported */ 2724 /* Temporary until RPM clocks supported */
2751 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 19200000); 2725 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 19200000);
@@ -2756,39 +2730,12 @@ static int gcc_msm8660_probe(struct platform_device *pdev)
2756 if (IS_ERR(clk)) 2730 if (IS_ERR(clk))
2757 return PTR_ERR(clk); 2731 return PTR_ERR(clk);
2758 2732
2759 for (i = 0; i < num_clks; i++) { 2733 return qcom_cc_probe(pdev, &gcc_msm8660_desc);
2760 if (!gcc_msm8660_clks[i])
2761 continue;
2762 clk = devm_clk_register_regmap(dev, gcc_msm8660_clks[i]);
2763 if (IS_ERR(clk))
2764 return PTR_ERR(clk);
2765 clks[i] = clk;
2766 }
2767
2768 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);
2769 if (ret)
2770 return ret;
2771
2772 reset = &cc->reset;
2773 reset->rcdev.of_node = dev->of_node;
2774 reset->rcdev.ops = &qcom_reset_ops,
2775 reset->rcdev.owner = THIS_MODULE,
2776 reset->rcdev.nr_resets = ARRAY_SIZE(gcc_msm8660_resets),
2777 reset->regmap = regmap;
2778 reset->reset_map = gcc_msm8660_resets,
2779 platform_set_drvdata(pdev, &reset->rcdev);
2780
2781 ret = reset_controller_register(&reset->rcdev);
2782 if (ret)
2783 of_clk_del_provider(dev->of_node);
2784
2785 return ret;
2786} 2734}
2787 2735
2788static int gcc_msm8660_remove(struct platform_device *pdev) 2736static int gcc_msm8660_remove(struct platform_device *pdev)
2789{ 2737{
2790 of_clk_del_provider(pdev->dev.of_node); 2738 qcom_cc_remove(pdev);
2791 reset_controller_unregister(platform_get_drvdata(pdev));
2792 return 0; 2739 return 0;
2793} 2740}
2794 2741
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index fd446ab2fd98..f4ffd91901f8 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 2 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
3 * 3 *
4 * This software is licensed under the terms of the GNU General Public 4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and 5 * License version 2, as published by the Free Software Foundation, and
@@ -25,6 +25,7 @@
25#include <dt-bindings/clock/qcom,gcc-msm8960.h> 25#include <dt-bindings/clock/qcom,gcc-msm8960.h>
26#include <dt-bindings/reset/qcom,gcc-msm8960.h> 26#include <dt-bindings/reset/qcom,gcc-msm8960.h>
27 27
28#include "common.h"
28#include "clk-regmap.h" 29#include "clk-regmap.h"
29#include "clk-pll.h" 30#include "clk-pll.h"
30#include "clk-rcg.h" 31#include "clk-rcg.h"
@@ -2809,7 +2810,7 @@ static const struct qcom_reset_map gcc_msm8960_resets[] = {
2809 [PPSS_PROC_RESET] = { 0x2594, 1 }, 2810 [PPSS_PROC_RESET] = { 0x2594, 1 },
2810 [PPSS_RESET] = { 0x2594}, 2811 [PPSS_RESET] = { 0x2594},
2811 [DMA_BAM_RESET] = { 0x25c0, 7 }, 2812 [DMA_BAM_RESET] = { 0x25c0, 7 },
2812 [SIC_TIC_RESET] = { 0x2600, 7 }, 2813 [SPS_TIC_H_RESET] = { 0x2600, 7 },
2813 [SLIMBUS_H_RESET] = { 0x2620, 7 }, 2814 [SLIMBUS_H_RESET] = { 0x2620, 7 },
2814 [SFAB_CFPB_M_RESET] = { 0x2680, 7 }, 2815 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
2815 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 }, 2816 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
@@ -2822,7 +2823,7 @@ static const struct qcom_reset_map gcc_msm8960_resets[] = {
2822 [SFAB_SFPB_M_RESET] = { 0x2780, 7 }, 2823 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
2823 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 }, 2824 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
2824 [RPM_PROC_RESET] = { 0x27c0, 7 }, 2825 [RPM_PROC_RESET] = { 0x27c0, 7 },
2825 [PMIC_SSBI2_RESET] = { 0x270c, 12 }, 2826 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
2826 [SDC1_RESET] = { 0x2830 }, 2827 [SDC1_RESET] = { 0x2830 },
2827 [SDC2_RESET] = { 0x2850 }, 2828 [SDC2_RESET] = { 0x2850 },
2828 [SDC3_RESET] = { 0x2870 }, 2829 [SDC3_RESET] = { 0x2870 },
@@ -2867,6 +2868,16 @@ static const struct qcom_reset_map gcc_msm8960_resets[] = {
2867 [RIVA_RESET] = { 0x35e0 }, 2868 [RIVA_RESET] = { 0x35e0 },
2868}; 2869};
2869 2870
2871static struct clk_regmap *gcc_apq8064_clks[] = {
2872 [PLL8] = &pll8.clkr,
2873 [PLL8_VOTE] = &pll8_vote,
2874 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2875 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
2876 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2877 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
2878 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
2879};
2880
2870static const struct regmap_config gcc_msm8960_regmap_config = { 2881static const struct regmap_config gcc_msm8960_regmap_config = {
2871 .reg_bits = 32, 2882 .reg_bits = 32,
2872 .reg_stride = 4, 2883 .reg_stride = 4,
@@ -2875,51 +2886,38 @@ static const struct regmap_config gcc_msm8960_regmap_config = {
2875 .fast_io = true, 2886 .fast_io = true,
2876}; 2887};
2877 2888
2889static const struct qcom_cc_desc gcc_msm8960_desc = {
2890 .config = &gcc_msm8960_regmap_config,
2891 .clks = gcc_msm8960_clks,
2892 .num_clks = ARRAY_SIZE(gcc_msm8960_clks),
2893 .resets = gcc_msm8960_resets,
2894 .num_resets = ARRAY_SIZE(gcc_msm8960_resets),
2895};
2896
2897static const struct qcom_cc_desc gcc_apq8064_desc = {
2898 .config = &gcc_msm8960_regmap_config,
2899 .clks = gcc_apq8064_clks,
2900 .num_clks = ARRAY_SIZE(gcc_apq8064_clks),
2901 .resets = gcc_msm8960_resets,
2902 .num_resets = ARRAY_SIZE(gcc_msm8960_resets),
2903};
2904
2878static const struct of_device_id gcc_msm8960_match_table[] = { 2905static const struct of_device_id gcc_msm8960_match_table[] = {
2879 { .compatible = "qcom,gcc-msm8960" }, 2906 { .compatible = "qcom,gcc-msm8960", .data = &gcc_msm8960_desc },
2907 { .compatible = "qcom,gcc-apq8064", .data = &gcc_apq8064_desc },
2880 { } 2908 { }
2881}; 2909};
2882MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table); 2910MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table);
2883 2911
2884struct qcom_cc {
2885 struct qcom_reset_controller reset;
2886 struct clk_onecell_data data;
2887 struct clk *clks[];
2888};
2889
2890static int gcc_msm8960_probe(struct platform_device *pdev) 2912static int gcc_msm8960_probe(struct platform_device *pdev)
2891{ 2913{
2892 void __iomem *base;
2893 struct resource *res;
2894 int i, ret;
2895 struct device *dev = &pdev->dev;
2896 struct clk *clk; 2914 struct clk *clk;
2897 struct clk_onecell_data *data; 2915 struct device *dev = &pdev->dev;
2898 struct clk **clks; 2916 const struct of_device_id *match;
2899 struct regmap *regmap; 2917
2900 size_t num_clks; 2918 match = of_match_device(gcc_msm8960_match_table, &pdev->dev);
2901 struct qcom_reset_controller *reset; 2919 if (!match)
2902 struct qcom_cc *cc; 2920 return -EINVAL;
2903
2904 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2905 base = devm_ioremap_resource(dev, res);
2906 if (IS_ERR(base))
2907 return PTR_ERR(base);
2908
2909 regmap = devm_regmap_init_mmio(dev, base, &gcc_msm8960_regmap_config);
2910 if (IS_ERR(regmap))
2911 return PTR_ERR(regmap);
2912
2913 num_clks = ARRAY_SIZE(gcc_msm8960_clks);
2914 cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
2915 GFP_KERNEL);
2916 if (!cc)
2917 return -ENOMEM;
2918
2919 clks = cc->clks;
2920 data = &cc->data;
2921 data->clks = clks;
2922 data->clk_num = num_clks;
2923 2921
2924 /* Temporary until RPM clocks supported */ 2922 /* Temporary until RPM clocks supported */
2925 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 19200000); 2923 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 19200000);
@@ -2930,39 +2928,12 @@ static int gcc_msm8960_probe(struct platform_device *pdev)
2930 if (IS_ERR(clk)) 2928 if (IS_ERR(clk))
2931 return PTR_ERR(clk); 2929 return PTR_ERR(clk);
2932 2930
2933 for (i = 0; i < num_clks; i++) { 2931 return qcom_cc_probe(pdev, match->data);
2934 if (!gcc_msm8960_clks[i])
2935 continue;
2936 clk = devm_clk_register_regmap(dev, gcc_msm8960_clks[i]);
2937 if (IS_ERR(clk))
2938 return PTR_ERR(clk);
2939 clks[i] = clk;
2940 }
2941
2942 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);
2943 if (ret)
2944 return ret;
2945
2946 reset = &cc->reset;
2947 reset->rcdev.of_node = dev->of_node;
2948 reset->rcdev.ops = &qcom_reset_ops,
2949 reset->rcdev.owner = THIS_MODULE,
2950 reset->rcdev.nr_resets = ARRAY_SIZE(gcc_msm8960_resets),
2951 reset->regmap = regmap;
2952 reset->reset_map = gcc_msm8960_resets,
2953 platform_set_drvdata(pdev, &reset->rcdev);
2954
2955 ret = reset_controller_register(&reset->rcdev);
2956 if (ret)
2957 of_clk_del_provider(dev->of_node);
2958
2959 return ret;
2960} 2932}
2961 2933
2962static int gcc_msm8960_remove(struct platform_device *pdev) 2934static int gcc_msm8960_remove(struct platform_device *pdev)
2963{ 2935{
2964 of_clk_del_provider(pdev->dev.of_node); 2936 qcom_cc_remove(pdev);
2965 reset_controller_unregister(platform_get_drvdata(pdev));
2966 return 0; 2937 return 0;
2967} 2938}
2968 2939
diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
index 51d457e2b959..0d1edc1e9b31 100644
--- a/drivers/clk/qcom/gcc-msm8974.c
+++ b/drivers/clk/qcom/gcc-msm8974.c
@@ -25,6 +25,7 @@
25#include <dt-bindings/clock/qcom,gcc-msm8974.h> 25#include <dt-bindings/clock/qcom,gcc-msm8974.h>
26#include <dt-bindings/reset/qcom,gcc-msm8974.h> 26#include <dt-bindings/reset/qcom,gcc-msm8974.h>
27 27
28#include "common.h"
28#include "clk-regmap.h" 29#include "clk-regmap.h"
29#include "clk-pll.h" 30#include "clk-pll.h"
30#include "clk-rcg.h" 31#include "clk-rcg.h"
@@ -2574,51 +2575,24 @@ static const struct regmap_config gcc_msm8974_regmap_config = {
2574 .fast_io = true, 2575 .fast_io = true,
2575}; 2576};
2576 2577
2578static const struct qcom_cc_desc gcc_msm8974_desc = {
2579 .config = &gcc_msm8974_regmap_config,
2580 .clks = gcc_msm8974_clocks,
2581 .num_clks = ARRAY_SIZE(gcc_msm8974_clocks),
2582 .resets = gcc_msm8974_resets,
2583 .num_resets = ARRAY_SIZE(gcc_msm8974_resets),
2584};
2585
2577static const struct of_device_id gcc_msm8974_match_table[] = { 2586static const struct of_device_id gcc_msm8974_match_table[] = {
2578 { .compatible = "qcom,gcc-msm8974" }, 2587 { .compatible = "qcom,gcc-msm8974" },
2579 { } 2588 { }
2580}; 2589};
2581MODULE_DEVICE_TABLE(of, gcc_msm8974_match_table); 2590MODULE_DEVICE_TABLE(of, gcc_msm8974_match_table);
2582 2591
2583struct qcom_cc {
2584 struct qcom_reset_controller reset;
2585 struct clk_onecell_data data;
2586 struct clk *clks[];
2587};
2588
2589static int gcc_msm8974_probe(struct platform_device *pdev) 2592static int gcc_msm8974_probe(struct platform_device *pdev)
2590{ 2593{
2591 void __iomem *base;
2592 struct resource *res;
2593 int i, ret;
2594 struct device *dev = &pdev->dev;
2595 struct clk *clk; 2594 struct clk *clk;
2596 struct clk_onecell_data *data; 2595 struct device *dev = &pdev->dev;
2597 struct clk **clks;
2598 struct regmap *regmap;
2599 size_t num_clks;
2600 struct qcom_reset_controller *reset;
2601 struct qcom_cc *cc;
2602
2603 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2604 base = devm_ioremap_resource(dev, res);
2605 if (IS_ERR(base))
2606 return PTR_ERR(base);
2607
2608 regmap = devm_regmap_init_mmio(dev, base, &gcc_msm8974_regmap_config);
2609 if (IS_ERR(regmap))
2610 return PTR_ERR(regmap);
2611
2612 num_clks = ARRAY_SIZE(gcc_msm8974_clocks);
2613 cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
2614 GFP_KERNEL);
2615 if (!cc)
2616 return -ENOMEM;
2617
2618 clks = cc->clks;
2619 data = &cc->data;
2620 data->clks = clks;
2621 data->clk_num = num_clks;
2622 2596
2623 /* Temporary until RPM clocks supported */ 2597 /* Temporary until RPM clocks supported */
2624 clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000); 2598 clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000);
@@ -2631,39 +2605,12 @@ static int gcc_msm8974_probe(struct platform_device *pdev)
2631 if (IS_ERR(clk)) 2605 if (IS_ERR(clk))
2632 return PTR_ERR(clk); 2606 return PTR_ERR(clk);
2633 2607
2634 for (i = 0; i < num_clks; i++) { 2608 return qcom_cc_probe(pdev, &gcc_msm8974_desc);
2635 if (!gcc_msm8974_clocks[i])
2636 continue;
2637 clk = devm_clk_register_regmap(dev, gcc_msm8974_clocks[i]);
2638 if (IS_ERR(clk))
2639 return PTR_ERR(clk);
2640 clks[i] = clk;
2641 }
2642
2643 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);
2644 if (ret)
2645 return ret;
2646
2647 reset = &cc->reset;
2648 reset->rcdev.of_node = dev->of_node;
2649 reset->rcdev.ops = &qcom_reset_ops,
2650 reset->rcdev.owner = THIS_MODULE,
2651 reset->rcdev.nr_resets = ARRAY_SIZE(gcc_msm8974_resets),
2652 reset->regmap = regmap;
2653 reset->reset_map = gcc_msm8974_resets,
2654 platform_set_drvdata(pdev, &reset->rcdev);
2655
2656 ret = reset_controller_register(&reset->rcdev);
2657 if (ret)
2658 of_clk_del_provider(dev->of_node);
2659
2660 return ret;
2661} 2609}
2662 2610
2663static int gcc_msm8974_remove(struct platform_device *pdev) 2611static int gcc_msm8974_remove(struct platform_device *pdev)
2664{ 2612{
2665 of_clk_del_provider(pdev->dev.of_node); 2613 qcom_cc_remove(pdev);
2666 reset_controller_unregister(platform_get_drvdata(pdev));
2667 return 0; 2614 return 0;
2668} 2615}
2669 2616
diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c
index f9b59c7e48e9..12f3c0b64fcd 100644
--- a/drivers/clk/qcom/mmcc-msm8960.c
+++ b/drivers/clk/qcom/mmcc-msm8960.c
@@ -26,6 +26,7 @@
26#include <dt-bindings/clock/qcom,mmcc-msm8960.h> 26#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
27#include <dt-bindings/reset/qcom,mmcc-msm8960.h> 27#include <dt-bindings/reset/qcom,mmcc-msm8960.h>
28 28
29#include "common.h"
29#include "clk-regmap.h" 30#include "clk-regmap.h"
30#include "clk-pll.h" 31#include "clk-pll.h"
31#include "clk-rcg.h" 32#include "clk-rcg.h"
@@ -2222,85 +2223,28 @@ static const struct regmap_config mmcc_msm8960_regmap_config = {
2222 .fast_io = true, 2223 .fast_io = true,
2223}; 2224};
2224 2225
2226static const struct qcom_cc_desc mmcc_msm8960_desc = {
2227 .config = &mmcc_msm8960_regmap_config,
2228 .clks = mmcc_msm8960_clks,
2229 .num_clks = ARRAY_SIZE(mmcc_msm8960_clks),
2230 .resets = mmcc_msm8960_resets,
2231 .num_resets = ARRAY_SIZE(mmcc_msm8960_resets),
2232};
2233
2225static const struct of_device_id mmcc_msm8960_match_table[] = { 2234static const struct of_device_id mmcc_msm8960_match_table[] = {
2226 { .compatible = "qcom,mmcc-msm8960" }, 2235 { .compatible = "qcom,mmcc-msm8960" },
2227 { } 2236 { }
2228}; 2237};
2229MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table); 2238MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table);
2230 2239
2231struct qcom_cc {
2232 struct qcom_reset_controller reset;
2233 struct clk_onecell_data data;
2234 struct clk *clks[];
2235};
2236
2237static int mmcc_msm8960_probe(struct platform_device *pdev) 2240static int mmcc_msm8960_probe(struct platform_device *pdev)
2238{ 2241{
2239 void __iomem *base; 2242 return qcom_cc_probe(pdev, &mmcc_msm8960_desc);
2240 struct resource *res;
2241 int i, ret;
2242 struct device *dev = &pdev->dev;
2243 struct clk *clk;
2244 struct clk_onecell_data *data;
2245 struct clk **clks;
2246 struct regmap *regmap;
2247 size_t num_clks;
2248 struct qcom_reset_controller *reset;
2249 struct qcom_cc *cc;
2250
2251 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2252 base = devm_ioremap_resource(dev, res);
2253 if (IS_ERR(base))
2254 return PTR_ERR(base);
2255
2256 regmap = devm_regmap_init_mmio(dev, base, &mmcc_msm8960_regmap_config);
2257 if (IS_ERR(regmap))
2258 return PTR_ERR(regmap);
2259
2260 num_clks = ARRAY_SIZE(mmcc_msm8960_clks);
2261 cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
2262 GFP_KERNEL);
2263 if (!cc)
2264 return -ENOMEM;
2265
2266 clks = cc->clks;
2267 data = &cc->data;
2268 data->clks = clks;
2269 data->clk_num = num_clks;
2270
2271 for (i = 0; i < num_clks; i++) {
2272 if (!mmcc_msm8960_clks[i])
2273 continue;
2274 clk = devm_clk_register_regmap(dev, mmcc_msm8960_clks[i]);
2275 if (IS_ERR(clk))
2276 return PTR_ERR(clk);
2277 clks[i] = clk;
2278 }
2279
2280 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);
2281 if (ret)
2282 return ret;
2283
2284 reset = &cc->reset;
2285 reset->rcdev.of_node = dev->of_node;
2286 reset->rcdev.ops = &qcom_reset_ops,
2287 reset->rcdev.owner = THIS_MODULE,
2288 reset->rcdev.nr_resets = ARRAY_SIZE(mmcc_msm8960_resets),
2289 reset->regmap = regmap;
2290 reset->reset_map = mmcc_msm8960_resets,
2291 platform_set_drvdata(pdev, &reset->rcdev);
2292
2293 ret = reset_controller_register(&reset->rcdev);
2294 if (ret)
2295 of_clk_del_provider(dev->of_node);
2296
2297 return ret;
2298} 2243}
2299 2244
2300static int mmcc_msm8960_remove(struct platform_device *pdev) 2245static int mmcc_msm8960_remove(struct platform_device *pdev)
2301{ 2246{
2302 of_clk_del_provider(pdev->dev.of_node); 2247 qcom_cc_remove(pdev);
2303 reset_controller_unregister(platform_get_drvdata(pdev));
2304 return 0; 2248 return 0;
2305} 2249}
2306 2250
diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
index c95774514b81..60b7c24a5cd6 100644
--- a/drivers/clk/qcom/mmcc-msm8974.c
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -25,6 +25,7 @@
25#include <dt-bindings/clock/qcom,mmcc-msm8974.h> 25#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
26#include <dt-bindings/reset/qcom,mmcc-msm8974.h> 26#include <dt-bindings/reset/qcom,mmcc-msm8974.h>
27 27
28#include "common.h"
28#include "clk-regmap.h" 29#include "clk-regmap.h"
29#include "clk-pll.h" 30#include "clk-pll.h"
30#include "clk-rcg.h" 31#include "clk-rcg.h"
@@ -2524,88 +2525,39 @@ static const struct regmap_config mmcc_msm8974_regmap_config = {
2524 .fast_io = true, 2525 .fast_io = true,
2525}; 2526};
2526 2527
2528static const struct qcom_cc_desc mmcc_msm8974_desc = {
2529 .config = &mmcc_msm8974_regmap_config,
2530 .clks = mmcc_msm8974_clocks,
2531 .num_clks = ARRAY_SIZE(mmcc_msm8974_clocks),
2532 .resets = mmcc_msm8974_resets,
2533 .num_resets = ARRAY_SIZE(mmcc_msm8974_resets),
2534};
2535
2527static const struct of_device_id mmcc_msm8974_match_table[] = { 2536static const struct of_device_id mmcc_msm8974_match_table[] = {
2528 { .compatible = "qcom,mmcc-msm8974" }, 2537 { .compatible = "qcom,mmcc-msm8974" },
2529 { } 2538 { }
2530}; 2539};
2531MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table); 2540MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table);
2532 2541
2533struct qcom_cc {
2534 struct qcom_reset_controller reset;
2535 struct clk_onecell_data data;
2536 struct clk *clks[];
2537};
2538
2539static int mmcc_msm8974_probe(struct platform_device *pdev) 2542static int mmcc_msm8974_probe(struct platform_device *pdev)
2540{ 2543{
2541 void __iomem *base; 2544 int ret;
2542 struct resource *res;
2543 int i, ret;
2544 struct device *dev = &pdev->dev;
2545 struct clk *clk;
2546 struct clk_onecell_data *data;
2547 struct clk **clks;
2548 struct regmap *regmap; 2545 struct regmap *regmap;
2549 size_t num_clks;
2550 struct qcom_reset_controller *reset;
2551 struct qcom_cc *cc;
2552
2553 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2554 base = devm_ioremap_resource(dev, res);
2555 if (IS_ERR(base))
2556 return PTR_ERR(base);
2557
2558 regmap = devm_regmap_init_mmio(dev, base, &mmcc_msm8974_regmap_config);
2559 if (IS_ERR(regmap))
2560 return PTR_ERR(regmap);
2561
2562 num_clks = ARRAY_SIZE(mmcc_msm8974_clocks);
2563 cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
2564 GFP_KERNEL);
2565 if (!cc)
2566 return -ENOMEM;
2567
2568 clks = cc->clks;
2569 data = &cc->data;
2570 data->clks = clks;
2571 data->clk_num = num_clks;
2572
2573 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
2574 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
2575 2546
2576 for (i = 0; i < num_clks; i++) { 2547 ret = qcom_cc_probe(pdev, &mmcc_msm8974_desc);
2577 if (!mmcc_msm8974_clocks[i])
2578 continue;
2579 clk = devm_clk_register_regmap(dev, mmcc_msm8974_clocks[i]);
2580 if (IS_ERR(clk))
2581 return PTR_ERR(clk);
2582 clks[i] = clk;
2583 }
2584
2585 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);
2586 if (ret) 2548 if (ret)
2587 return ret; 2549 return ret;
2588 2550
2589 reset = &cc->reset; 2551 regmap = dev_get_regmap(&pdev->dev, NULL);
2590 reset->rcdev.of_node = dev->of_node; 2552 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
2591 reset->rcdev.ops = &qcom_reset_ops, 2553 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
2592 reset->rcdev.owner = THIS_MODULE,
2593 reset->rcdev.nr_resets = ARRAY_SIZE(mmcc_msm8974_resets),
2594 reset->regmap = regmap;
2595 reset->reset_map = mmcc_msm8974_resets,
2596 platform_set_drvdata(pdev, &reset->rcdev);
2597
2598 ret = reset_controller_register(&reset->rcdev);
2599 if (ret)
2600 of_clk_del_provider(dev->of_node);
2601 2554
2602 return ret; 2555 return 0;
2603} 2556}
2604 2557
2605static int mmcc_msm8974_remove(struct platform_device *pdev) 2558static int mmcc_msm8974_remove(struct platform_device *pdev)
2606{ 2559{
2607 of_clk_del_provider(pdev->dev.of_node); 2560 qcom_cc_remove(pdev);
2608 reset_controller_unregister(platform_get_drvdata(pdev));
2609 return 0; 2561 return 0;
2610} 2562}
2611 2563
diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
index 5404cb931ebf..e0029237827a 100644
--- a/drivers/clk/shmobile/Makefile
+++ b/drivers/clk/shmobile/Makefile
@@ -1,5 +1,7 @@
1obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o 1obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o
2obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o 2obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o
3obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o
4obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o
3obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o 5obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o
4obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o 6obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o
5obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-div6.o 7obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-div6.o
diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c
index 1f6324e29a80..2d2fe773ac81 100644
--- a/drivers/clk/shmobile/clk-mstp.c
+++ b/drivers/clk/shmobile/clk-mstp.c
@@ -112,7 +112,7 @@ static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
112 else 112 else
113 value = clk_readl(group->smstpcr); 113 value = clk_readl(group->smstpcr);
114 114
115 return !!(value & BIT(clock->bit_index)); 115 return !(value & BIT(clock->bit_index));
116} 116}
117 117
118static const struct clk_ops cpg_mstp_clock_ops = { 118static const struct clk_ops cpg_mstp_clock_ops = {
diff --git a/drivers/clk/shmobile/clk-r8a7740.c b/drivers/clk/shmobile/clk-r8a7740.c
new file mode 100644
index 000000000000..1e2eaae21e01
--- /dev/null
+++ b/drivers/clk/shmobile/clk-r8a7740.c
@@ -0,0 +1,199 @@
1/*
2 * r8a7740 Core CPG Clocks
3 *
4 * Copyright (C) 2014 Ulrich Hecht
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/shmobile.h>
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/spinlock.h>
19
20struct r8a7740_cpg {
21 struct clk_onecell_data data;
22 spinlock_t lock;
23 void __iomem *reg;
24};
25
26#define CPG_FRQCRA 0x00
27#define CPG_FRQCRB 0x04
28#define CPG_PLLC2CR 0x2c
29#define CPG_USBCKCR 0x8c
30#define CPG_FRQCRC 0xe0
31
32#define CLK_ENABLE_ON_INIT BIT(0)
33
34struct div4_clk {
35 const char *name;
36 unsigned int reg;
37 unsigned int shift;
38 int flags;
39};
40
41static struct div4_clk div4_clks[] = {
42 { "i", CPG_FRQCRA, 20, CLK_ENABLE_ON_INIT },
43 { "zg", CPG_FRQCRA, 16, CLK_ENABLE_ON_INIT },
44 { "b", CPG_FRQCRA, 8, CLK_ENABLE_ON_INIT },
45 { "m1", CPG_FRQCRA, 4, CLK_ENABLE_ON_INIT },
46 { "hp", CPG_FRQCRB, 4, 0 },
47 { "hpp", CPG_FRQCRC, 20, 0 },
48 { "usbp", CPG_FRQCRC, 16, 0 },
49 { "s", CPG_FRQCRC, 12, 0 },
50 { "zb", CPG_FRQCRC, 8, 0 },
51 { "m3", CPG_FRQCRC, 4, 0 },
52 { "cp", CPG_FRQCRC, 0, 0 },
53 { NULL, 0, 0, 0 },
54};
55
56static const struct clk_div_table div4_div_table[] = {
57 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
58 { 6, 16 }, { 7, 18 }, { 8, 24 }, { 9, 32 }, { 10, 36 }, { 11, 48 },
59 { 13, 72 }, { 14, 96 }, { 0, 0 }
60};
61
62static u32 cpg_mode __initdata;
63
64static struct clk * __init
65r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg,
66 const char *name)
67{
68 const struct clk_div_table *table = NULL;
69 const char *parent_name;
70 unsigned int shift, reg;
71 unsigned int mult = 1;
72 unsigned int div = 1;
73
74 if (!strcmp(name, "r")) {
75 switch (cpg_mode & (BIT(2) | BIT(1))) {
76 case BIT(1) | BIT(2):
77 /* extal1 */
78 parent_name = of_clk_get_parent_name(np, 0);
79 div = 2048;
80 break;
81 case BIT(2):
82 /* extal1 */
83 parent_name = of_clk_get_parent_name(np, 0);
84 div = 1024;
85 break;
86 default:
87 /* extalr */
88 parent_name = of_clk_get_parent_name(np, 2);
89 break;
90 }
91 } else if (!strcmp(name, "system")) {
92 parent_name = of_clk_get_parent_name(np, 0);
93 if (cpg_mode & BIT(1))
94 div = 2;
95 } else if (!strcmp(name, "pllc0")) {
96 /* PLLC0/1 are configurable multiplier clocks. Register them as
97 * fixed factor clocks for now as there's no generic multiplier
98 * clock implementation and we currently have no need to change
99 * the multiplier value.
100 */
101 u32 value = clk_readl(cpg->reg + CPG_FRQCRC);
102 parent_name = "system";
103 mult = ((value >> 24) & 0x7f) + 1;
104 } else if (!strcmp(name, "pllc1")) {
105 u32 value = clk_readl(cpg->reg + CPG_FRQCRA);
106 parent_name = "system";
107 mult = ((value >> 24) & 0x7f) + 1;
108 div = 2;
109 } else if (!strcmp(name, "pllc2")) {
110 u32 value = clk_readl(cpg->reg + CPG_PLLC2CR);
111 parent_name = "system";
112 mult = ((value >> 24) & 0x3f) + 1;
113 } else if (!strcmp(name, "usb24s")) {
114 u32 value = clk_readl(cpg->reg + CPG_USBCKCR);
115 if (value & BIT(7))
116 /* extal2 */
117 parent_name = of_clk_get_parent_name(np, 1);
118 else
119 parent_name = "system";
120 if (!(value & BIT(6)))
121 div = 2;
122 } else {
123 struct div4_clk *c;
124 for (c = div4_clks; c->name; c++) {
125 if (!strcmp(name, c->name)) {
126 parent_name = "pllc1";
127 table = div4_div_table;
128 reg = c->reg;
129 shift = c->shift;
130 break;
131 }
132 }
133 if (!c->name)
134 return ERR_PTR(-EINVAL);
135 }
136
137 if (!table) {
138 return clk_register_fixed_factor(NULL, name, parent_name, 0,
139 mult, div);
140 } else {
141 return clk_register_divider_table(NULL, name, parent_name, 0,
142 cpg->reg + reg, shift, 4, 0,
143 table, &cpg->lock);
144 }
145}
146
147static void __init r8a7740_cpg_clocks_init(struct device_node *np)
148{
149 struct r8a7740_cpg *cpg;
150 struct clk **clks;
151 unsigned int i;
152 int num_clks;
153
154 if (of_property_read_u32(np, "renesas,mode", &cpg_mode))
155 pr_warn("%s: missing renesas,mode property\n", __func__);
156
157 num_clks = of_property_count_strings(np, "clock-output-names");
158 if (num_clks < 0) {
159 pr_err("%s: failed to count clocks\n", __func__);
160 return;
161 }
162
163 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
164 clks = kzalloc(num_clks * sizeof(*clks), GFP_KERNEL);
165 if (cpg == NULL || clks == NULL) {
166 /* We're leaking memory on purpose, there's no point in cleaning
167 * up as the system won't boot anyway.
168 */
169 return;
170 }
171
172 spin_lock_init(&cpg->lock);
173
174 cpg->data.clks = clks;
175 cpg->data.clk_num = num_clks;
176
177 cpg->reg = of_iomap(np, 0);
178 if (WARN_ON(cpg->reg == NULL))
179 return;
180
181 for (i = 0; i < num_clks; ++i) {
182 const char *name;
183 struct clk *clk;
184
185 of_property_read_string_index(np, "clock-output-names", i,
186 &name);
187
188 clk = r8a7740_cpg_register_clock(np, cpg, name);
189 if (IS_ERR(clk))
190 pr_err("%s: failed to register %s %s clock (%ld)\n",
191 __func__, np->name, name, PTR_ERR(clk));
192 else
193 cpg->data.clks[i] = clk;
194 }
195
196 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
197}
198CLK_OF_DECLARE(r8a7740_cpg_clks, "renesas,r8a7740-cpg-clocks",
199 r8a7740_cpg_clocks_init);
diff --git a/drivers/clk/shmobile/clk-r8a7779.c b/drivers/clk/shmobile/clk-r8a7779.c
new file mode 100644
index 000000000000..652ecacb6daf
--- /dev/null
+++ b/drivers/clk/shmobile/clk-r8a7779.c
@@ -0,0 +1,180 @@
1/*
2 * r8a7779 Core CPG Clocks
3 *
4 * Copyright (C) 2013, 2014 Horms Solutions Ltd.
5 *
6 * Contact: Simon Horman <horms@verge.net.au>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 */
12
13#include <linux/clk-provider.h>
14#include <linux/clkdev.h>
15#include <linux/clk/shmobile.h>
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/spinlock.h>
21
22#include <dt-bindings/clock/r8a7779-clock.h>
23
24#define CPG_NUM_CLOCKS (R8A7779_CLK_OUT + 1)
25
26struct r8a7779_cpg {
27 struct clk_onecell_data data;
28 spinlock_t lock;
29 void __iomem *reg;
30};
31
32/* -----------------------------------------------------------------------------
33 * CPG Clock Data
34 */
35
36/*
37 * MD1 = 1 MD1 = 0
38 * (PLLA = 1500) (PLLA = 1600)
39 * (MHz) (MHz)
40 *------------------------------------------------+--------------------
41 * clkz 1000 (2/3) 800 (1/2)
42 * clkzs 250 (1/6) 200 (1/8)
43 * clki 750 (1/2) 800 (1/2)
44 * clks 250 (1/6) 200 (1/8)
45 * clks1 125 (1/12) 100 (1/16)
46 * clks3 187.5 (1/8) 200 (1/8)
47 * clks4 93.7 (1/16) 100 (1/16)
48 * clkp 62.5 (1/24) 50 (1/32)
49 * clkg 62.5 (1/24) 66.6 (1/24)
50 * clkb, CLKOUT
51 * (MD2 = 0) 62.5 (1/24) 66.6 (1/24)
52 * (MD2 = 1) 41.6 (1/36) 50 (1/32)
53 */
54
55#define CPG_CLK_CONFIG_INDEX(md) (((md) & (BIT(2)|BIT(1))) >> 1)
56
57struct cpg_clk_config {
58 unsigned int z_mult;
59 unsigned int z_div;
60 unsigned int zs_and_s_div;
61 unsigned int s1_div;
62 unsigned int p_div;
63 unsigned int b_and_out_div;
64};
65
66static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
67 { 1, 2, 8, 16, 32, 24 },
68 { 2, 3, 6, 12, 24, 24 },
69 { 1, 2, 8, 16, 32, 32 },
70 { 2, 3, 6, 12, 24, 36 },
71};
72
73/*
74 * MD PLLA Ratio
75 * 12 11
76 *------------------------
77 * 0 0 x42
78 * 0 1 x48
79 * 1 0 x56
80 * 1 1 x64
81 */
82
83#define CPG_PLLA_MULT_INDEX(md) (((md) & (BIT(12)|BIT(11))) >> 11)
84
85static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64 };
86
87/* -----------------------------------------------------------------------------
88 * Initialization
89 */
90
91static u32 cpg_mode __initdata;
92
93static struct clk * __init
94r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg,
95 const struct cpg_clk_config *config,
96 unsigned int plla_mult, const char *name)
97{
98 const char *parent_name = "plla";
99 unsigned int mult = 1;
100 unsigned int div = 1;
101
102 if (!strcmp(name, "plla")) {
103 parent_name = of_clk_get_parent_name(np, 0);
104 mult = plla_mult;
105 } else if (!strcmp(name, "z")) {
106 div = config->z_div;
107 mult = config->z_mult;
108 } else if (!strcmp(name, "zs") || !strcmp(name, "s")) {
109 div = config->zs_and_s_div;
110 } else if (!strcmp(name, "s1")) {
111 div = config->s1_div;
112 } else if (!strcmp(name, "p")) {
113 div = config->p_div;
114 } else if (!strcmp(name, "b") || !strcmp(name, "out")) {
115 div = config->b_and_out_div;
116 } else {
117 return ERR_PTR(-EINVAL);
118 }
119
120 return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
121}
122
123static void __init r8a7779_cpg_clocks_init(struct device_node *np)
124{
125 const struct cpg_clk_config *config;
126 struct r8a7779_cpg *cpg;
127 struct clk **clks;
128 unsigned int i, plla_mult;
129 int num_clks;
130
131 num_clks = of_property_count_strings(np, "clock-output-names");
132 if (num_clks < 0) {
133 pr_err("%s: failed to count clocks\n", __func__);
134 return;
135 }
136
137 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
138 clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL);
139 if (cpg == NULL || clks == NULL) {
140 /* We're leaking memory on purpose, there's no point in cleaning
141 * up as the system won't boot anyway.
142 */
143 return;
144 }
145
146 spin_lock_init(&cpg->lock);
147
148 cpg->data.clks = clks;
149 cpg->data.clk_num = num_clks;
150
151 config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(cpg_mode)];
152 plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(cpg_mode)];
153
154 for (i = 0; i < num_clks; ++i) {
155 const char *name;
156 struct clk *clk;
157
158 of_property_read_string_index(np, "clock-output-names", i,
159 &name);
160
161 clk = r8a7779_cpg_register_clock(np, cpg, config,
162 plla_mult, name);
163 if (IS_ERR(clk))
164 pr_err("%s: failed to register %s %s clock (%ld)\n",
165 __func__, np->name, name, PTR_ERR(clk));
166 else
167 cpg->data.clks[i] = clk;
168 }
169
170 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
171}
172CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
173 r8a7779_cpg_clocks_init);
174
175void __init r8a7779_clocks_init(u32 mode)
176{
177 cpg_mode = mode;
178
179 of_clk_init(NULL);
180}
diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
index 501d513bf890..dd3a78c64795 100644
--- a/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -32,7 +32,6 @@
32#define SOCFPGA_MMC_CLK "sdmmc_clk" 32#define SOCFPGA_MMC_CLK "sdmmc_clk"
33#define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8 33#define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8
34 34
35#define div_mask(width) ((1 << (width)) - 1)
36#define streq(a, b) (strcmp((a), (b)) == 0) 35#define streq(a, b) (strcmp((a), (b)) == 0)
37 36
38#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw) 37#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
diff --git a/drivers/clk/socfpga/clk-periph.c b/drivers/clk/socfpga/clk-periph.c
index 81623a3736f9..46531c34ec9b 100644
--- a/drivers/clk/socfpga/clk-periph.c
+++ b/drivers/clk/socfpga/clk-periph.c
@@ -29,12 +29,18 @@ static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
29 unsigned long parent_rate) 29 unsigned long parent_rate)
30{ 30{
31 struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk); 31 struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk);
32 u32 div; 32 u32 div, val;
33 33
34 if (socfpgaclk->fixed_div) 34 if (socfpgaclk->fixed_div) {
35 div = socfpgaclk->fixed_div; 35 div = socfpgaclk->fixed_div;
36 else 36 } else {
37 if (socfpgaclk->div_reg) {
38 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
39 val &= div_mask(socfpgaclk->width);
40 parent_rate /= (val + 1);
41 }
37 div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1); 42 div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);
43 }
38 44
39 return parent_rate / div; 45 return parent_rate / div;
40} 46}
@@ -54,6 +60,7 @@ static __init void __socfpga_periph_init(struct device_node *node,
54 struct clk_init_data init; 60 struct clk_init_data init;
55 int rc; 61 int rc;
56 u32 fixed_div; 62 u32 fixed_div;
63 u32 div_reg[3];
57 64
58 of_property_read_u32(node, "reg", &reg); 65 of_property_read_u32(node, "reg", &reg);
59 66
@@ -63,6 +70,15 @@ static __init void __socfpga_periph_init(struct device_node *node,
63 70
64 periph_clk->hw.reg = clk_mgr_base_addr + reg; 71 periph_clk->hw.reg = clk_mgr_base_addr + reg;
65 72
73 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
74 if (!rc) {
75 periph_clk->div_reg = clk_mgr_base_addr + div_reg[0];
76 periph_clk->shift = div_reg[1];
77 periph_clk->width = div_reg[2];
78 } else {
79 periph_clk->div_reg = 0;
80 }
81
66 rc = of_property_read_u32(node, "fixed-divider", &fixed_div); 82 rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
67 if (rc) 83 if (rc)
68 periph_clk->fixed_div = 0; 84 periph_clk->fixed_div = 0;
diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
index d2e54019c94f..d291f60c46e1 100644
--- a/drivers/clk/socfpga/clk.h
+++ b/drivers/clk/socfpga/clk.h
@@ -27,6 +27,7 @@
27#define CLKMGR_PERPLL_SRC 0xAC 27#define CLKMGR_PERPLL_SRC 0xAC
28 28
29#define SOCFPGA_MAX_PARENTS 3 29#define SOCFPGA_MAX_PARENTS 3
30#define div_mask(width) ((1 << (width)) - 1)
30 31
31extern void __iomem *clk_mgr_base_addr; 32extern void __iomem *clk_mgr_base_addr;
32 33
@@ -52,6 +53,9 @@ struct socfpga_periph_clk {
52 struct clk_gate hw; 53 struct clk_gate hw;
53 char *parent_name; 54 char *parent_name;
54 u32 fixed_div; 55 u32 fixed_div;
56 void __iomem *div_reg;
57 u32 width; /* only valid if div_reg != 0 */
58 u32 shift; /* only valid if div_reg != 0 */
55}; 59};
56 60
57#endif /* SOCFPGA_CLK_H */ 61#endif /* SOCFPGA_CLK_H */
diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
index 9e232644f07e..3806d97e529b 100644
--- a/drivers/clk/sunxi/clk-factors.c
+++ b/drivers/clk/sunxi/clk-factors.c
@@ -77,6 +77,41 @@ static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate,
77 return rate; 77 return rate;
78} 78}
79 79
80static long clk_factors_determine_rate(struct clk_hw *hw, unsigned long rate,
81 unsigned long *best_parent_rate,
82 struct clk **best_parent_p)
83{
84 struct clk *clk = hw->clk, *parent, *best_parent = NULL;
85 int i, num_parents;
86 unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0;
87
88 /* find the parent that can help provide the fastest rate <= rate */
89 num_parents = __clk_get_num_parents(clk);
90 for (i = 0; i < num_parents; i++) {
91 parent = clk_get_parent_by_index(clk, i);
92 if (!parent)
93 continue;
94 if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT)
95 parent_rate = __clk_round_rate(parent, rate);
96 else
97 parent_rate = __clk_get_rate(parent);
98
99 child_rate = clk_factors_round_rate(hw, rate, &parent_rate);
100
101 if (child_rate <= rate && child_rate > best_child_rate) {
102 best_parent = parent;
103 best = parent_rate;
104 best_child_rate = child_rate;
105 }
106 }
107
108 if (best_parent)
109 *best_parent_p = best_parent;
110 *best_parent_rate = best;
111
112 return best_child_rate;
113}
114
80static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate, 115static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
81 unsigned long parent_rate) 116 unsigned long parent_rate)
82{ 117{
@@ -113,6 +148,7 @@ static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
113} 148}
114 149
115const struct clk_ops clk_factors_ops = { 150const struct clk_ops clk_factors_ops = {
151 .determine_rate = clk_factors_determine_rate,
116 .recalc_rate = clk_factors_recalc_rate, 152 .recalc_rate = clk_factors_recalc_rate,
117 .round_rate = clk_factors_round_rate, 153 .round_rate = clk_factors_round_rate,
118 .set_rate = clk_factors_set_rate, 154 .set_rate = clk_factors_set_rate,
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index bd7dc733c1ca..4cc2b2a5aa75 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -507,6 +507,43 @@ CLK_OF_DECLARE(sun7i_a20_gmac, "allwinner,sun7i-a20-gmac-clk",
507 507
508 508
509/** 509/**
510 * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
511 */
512
513void clk_sunxi_mmc_phase_control(struct clk *clk, u8 sample, u8 output)
514{
515 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
516 #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
517
518 struct clk_hw *hw = __clk_get_hw(clk);
519 struct clk_composite *composite = to_clk_composite(hw);
520 struct clk_hw *rate_hw = composite->rate_hw;
521 struct clk_factors *factors = to_clk_factors(rate_hw);
522 unsigned long flags = 0;
523 u32 reg;
524
525 if (factors->lock)
526 spin_lock_irqsave(factors->lock, flags);
527
528 reg = readl(factors->reg);
529
530 /* set sample clock phase control */
531 reg &= ~(0x7 << 20);
532 reg |= ((sample & 0x7) << 20);
533
534 /* set output clock phase control */
535 reg &= ~(0x7 << 8);
536 reg |= ((output & 0x7) << 8);
537
538 writel(reg, factors->reg);
539
540 if (factors->lock)
541 spin_unlock_irqrestore(factors->lock, flags);
542}
543EXPORT_SYMBOL(clk_sunxi_mmc_phase_control);
544
545
546/**
510 * sunxi_factors_clk_setup() - Setup function for factor clocks 547 * sunxi_factors_clk_setup() - Setup function for factor clocks
511 */ 548 */
512 549
diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index c39613c519af..0011d547a9f7 100644
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -233,6 +233,7 @@ enum clk_id {
233 tegra_clk_xusb_hs_src, 233 tegra_clk_xusb_hs_src,
234 tegra_clk_xusb_ss, 234 tegra_clk_xusb_ss,
235 tegra_clk_xusb_ss_src, 235 tegra_clk_xusb_ss_src,
236 tegra_clk_xusb_ss_div2,
236 tegra_clk_max, 237 tegra_clk_max,
237}; 238};
238 239
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index e1769addf435..39e0959b61bd 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -96,10 +96,20 @@
96 (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL) 96 (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL)
97 97
98#define PLLE_AUX_PLLP_SEL BIT(2) 98#define PLLE_AUX_PLLP_SEL BIT(2)
99#define PLLE_AUX_USE_LOCKDET BIT(3)
99#define PLLE_AUX_ENABLE_SWCTL BIT(4) 100#define PLLE_AUX_ENABLE_SWCTL BIT(4)
101#define PLLE_AUX_SS_SWCTL BIT(6)
100#define PLLE_AUX_SEQ_ENABLE BIT(24) 102#define PLLE_AUX_SEQ_ENABLE BIT(24)
103#define PLLE_AUX_SEQ_START_STATE BIT(25)
101#define PLLE_AUX_PLLRE_SEL BIT(28) 104#define PLLE_AUX_PLLRE_SEL BIT(28)
102 105
106#define XUSBIO_PLL_CFG0 0x51c
107#define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
108#define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2)
109#define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6)
110#define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24)
111#define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25)
112
103#define PLLE_MISC_PLLE_PTS BIT(8) 113#define PLLE_MISC_PLLE_PTS BIT(8)
104#define PLLE_MISC_IDDQ_SW_VALUE BIT(13) 114#define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
105#define PLLE_MISC_IDDQ_SW_CTRL BIT(14) 115#define PLLE_MISC_IDDQ_SW_CTRL BIT(14)
@@ -1318,7 +1328,28 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
1318 pll_writel(val, PLLE_SS_CTRL, pll); 1328 pll_writel(val, PLLE_SS_CTRL, pll);
1319 udelay(1); 1329 udelay(1);
1320 1330
1321 /* TODO: enable hw control of xusb brick pll */ 1331 /* Enable hw control of xusb brick pll */
1332 val = pll_readl_misc(pll);
1333 val &= ~PLLE_MISC_IDDQ_SW_CTRL;
1334 pll_writel_misc(val, pll);
1335
1336 val = pll_readl(pll->params->aux_reg, pll);
1337 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE);
1338 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
1339 pll_writel(val, pll->params->aux_reg, pll);
1340 udelay(1);
1341 val |= PLLE_AUX_SEQ_ENABLE;
1342 pll_writel(val, pll->params->aux_reg, pll);
1343
1344 val = pll_readl(XUSBIO_PLL_CFG0, pll);
1345 val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
1346 XUSBIO_PLL_CFG0_SEQ_START_STATE);
1347 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
1348 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
1349 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1350 udelay(1);
1351 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
1352 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1322 1353
1323out: 1354out:
1324 if (pll->lock) 1355 if (pll->lock)
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index 1fa5c3f33b20..adf6b814b5bc 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -329,7 +329,9 @@ static u32 mux_clkm_pllp_pllc_pllre_idx[] = {
329static const char *mux_clkm_48M_pllp_480M[] = { 329static const char *mux_clkm_48M_pllp_480M[] = {
330 "clk_m", "pll_u_48M", "pll_p", "pll_u_480M" 330 "clk_m", "pll_u_48M", "pll_p", "pll_u_480M"
331}; 331};
332#define mux_clkm_48M_pllp_480M_idx NULL 332static u32 mux_clkm_48M_pllp_480M_idx[] = {
333 [0] = 0, [1] = 2, [2] = 4, [3] = 6,
334};
333 335
334static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = { 336static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = {
335 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref" 337 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"
@@ -338,6 +340,11 @@ static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = {
338 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7, 340 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7,
339}; 341};
340 342
343static const char *mux_ss_60M[] = {
344 "xusb_ss_div2", "pll_u_60M"
345};
346#define mux_ss_60M_idx NULL
347
341static const char *mux_d_audio_clk[] = { 348static const char *mux_d_audio_clk[] = {
342 "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync", 349 "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync",
343 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync", 350 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
@@ -499,6 +506,7 @@ static struct tegra_periph_init_data periph_clks[] = {
499 XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src), 506 XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src),
500 XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src), 507 XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src),
501 XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src), 508 XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src),
509 NODIV("xusb_hs_src", mux_ss_60M, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src, NULL),
502 XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src), 510 XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src),
503}; 511};
504 512
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 80431f0fb268..b9c8ba258ef0 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -142,7 +142,6 @@
142#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0) 142#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
143 143
144#define CLK_SOURCE_CSITE 0x1d4 144#define CLK_SOURCE_CSITE 0x1d4
145#define CLK_SOURCE_XUSB_SS_SRC 0x610
146#define CLK_SOURCE_EMC 0x19c 145#define CLK_SOURCE_EMC 0x19c
147 146
148/* PLLM override registers */ 147/* PLLM override registers */
@@ -834,6 +833,7 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
834 [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true }, 833 [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true },
835 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true }, 834 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true },
836 [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA114_CLK_XUSB_SS_SRC, .present = true }, 835 [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA114_CLK_XUSB_SS_SRC, .present = true },
836 [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA114_CLK_XUSB_SS_DIV2, .present = true},
837 [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA114_CLK_XUSB_DEV_SRC, .present = true }, 837 [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA114_CLK_XUSB_DEV_SRC, .present = true },
838 [tegra_clk_xusb_dev] = { .dt_id = TEGRA114_CLK_XUSB_DEV, .present = true }, 838 [tegra_clk_xusb_dev] = { .dt_id = TEGRA114_CLK_XUSB_DEV, .present = true },
839 [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA114_CLK_XUSB_HS_SRC, .present = true }, 839 [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA114_CLK_XUSB_HS_SRC, .present = true },
@@ -1182,16 +1182,11 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,
1182 void __iomem *pmc_base) 1182 void __iomem *pmc_base)
1183{ 1183{
1184 struct clk *clk; 1184 struct clk *clk;
1185 u32 val;
1186
1187 /* xusb_hs_src */
1188 val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
1189 val |= BIT(25); /* always select PLLU_60M */
1190 writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
1191 1185
1192 clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0, 1186 /* xusb_ss_div2 */
1193 1, 1); 1187 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
1194 clks[TEGRA114_CLK_XUSB_HS_SRC] = clk; 1188 1, 2);
1189 clks[TEGRA114_CLK_XUSB_SS_DIV2] = clk;
1195 1190
1196 /* dsia mux */ 1191 /* dsia mux */
1197 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0, 1192 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
@@ -1301,7 +1296,12 @@ static struct tegra_clk_init_table init_table[] __initdata = {
1301 {TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0}, 1296 {TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0},
1302 {TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0}, 1297 {TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0},
1303 {TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0}, 1298 {TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0},
1304 1299 {TEGRA114_CLK_PLL_RE_VCO, TEGRA114_CLK_CLK_MAX, 612000000, 0},
1300 {TEGRA114_CLK_XUSB_SS_SRC, TEGRA114_CLK_PLL_RE_OUT, 122400000, 0},
1301 {TEGRA114_CLK_XUSB_FS_SRC, TEGRA114_CLK_PLL_U_48M, 48000000, 0},
1302 {TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0},
1303 {TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0},
1304 {TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0},
1305 /* This MUST be the last entry. */ 1305 /* This MUST be the last entry. */
1306 {TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0}, 1306 {TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0},
1307}; 1307};
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index cc37c342c4cb..80efe51fdcdf 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -30,7 +30,6 @@
30 30
31#define CLK_SOURCE_CSITE 0x1d4 31#define CLK_SOURCE_CSITE 0x1d4
32#define CLK_SOURCE_EMC 0x19c 32#define CLK_SOURCE_EMC 0x19c
33#define CLK_SOURCE_XUSB_SS_SRC 0x610
34 33
35#define PLLC_BASE 0x80 34#define PLLC_BASE 0x80
36#define PLLC_OUT 0x84 35#define PLLC_OUT 0x84
@@ -925,6 +924,7 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
925 [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true }, 924 [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true },
926 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true }, 925 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true },
927 [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA124_CLK_XUSB_SS_SRC, .present = true }, 926 [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA124_CLK_XUSB_SS_SRC, .present = true },
927 [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA124_CLK_XUSB_SS_DIV2, .present = true },
928 [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA124_CLK_XUSB_DEV_SRC, .present = true }, 928 [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA124_CLK_XUSB_DEV_SRC, .present = true },
929 [tegra_clk_xusb_dev] = { .dt_id = TEGRA124_CLK_XUSB_DEV, .present = true }, 929 [tegra_clk_xusb_dev] = { .dt_id = TEGRA124_CLK_XUSB_DEV, .present = true },
930 [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA124_CLK_XUSB_HS_SRC, .present = true }, 930 [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA124_CLK_XUSB_HS_SRC, .present = true },
@@ -1105,16 +1105,11 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base,
1105 void __iomem *pmc_base) 1105 void __iomem *pmc_base)
1106{ 1106{
1107 struct clk *clk; 1107 struct clk *clk;
1108 u32 val;
1109
1110 /* xusb_hs_src */
1111 val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
1112 val |= BIT(25); /* always select PLLU_60M */
1113 writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
1114 1108
1115 clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0, 1109 /* xusb_ss_div2 */
1116 1, 1); 1110 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
1117 clks[TEGRA124_CLK_XUSB_HS_SRC] = clk; 1111 1, 2);
1112 clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk;
1118 1113
1119 /* dsia mux */ 1114 /* dsia mux */
1120 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0, 1115 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
@@ -1368,6 +1363,12 @@ static struct tegra_clk_init_table init_table[] __initdata = {
1368 {TEGRA124_CLK_SBC4, TEGRA124_CLK_PLL_P, 12000000, 1}, 1363 {TEGRA124_CLK_SBC4, TEGRA124_CLK_PLL_P, 12000000, 1},
1369 {TEGRA124_CLK_TSEC, TEGRA124_CLK_PLL_C3, 0, 0}, 1364 {TEGRA124_CLK_TSEC, TEGRA124_CLK_PLL_C3, 0, 0},
1370 {TEGRA124_CLK_MSENC, TEGRA124_CLK_PLL_C3, 0, 0}, 1365 {TEGRA124_CLK_MSENC, TEGRA124_CLK_PLL_C3, 0, 0},
1366 {TEGRA124_CLK_PLL_RE_VCO, TEGRA124_CLK_CLK_MAX, 672000000, 0},
1367 {TEGRA124_CLK_XUSB_SS_SRC, TEGRA124_CLK_PLL_U_480M, 120000000, 0},
1368 {TEGRA124_CLK_XUSB_FS_SRC, TEGRA124_CLK_PLL_U_48M, 48000000, 0},
1369 {TEGRA124_CLK_XUSB_HS_SRC, TEGRA124_CLK_PLL_U_60M, 60000000, 0},
1370 {TEGRA124_CLK_XUSB_FALCON_SRC, TEGRA124_CLK_PLL_RE_OUT, 224000000, 0},
1371 {TEGRA124_CLK_XUSB_HOST_SRC, TEGRA124_CLK_PLL_RE_OUT, 112000000, 0},
1371 /* This MUST be the last entry. */ 1372 /* This MUST be the last entry. */
1372 {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0}, 1373 {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
1373}; 1374};
diff --git a/drivers/clk/versatile/clk-icst.c b/drivers/clk/versatile/clk-icst.c
index a820b0cfcf57..7f3868a227c8 100644
--- a/drivers/clk/versatile/clk-icst.c
+++ b/drivers/clk/versatile/clk-icst.c
@@ -160,3 +160,4 @@ struct clk *icst_clk_register(struct device *dev,
160 160
161 return clk; 161 return clk;
162} 162}
163EXPORT_SYMBOL_GPL(icst_clk_register);
diff --git a/drivers/clk/versatile/clk-impd1.c b/drivers/clk/versatile/clk-impd1.c
index 31b44f025f9e..1cc1330dc570 100644
--- a/drivers/clk/versatile/clk-impd1.c
+++ b/drivers/clk/versatile/clk-impd1.c
@@ -20,6 +20,8 @@
20#define IMPD1_LOCK 0x08 20#define IMPD1_LOCK 0x08
21 21
22struct impd1_clk { 22struct impd1_clk {
23 char *pclkname;
24 struct clk *pclk;
23 char *vco1name; 25 char *vco1name;
24 struct clk *vco1clk; 26 struct clk *vco1clk;
25 char *vco2name; 27 char *vco2name;
@@ -31,7 +33,7 @@ struct impd1_clk {
31 struct clk *spiclk; 33 struct clk *spiclk;
32 char *scname; 34 char *scname;
33 struct clk *scclk; 35 struct clk *scclk;
34 struct clk_lookup *clks[6]; 36 struct clk_lookup *clks[15];
35}; 37};
36 38
37/* One entry for each connected IM-PD1 LM */ 39/* One entry for each connected IM-PD1 LM */
@@ -86,6 +88,7 @@ void integrator_impd1_clk_init(void __iomem *base, unsigned int id)
86{ 88{
87 struct impd1_clk *imc; 89 struct impd1_clk *imc;
88 struct clk *clk; 90 struct clk *clk;
91 struct clk *pclk;
89 int i; 92 int i;
90 93
91 if (id > 3) { 94 if (id > 3) {
@@ -94,11 +97,18 @@ void integrator_impd1_clk_init(void __iomem *base, unsigned int id)
94 } 97 }
95 imc = &impd1_clks[id]; 98 imc = &impd1_clks[id];
96 99
100 /* Register the fixed rate PCLK */
101 imc->pclkname = kasprintf(GFP_KERNEL, "lm%x-pclk", id);
102 pclk = clk_register_fixed_rate(NULL, imc->pclkname, NULL,
103 CLK_IS_ROOT, 0);
104 imc->pclk = pclk;
105
97 imc->vco1name = kasprintf(GFP_KERNEL, "lm%x-vco1", id); 106 imc->vco1name = kasprintf(GFP_KERNEL, "lm%x-vco1", id);
98 clk = icst_clk_register(NULL, &impd1_icst1_desc, imc->vco1name, NULL, 107 clk = icst_clk_register(NULL, &impd1_icst1_desc, imc->vco1name, NULL,
99 base); 108 base);
100 imc->vco1clk = clk; 109 imc->vco1clk = clk;
101 imc->clks[0] = clkdev_alloc(clk, NULL, "lm%x:01000", id); 110 imc->clks[0] = clkdev_alloc(pclk, "apb_pclk", "lm%x:01000", id);
111 imc->clks[1] = clkdev_alloc(clk, NULL, "lm%x:01000", id);
102 112
103 /* VCO2 is also called "CLK2" */ 113 /* VCO2 is also called "CLK2" */
104 imc->vco2name = kasprintf(GFP_KERNEL, "lm%x-vco2", id); 114 imc->vco2name = kasprintf(GFP_KERNEL, "lm%x-vco2", id);
@@ -107,32 +117,43 @@ void integrator_impd1_clk_init(void __iomem *base, unsigned int id)
107 imc->vco2clk = clk; 117 imc->vco2clk = clk;
108 118
109 /* MMCI uses CLK2 right off */ 119 /* MMCI uses CLK2 right off */
110 imc->clks[1] = clkdev_alloc(clk, NULL, "lm%x:00700", id); 120 imc->clks[2] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00700", id);
121 imc->clks[3] = clkdev_alloc(clk, NULL, "lm%x:00700", id);
111 122
112 /* UART reference clock divides CLK2 by a fixed factor 4 */ 123 /* UART reference clock divides CLK2 by a fixed factor 4 */
113 imc->uartname = kasprintf(GFP_KERNEL, "lm%x-uartclk", id); 124 imc->uartname = kasprintf(GFP_KERNEL, "lm%x-uartclk", id);
114 clk = clk_register_fixed_factor(NULL, imc->uartname, imc->vco2name, 125 clk = clk_register_fixed_factor(NULL, imc->uartname, imc->vco2name,
115 CLK_IGNORE_UNUSED, 1, 4); 126 CLK_IGNORE_UNUSED, 1, 4);
116 imc->uartclk = clk; 127 imc->uartclk = clk;
117 imc->clks[2] = clkdev_alloc(clk, NULL, "lm%x:00100", id); 128 imc->clks[4] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00100", id);
118 imc->clks[3] = clkdev_alloc(clk, NULL, "lm%x:00200", id); 129 imc->clks[5] = clkdev_alloc(clk, NULL, "lm%x:00100", id);
130 imc->clks[6] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00200", id);
131 imc->clks[7] = clkdev_alloc(clk, NULL, "lm%x:00200", id);
119 132
120 /* SPI PL022 clock divides CLK2 by a fixed factor 64 */ 133 /* SPI PL022 clock divides CLK2 by a fixed factor 64 */
121 imc->spiname = kasprintf(GFP_KERNEL, "lm%x-spiclk", id); 134 imc->spiname = kasprintf(GFP_KERNEL, "lm%x-spiclk", id);
122 clk = clk_register_fixed_factor(NULL, imc->spiname, imc->vco2name, 135 clk = clk_register_fixed_factor(NULL, imc->spiname, imc->vco2name,
123 CLK_IGNORE_UNUSED, 1, 64); 136 CLK_IGNORE_UNUSED, 1, 64);
124 imc->clks[4] = clkdev_alloc(clk, NULL, "lm%x:00300", id); 137 imc->clks[8] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00300", id);
138 imc->clks[9] = clkdev_alloc(clk, NULL, "lm%x:00300", id);
139
140 /* The GPIO blocks and AACI have only PCLK */
141 imc->clks[10] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00400", id);
142 imc->clks[11] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00500", id);
143 imc->clks[12] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00800", id);
125 144
126 /* Smart Card clock divides CLK2 by a fixed factor 4 */ 145 /* Smart Card clock divides CLK2 by a fixed factor 4 */
127 imc->scname = kasprintf(GFP_KERNEL, "lm%x-scclk", id); 146 imc->scname = kasprintf(GFP_KERNEL, "lm%x-scclk", id);
128 clk = clk_register_fixed_factor(NULL, imc->scname, imc->vco2name, 147 clk = clk_register_fixed_factor(NULL, imc->scname, imc->vco2name,
129 CLK_IGNORE_UNUSED, 1, 4); 148 CLK_IGNORE_UNUSED, 1, 4);
130 imc->scclk = clk; 149 imc->scclk = clk;
131 imc->clks[5] = clkdev_alloc(clk, NULL, "lm%x:00600", id); 150 imc->clks[13] = clkdev_alloc(pclk, "apb_pclk", "lm%x:00600", id);
151 imc->clks[14] = clkdev_alloc(clk, NULL, "lm%x:00600", id);
132 152
133 for (i = 0; i < ARRAY_SIZE(imc->clks); i++) 153 for (i = 0; i < ARRAY_SIZE(imc->clks); i++)
134 clkdev_add(imc->clks[i]); 154 clkdev_add(imc->clks[i]);
135} 155}
156EXPORT_SYMBOL_GPL(integrator_impd1_clk_init);
136 157
137void integrator_impd1_clk_exit(unsigned int id) 158void integrator_impd1_clk_exit(unsigned int id)
138{ 159{
@@ -149,9 +170,12 @@ void integrator_impd1_clk_exit(unsigned int id)
149 clk_unregister(imc->uartclk); 170 clk_unregister(imc->uartclk);
150 clk_unregister(imc->vco2clk); 171 clk_unregister(imc->vco2clk);
151 clk_unregister(imc->vco1clk); 172 clk_unregister(imc->vco1clk);
173 clk_unregister(imc->pclk);
152 kfree(imc->scname); 174 kfree(imc->scname);
153 kfree(imc->spiname); 175 kfree(imc->spiname);
154 kfree(imc->uartname); 176 kfree(imc->uartname);
155 kfree(imc->vco2name); 177 kfree(imc->vco2name);
156 kfree(imc->vco1name); 178 kfree(imc->vco1name);
179 kfree(imc->pclkname);
157} 180}
181EXPORT_SYMBOL_GPL(integrator_impd1_clk_exit);
diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
index 52c09afdcfb7..246cf1226eaa 100644
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@ -53,6 +53,9 @@ static void __iomem *zynq_clkc_base;
53 53
54#define NUM_MIO_PINS 54 54#define NUM_MIO_PINS 54
55 55
56#define DBG_CLK_CTRL_CLKACT_TRC BIT(0)
57#define DBG_CLK_CTRL_CPU_1XCLKACT BIT(1)
58
56enum zynq_clk { 59enum zynq_clk {
57 armpll, ddrpll, iopll, 60 armpll, ddrpll, iopll,
58 cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x, 61 cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x,
@@ -499,6 +502,15 @@ static void __init zynq_clk_setup(struct device_node *np)
499 clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0, 502 clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0,
500 &dbgclk_lock); 503 &dbgclk_lock);
501 504
505 /* leave debug clocks in the state the bootloader set them up to */
506 tmp = clk_readl(SLCR_DBG_CLK_CTRL);
507 if (tmp & DBG_CLK_CTRL_CLKACT_TRC)
508 if (clk_prepare_enable(clks[dbg_trc]))
509 pr_warn("%s: trace clk enable failed\n", __func__);
510 if (tmp & DBG_CLK_CTRL_CPU_1XCLKACT)
511 if (clk_prepare_enable(clks[dbg_apb]))
512 pr_warn("%s: debug APB clk enable failed\n", __func__);
513
502 /* One gated clock for all APER clocks. */ 514 /* One gated clock for all APER clocks. */
503 clks[dma] = clk_register_gate(NULL, clk_output_name[dma], 515 clks[dma] = clk_register_gate(NULL, clk_output_name[dma],
504 clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0, 516 clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0,
diff --git a/include/dt-bindings/clock/bcm21664.h b/include/dt-bindings/clock/bcm21664.h
new file mode 100644
index 000000000000..5a7f0e4750a8
--- /dev/null
+++ b/include/dt-bindings/clock/bcm21664.h
@@ -0,0 +1,62 @@
1/*
2 * Copyright (C) 2013 Broadcom Corporation
3 * Copyright 2013 Linaro Limited
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation version 2.
8 *
9 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
10 * kind, whether express or implied; without even the implied warranty
11 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef _CLOCK_BCM21664_H
16#define _CLOCK_BCM21664_H
17
18/*
19 * This file defines the values used to specify clocks provided by
20 * the clock control units (CCUs) on Broadcom BCM21664 family SoCs.
21 */
22
23/* bcm21664 CCU device tree "compatible" strings */
24#define BCM21664_DT_ROOT_CCU_COMPAT "brcm,bcm21664-root-ccu"
25#define BCM21664_DT_AON_CCU_COMPAT "brcm,bcm21664-aon-ccu"
26#define BCM21664_DT_MASTER_CCU_COMPAT "brcm,bcm21664-master-ccu"
27#define BCM21664_DT_SLAVE_CCU_COMPAT "brcm,bcm21664-slave-ccu"
28
29/* root CCU clock ids */
30
31#define BCM21664_ROOT_CCU_FRAC_1M 0
32#define BCM21664_ROOT_CCU_CLOCK_COUNT 1
33
34/* aon CCU clock ids */
35
36#define BCM21664_AON_CCU_HUB_TIMER 0
37#define BCM21664_AON_CCU_CLOCK_COUNT 1
38
39/* master CCU clock ids */
40
41#define BCM21664_MASTER_CCU_SDIO1 0
42#define BCM21664_MASTER_CCU_SDIO2 1
43#define BCM21664_MASTER_CCU_SDIO3 2
44#define BCM21664_MASTER_CCU_SDIO4 3
45#define BCM21664_MASTER_CCU_SDIO1_SLEEP 4
46#define BCM21664_MASTER_CCU_SDIO2_SLEEP 5
47#define BCM21664_MASTER_CCU_SDIO3_SLEEP 6
48#define BCM21664_MASTER_CCU_SDIO4_SLEEP 7
49#define BCM21664_MASTER_CCU_CLOCK_COUNT 8
50
51/* slave CCU clock ids */
52
53#define BCM21664_SLAVE_CCU_UARTB 0
54#define BCM21664_SLAVE_CCU_UARTB2 1
55#define BCM21664_SLAVE_CCU_UARTB3 2
56#define BCM21664_SLAVE_CCU_BSC1 3
57#define BCM21664_SLAVE_CCU_BSC2 4
58#define BCM21664_SLAVE_CCU_BSC3 5
59#define BCM21664_SLAVE_CCU_BSC4 6
60#define BCM21664_SLAVE_CCU_CLOCK_COUNT 7
61
62#endif /* _CLOCK_BCM21664_H */
diff --git a/include/dt-bindings/clock/bcm281xx.h b/include/dt-bindings/clock/bcm281xx.h
index e0096940886d..a763460cf1af 100644
--- a/include/dt-bindings/clock/bcm281xx.h
+++ b/include/dt-bindings/clock/bcm281xx.h
@@ -20,6 +20,18 @@
20 * the clock control units (CCUs) on Broadcom BCM281XX family SoCs. 20 * the clock control units (CCUs) on Broadcom BCM281XX family SoCs.
21 */ 21 */
22 22
23/*
24 * These are the bcm281xx CCU device tree "compatible" strings.
25 * We're stuck with using "bcm11351" in the string because wild
26 * cards aren't allowed, and that name was the first one defined
27 * in this family of devices.
28 */
29#define BCM281XX_DT_ROOT_CCU_COMPAT "brcm,bcm11351-root-ccu"
30#define BCM281XX_DT_AON_CCU_COMPAT "brcm,bcm11351-aon-ccu"
31#define BCM281XX_DT_HUB_CCU_COMPAT "brcm,bcm11351-hub-ccu"
32#define BCM281XX_DT_MASTER_CCU_COMPAT "brcm,bcm11351-master-ccu"
33#define BCM281XX_DT_SLAVE_CCU_COMPAT "brcm,bcm11351-slave-ccu"
34
23/* root CCU clock ids */ 35/* root CCU clock ids */
24 36
25#define BCM281XX_ROOT_CCU_FRAC_1M 0 37#define BCM281XX_ROOT_CCU_FRAC_1M 0
diff --git a/include/dt-bindings/clock/hix5hd2-clock.h b/include/dt-bindings/clock/hix5hd2-clock.h
new file mode 100644
index 000000000000..aad579a75802
--- /dev/null
+++ b/include/dt-bindings/clock/hix5hd2-clock.h
@@ -0,0 +1,58 @@
1/*
2 * Copyright (c) 2014 Linaro Ltd.
3 * Copyright (c) 2014 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10#ifndef __DTS_HIX5HD2_CLOCK_H
11#define __DTS_HIX5HD2_CLOCK_H
12
13/* fixed rate */
14#define HIX5HD2_FIXED_1200M 1
15#define HIX5HD2_FIXED_400M 2
16#define HIX5HD2_FIXED_48M 3
17#define HIX5HD2_FIXED_24M 4
18#define HIX5HD2_FIXED_600M 5
19#define HIX5HD2_FIXED_300M 6
20#define HIX5HD2_FIXED_75M 7
21#define HIX5HD2_FIXED_200M 8
22#define HIX5HD2_FIXED_100M 9
23#define HIX5HD2_FIXED_40M 10
24#define HIX5HD2_FIXED_150M 11
25#define HIX5HD2_FIXED_1728M 12
26#define HIX5HD2_FIXED_28P8M 13
27#define HIX5HD2_FIXED_432M 14
28#define HIX5HD2_FIXED_345P6M 15
29#define HIX5HD2_FIXED_288M 16
30#define HIX5HD2_FIXED_60M 17
31#define HIX5HD2_FIXED_750M 18
32#define HIX5HD2_FIXED_500M 19
33#define HIX5HD2_FIXED_54M 20
34#define HIX5HD2_FIXED_27M 21
35#define HIX5HD2_FIXED_1500M 22
36#define HIX5HD2_FIXED_375M 23
37#define HIX5HD2_FIXED_187M 24
38#define HIX5HD2_FIXED_250M 25
39#define HIX5HD2_FIXED_125M 26
40#define HIX5HD2_FIXED_2P02M 27
41#define HIX5HD2_FIXED_50M 28
42#define HIX5HD2_FIXED_25M 29
43#define HIX5HD2_FIXED_83M 30
44
45/* mux clocks */
46#define HIX5HD2_SFC_MUX 64
47#define HIX5HD2_MMC_MUX 65
48#define HIX5HD2_FEPHY_MUX 66
49
50/* gate clocks */
51#define HIX5HD2_SFC_RST 128
52#define HIX5HD2_SFC_CLK 129
53#define HIX5HD2_MMC_CIU_CLK 130
54#define HIX5HD2_MMC_BIU_CLK 131
55#define HIX5HD2_MMC_CIU_RST 132
56
57#define HIX5HD2_NR_CLKS 256
58#endif /* __DTS_HIX5HD2_CLOCK_H */
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8960.h b/include/dt-bindings/clock/qcom,gcc-msm8960.h
index 03bbf49d43b7..f9f547146a15 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8960.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8960.h
@@ -51,7 +51,7 @@
51#define QDSS_TSCTR_CLK 34 51#define QDSS_TSCTR_CLK 34
52#define SFAB_ADM0_M0_A_CLK 35 52#define SFAB_ADM0_M0_A_CLK 35
53#define SFAB_ADM0_M1_A_CLK 36 53#define SFAB_ADM0_M1_A_CLK 36
54#define SFAB_ADM0_M2_A_CLK 37 54#define SFAB_ADM0_M2_H_CLK 37
55#define ADM0_CLK 38 55#define ADM0_CLK 38
56#define ADM0_PBUS_CLK 39 56#define ADM0_PBUS_CLK 39
57#define MSS_XPU_CLK 40 57#define MSS_XPU_CLK 40
@@ -99,7 +99,7 @@
99#define CFPB2_H_CLK 82 99#define CFPB2_H_CLK 82
100#define SFAB_CFPB_M_H_CLK 83 100#define SFAB_CFPB_M_H_CLK 83
101#define CFPB_MASTER_H_CLK 84 101#define CFPB_MASTER_H_CLK 84
102#define SFAB_CFPB_S_HCLK 85 102#define SFAB_CFPB_S_H_CLK 85
103#define CFPB_SPLITTER_H_CLK 86 103#define CFPB_SPLITTER_H_CLK 86
104#define TSIF_H_CLK 87 104#define TSIF_H_CLK 87
105#define TSIF_INACTIVITY_TIMERS_CLK 88 105#define TSIF_INACTIVITY_TIMERS_CLK 88
@@ -110,7 +110,6 @@
110#define CE1_SLEEP_CLK 93 110#define CE1_SLEEP_CLK 93
111#define CE2_H_CLK 94 111#define CE2_H_CLK 94
112#define CE2_CORE_CLK 95 112#define CE2_CORE_CLK 95
113#define CE2_SLEEP_CLK 96
114#define SFPB_H_CLK_SRC 97 113#define SFPB_H_CLK_SRC 97
115#define SFPB_H_CLK 98 114#define SFPB_H_CLK 98
116#define SFAB_SFPB_M_H_CLK 99 115#define SFAB_SFPB_M_H_CLK 99
@@ -252,7 +251,7 @@
252#define MSS_S_H_CLK 235 251#define MSS_S_H_CLK 235
253#define MSS_CXO_SRC_CLK 236 252#define MSS_CXO_SRC_CLK 236
254#define SATA_H_CLK 237 253#define SATA_H_CLK 237
255#define SATA_SRC_CLK 238 254#define SATA_CLK_SRC 238
256#define SATA_RXOOB_CLK 239 255#define SATA_RXOOB_CLK 239
257#define SATA_PMALIVE_CLK 240 256#define SATA_PMALIVE_CLK 240
258#define SATA_PHY_REF_CLK 241 257#define SATA_PHY_REF_CLK 241
diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
index 6d0d8d8ef31e..fc12621fb432 100644
--- a/include/dt-bindings/clock/tegra114-car.h
+++ b/include/dt-bindings/clock/tegra114-car.h
@@ -337,6 +337,7 @@
337#define TEGRA114_CLK_CLK_OUT_3_MUX 308 337#define TEGRA114_CLK_CLK_OUT_3_MUX 308
338#define TEGRA114_CLK_DSIA_MUX 309 338#define TEGRA114_CLK_DSIA_MUX 309
339#define TEGRA114_CLK_DSIB_MUX 310 339#define TEGRA114_CLK_DSIB_MUX 310
340#define TEGRA114_CLK_CLK_MAX 311 340#define TEGRA114_CLK_XUSB_SS_DIV2 311
341#define TEGRA114_CLK_CLK_MAX 312
341 342
342#endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */ 343#endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */
diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h
index 433528ab5161..8a4c5892890f 100644
--- a/include/dt-bindings/clock/tegra124-car.h
+++ b/include/dt-bindings/clock/tegra124-car.h
@@ -336,6 +336,7 @@
336#define TEGRA124_CLK_DSIA_MUX 309 336#define TEGRA124_CLK_DSIA_MUX 309
337#define TEGRA124_CLK_DSIB_MUX 310 337#define TEGRA124_CLK_DSIB_MUX 310
338#define TEGRA124_CLK_SOR0_LVDS 311 338#define TEGRA124_CLK_SOR0_LVDS 311
339#define TEGRA124_CLK_CLK_MAX 312 339#define TEGRA124_CLK_XUSB_SS_DIV2 312
340#define TEGRA124_CLK_CLK_MAX 313
340 341
341#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */ 342#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */
diff --git a/include/dt-bindings/reset/qcom,gcc-msm8960.h b/include/dt-bindings/reset/qcom,gcc-msm8960.h
index a840e680323c..07edd0e65eed 100644
--- a/include/dt-bindings/reset/qcom,gcc-msm8960.h
+++ b/include/dt-bindings/reset/qcom,gcc-msm8960.h
@@ -58,7 +58,7 @@
58#define PPSS_PROC_RESET 41 58#define PPSS_PROC_RESET 41
59#define PPSS_RESET 42 59#define PPSS_RESET 42
60#define DMA_BAM_RESET 43 60#define DMA_BAM_RESET 43
61#define SIC_TIC_RESET 44 61#define SPS_TIC_H_RESET 44
62#define SLIMBUS_H_RESET 45 62#define SLIMBUS_H_RESET 45
63#define SFAB_CFPB_M_RESET 46 63#define SFAB_CFPB_M_RESET 46
64#define SFAB_CFPB_S_RESET 47 64#define SFAB_CFPB_S_RESET 47
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 511917416fb0..c7135dbbcd65 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -40,14 +40,14 @@ struct dentry;
40 * through the clk_* api. 40 * through the clk_* api.
41 * 41 *
42 * @prepare: Prepare the clock for enabling. This must not return until 42 * @prepare: Prepare the clock for enabling. This must not return until
43 * the clock is fully prepared, and it's safe to call clk_enable. 43 * the clock is fully prepared, and it's safe to call clk_enable.
44 * This callback is intended to allow clock implementations to 44 * This callback is intended to allow clock implementations to
45 * do any initialisation that may sleep. Called with 45 * do any initialisation that may sleep. Called with
46 * prepare_lock held. 46 * prepare_lock held.
47 * 47 *
48 * @unprepare: Release the clock from its prepared state. This will typically 48 * @unprepare: Release the clock from its prepared state. This will typically
49 * undo any work done in the @prepare callback. Called with 49 * undo any work done in the @prepare callback. Called with
50 * prepare_lock held. 50 * prepare_lock held.
51 * 51 *
52 * @is_prepared: Queries the hardware to determine if the clock is prepared. 52 * @is_prepared: Queries the hardware to determine if the clock is prepared.
53 * This function is allowed to sleep. Optional, if this op is not 53 * This function is allowed to sleep. Optional, if this op is not
@@ -58,16 +58,16 @@ struct dentry;
58 * Called with prepare mutex held. This function may sleep. 58 * Called with prepare mutex held. This function may sleep.
59 * 59 *
60 * @enable: Enable the clock atomically. This must not return until the 60 * @enable: Enable the clock atomically. This must not return until the
61 * clock is generating a valid clock signal, usable by consumer 61 * clock is generating a valid clock signal, usable by consumer
62 * devices. Called with enable_lock held. This function must not 62 * devices. Called with enable_lock held. This function must not
63 * sleep. 63 * sleep.
64 * 64 *
65 * @disable: Disable the clock atomically. Called with enable_lock held. 65 * @disable: Disable the clock atomically. Called with enable_lock held.
66 * This function must not sleep. 66 * This function must not sleep.
67 * 67 *
68 * @is_enabled: Queries the hardware to determine if the clock is enabled. 68 * @is_enabled: Queries the hardware to determine if the clock is enabled.
69 * This function must not sleep. Optional, if this op is not 69 * This function must not sleep. Optional, if this op is not
70 * set then the enable count will be used. 70 * set then the enable count will be used.
71 * 71 *
72 * @disable_unused: Disable the clock atomically. Only called from 72 * @disable_unused: Disable the clock atomically. Only called from
73 * clk_disable_unused for gate clocks with special needs. 73 * clk_disable_unused for gate clocks with special needs.
@@ -75,34 +75,35 @@ struct dentry;
75 * sleep. 75 * sleep.
76 * 76 *
77 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The 77 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
78 * parent rate is an input parameter. It is up to the caller to 78 * parent rate is an input parameter. It is up to the caller to
79 * ensure that the prepare_mutex is held across this call. 79 * ensure that the prepare_mutex is held across this call.
80 * Returns the calculated rate. Optional, but recommended - if 80 * Returns the calculated rate. Optional, but recommended - if
81 * this op is not set then clock rate will be initialized to 0. 81 * this op is not set then clock rate will be initialized to 0.
82 * 82 *
83 * @round_rate: Given a target rate as input, returns the closest rate actually 83 * @round_rate: Given a target rate as input, returns the closest rate actually
84 * supported by the clock. 84 * supported by the clock. The parent rate is an input/output
85 * parameter.
85 * 86 *
86 * @determine_rate: Given a target rate as input, returns the closest rate 87 * @determine_rate: Given a target rate as input, returns the closest rate
87 * actually supported by the clock, and optionally the parent clock 88 * actually supported by the clock, and optionally the parent clock
88 * that should be used to provide the clock rate. 89 * that should be used to provide the clock rate.
89 * 90 *
90 * @get_parent: Queries the hardware to determine the parent of a clock. The
91 * return value is a u8 which specifies the index corresponding to
92 * the parent clock. This index can be applied to either the
93 * .parent_names or .parents arrays. In short, this function
94 * translates the parent value read from hardware into an array
95 * index. Currently only called when the clock is initialized by
96 * __clk_init. This callback is mandatory for clocks with
97 * multiple parents. It is optional (and unnecessary) for clocks
98 * with 0 or 1 parents.
99 *
100 * @set_parent: Change the input source of this clock; for clocks with multiple 91 * @set_parent: Change the input source of this clock; for clocks with multiple
101 * possible parents specify a new parent by passing in the index 92 * possible parents specify a new parent by passing in the index
102 * as a u8 corresponding to the parent in either the .parent_names 93 * as a u8 corresponding to the parent in either the .parent_names
103 * or .parents arrays. This function in affect translates an 94 * or .parents arrays. This function in affect translates an
104 * array index into the value programmed into the hardware. 95 * array index into the value programmed into the hardware.
105 * Returns 0 on success, -EERROR otherwise. 96 * Returns 0 on success, -EERROR otherwise.
97 *
98 * @get_parent: Queries the hardware to determine the parent of a clock. The
99 * return value is a u8 which specifies the index corresponding to
100 * the parent clock. This index can be applied to either the
101 * .parent_names or .parents arrays. In short, this function
102 * translates the parent value read from hardware into an array
103 * index. Currently only called when the clock is initialized by
104 * __clk_init. This callback is mandatory for clocks with
105 * multiple parents. It is optional (and unnecessary) for clocks
106 * with 0 or 1 parents.
106 * 107 *
107 * @set_rate: Change the rate of this clock. The requested rate is specified 108 * @set_rate: Change the rate of this clock. The requested rate is specified
108 * by the second argument, which should typically be the return 109 * by the second argument, which should typically be the return
@@ -110,13 +111,6 @@ struct dentry;
110 * which is likely helpful for most .set_rate implementation. 111 * which is likely helpful for most .set_rate implementation.
111 * Returns 0 on success, -EERROR otherwise. 112 * Returns 0 on success, -EERROR otherwise.
112 * 113 *
113 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
114 * is expressed in ppb (parts per billion). The parent accuracy is
115 * an input parameter.
116 * Returns the calculated accuracy. Optional - if this op is not
117 * set then clock accuracy will be initialized to parent accuracy
118 * or 0 (perfect clock) if clock has no parent.
119 *
120 * @set_rate_and_parent: Change the rate and the parent of this clock. The 114 * @set_rate_and_parent: Change the rate and the parent of this clock. The
121 * requested rate is specified by the second argument, which 115 * requested rate is specified by the second argument, which
122 * should typically be the return of .round_rate call. The 116 * should typically be the return of .round_rate call. The
@@ -128,6 +122,18 @@ struct dentry;
128 * separately via calls to .set_parent and .set_rate. 122 * separately via calls to .set_parent and .set_rate.
129 * Returns 0 on success, -EERROR otherwise. 123 * Returns 0 on success, -EERROR otherwise.
130 * 124 *
125 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
126 * is expressed in ppb (parts per billion). The parent accuracy is
127 * an input parameter.
128 * Returns the calculated accuracy. Optional - if this op is not
129 * set then clock accuracy will be initialized to parent accuracy
130 * or 0 (perfect clock) if clock has no parent.
131 *
132 * @init: Perform platform-specific initialization magic.
133 * This is not not used by any of the basic clock types.
134 * Please consider other ways of solving initialization problems
135 * before using this callback, as its use is discouraged.
136 *
131 * @debug_init: Set up type-specific debugfs entries for this clock. This 137 * @debug_init: Set up type-specific debugfs entries for this clock. This
132 * is called once, after the debugfs directory entry for this 138 * is called once, after the debugfs directory entry for this
133 * clock has been created. The dentry pointer representing that 139 * clock has been created. The dentry pointer representing that
@@ -157,15 +163,15 @@ struct clk_ops {
157 void (*disable_unused)(struct clk_hw *hw); 163 void (*disable_unused)(struct clk_hw *hw);
158 unsigned long (*recalc_rate)(struct clk_hw *hw, 164 unsigned long (*recalc_rate)(struct clk_hw *hw,
159 unsigned long parent_rate); 165 unsigned long parent_rate);
160 long (*round_rate)(struct clk_hw *hw, unsigned long, 166 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
161 unsigned long *); 167 unsigned long *parent_rate);
162 long (*determine_rate)(struct clk_hw *hw, unsigned long rate, 168 long (*determine_rate)(struct clk_hw *hw, unsigned long rate,
163 unsigned long *best_parent_rate, 169 unsigned long *best_parent_rate,
164 struct clk **best_parent_clk); 170 struct clk **best_parent_clk);
165 int (*set_parent)(struct clk_hw *hw, u8 index); 171 int (*set_parent)(struct clk_hw *hw, u8 index);
166 u8 (*get_parent)(struct clk_hw *hw); 172 u8 (*get_parent)(struct clk_hw *hw);
167 int (*set_rate)(struct clk_hw *hw, unsigned long, 173 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
168 unsigned long); 174 unsigned long parent_rate);
169 int (*set_rate_and_parent)(struct clk_hw *hw, 175 int (*set_rate_and_parent)(struct clk_hw *hw,
170 unsigned long rate, 176 unsigned long rate,
171 unsigned long parent_rate, u8 index); 177 unsigned long parent_rate, u8 index);
@@ -254,12 +260,12 @@ void of_fixed_clk_setup(struct device_node *np);
254 * 260 *
255 * Flags: 261 * Flags:
256 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to 262 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
257 * enable the clock. Setting this flag does the opposite: setting the bit 263 * enable the clock. Setting this flag does the opposite: setting the bit
258 * disable the clock and clearing it enables the clock 264 * disable the clock and clearing it enables the clock
259 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit 265 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
260 * of this register, and mask of gate bits are in higher 16-bit of this 266 * of this register, and mask of gate bits are in higher 16-bit of this
261 * register. While setting the gate bits, higher 16-bit should also be 267 * register. While setting the gate bits, higher 16-bit should also be
262 * updated to indicate changing gate bits. 268 * updated to indicate changing gate bits.
263 */ 269 */
264struct clk_gate { 270struct clk_gate {
265 struct clk_hw hw; 271 struct clk_hw hw;
@@ -298,20 +304,24 @@ struct clk_div_table {
298 * 304 *
299 * Flags: 305 * Flags:
300 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the 306 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
301 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is 307 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
302 * the raw value read from the register, with the value of zero considered 308 * the raw value read from the register, with the value of zero considered
303 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. 309 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
304 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from 310 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
305 * the hardware register 311 * the hardware register
306 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have 312 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
307 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. 313 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
308 * Some hardware implementations gracefully handle this case and allow a 314 * Some hardware implementations gracefully handle this case and allow a
309 * zero divisor by not modifying their input clock 315 * zero divisor by not modifying their input clock
310 * (divide by one / bypass). 316 * (divide by one / bypass).
311 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit 317 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
312 * of this register, and mask of divider bits are in higher 16-bit of this 318 * of this register, and mask of divider bits are in higher 16-bit of this
313 * register. While setting the divider bits, higher 16-bit should also be 319 * register. While setting the divider bits, higher 16-bit should also be
314 * updated to indicate changing divider bits. 320 * updated to indicate changing divider bits.
321 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
322 * to the closest integer instead of the up one.
323 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
324 * not be changed by the clock framework.
315 */ 325 */
316struct clk_divider { 326struct clk_divider {
317 struct clk_hw hw; 327 struct clk_hw hw;
@@ -327,8 +337,11 @@ struct clk_divider {
327#define CLK_DIVIDER_POWER_OF_TWO BIT(1) 337#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
328#define CLK_DIVIDER_ALLOW_ZERO BIT(2) 338#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
329#define CLK_DIVIDER_HIWORD_MASK BIT(3) 339#define CLK_DIVIDER_HIWORD_MASK BIT(3)
340#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
341#define CLK_DIVIDER_READ_ONLY BIT(5)
330 342
331extern const struct clk_ops clk_divider_ops; 343extern const struct clk_ops clk_divider_ops;
344extern const struct clk_ops clk_divider_ro_ops;
332struct clk *clk_register_divider(struct device *dev, const char *name, 345struct clk *clk_register_divider(struct device *dev, const char *name,
333 const char *parent_name, unsigned long flags, 346 const char *parent_name, unsigned long flags,
334 void __iomem *reg, u8 shift, u8 width, 347 void __iomem *reg, u8 shift, u8 width,
@@ -356,9 +369,9 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
356 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 369 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
357 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) 370 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
358 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this 371 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
359 * register, and mask of mux bits are in higher 16-bit of this register. 372 * register, and mask of mux bits are in higher 16-bit of this register.
360 * While setting the mux bits, higher 16-bit should also be updated to 373 * While setting the mux bits, higher 16-bit should also be updated to
361 * indicate changing mux bits. 374 * indicate changing mux bits.
362 */ 375 */
363struct clk_mux { 376struct clk_mux {
364 struct clk_hw hw; 377 struct clk_hw hw;
diff --git a/include/linux/clk/shmobile.h b/include/linux/clk/shmobile.h
index f9bf080a1123..9f8a14041dd5 100644
--- a/include/linux/clk/shmobile.h
+++ b/include/linux/clk/shmobile.h
@@ -1,7 +1,9 @@
1/* 1/*
2 * Copyright 2013 Ideas On Board SPRL 2 * Copyright 2013 Ideas On Board SPRL
3 * Copyright 2013, 2014 Horms Solutions Ltd.
3 * 4 *
4 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com> 5 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
6 * Contact: Simon Horman <horms@verge.net.au>
5 * 7 *
6 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -14,6 +16,7 @@
14 16
15#include <linux/types.h> 17#include <linux/types.h>
16 18
19void r8a7779_clocks_init(u32 mode);
17void rcar_gen2_clocks_init(u32 mode); 20void rcar_gen2_clocks_init(u32 mode);
18 21
19#endif 22#endif
diff --git a/include/linux/clk/sunxi.h b/include/linux/clk/sunxi.h
new file mode 100644
index 000000000000..aed28c4451d9
--- /dev/null
+++ b/include/linux/clk/sunxi.h
@@ -0,0 +1,22 @@
1/*
2 * Copyright 2013 - Hans de Goede <hdegoede@redhat.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __LINUX_CLK_SUNXI_H_
16#define __LINUX_CLK_SUNXI_H_
17
18#include <linux/clk.h>
19
20void clk_sunxi_mmc_phase_control(struct clk *clk, u8 sample, u8 output);
21
22#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-28 01:45:24 -0400