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authorRasmus Villemoes <linux@rasmusvillemoes.dk>2015-06-11 07:27:52 -0400
committerMichael Ellerman <mpe@ellerman.id.au>2015-07-12 20:10:54 -0400
commitde369538436ae0caf784c69187ad0e53152b7ddf (patch)
tree266fef73ade51dd0500e320129bde3e40adea581
parent80c394fab89649585089f5bd5013f2d99e5756ef (diff)
cxl: use more common format specifier
A precision of 16 (%.16llx) has the same effect as a field width of 16 along with passing the 0 flag (%016llx), but the latter is much more common in the kernel tree. Update cxl to use that. Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Acked-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
-rw-r--r--drivers/misc/cxl/irq.c32
-rw-r--r--drivers/misc/cxl/native.c10
-rw-r--r--drivers/misc/cxl/pci.c10
-rw-r--r--drivers/misc/cxl/trace.h10
4 files changed, 31 insertions, 31 deletions
diff --git a/drivers/misc/cxl/irq.c b/drivers/misc/cxl/irq.c
index 2b64bb43b304..abfce494ca6b 100644
--- a/drivers/misc/cxl/irq.c
+++ b/drivers/misc/cxl/irq.c
@@ -30,12 +30,12 @@ static irqreturn_t handle_psl_slice_error(struct cxl_context *ctx, u64 dsisr, u6
30 serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An); 30 serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An);
31 afu_debug = cxl_p1n_read(ctx->afu, CXL_AFU_DEBUG_An); 31 afu_debug = cxl_p1n_read(ctx->afu, CXL_AFU_DEBUG_An);
32 32
33 dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%.16llx\n", errstat); 33 dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%016llx\n", errstat);
34 dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%.16llx\n", fir1); 34 dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1);
35 dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%.16llx\n", fir2); 35 dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%016llx\n", fir2);
36 dev_crit(&ctx->afu->dev, "PSL_SERR_An: 0x%.16llx\n", serr); 36 dev_crit(&ctx->afu->dev, "PSL_SERR_An: 0x%016llx\n", serr);
37 dev_crit(&ctx->afu->dev, "PSL_FIR_SLICE_An: 0x%.16llx\n", fir_slice); 37 dev_crit(&ctx->afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice);
38 dev_crit(&ctx->afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%.16llx\n", afu_debug); 38 dev_crit(&ctx->afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug);
39 39
40 dev_crit(&ctx->afu->dev, "STOPPING CXL TRACE\n"); 40 dev_crit(&ctx->afu->dev, "STOPPING CXL TRACE\n");
41 cxl_stop_trace(ctx->afu->adapter); 41 cxl_stop_trace(ctx->afu->adapter);
@@ -54,10 +54,10 @@ irqreturn_t cxl_slice_irq_err(int irq, void *data)
54 fir_slice = cxl_p1n_read(afu, CXL_PSL_FIR_SLICE_An); 54 fir_slice = cxl_p1n_read(afu, CXL_PSL_FIR_SLICE_An);
55 errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); 55 errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
56 afu_debug = cxl_p1n_read(afu, CXL_AFU_DEBUG_An); 56 afu_debug = cxl_p1n_read(afu, CXL_AFU_DEBUG_An);
57 dev_crit(&afu->dev, "PSL_SERR_An: 0x%.16llx\n", serr); 57 dev_crit(&afu->dev, "PSL_SERR_An: 0x%016llx\n", serr);
58 dev_crit(&afu->dev, "PSL_FIR_SLICE_An: 0x%.16llx\n", fir_slice); 58 dev_crit(&afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice);
59 dev_crit(&afu->dev, "CXL_PSL_ErrStat_An: 0x%.16llx\n", errstat); 59 dev_crit(&afu->dev, "CXL_PSL_ErrStat_An: 0x%016llx\n", errstat);
60 dev_crit(&afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%.16llx\n", afu_debug); 60 dev_crit(&afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug);
61 61
62 cxl_p1n_write(afu, CXL_PSL_SERR_An, serr); 62 cxl_p1n_write(afu, CXL_PSL_SERR_An, serr);
63 63
@@ -72,7 +72,7 @@ static irqreturn_t cxl_irq_err(int irq, void *data)
72 WARN(1, "CXL ERROR interrupt %i\n", irq); 72 WARN(1, "CXL ERROR interrupt %i\n", irq);
73 73
74 err_ivte = cxl_p1_read(adapter, CXL_PSL_ErrIVTE); 74 err_ivte = cxl_p1_read(adapter, CXL_PSL_ErrIVTE);
75 dev_crit(&adapter->dev, "PSL_ErrIVTE: 0x%.16llx\n", err_ivte); 75 dev_crit(&adapter->dev, "PSL_ErrIVTE: 0x%016llx\n", err_ivte);
76 76
77 dev_crit(&adapter->dev, "STOPPING CXL TRACE\n"); 77 dev_crit(&adapter->dev, "STOPPING CXL TRACE\n");
78 cxl_stop_trace(adapter); 78 cxl_stop_trace(adapter);
@@ -80,7 +80,7 @@ static irqreturn_t cxl_irq_err(int irq, void *data)
80 fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1); 80 fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1);
81 fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2); 81 fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2);
82 82
83 dev_crit(&adapter->dev, "PSL_FIR1: 0x%.16llx\nPSL_FIR2: 0x%.16llx\n", fir1, fir2); 83 dev_crit(&adapter->dev, "PSL_FIR1: 0x%016llx\nPSL_FIR2: 0x%016llx\n", fir1, fir2);
84 84
85 return IRQ_HANDLED; 85 return IRQ_HANDLED;
86} 86}
@@ -147,7 +147,7 @@ static irqreturn_t cxl_irq(int irq, void *data, struct cxl_irq_info *irq_info)
147 if (dsisr & CXL_PSL_DSISR_An_PE) 147 if (dsisr & CXL_PSL_DSISR_An_PE)
148 return handle_psl_slice_error(ctx, dsisr, irq_info->errstat); 148 return handle_psl_slice_error(ctx, dsisr, irq_info->errstat);
149 if (dsisr & CXL_PSL_DSISR_An_AE) { 149 if (dsisr & CXL_PSL_DSISR_An_AE) {
150 pr_devel("CXL interrupt: AFU Error 0x%.16llx\n", irq_info->afu_err); 150 pr_devel("CXL interrupt: AFU Error 0x%016llx\n", irq_info->afu_err);
151 151
152 if (ctx->pending_afu_err) { 152 if (ctx->pending_afu_err) {
153 /* 153 /*
@@ -158,7 +158,7 @@ static irqreturn_t cxl_irq(int irq, void *data, struct cxl_irq_info *irq_info)
158 * probably best that we log them somewhere: 158 * probably best that we log them somewhere:
159 */ 159 */
160 dev_err_ratelimited(&ctx->afu->dev, "CXL AFU Error " 160 dev_err_ratelimited(&ctx->afu->dev, "CXL AFU Error "
161 "undelivered to pe %i: 0x%.16llx\n", 161 "undelivered to pe %i: 0x%016llx\n",
162 ctx->pe, irq_info->afu_err); 162 ctx->pe, irq_info->afu_err);
163 } else { 163 } else {
164 spin_lock(&ctx->lock); 164 spin_lock(&ctx->lock);
@@ -211,8 +211,8 @@ static irqreturn_t cxl_irq_multiplexed(int irq, void *data)
211 } 211 }
212 rcu_read_unlock(); 212 rcu_read_unlock();
213 213
214 WARN(1, "Unable to demultiplex CXL PSL IRQ for PE %i DSISR %.16llx DAR" 214 WARN(1, "Unable to demultiplex CXL PSL IRQ for PE %i DSISR %016llx DAR"
215 " %.16llx\n(Possible AFU HW issue - was a term/remove acked" 215 " %016llx\n(Possible AFU HW issue - was a term/remove acked"
216 " with outstanding transactions?)\n", ph, irq_info.dsisr, 216 " with outstanding transactions?)\n", ph, irq_info.dsisr,
217 irq_info.dar); 217 irq_info.dar);
218 return fail_psl_irq(afu, &irq_info); 218 return fail_psl_irq(afu, &irq_info);
diff --git a/drivers/misc/cxl/native.c b/drivers/misc/cxl/native.c
index 10567f245818..fc9310dd2367 100644
--- a/drivers/misc/cxl/native.c
+++ b/drivers/misc/cxl/native.c
@@ -41,7 +41,7 @@ static int afu_control(struct cxl_afu *afu, u64 command,
41 rc = -EBUSY; 41 rc = -EBUSY;
42 goto out; 42 goto out;
43 } 43 }
44 pr_devel_ratelimited("AFU control... (0x%.16llx)\n", 44 pr_devel_ratelimited("AFU control... (0x%016llx)\n",
45 AFU_Cntl | command); 45 AFU_Cntl | command);
46 cpu_relax(); 46 cpu_relax();
47 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); 47 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
@@ -120,13 +120,13 @@ int cxl_psl_purge(struct cxl_afu *afu)
120 goto out; 120 goto out;
121 } 121 }
122 dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); 122 dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
123 pr_devel_ratelimited("PSL purging... PSL_CNTL: 0x%.16llx PSL_DSISR: 0x%.16llx\n", PSL_CNTL, dsisr); 123 pr_devel_ratelimited("PSL purging... PSL_CNTL: 0x%016llx PSL_DSISR: 0x%016llx\n", PSL_CNTL, dsisr);
124 if (dsisr & CXL_PSL_DSISR_TRANS) { 124 if (dsisr & CXL_PSL_DSISR_TRANS) {
125 dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); 125 dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);
126 dev_notice(&afu->dev, "PSL purge terminating pending translation, DSISR: 0x%.16llx, DAR: 0x%.16llx\n", dsisr, dar); 126 dev_notice(&afu->dev, "PSL purge terminating pending translation, DSISR: 0x%016llx, DAR: 0x%016llx\n", dsisr, dar);
127 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); 127 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
128 } else if (dsisr) { 128 } else if (dsisr) {
129 dev_notice(&afu->dev, "PSL purge acknowledging pending non-translation fault, DSISR: 0x%.16llx\n", dsisr); 129 dev_notice(&afu->dev, "PSL purge acknowledging pending non-translation fault, DSISR: 0x%016llx\n", dsisr);
130 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); 130 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
131 } else { 131 } else {
132 cpu_relax(); 132 cpu_relax();
@@ -684,7 +684,7 @@ static void recover_psl_err(struct cxl_afu *afu, u64 errstat)
684{ 684{
685 u64 dsisr; 685 u64 dsisr;
686 686
687 pr_devel("RECOVERING FROM PSL ERROR... (0x%.16llx)\n", errstat); 687 pr_devel("RECOVERING FROM PSL ERROR... (0x%016llx)\n", errstat);
688 688
689 /* Clear PSL_DSISR[PE] */ 689 /* Clear PSL_DSISR[PE] */
690 dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); 690 dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index 32ad09705949..eb05efb74eed 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -656,7 +656,7 @@ static int sanitise_afu_regs(struct cxl_afu *afu)
656 */ 656 */
657 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An); 657 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
658 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) { 658 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
659 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#.16llx\n", reg); 659 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
660 if (__cxl_afu_reset(afu)) 660 if (__cxl_afu_reset(afu))
661 return -EIO; 661 return -EIO;
662 if (cxl_afu_disable(afu)) 662 if (cxl_afu_disable(afu))
@@ -677,7 +677,7 @@ static int sanitise_afu_regs(struct cxl_afu *afu)
677 cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000); 677 cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000);
678 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An); 678 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
679 if (reg) { 679 if (reg) {
680 dev_warn(&afu->dev, "AFU had pending DSISR: %#.16llx\n", reg); 680 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
681 if (reg & CXL_PSL_DSISR_TRANS) 681 if (reg & CXL_PSL_DSISR_TRANS)
682 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); 682 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
683 else 683 else
@@ -686,12 +686,12 @@ static int sanitise_afu_regs(struct cxl_afu *afu)
686 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An); 686 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
687 if (reg) { 687 if (reg) {
688 if (reg & ~0xffff) 688 if (reg & ~0xffff)
689 dev_warn(&afu->dev, "AFU had pending SERR: %#.16llx\n", reg); 689 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
690 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff); 690 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
691 } 691 }
692 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); 692 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
693 if (reg) { 693 if (reg) {
694 dev_warn(&afu->dev, "AFU had pending error status: %#.16llx\n", reg); 694 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
695 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg); 695 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
696 } 696 }
697 697
@@ -893,7 +893,7 @@ static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
893 if (pci_request_region(dev, 0, "priv 1 regs")) 893 if (pci_request_region(dev, 0, "priv 1 regs"))
894 goto err2; 894 goto err2;
895 895
896 pr_devel("cxl_map_adapter_regs: p1: %#.16llx %#llx, p2: %#.16llx %#llx", 896 pr_devel("cxl_map_adapter_regs: p1: %#016llx %#llx, p2: %#016llx %#llx",
897 p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev)); 897 p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev));
898 898
899 if (!(adapter->p1_mmio = ioremap(p1_base(dev), p1_size(dev)))) 899 if (!(adapter->p1_mmio = ioremap(p1_base(dev), p1_size(dev))))
diff --git a/drivers/misc/cxl/trace.h b/drivers/misc/cxl/trace.h
index ae434d87887e..6e1e2adfba8e 100644
--- a/drivers/misc/cxl/trace.h
+++ b/drivers/misc/cxl/trace.h
@@ -105,7 +105,7 @@ TRACE_EVENT(cxl_attach,
105 __entry->num_interrupts = num_interrupts; 105 __entry->num_interrupts = num_interrupts;
106 ), 106 ),
107 107
108 TP_printk("afu%i.%i pid=%i pe=%i wed=0x%.16llx irqs=%i amr=0x%llx", 108 TP_printk("afu%i.%i pid=%i pe=%i wed=0x%016llx irqs=%i amr=0x%llx",
109 __entry->card, 109 __entry->card,
110 __entry->afu, 110 __entry->afu,
111 __entry->pid, 111 __entry->pid,
@@ -177,7 +177,7 @@ TRACE_EVENT(cxl_psl_irq,
177 __entry->dar = dar; 177 __entry->dar = dar;
178 ), 178 ),
179 179
180 TP_printk("afu%i.%i pe=%i irq=%i dsisr=%s dar=0x%.16llx", 180 TP_printk("afu%i.%i pe=%i irq=%i dsisr=%s dar=0x%016llx",
181 __entry->card, 181 __entry->card,
182 __entry->afu, 182 __entry->afu,
183 __entry->pe, 183 __entry->pe,
@@ -233,7 +233,7 @@ TRACE_EVENT(cxl_ste_miss,
233 __entry->dar = dar; 233 __entry->dar = dar;
234 ), 234 ),
235 235
236 TP_printk("afu%i.%i pe=%i dar=0x%.16llx", 236 TP_printk("afu%i.%i pe=%i dar=0x%016llx",
237 __entry->card, 237 __entry->card,
238 __entry->afu, 238 __entry->afu,
239 __entry->pe, 239 __entry->pe,
@@ -264,7 +264,7 @@ TRACE_EVENT(cxl_ste_write,
264 __entry->v = v; 264 __entry->v = v;
265 ), 265 ),
266 266
267 TP_printk("afu%i.%i pe=%i SSTE[%i] E=0x%.16llx V=0x%.16llx", 267 TP_printk("afu%i.%i pe=%i SSTE[%i] E=0x%016llx V=0x%016llx",
268 __entry->card, 268 __entry->card,
269 __entry->afu, 269 __entry->afu,
270 __entry->pe, 270 __entry->pe,
@@ -295,7 +295,7 @@ TRACE_EVENT(cxl_pte_miss,
295 __entry->dar = dar; 295 __entry->dar = dar;
296 ), 296 ),
297 297
298 TP_printk("afu%i.%i pe=%i dsisr=%s dar=0x%.16llx", 298 TP_printk("afu%i.%i pe=%i dsisr=%s dar=0x%016llx",
299 __entry->card, 299 __entry->card,
300 __entry->afu, 300 __entry->afu,
301 __entry->pe, 301 __entry->pe,