diff options
| author | Felipe Balbi <balbi@ti.com> | 2014-07-08 15:09:13 -0400 |
|---|---|---|
| committer | Mark Brown <broonie@linaro.org> | 2014-07-09 04:29:11 -0400 |
| commit | dd648ef2471602d5fc1ec80a546eb0c3f57ca172 (patch) | |
| tree | 2d6f6f94f07976f24e782f2a23c5fdc114968356 | |
| parent | e60781b4eb4849ae02f2f103acbde873a2ee55c9 (diff) | |
regulator: tps65218: drop unneeded field from our regulator macro
volt table is always NULL for all regulators,
might as well drop the argument.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
| -rw-r--r-- | drivers/regulator/tps65218-regulator.c | 19 |
1 files changed, 9 insertions, 10 deletions
diff --git a/drivers/regulator/tps65218-regulator.c b/drivers/regulator/tps65218-regulator.c index f56bc06389e4..633d793cd053 100644 --- a/drivers/regulator/tps65218-regulator.c +++ b/drivers/regulator/tps65218-regulator.c | |||
| @@ -29,7 +29,7 @@ | |||
| 29 | 29 | ||
| 30 | enum tps65218_regulators { DCDC1, DCDC2, DCDC3, DCDC4, DCDC5, DCDC6, LDO1 }; | 30 | enum tps65218_regulators { DCDC1, DCDC2, DCDC3, DCDC4, DCDC5, DCDC6, LDO1 }; |
| 31 | 31 | ||
| 32 | #define TPS65218_REGULATOR(_name, _id, _ops, _n, _vr, _vm, _er, _em, _t, \ | 32 | #define TPS65218_REGULATOR(_name, _id, _ops, _n, _vr, _vm, _er, _em, \ |
| 33 | _lr, _nlr, _delay) \ | 33 | _lr, _nlr, _delay) \ |
| 34 | { \ | 34 | { \ |
| 35 | .name = _name, \ | 35 | .name = _name, \ |
| @@ -42,7 +42,7 @@ enum tps65218_regulators { DCDC1, DCDC2, DCDC3, DCDC4, DCDC5, DCDC6, LDO1 }; | |||
| 42 | .vsel_mask = _vm, \ | 42 | .vsel_mask = _vm, \ |
| 43 | .enable_reg = _er, \ | 43 | .enable_reg = _er, \ |
| 44 | .enable_mask = _em, \ | 44 | .enable_mask = _em, \ |
| 45 | .volt_table = _t, \ | 45 | .volt_table = NULL, \ |
| 46 | .linear_ranges = _lr, \ | 46 | .linear_ranges = _lr, \ |
| 47 | .n_linear_ranges = _nlr, \ | 47 | .n_linear_ranges = _nlr, \ |
| 48 | .ramp_delay = _delay, \ | 48 | .ramp_delay = _delay, \ |
| @@ -185,33 +185,32 @@ static const struct regulator_desc regulators[] = { | |||
| 185 | TPS65218_REGULATOR("DCDC1", TPS65218_DCDC_1, tps65218_dcdc12_ops, 64, | 185 | TPS65218_REGULATOR("DCDC1", TPS65218_DCDC_1, tps65218_dcdc12_ops, 64, |
| 186 | TPS65218_REG_CONTROL_DCDC1, | 186 | TPS65218_REG_CONTROL_DCDC1, |
| 187 | TPS65218_CONTROL_DCDC1_MASK, | 187 | TPS65218_CONTROL_DCDC1_MASK, |
| 188 | TPS65218_REG_ENABLE1, TPS65218_ENABLE1_DC1_EN, NULL, | 188 | TPS65218_REG_ENABLE1, TPS65218_ENABLE1_DC1_EN, |
| 189 | dcdc1_dcdc2_ranges, 2, 4000), | 189 | dcdc1_dcdc2_ranges, 2, 4000), |
| 190 | TPS65218_REGULATOR("DCDC2", TPS65218_DCDC_2, tps65218_dcdc12_ops, 64, | 190 | TPS65218_REGULATOR("DCDC2", TPS65218_DCDC_2, tps65218_dcdc12_ops, 64, |
| 191 | TPS65218_REG_CONTROL_DCDC2, | 191 | TPS65218_REG_CONTROL_DCDC2, |
| 192 | TPS65218_CONTROL_DCDC2_MASK, | 192 | TPS65218_CONTROL_DCDC2_MASK, |
| 193 | TPS65218_REG_ENABLE1, TPS65218_ENABLE1_DC2_EN, NULL, | 193 | TPS65218_REG_ENABLE1, TPS65218_ENABLE1_DC2_EN, |
| 194 | dcdc1_dcdc2_ranges, 2, 4000), | 194 | dcdc1_dcdc2_ranges, 2, 4000), |
| 195 | TPS65218_REGULATOR("DCDC3", TPS65218_DCDC_3, tps65218_ldo1_dcdc34_ops, | 195 | TPS65218_REGULATOR("DCDC3", TPS65218_DCDC_3, tps65218_ldo1_dcdc34_ops, |
| 196 | 64, TPS65218_REG_CONTROL_DCDC3, | 196 | 64, TPS65218_REG_CONTROL_DCDC3, |
| 197 | TPS65218_CONTROL_DCDC3_MASK, TPS65218_REG_ENABLE1, | 197 | TPS65218_CONTROL_DCDC3_MASK, TPS65218_REG_ENABLE1, |
| 198 | TPS65218_ENABLE1_DC3_EN, NULL, | 198 | TPS65218_ENABLE1_DC3_EN, ldo1_dcdc3_ranges, 2, 0), |
| 199 | ldo1_dcdc3_ranges, 2, 0), | ||
| 200 | TPS65218_REGULATOR("DCDC4", TPS65218_DCDC_4, tps65218_ldo1_dcdc34_ops, | 199 | TPS65218_REGULATOR("DCDC4", TPS65218_DCDC_4, tps65218_ldo1_dcdc34_ops, |
| 201 | 53, TPS65218_REG_CONTROL_DCDC4, | 200 | 53, TPS65218_REG_CONTROL_DCDC4, |
| 202 | TPS65218_CONTROL_DCDC4_MASK, | 201 | TPS65218_CONTROL_DCDC4_MASK, |
| 203 | TPS65218_REG_ENABLE1, TPS65218_ENABLE1_DC4_EN, NULL, | 202 | TPS65218_REG_ENABLE1, TPS65218_ENABLE1_DC4_EN, |
| 204 | dcdc4_ranges, 2, 0), | 203 | dcdc4_ranges, 2, 0), |
| 205 | TPS65218_REGULATOR("DCDC5", TPS65218_DCDC_5, tps65218_dcdc56_pmic_ops, | 204 | TPS65218_REGULATOR("DCDC5", TPS65218_DCDC_5, tps65218_dcdc56_pmic_ops, |
| 206 | 1, -1, -1, TPS65218_REG_ENABLE1, | 205 | 1, -1, -1, TPS65218_REG_ENABLE1, |
| 207 | TPS65218_ENABLE1_DC5_EN, NULL, NULL, 0, 0), | 206 | TPS65218_ENABLE1_DC5_EN, NULL, 0, 0), |
| 208 | TPS65218_REGULATOR("DCDC6", TPS65218_DCDC_6, tps65218_dcdc56_pmic_ops, | 207 | TPS65218_REGULATOR("DCDC6", TPS65218_DCDC_6, tps65218_dcdc56_pmic_ops, |
| 209 | 1, -1, -1, TPS65218_REG_ENABLE1, | 208 | 1, -1, -1, TPS65218_REG_ENABLE1, |
| 210 | TPS65218_ENABLE1_DC6_EN, NULL, NULL, 0, 0), | 209 | TPS65218_ENABLE1_DC6_EN, NULL, 0, 0), |
| 211 | TPS65218_REGULATOR("LDO1", TPS65218_LDO_1, tps65218_ldo1_dcdc34_ops, 64, | 210 | TPS65218_REGULATOR("LDO1", TPS65218_LDO_1, tps65218_ldo1_dcdc34_ops, 64, |
| 212 | TPS65218_REG_CONTROL_LDO1, | 211 | TPS65218_REG_CONTROL_LDO1, |
| 213 | TPS65218_CONTROL_LDO1_MASK, TPS65218_REG_ENABLE2, | 212 | TPS65218_CONTROL_LDO1_MASK, TPS65218_REG_ENABLE2, |
| 214 | TPS65218_ENABLE2_LDO1_EN, NULL, ldo1_dcdc3_ranges, | 213 | TPS65218_ENABLE2_LDO1_EN, ldo1_dcdc3_ranges, |
| 215 | 2, 0), | 214 | 2, 0), |
| 216 | }; | 215 | }; |
| 217 | 216 | ||
