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authorAlexander Stein <alexander.stein@systec-electronic.com>2015-09-30 02:23:40 -0400
committerShawn Guo <shawnguo@kernel.org>2015-09-30 02:43:37 -0400
commitd9388c8432379e8c99b2315bff207f0773554462 (patch)
tree157b4ca897da1b1a0f6655c05c263cbbbe7c8e1b
parent1b9af68f325cb91ac9fc691f52d69dfb0826afd7 (diff)
clk: imx31: Do not call mxc_timer_init twice when booting with DT
mxc_timer_init must not be called from within mx31_clocks_init_dt. It will eventually be called by imx31_timer_init_dt (drivers/clocksource/timer-imx-gpt.c). This arranges the initialization code similar to clk-imx27.c Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
-rw-r--r--drivers/clk/imx/clk-imx31.c25
1 files changed, 17 insertions, 8 deletions
diff --git a/drivers/clk/imx/clk-imx31.c b/drivers/clk/imx/clk-imx31.c
index 5520e20eaceb..f65b8b1a974a 100644
--- a/drivers/clk/imx/clk-imx31.c
+++ b/drivers/clk/imx/clk-imx31.c
@@ -72,7 +72,7 @@ static struct clk ** const uart_clks[] __initconst = {
72 NULL 72 NULL
73}; 73};
74 74
75int __init mx31_clocks_init(unsigned long fref) 75static void __init _mx31_clocks_init(unsigned long fref)
76{ 76{
77 void __iomem *base; 77 void __iomem *base;
78 struct device_node *np; 78 struct device_node *np;
@@ -142,6 +142,12 @@ int __init mx31_clocks_init(unsigned long fref)
142 142
143 imx_check_clocks(clk, ARRAY_SIZE(clk)); 143 imx_check_clocks(clk, ARRAY_SIZE(clk));
144 144
145 clk_set_parent(clk[csi], clk[upll]);
146 clk_prepare_enable(clk[emi_gate]);
147 clk_prepare_enable(clk[iim_gate]);
148 mx31_revision();
149 clk_disable_unprepare(clk[iim_gate]);
150
145 np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm"); 151 np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
146 152
147 if (np) { 153 if (np) {
@@ -149,6 +155,13 @@ int __init mx31_clocks_init(unsigned long fref)
149 clk_data.clk_num = ARRAY_SIZE(clk); 155 clk_data.clk_num = ARRAY_SIZE(clk);
150 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 156 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
151 } 157 }
158}
159
160int __init mx31_clocks_init(void)
161{
162 u32 fref = 26000000; /* default */
163
164 _mx31_clocks_init(fref);
152 165
153 clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0"); 166 clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
154 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); 167 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
@@ -204,14 +217,8 @@ int __init mx31_clocks_init(unsigned long fref)
204 clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma"); 217 clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma");
205 clk_register_clkdev(clk[iim_gate], "iim", NULL); 218 clk_register_clkdev(clk[iim_gate], "iim", NULL);
206 219
207 clk_set_parent(clk[csi], clk[upll]);
208 clk_prepare_enable(clk[emi_gate]);
209 clk_prepare_enable(clk[iim_gate]);
210 mx31_revision();
211 clk_disable_unprepare(clk[iim_gate]);
212 220
213 imx_register_uart_clocks(uart_clks); 221 imx_register_uart_clocks(uart_clks);
214
215 mxc_timer_init(MX31_GPT1_BASE_ADDR, MX31_INT_GPT, GPT_TYPE_IMX31); 222 mxc_timer_init(MX31_GPT1_BASE_ADDR, MX31_INT_GPT, GPT_TYPE_IMX31);
216 223
217 return 0; 224 return 0;
@@ -230,5 +237,7 @@ int __init mx31_clocks_init_dt(void)
230 break; 237 break;
231 } 238 }
232 239
233 return mx31_clocks_init(fref); 240 _mx31_clocks_init(fref);
241
242 return 0;
234} 243}