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authorTero Kristo <t-kristo@ti.com>2015-10-14 07:49:16 -0400
committerTony Lindgren <tony@atomide.com>2015-10-14 15:35:27 -0400
commitd42f265a5d7a352d40fa2911666cd5236bc3ccaf (patch)
treea2fc266bee5a390513eba326b1360aa43a8ae9f0
parentae428a72b4c46c4553206cf5a2917846c12ef4c2 (diff)
ARM: OMAP3: clock: remove un-used core dpll re-program code
Remove the OMAP3 core DPLL re-program code, and the associated SRAM code that does the low-level programming of the DPLL divider, idling of the SDRAM etc. This code was never fully implemented in the kernel; things missing were driver side handling of core clock changes (they need to account for their functional clock rate being changed on-the-fly), and the whole framework required for handling this. Thus, there is not much point to keep carrying the low-level support code either. Signed-off-by: Tero Kristo <t-kristo@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat
-rw-r--r--arch/arm/mach-omap2/Makefile3
-rw-r--r--arch/arm/mach-omap2/clkt34xx_dpll3m2.c122
-rw-r--r--arch/arm/mach-omap2/sram.c25
-rw-r--r--arch/arm/mach-omap2/sram.h14
-rw-r--r--arch/arm/mach-omap2/sram34xx.S346
5 files changed, 0 insertions, 510 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 935869698cbc..ceefcee6bb85 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -48,11 +48,9 @@ AFLAGS_sleep44xx.o :=-Wa,-march=armv7-a$(plus_sec)
48# Functions loaded to SRAM 48# Functions loaded to SRAM
49obj-$(CONFIG_SOC_OMAP2420) += sram242x.o 49obj-$(CONFIG_SOC_OMAP2420) += sram242x.o
50obj-$(CONFIG_SOC_OMAP2430) += sram243x.o 50obj-$(CONFIG_SOC_OMAP2430) += sram243x.o
51obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o
52 51
53AFLAGS_sram242x.o :=-Wa,-march=armv6 52AFLAGS_sram242x.o :=-Wa,-march=armv6
54AFLAGS_sram243x.o :=-Wa,-march=armv6 53AFLAGS_sram243x.o :=-Wa,-march=armv6
55AFLAGS_sram34xx.o :=-Wa,-march=armv7-a
56 54
57# Restart code (OMAP4/5 currently in omap4-common.c) 55# Restart code (OMAP4/5 currently in omap4-common.c)
58obj-$(CONFIG_SOC_OMAP2420) += omap2-restart.o 56obj-$(CONFIG_SOC_OMAP2420) += omap2-restart.o
@@ -186,7 +184,6 @@ obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o
186obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o 184obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o
187obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o 185obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o
188obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) 186obj-$(CONFIG_ARCH_OMAP3) += $(clock-common)
189obj-$(CONFIG_ARCH_OMAP3) += clkt34xx_dpll3m2.o
190obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) 187obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
191obj-$(CONFIG_SOC_AM33XX) += $(clock-common) 188obj-$(CONFIG_SOC_AM33XX) += $(clock-common)
192obj-$(CONFIG_SOC_OMAP5) += $(clock-common) 189obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
deleted file mode 100644
index 3f6521313c93..000000000000
--- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
+++ /dev/null
@@ -1,122 +0,0 @@
1/*
2 * OMAP34xx M2 divider clock code
3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 * Jouni Högander
9 *
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17#undef DEBUG
18
19#include <linux/kernel.h>
20#include <linux/errno.h>
21#include <linux/clk.h>
22#include <linux/io.h>
23
24#include "clock.h"
25#include "clock3xxx.h"
26#include "sdrc.h"
27#include "sram.h"
28
29#define CYCLES_PER_MHZ 1000000
30
31struct clk *sdrc_ick_p, *arm_fck_p;
32
33/*
34 * CORE DPLL (DPLL3) M2 divider rate programming functions
35 *
36 * These call into SRAM code to do the actual CM writes, since the SDRAM
37 * is clocked from DPLL3.
38 */
39
40/**
41 * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
42 * @clk: struct clk * of DPLL to set
43 * @rate: rounded target rate
44 *
45 * Program the DPLL M2 divider with the rounded target rate. Returns
46 * -EINVAL upon error, or 0 upon success.
47 */
48int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate,
49 unsigned long parent_rate)
50{
51 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
52 u32 new_div = 0;
53 u32 unlock_dll = 0;
54 u32 c;
55 unsigned long validrate, sdrcrate, _mpurate;
56 struct omap_sdrc_params *sdrc_cs0;
57 struct omap_sdrc_params *sdrc_cs1;
58 int ret;
59 unsigned long clkrate;
60
61 if (!clk || !rate)
62 return -EINVAL;
63
64 new_div = DIV_ROUND_UP(parent_rate, rate);
65 validrate = parent_rate / new_div;
66
67 if (validrate != rate)
68 return -EINVAL;
69
70 sdrcrate = clk_get_rate(sdrc_ick_p);
71 clkrate = clk_hw_get_rate(hw);
72 if (rate > clkrate)
73 sdrcrate <<= ((rate / clkrate) >> 1);
74 else
75 sdrcrate >>= ((clkrate / rate) >> 1);
76
77 ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
78 if (ret)
79 return -EINVAL;
80
81 if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
82 pr_debug("clock: will unlock SDRC DLL\n");
83 unlock_dll = 1;
84 }
85
86 /*
87 * XXX This only needs to be done when the CPU frequency changes
88 */
89 _mpurate = clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
90 c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
91 c += 1; /* for safety */
92 c *= SDRC_MPURATE_LOOPS;
93 c >>= SDRC_MPURATE_SCALE;
94 if (c == 0)
95 c = 1;
96
97 pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
98 clkrate, validrate);
99 pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
100 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
101 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
102 if (sdrc_cs1)
103 pr_debug("clock: SDRC CS1 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
104 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
105 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
106
107 if (sdrc_cs1)
108 omap3_configure_core_dpll(
109 new_div, unlock_dll, c, rate > clkrate,
110 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
111 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
112 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
113 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
114 else
115 omap3_configure_core_dpll(
116 new_div, unlock_dll, c, rate > clkrate,
117 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
118 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
119 0, 0, 0, 0);
120 return 0;
121}
122
diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c
index cd488b80ba36..83d0e61f49e6 100644
--- a/arch/arm/mach-omap2/sram.c
+++ b/arch/arm/mach-omap2/sram.c
@@ -211,35 +211,10 @@ static inline int omap243x_sram_init(void)
211 211
212#ifdef CONFIG_ARCH_OMAP3 212#ifdef CONFIG_ARCH_OMAP3
213 213
214static u32 (*_omap3_sram_configure_core_dpll)(
215 u32 m2, u32 unlock_dll, u32 f, u32 inc,
216 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
217 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
218 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
219 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
220
221u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
222 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
223 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
224 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
225 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
226{
227 BUG_ON(!_omap3_sram_configure_core_dpll);
228 return _omap3_sram_configure_core_dpll(
229 m2, unlock_dll, f, inc,
230 sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
231 sdrc_actim_ctrl_b_0, sdrc_mr_0,
232 sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
233 sdrc_actim_ctrl_b_1, sdrc_mr_1);
234}
235
236void omap3_sram_restore_context(void) 214void omap3_sram_restore_context(void)
237{ 215{
238 omap_sram_reset(); 216 omap_sram_reset();
239 217
240 _omap3_sram_configure_core_dpll =
241 omap_sram_push(omap3_sram_configure_core_dpll,
242 omap3_sram_configure_core_dpll_sz);
243 omap_push_sram_idle(); 218 omap_push_sram_idle();
244} 219}
245 220
diff --git a/arch/arm/mach-omap2/sram.h b/arch/arm/mach-omap2/sram.h
index 948d3edefc38..18dc884267fa 100644
--- a/arch/arm/mach-omap2/sram.h
+++ b/arch/arm/mach-omap2/sram.h
@@ -15,12 +15,6 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
15 u32 mem_type); 15 u32 mem_type);
16extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); 16extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
17 17
18extern u32 omap3_configure_core_dpll(
19 u32 m2, u32 unlock_dll, u32 f, u32 inc,
20 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
21 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
22 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
23 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
24extern void omap3_sram_restore_context(void); 18extern void omap3_sram_restore_context(void);
25 19
26/* Do not use these */ 20/* Do not use these */
@@ -52,14 +46,6 @@ extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
52 u32 mem_type); 46 u32 mem_type);
53extern unsigned long omap243x_sram_reprogram_sdrc_sz; 47extern unsigned long omap243x_sram_reprogram_sdrc_sz;
54 48
55extern u32 omap3_sram_configure_core_dpll(
56 u32 m2, u32 unlock_dll, u32 f, u32 inc,
57 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
58 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
59 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
60 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
61extern unsigned long omap3_sram_configure_core_dpll_sz;
62
63#ifdef CONFIG_PM 49#ifdef CONFIG_PM
64extern void omap_push_sram_idle(void); 50extern void omap_push_sram_idle(void);
65#else 51#else
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
deleted file mode 100644
index 1446331b576a..000000000000
--- a/arch/arm/mach-omap2/sram34xx.S
+++ /dev/null
@@ -1,346 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap3/sram.S
3 *
4 * Omap3 specific functions that need to be run in internal SRAM
5 *
6 * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
7 * Copyright (C) 2008 Nokia Corporation
8 *
9 * Rajendra Nayak <rnayak@ti.com>
10 * Richard Woodruff <r-woodruff2@ti.com>
11 * Paul Walmsley
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28#include <linux/linkage.h>
29
30#include <asm/assembler.h>
31
32#include "soc.h"
33#include "iomap.h"
34#include "sdrc.h"
35#include "cm3xxx.h"
36
37/*
38 * This file needs be built unconditionally as ARM to interoperate correctly
39 * with non-Thumb-2-capable firmware.
40 */
41 .arm
42
43 .text
44
45/* r1 parameters */
46#define SDRC_NO_UNLOCK_DLL 0x0
47#define SDRC_UNLOCK_DLL 0x1
48
49/* SDRC_DLLA_CTRL bit settings */
50#define FIXEDDELAY_SHIFT 24
51#define FIXEDDELAY_MASK (0xff << FIXEDDELAY_SHIFT)
52#define DLLIDLE_MASK 0x4
53
54/*
55 * SDRC_DLLA_CTRL default values: TI hardware team indicates that
56 * FIXEDDELAY should be initialized to 0xf. This apparently was
57 * empirically determined during process testing, so no derivation
58 * was provided.
59 */
60#define FIXEDDELAY_DEFAULT (0x0f << FIXEDDELAY_SHIFT)
61
62/* SDRC_DLLA_STATUS bit settings */
63#define LOCKSTATUS_MASK 0x4
64
65/* SDRC_POWER bit settings */
66#define SRFRONIDLEREQ_MASK 0x40
67
68/* CM_IDLEST1_CORE bit settings */
69#define ST_SDRC_MASK 0x2
70
71/* CM_ICLKEN1_CORE bit settings */
72#define EN_SDRC_MASK 0x2
73
74/* CM_CLKSEL1_PLL bit settings */
75#define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b
76
77/*
78 * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
79 *
80 * Params passed in registers:
81 * r0 = new M2 divider setting (only 1 and 2 supported right now)
82 * r1 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
83 * SDRC rates < 83MHz
84 * r2 = number of MPU cycles to wait for SDRC to stabilize after
85 * reprogramming the SDRC when switching to a slower MPU speed
86 * r3 = increasing SDRC rate? (1 = yes, 0 = no)
87 *
88 * Params passed via the stack. The needed params will be copied in SRAM
89 * before use by the code in SRAM (SDRAM is not accessible during SDRC
90 * reconfiguration):
91 * new SDRC_RFR_CTRL_0 register contents
92 * new SDRC_ACTIM_CTRL_A_0 register contents
93 * new SDRC_ACTIM_CTRL_B_0 register contents
94 * new SDRC_MR_0 register value
95 * new SDRC_RFR_CTRL_1 register contents
96 * new SDRC_ACTIM_CTRL_A_1 register contents
97 * new SDRC_ACTIM_CTRL_B_1 register contents
98 * new SDRC_MR_1 register value
99 *
100 * If the param SDRC_RFR_CTRL_1 is 0, the parameters are not programmed into
101 * the SDRC CS1 registers
102 *
103 * NOTE: This code no longer attempts to program the SDRC AC timing and MR
104 * registers. This is because the code currently cannot ensure that all
105 * L3 initiators (e.g., sDMA, IVA, DSS DISPC, etc.) are not accessing the
106 * SDRAM when the registers are written. If the registers are changed while
107 * an initiator is accessing SDRAM, memory can be corrupted and/or the SDRC
108 * may enter an unpredictable state. In the future, the intent is to
109 * re-enable this code in cases where we can ensure that no initiators are
110 * touching the SDRAM. Until that time, users who know that their use case
111 * can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING
112 * option.
113 *
114 * Richard Woodruff notes that any changes to this code must be carefully
115 * audited and tested to ensure that they don't cause a TLB miss while
116 * the SDRAM is inaccessible. Such a situation will crash the system
117 * since it will cause the ARM MMU to attempt to walk the page tables.
118 * These crashes may be intermittent.
119 */
120 .align 3
121ENTRY(omap3_sram_configure_core_dpll)
122 stmfd sp!, {r1-r12, lr} @ store regs to stack
123
124 @ pull the extra args off the stack
125 @ and store them in SRAM
126
127/*
128 * PC-relative stores are deprecated in ARMv7 and lead to undefined behaviour
129 * in Thumb-2: use a r7 as a base instead.
130 * Be careful not to clobber r7 when maintaing this file.
131 */
132 THUMB( adr r7, omap3_sram_configure_core_dpll )
133 .macro strtext Rt:req, label:req
134 ARM( str \Rt, \label )
135 THUMB( str \Rt, [r7, \label - omap3_sram_configure_core_dpll] )
136 .endm
137
138 ldr r4, [sp, #52]
139 strtext r4, omap_sdrc_rfr_ctrl_0_val
140 ldr r4, [sp, #56]
141 strtext r4, omap_sdrc_actim_ctrl_a_0_val
142 ldr r4, [sp, #60]
143 strtext r4, omap_sdrc_actim_ctrl_b_0_val
144 ldr r4, [sp, #64]
145 strtext r4, omap_sdrc_mr_0_val
146 ldr r4, [sp, #68]
147 strtext r4, omap_sdrc_rfr_ctrl_1_val
148 cmp r4, #0 @ if SDRC_RFR_CTRL_1 is 0,
149 beq skip_cs1_params @ do not use cs1 params
150 ldr r4, [sp, #72]
151 strtext r4, omap_sdrc_actim_ctrl_a_1_val
152 ldr r4, [sp, #76]
153 strtext r4, omap_sdrc_actim_ctrl_b_1_val
154 ldr r4, [sp, #80]
155 strtext r4, omap_sdrc_mr_1_val
156skip_cs1_params:
157 mrc p15, 0, r8, c1, c0, 0 @ read ctrl register
158 bic r10, r8, #0x800 @ clear Z-bit, disable branch prediction
159 mcr p15, 0, r10, c1, c0, 0 @ write ctrl register
160 dsb @ flush buffered writes to interconnect
161 isb @ prevent speculative exec past here
162 cmp r3, #1 @ if increasing SDRC clk rate,
163 bleq configure_sdrc @ program the SDRC regs early (for RFR)
164 cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state
165 bleq unlock_dll
166 blne lock_dll
167 bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
168 bl configure_core_dpll @ change the DPLL3 M2 divider
169 mov r12, r2
170 bl wait_clk_stable @ wait for SDRC to stabilize
171 bl enable_sdrc @ take SDRC out of idle
172 cmp r1, #SDRC_UNLOCK_DLL @ wait for DLL status to change
173 bleq wait_dll_unlock
174 blne wait_dll_lock
175 cmp r3, #1 @ if increasing SDRC clk rate,
176 beq return_to_sdram @ return to SDRAM code, otherwise,
177 bl configure_sdrc @ reprogram SDRC regs now
178return_to_sdram:
179 mcr p15, 0, r8, c1, c0, 0 @ restore ctrl register
180 isb @ prevent speculative exec past here
181 mov r0, #0 @ return value
182 ldmfd sp!, {r1-r12, pc} @ restore regs and return
183unlock_dll:
184 ldr r11, omap3_sdrc_dlla_ctrl
185 ldr r12, [r11]
186 bic r12, r12, #FIXEDDELAY_MASK
187 orr r12, r12, #FIXEDDELAY_DEFAULT
188 orr r12, r12, #DLLIDLE_MASK
189 str r12, [r11] @ (no OCP barrier needed)
190 bx lr
191lock_dll:
192 ldr r11, omap3_sdrc_dlla_ctrl
193 ldr r12, [r11]
194 bic r12, r12, #DLLIDLE_MASK
195 str r12, [r11] @ (no OCP barrier needed)
196 bx lr
197sdram_in_selfrefresh:
198 ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
199 ldr r12, [r11] @ read the contents of SDRC_POWER
200 mov r9, r12 @ keep a copy of SDRC_POWER bits
201 orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
202 str r12, [r11] @ write back to SDRC_POWER register
203 ldr r12, [r11] @ posted-write barrier for SDRC
204idle_sdrc:
205 ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
206 ldr r12, [r11]
207 bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC
208 str r12, [r11]
209wait_sdrc_idle:
210 ldr r11, omap3_cm_idlest1_core
211 ldr r12, [r11]
212 and r12, r12, #ST_SDRC_MASK @ check for SDRC idle
213 cmp r12, #ST_SDRC_MASK
214 bne wait_sdrc_idle
215 bx lr
216configure_core_dpll:
217 ldr r11, omap3_cm_clksel1_pll
218 ldr r12, [r11]
219 ldr r10, core_m2_mask_val @ modify m2 for core dpll
220 and r12, r12, r10
221 orr r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
222 str r12, [r11]
223 ldr r12, [r11] @ posted-write barrier for CM
224 bx lr
225wait_clk_stable:
226 subs r12, r12, #1
227 bne wait_clk_stable
228 bx lr
229enable_sdrc:
230 ldr r11, omap3_cm_iclken1_core
231 ldr r12, [r11]
232 orr r12, r12, #EN_SDRC_MASK @ enable iclk bit for SDRC
233 str r12, [r11]
234wait_sdrc_idle1:
235 ldr r11, omap3_cm_idlest1_core
236 ldr r12, [r11]
237 and r12, r12, #ST_SDRC_MASK
238 cmp r12, #0
239 bne wait_sdrc_idle1
240restore_sdrc_power_val:
241 ldr r11, omap3_sdrc_power
242 str r9, [r11] @ restore SDRC_POWER, no barrier needed
243 bx lr
244wait_dll_lock:
245 ldr r11, omap3_sdrc_dlla_status
246 ldr r12, [r11]
247 and r12, r12, #LOCKSTATUS_MASK
248 cmp r12, #LOCKSTATUS_MASK
249 bne wait_dll_lock
250 bx lr
251wait_dll_unlock:
252 ldr r11, omap3_sdrc_dlla_status
253 ldr r12, [r11]
254 and r12, r12, #LOCKSTATUS_MASK
255 cmp r12, #0x0
256 bne wait_dll_unlock
257 bx lr
258configure_sdrc:
259 ldr r12, omap_sdrc_rfr_ctrl_0_val @ fetch value from SRAM
260 ldr r11, omap3_sdrc_rfr_ctrl_0 @ fetch addr from SRAM
261 str r12, [r11] @ store
262#ifdef CONFIG_OMAP3_SDRC_AC_TIMING
263 ldr r12, omap_sdrc_actim_ctrl_a_0_val
264 ldr r11, omap3_sdrc_actim_ctrl_a_0
265 str r12, [r11]
266 ldr r12, omap_sdrc_actim_ctrl_b_0_val
267 ldr r11, omap3_sdrc_actim_ctrl_b_0
268 str r12, [r11]
269 ldr r12, omap_sdrc_mr_0_val
270 ldr r11, omap3_sdrc_mr_0
271 str r12, [r11]
272#endif
273 ldr r12, omap_sdrc_rfr_ctrl_1_val
274 cmp r12, #0 @ if SDRC_RFR_CTRL_1 is 0,
275 beq skip_cs1_prog @ do not program cs1 params
276 ldr r11, omap3_sdrc_rfr_ctrl_1
277 str r12, [r11]
278#ifdef CONFIG_OMAP3_SDRC_AC_TIMING
279 ldr r12, omap_sdrc_actim_ctrl_a_1_val
280 ldr r11, omap3_sdrc_actim_ctrl_a_1
281 str r12, [r11]
282 ldr r12, omap_sdrc_actim_ctrl_b_1_val
283 ldr r11, omap3_sdrc_actim_ctrl_b_1
284 str r12, [r11]
285 ldr r12, omap_sdrc_mr_1_val
286 ldr r11, omap3_sdrc_mr_1
287 str r12, [r11]
288#endif
289skip_cs1_prog:
290 ldr r12, [r11] @ posted-write barrier for SDRC
291 bx lr
292
293 .align
294omap3_sdrc_power:
295 .word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
296omap3_cm_clksel1_pll:
297 .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
298omap3_cm_idlest1_core:
299 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
300omap3_cm_iclken1_core:
301 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
302
303omap3_sdrc_rfr_ctrl_0:
304 .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
305omap3_sdrc_rfr_ctrl_1:
306 .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
307omap3_sdrc_actim_ctrl_a_0:
308 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
309omap3_sdrc_actim_ctrl_a_1:
310 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
311omap3_sdrc_actim_ctrl_b_0:
312 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
313omap3_sdrc_actim_ctrl_b_1:
314 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
315omap3_sdrc_mr_0:
316 .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
317omap3_sdrc_mr_1:
318 .word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
319omap_sdrc_rfr_ctrl_0_val:
320 .word 0xDEADBEEF
321omap_sdrc_rfr_ctrl_1_val:
322 .word 0xDEADBEEF
323omap_sdrc_actim_ctrl_a_0_val:
324 .word 0xDEADBEEF
325omap_sdrc_actim_ctrl_a_1_val:
326 .word 0xDEADBEEF
327omap_sdrc_actim_ctrl_b_0_val:
328 .word 0xDEADBEEF
329omap_sdrc_actim_ctrl_b_1_val:
330 .word 0xDEADBEEF
331omap_sdrc_mr_0_val:
332 .word 0xDEADBEEF
333omap_sdrc_mr_1_val:
334 .word 0xDEADBEEF
335
336omap3_sdrc_dlla_status:
337 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
338omap3_sdrc_dlla_ctrl:
339 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
340core_m2_mask_val:
341 .word 0x07FFFFFF
342ENDPROC(omap3_sram_configure_core_dpll)
343
344ENTRY(omap3_sram_configure_core_dpll_sz)
345 .word . - omap3_sram_configure_core_dpll
346
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-13 23:24:18 -0400