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authorAlexander Müller <serveralex@gmail.com>2016-08-27 13:40:50 -0400
committerMichael Turquette <mturquette@baylibre.com>2016-09-01 20:31:47 -0400
commitd0c175da68d7e8f6b52b9fcaffae1d73d51a8655 (patch)
tree3e89c2c9e6623fa2b28465ecae72b4f43e9edb36
parent23353817f85934528d056541894c70346c3822b3 (diff)
meson: clk: Move register definitions to meson8b.h
Move the register definitions into a separate header file to reflect the gxbb implementation. Signed-off-by: Alexander Müller <serveralex@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1472319654-59048-3-git-send-email-serveralex@gmail.com
-rw-r--r--drivers/clk/meson/meson8b.c17
-rw-r--r--drivers/clk/meson/meson8b.h40
2 files changed, 41 insertions, 16 deletions
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 4c9413cdf373..d52ae534e056 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -28,22 +28,7 @@
28#include <linux/init.h> 28#include <linux/init.h>
29 29
30#include "clkc.h" 30#include "clkc.h"
31 31#include "meson8b.h"
32/*
33 * Clock controller register offsets
34 *
35 * Register offsets from the HardKernel[0] data sheet are listed in comment
36 * blocks below. Those offsets must be multiplied by 4 before adding them to
37 * the base address to get the right value
38 *
39 * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
40 */
41#define MESON8B_REG_SYS_CPU_CNTL1 0x015c /* 0x57 offset in data sheet */
42#define MESON8B_REG_HHI_MPEG 0x0174 /* 0x5d offset in data sheet */
43#define MESON8B_REG_MALI 0x01b0 /* 0x6c offset in data sheet */
44#define MESON8B_REG_PLL_FIXED 0x0280
45#define MESON8B_REG_PLL_SYS 0x0300
46#define MESON8B_REG_PLL_VID 0x0320
47 32
48static DEFINE_SPINLOCK(clk_lock); 33static DEFINE_SPINLOCK(clk_lock);
49 34
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
new file mode 100644
index 000000000000..5b9cb9f72471
--- /dev/null
+++ b/drivers/clk/meson/meson8b.h
@@ -0,0 +1,40 @@
1/*
2 * Copyright (c) 2015 Endless Mobile, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * Copyright (c) 2016 BayLibre, Inc.
6 * Michael Turquette <mturquette@baylibre.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#ifndef __MESON8B_H
22#define __MESON8B_H
23
24/*
25 * Clock controller register offsets
26 *
27 * Register offsets from the HardKernel[0] data sheet are listed in comment
28 * blocks below. Those offsets must be multiplied by 4 before adding them to
29 * the base address to get the right value
30 *
31 * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
32 */
33#define MESON8B_REG_SYS_CPU_CNTL1 0x015c /* 0x57 offset in data sheet */
34#define MESON8B_REG_HHI_MPEG 0x0174 /* 0x5d offset in data sheet */
35#define MESON8B_REG_MALI 0x01b0 /* 0x6c offset in data sheet */
36#define MESON8B_REG_PLL_FIXED 0x0280
37#define MESON8B_REG_PLL_SYS 0x0300
38#define MESON8B_REG_PLL_VID 0x0320
39
40#endif /* __MESON8B_H */