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authorVineet Gupta <vgupta@synopsys.com>2016-12-19 14:38:38 -0500
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2017-01-09 02:32:21 -0500
commitce7ec3d7526cb26307eb5fee516b2873a88ca3ef (patch)
tree970278a6152140195064d2410345ecb90b81652a
parent9d33a399566771b023a08f490344b70a200c87da (diff)
ARC: mm: arc700: Don't assume 2 colours for aliasing VIPT dcache
commit 08fe007968b2b45e831daf74899f79a54d73f773 upstream. An ARC700 customer reported linux boot crashes when upgrading to bigger L1 dcache (64K from 32K). Turns out they had an aliasing VIPT config and current code only assumed 2 colours, while theirs had 4. So default to 4 colours and complain if there are fewer. Ideally this needs to be a Kconfig option, but heck that's too much of hassle for a single user. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--arch/arc/include/asm/cacheflush.h6
-rw-r--r--arch/arc/mm/cache.c13
2 files changed, 13 insertions, 6 deletions
diff --git a/arch/arc/include/asm/cacheflush.h b/arch/arc/include/asm/cacheflush.h
index a093adbdb017..fc662f49c55a 100644
--- a/arch/arc/include/asm/cacheflush.h
+++ b/arch/arc/include/asm/cacheflush.h
@@ -85,6 +85,10 @@ void flush_anon_page(struct vm_area_struct *vma,
85 */ 85 */
86#define PG_dc_clean PG_arch_1 86#define PG_dc_clean PG_arch_1
87 87
88#define CACHE_COLORS_NUM 4
89#define CACHE_COLORS_MSK (CACHE_COLORS_NUM - 1)
90#define CACHE_COLOR(addr) (((unsigned long)(addr) >> (PAGE_SHIFT)) & CACHE_COLORS_MSK)
91
88/* 92/*
89 * Simple wrapper over config option 93 * Simple wrapper over config option
90 * Bootup code ensures that hardware matches kernel configuration 94 * Bootup code ensures that hardware matches kernel configuration
@@ -94,8 +98,6 @@ static inline int cache_is_vipt_aliasing(void)
94 return IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING); 98 return IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING);
95} 99}
96 100
97#define CACHE_COLOR(addr) (((unsigned long)(addr) >> (PAGE_SHIFT)) & 1)
98
99/* 101/*
100 * checks if two addresses (after page aligning) index into same cache set 102 * checks if two addresses (after page aligning) index into same cache set
101 */ 103 */
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 50d71695cd4e..8147583c4434 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -979,11 +979,16 @@ void arc_cache_init(void)
979 /* check for D-Cache aliasing on ARCompact: ARCv2 has PIPT */ 979 /* check for D-Cache aliasing on ARCompact: ARCv2 has PIPT */
980 if (is_isa_arcompact()) { 980 if (is_isa_arcompact()) {
981 int handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING); 981 int handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING);
982 982 int num_colors = dc->sz_k/dc->assoc/TO_KB(PAGE_SIZE);
983 if (dc->alias && !handled) 983
984 panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); 984 if (dc->alias) {
985 else if (!dc->alias && handled) 985 if (!handled)
986 panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
987 if (CACHE_COLORS_NUM != num_colors)
988 panic("CACHE_COLORS_NUM not optimized for config\n");
989 } else if (!dc->alias && handled) {
986 panic("Disable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); 990 panic("Disable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
991 }
987 } 992 }
988 } 993 }
989 994