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authorJun Nie <jun.nie@linaro.org>2016-09-06 02:02:42 -0400
committerStephen Boyd <sboyd@codeaurora.org>2016-09-14 16:50:33 -0400
commitca0233285a93222b2b0c7384b9345711b3d68b5c (patch)
treee78f9315b19c8dfb2e638d0a660041df0ece9eba
parent8d9a0860b75525e3cf240bc152bfdeaeb2e562a1 (diff)
clk: zx: register ZX296718 clocks
The ZX296718 clocks are statically listed and registered. More clock will be added later. Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/zx296718-clk.txt35
-rw-r--r--drivers/clk/zte/Makefile1
-rw-r--r--drivers/clk/zte/clk-zx296718.c924
-rw-r--r--drivers/clk/zte/clk.h125
-rw-r--r--include/dt-bindings/clock/zx296718-clock.h163
5 files changed, 1248 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/zx296718-clk.txt b/Documentation/devicetree/bindings/clock/zx296718-clk.txt
new file mode 100644
index 000000000000..8c18b7b237bf
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/zx296718-clk.txt
@@ -0,0 +1,35 @@
1Device Tree Clock bindings for ZTE zx296718
2
3This binding uses the common clock binding[1].
4
5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6
7Required properties:
8- compatible : shall be one of the following:
9 "zte,zx296718-topcrm":
10 zx296718 top clock selection, divider and gating
11
12 "zte,zx296718-lsp0crm" and
13 "zte,zx296718-lsp1crm":
14 zx296718 device level clock selection and gating
15
16- reg: Address and length of the register set
17
18The clock consumer should specify the desired clock by having the clock
19ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296718-clock.h
20for the full list of zx296718 clock IDs.
21
22
23topclk: topcrm@1461000 {
24 compatible = "zte,zx296718-topcrm-clk";
25 reg = <0x01461000 0x1000>;
26 #clock-cells = <1>;
27};
28
29usbphy0:usb-phy0 {
30 compatible = "zte,zx296718-usb-phy";
31 #phy-cells = <0>;
32 clocks = <&topclk USB20_PHY_CLK>;
33 clock-names = "phyclk";
34 status = "okay";
35};
diff --git a/drivers/clk/zte/Makefile b/drivers/clk/zte/Makefile
index 74005aa322a2..83374bfc4c07 100644
--- a/drivers/clk/zte/Makefile
+++ b/drivers/clk/zte/Makefile
@@ -1,2 +1,3 @@
1obj-y := clk.o 1obj-y := clk.o
2obj-$(CONFIG_SOC_ZX296702) += clk-zx296702.o 2obj-$(CONFIG_SOC_ZX296702) += clk-zx296702.o
3obj-$(CONFIG_ARCH_ZX) += clk-zx296718.o
diff --git a/drivers/clk/zte/clk-zx296718.c b/drivers/clk/zte/clk-zx296718.c
new file mode 100644
index 000000000000..025e324fab5c
--- /dev/null
+++ b/drivers/clk/zte/clk-zx296718.c
@@ -0,0 +1,924 @@
1/*
2 * Copyright (C) 2015 - 2016 ZTE Corporation.
3 * Copyright (C) 2016 Linaro Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/clk-provider.h>
10#include <linux/device.h>
11#include <linux/kernel.h>
12#include <linux/of_address.h>
13#include <linux/of_device.h>
14#include <linux/platform_device.h>
15
16#include <dt-bindings/clock/zx296718-clock.h>
17#include "clk.h"
18
19/* TOP CRM */
20#define TOP_CLK_MUX0 0x04
21#define TOP_CLK_MUX1 0x08
22#define TOP_CLK_MUX2 0x0c
23#define TOP_CLK_MUX3 0x10
24#define TOP_CLK_MUX4 0x14
25#define TOP_CLK_MUX5 0x18
26#define TOP_CLK_MUX6 0x1c
27#define TOP_CLK_MUX7 0x20
28#define TOP_CLK_MUX9 0x28
29
30
31#define TOP_CLK_GATE0 0x34
32#define TOP_CLK_GATE1 0x38
33#define TOP_CLK_GATE2 0x3c
34#define TOP_CLK_GATE3 0x40
35#define TOP_CLK_GATE4 0x44
36#define TOP_CLK_GATE5 0x48
37#define TOP_CLK_GATE6 0x4c
38
39#define TOP_CLK_DIV0 0x58
40
41#define PLL_CPU_REG 0x80
42#define PLL_VGA_REG 0xb0
43#define PLL_DDR_REG 0xa0
44
45/* LSP0 CRM */
46#define LSP0_TIMER3_CLK 0x4
47#define LSP0_TIMER4_CLK 0x8
48#define LSP0_TIMER5_CLK 0xc
49#define LSP0_UART3_CLK 0x10
50#define LSP0_UART1_CLK 0x14
51#define LSP0_UART2_CLK 0x18
52#define LSP0_SPIFC0_CLK 0x1c
53#define LSP0_I2C4_CLK 0x20
54#define LSP0_I2C5_CLK 0x24
55#define LSP0_SSP0_CLK 0x28
56#define LSP0_SSP1_CLK 0x2c
57#define LSP0_USIM0_CLK 0x30
58#define LSP0_GPIO_CLK 0x34
59#define LSP0_I2C3_CLK 0x38
60
61/* LSP1 CRM */
62#define LSP1_UART4_CLK 0x08
63#define LSP1_UART5_CLK 0x0c
64#define LSP1_PWM_CLK 0x10
65#define LSP1_I2C2_CLK 0x14
66#define LSP1_SSP2_CLK 0x1c
67#define LSP1_SSP3_CLK 0x20
68#define LSP1_SSP4_CLK 0x24
69#define LSP1_USIM1_CLK 0x28
70
71/* audio lsp */
72#define AUDIO_I2S0_DIV_CFG1 0x10
73#define AUDIO_I2S0_DIV_CFG2 0x14
74#define AUDIO_I2S0_CLK 0x18
75#define AUDIO_I2S1_DIV_CFG1 0x20
76#define AUDIO_I2S1_DIV_CFG2 0x24
77#define AUDIO_I2S1_CLK 0x28
78#define AUDIO_I2S2_DIV_CFG1 0x30
79#define AUDIO_I2S2_DIV_CFG2 0x34
80#define AUDIO_I2S2_CLK 0x38
81#define AUDIO_I2S3_DIV_CFG1 0x40
82#define AUDIO_I2S3_DIV_CFG2 0x44
83#define AUDIO_I2S3_CLK 0x48
84#define AUDIO_I2C0_CLK 0x50
85#define AUDIO_SPDIF0_DIV_CFG1 0x60
86#define AUDIO_SPDIF0_DIV_CFG2 0x64
87#define AUDIO_SPDIF0_CLK 0x68
88#define AUDIO_SPDIF1_DIV_CFG1 0x70
89#define AUDIO_SPDIF1_DIV_CFG2 0x74
90#define AUDIO_SPDIF1_CLK 0x78
91#define AUDIO_TIMER_CLK 0x80
92#define AUDIO_TDM_CLK 0x90
93#define AUDIO_TS_CLK 0xa0
94
95static DEFINE_SPINLOCK(clk_lock);
96
97static struct zx_pll_config pll_cpu_table[] = {
98 PLL_RATE(1312000000, 0x00103621, 0x04aaaaaa),
99 PLL_RATE(1407000000, 0x00103a21, 0x04aaaaaa),
100 PLL_RATE(1503000000, 0x00103e21, 0x04aaaaaa),
101 PLL_RATE(1600000000, 0x00104221, 0x04aaaaaa),
102};
103
104PNAME(osc) = {
105 "osc24m",
106 "osc32k",
107};
108
109PNAME(dbg_wclk_p) = {
110 "clk334m",
111 "clk466m",
112 "clk396m",
113 "clk250m",
114};
115
116PNAME(a72_coreclk_p) = {
117 "osc24m",
118 "pll_mm0_1188m",
119 "pll_mm1_1296m",
120 "clk1000m",
121 "clk648m",
122 "clk1600m",
123 "pll_audio_1800m",
124 "pll_vga_1800m",
125};
126
127PNAME(cpu_periclk_p) = {
128 "osc24m",
129 "clk500m",
130 "clk594m",
131 "clk466m",
132 "clk294m",
133 "clk334m",
134 "clk250m",
135 "clk125m",
136};
137
138PNAME(a53_coreclk_p) = {
139 "osc24m",
140 "clk1000m",
141 "pll_mm0_1188m",
142 "clk648m",
143 "clk500m",
144 "clk800m",
145 "clk1600m",
146 "pll_audio_1800m",
147};
148
149PNAME(sec_wclk_p) = {
150 "osc24m",
151 "clk396m",
152 "clk334m",
153 "clk297m",
154 "clk250m",
155 "clk198m",
156 "clk148m5",
157 "clk99m",
158};
159
160PNAME(sd_nand_wclk_p) = {
161 "osc24m",
162 "clk49m5",
163 "clk99m",
164 "clk198m",
165 "clk167m",
166 "clk148m5",
167 "clk125m",
168 "clk216m",
169};
170
171PNAME(emmc_wclk_p) = {
172 "osc24m",
173 "clk198m",
174 "clk99m",
175 "clk396m",
176 "clk334m",
177 "clk297m",
178 "clk250m",
179 "clk148m5",
180};
181
182PNAME(clk32_p) = {
183 "osc32k",
184 "clk32k768",
185};
186
187PNAME(usb_ref24m_p) = {
188 "osc32k",
189 "clk32k768",
190};
191
192PNAME(sys_noc_alck_p) = {
193 "osc24m",
194 "clk250m",
195 "clk198m",
196 "clk148m5",
197 "clk108m",
198 "clk54m",
199 "clk216m",
200 "clk240m",
201};
202
203PNAME(vde_aclk_p) = {
204 "clk334m",
205 "clk594m",
206 "clk500m",
207 "clk432m",
208 "clk480m",
209 "clk297m",
210 "clk_vga", /*600MHz*/
211 "clk294m",
212};
213
214PNAME(vce_aclk_p) = {
215 "clk334m",
216 "clk594m",
217 "clk500m",
218 "clk432m",
219 "clk396m",
220 "clk297m",
221 "clk_vga", /*600MHz*/
222 "clk294m",
223};
224
225PNAME(hde_aclk_p) = {
226 "clk334m",
227 "clk594m",
228 "clk500m",
229 "clk432m",
230 "clk396m",
231 "clk297m",
232 "clk_vga", /*600MHz*/
233 "clk294m",
234};
235
236PNAME(gpu_aclk_p) = {
237 "clk334m",
238 "clk648m",
239 "clk594m",
240 "clk500m",
241 "clk396m",
242 "clk297m",
243 "clk_vga", /*600MHz*/
244 "clk294m",
245};
246
247PNAME(sappu_aclk_p) = {
248 "clk396m",
249 "clk500m",
250 "clk250m",
251 "clk148m5",
252};
253
254PNAME(sappu_wclk_p) = {
255 "clk198m",
256 "clk396m",
257 "clk334m",
258 "clk297m",
259 "clk250m",
260 "clk148m5",
261 "clk125m",
262 "clk99m",
263};
264
265PNAME(vou_aclk_p) = {
266 "clk334m",
267 "clk594m",
268 "clk500m",
269 "clk432m",
270 "clk396m",
271 "clk297m",
272 "clk_vga", /*600MHz*/
273 "clk294m",
274};
275
276PNAME(vou_main_wclk_p) = {
277 "clk108m",
278 "clk594m",
279 "clk297m",
280 "clk148m5",
281 "clk74m25",
282 "clk54m",
283 "clk27m",
284 "clk_vga",
285};
286
287PNAME(vou_aux_wclk_p) = {
288 "clk108m",
289 "clk148m5",
290 "clk74m25",
291 "clk54m",
292 "clk27m",
293 "clk_vga",
294 "clk54m_mm0",
295 "clk"
296};
297
298PNAME(vou_ppu_wclk_p) = {
299 "clk334m",
300 "clk432m",
301 "clk396m",
302 "clk297m",
303 "clk250m",
304 "clk125m",
305 "clk198m",
306 "clk99m",
307};
308
309PNAME(vga_i2c_wclk_p) = {
310 "osc24m",
311 "clk99m",
312};
313
314PNAME(viu_m0_aclk_p) = {
315 "clk334m",
316 "clk432m",
317 "clk396m",
318 "clk297m",
319 "clk250m",
320 "clk125m",
321 "clk198m",
322 "osc24m",
323};
324
325PNAME(viu_m1_aclk_p) = {
326 "clk198m",
327 "clk250m",
328 "clk297m",
329 "clk125m",
330 "clk396m",
331 "clk334m",
332 "clk148m5",
333 "osc24m",
334};
335
336PNAME(viu_clk_p) = {
337 "clk198m",
338 "clk334m",
339 "clk297m",
340 "clk250m",
341 "clk396m",
342 "clk125m",
343 "clk99m",
344 "clk148m5",
345};
346
347PNAME(viu_jpeg_clk_p) = {
348 "clk334m",
349 "clk480m",
350 "clk432m",
351 "clk396m",
352 "clk297m",
353 "clk250m",
354 "clk125m",
355 "clk198m",
356};
357
358PNAME(ts_sys_clk_p) = {
359 "clk192m",
360 "clk167m",
361 "clk125m",
362 "clk99m",
363};
364
365PNAME(wdt_ares_p) = {
366 "osc24m",
367 "clk32k"
368};
369
370static struct clk_zx_pll zx296718_pll_clk[] = {
371 ZX296718_PLL("pll_cpu", "osc24m", PLL_CPU_REG, pll_cpu_table),
372};
373
374static struct zx_clk_fixed_factor top_ffactor_clk[] = {
375 FFACTOR(0, "clk4m", "osc24m", 1, 6, 0),
376 FFACTOR(0, "clk2m", "osc24m", 1, 12, 0),
377 /* pll cpu */
378 FFACTOR(0, "clk1600m", "pll_cpu", 1, 1, CLK_SET_RATE_PARENT),
379 FFACTOR(0, "clk800m", "pll_cpu", 1, 2, CLK_SET_RATE_PARENT),
380 /* pll mac */
381 FFACTOR(0, "clk25m", "pll_mac", 1, 40, 0),
382 FFACTOR(0, "clk125m", "pll_mac", 1, 8, 0),
383 FFACTOR(0, "clk250m", "pll_mac", 1, 4, 0),
384 FFACTOR(0, "clk50m", "pll_mac", 1, 20, 0),
385 FFACTOR(0, "clk500m", "pll_mac", 1, 2, 0),
386 FFACTOR(0, "clk1000m", "pll_mac", 1, 1, 0),
387 FFACTOR(0, "clk334m", "pll_mac", 1, 3, 0),
388 FFACTOR(0, "clk167m", "pll_mac", 1, 6, 0),
389 /* pll mm */
390 FFACTOR(0, "clk54m_mm0", "pll_mm0", 1, 22, 0),
391 FFACTOR(0, "clk74m25", "pll_mm0", 1, 16, 0),
392 FFACTOR(0, "clk148m5", "pll_mm0", 1, 8, 0),
393 FFACTOR(0, "clk297m", "pll_mm0", 1, 4, 0),
394 FFACTOR(0, "clk594m", "pll_mm0", 1, 2, 0),
395 FFACTOR(0, "pll_mm0_1188m", "pll_mm0", 1, 1, 0),
396 FFACTOR(0, "clk396m", "pll_mm0", 1, 3, 0),
397 FFACTOR(0, "clk198m", "pll_mm0", 1, 6, 0),
398 FFACTOR(0, "clk99m", "pll_mm0", 1, 12, 0),
399 FFACTOR(0, "clk49m5", "pll_mm0", 1, 24, 0),
400 /* pll mm */
401 FFACTOR(0, "clk324m", "pll_mm1", 1, 4, 0),
402 FFACTOR(0, "clk648m", "pll_mm1", 1, 2, 0),
403 FFACTOR(0, "pll_mm1_1296m", "pll_mm1", 1, 1, 0),
404 FFACTOR(0, "clk216m", "pll_mm1", 1, 6, 0),
405 FFACTOR(0, "clk432m", "pll_mm1", 1, 3, 0),
406 FFACTOR(0, "clk108m", "pll_mm1", 1, 12, 0),
407 FFACTOR(0, "clk72m", "pll_mm1", 1, 18, 0),
408 FFACTOR(0, "clk27m", "pll_mm1", 1, 48, 0),
409 FFACTOR(0, "clk54m", "pll_mm1", 1, 24, 0),
410 /* vga */
411 FFACTOR(0, "pll_vga_1800m", "pll_vga", 1, 1, 0),
412 FFACTOR(0, "clk_vga", "pll_vga", 1, 2, 0),
413 /* pll ddr */
414 FFACTOR(0, "clk466m", "pll_ddr", 1, 2, 0),
415
416 /* pll audio */
417 FFACTOR(0, "pll_audio_1800m", "pll_audio", 1, 1, 0),
418 FFACTOR(0, "clk32k768", "pll_audio", 1, 27000, 0),
419 FFACTOR(0, "clk16m384", "pll_audio", 1, 54, 0),
420 FFACTOR(0, "clk294m", "pll_audio", 1, 3, 0),
421
422 /* pll hsic*/
423 FFACTOR(0, "clk240m", "pll_hsic", 1, 4, 0),
424 FFACTOR(0, "clk480m", "pll_hsic", 1, 2, 0),
425 FFACTOR(0, "clk192m", "pll_hsic", 1, 5, 0),
426 FFACTOR(0, "clk_pll_24m", "pll_hsic", 1, 40, 0),
427 FFACTOR(0, "emmc_mux_div2", "emmc_mux", 1, 2, CLK_SET_RATE_PARENT),
428};
429
430static struct clk_div_table noc_div_table[] = {
431 { .val = 1, .div = 2, },
432 { .val = 3, .div = 4, },
433};
434static struct zx_clk_div top_div_clk[] = {
435 DIV_T(0, "sys_noc_hclk", "sys_noc_aclk", TOP_CLK_DIV0, 0, 2, 0, noc_div_table),
436 DIV_T(0, "sys_noc_pclk", "sys_noc_aclk", TOP_CLK_DIV0, 4, 2, 0, noc_div_table),
437};
438
439static struct zx_clk_mux top_mux_clk[] = {
440 MUX(0, "dbg_mux", dbg_wclk_p, TOP_CLK_MUX0, 12, 2),
441 MUX(0, "a72_mux", a72_coreclk_p, TOP_CLK_MUX0, 8, 3),
442 MUX(0, "cpu_peri_mux", cpu_periclk_p, TOP_CLK_MUX0, 4, 3),
443 MUX_F(0, "a53_mux", a53_coreclk_p, TOP_CLK_MUX0, 0, 3, CLK_SET_RATE_PARENT, 0),
444 MUX(0, "sys_noc_aclk", sys_noc_alck_p, TOP_CLK_MUX1, 0, 3),
445 MUX(0, "sec_mux", sec_wclk_p, TOP_CLK_MUX2, 16, 3),
446 MUX(0, "sd1_mux", sd_nand_wclk_p, TOP_CLK_MUX2, 12, 3),
447 MUX(0, "sd0_mux", sd_nand_wclk_p, TOP_CLK_MUX2, 8, 3),
448 MUX(0, "emmc_mux", emmc_wclk_p, TOP_CLK_MUX2, 4, 3),
449 MUX(0, "nand_mux", sd_nand_wclk_p, TOP_CLK_MUX2, 0, 3),
450 MUX(0, "usb_ref24m_mux", usb_ref24m_p, TOP_CLK_MUX9, 16, 1),
451 MUX(0, "clk32k", clk32_p, TOP_CLK_MUX9, 12, 1),
452 MUX_F(0, "wdt_mux", wdt_ares_p, TOP_CLK_MUX9, 8, 1, CLK_SET_RATE_PARENT, 0),
453 MUX(0, "timer_mux", osc, TOP_CLK_MUX9, 4, 1),
454 MUX(0, "vde_mux", vde_aclk_p, TOP_CLK_MUX4, 0, 3),
455 MUX(0, "vce_mux", vce_aclk_p, TOP_CLK_MUX4, 4, 3),
456 MUX(0, "hde_mux", hde_aclk_p, TOP_CLK_MUX4, 8, 3),
457 MUX(0, "gpu_mux", gpu_aclk_p, TOP_CLK_MUX5, 0, 3),
458 MUX(0, "sappu_a_mux", sappu_aclk_p, TOP_CLK_MUX5, 4, 2),
459 MUX(0, "sappu_w_mux", sappu_wclk_p, TOP_CLK_MUX5, 8, 3),
460 MUX(0, "vou_a_mux", vou_aclk_p, TOP_CLK_MUX7, 0, 3),
461 MUX(0, "vou_main_w_mux", vou_main_wclk_p, TOP_CLK_MUX7, 4, 3),
462 MUX(0, "vou_aux_w_mux", vou_aux_wclk_p, TOP_CLK_MUX7, 8, 3),
463 MUX(0, "vou_ppu_w_mux", vou_ppu_wclk_p, TOP_CLK_MUX7, 12, 3),
464 MUX(0, "vga_i2c_mux", vga_i2c_wclk_p, TOP_CLK_MUX7, 16, 1),
465 MUX(0, "viu_m0_a_mux", viu_m0_aclk_p, TOP_CLK_MUX6, 0, 3),
466 MUX(0, "viu_m1_a_mux", viu_m1_aclk_p, TOP_CLK_MUX6, 4, 3),
467 MUX(0, "viu_w_mux", viu_clk_p, TOP_CLK_MUX6, 8, 3),
468 MUX(0, "viu_jpeg_w_mux", viu_jpeg_clk_p, TOP_CLK_MUX6, 12, 3),
469 MUX(0, "ts_sys_mux", ts_sys_clk_p, TOP_CLK_MUX6, 16, 2),
470};
471
472static struct zx_clk_gate top_gate_clk[] = {
473 GATE(CPU_DBG_GATE, "dbg_wclk", "dbg_mux", TOP_CLK_GATE0, 4, CLK_SET_RATE_PARENT, 0),
474 GATE(A72_GATE, "a72_coreclk", "a72_mux", TOP_CLK_GATE0, 3, CLK_SET_RATE_PARENT, 0),
475 GATE(CPU_PERI_GATE, "cpu_peri", "cpu_peri_mux", TOP_CLK_GATE0, 1, CLK_SET_RATE_PARENT, 0),
476 GATE(A53_GATE, "a53_coreclk", "a53_mux", TOP_CLK_GATE0, 0, CLK_SET_RATE_PARENT, 0),
477 GATE(SD1_WCLK, "sd1_wclk", "sd1_mux", TOP_CLK_GATE1, 13, CLK_SET_RATE_PARENT, 0),
478 GATE(SD0_WCLK, "sd0_wclk", "sd0_mux", TOP_CLK_GATE1, 9, CLK_SET_RATE_PARENT, 0),
479 GATE(EMMC_WCLK, "emmc_wclk", "emmc_mux_div2", TOP_CLK_GATE0, 5, CLK_SET_RATE_PARENT, 0),
480 GATE(EMMC_NAND_AXI, "emmc_nand_aclk", "sys_noc_aclk", TOP_CLK_GATE1, 4, CLK_SET_RATE_PARENT, 0),
481 GATE(NAND_WCLK, "nand_wclk", "nand_mux", TOP_CLK_GATE0, 1, CLK_SET_RATE_PARENT, 0),
482 GATE(EMMC_NAND_AHB, "emmc_nand_hclk", "sys_noc_hclk", TOP_CLK_GATE1, 0, CLK_SET_RATE_PARENT, 0),
483 GATE(0, "lsp1_pclk", "sys_noc_pclk", TOP_CLK_GATE2, 31, 0, 0),
484 GATE(LSP1_148M5, "lsp1_148m5", "clk148m5", TOP_CLK_GATE2, 30, 0, 0),
485 GATE(LSP1_99M, "lsp1_99m", "clk99m", TOP_CLK_GATE2, 29, 0, 0),
486 GATE(LSP1_24M, "lsp1_24m", "osc24m", TOP_CLK_GATE2, 28, 0, 0),
487 GATE(LSP0_74M25, "lsp0_74m25", "clk74m25", TOP_CLK_GATE2, 25, 0, 0),
488 GATE(0, "lsp0_pclk", "sys_noc_pclk", TOP_CLK_GATE2, 24, 0, 0),
489 GATE(LSP0_32K, "lsp0_32k", "osc32k", TOP_CLK_GATE2, 23, 0, 0),
490 GATE(LSP0_148M5, "lsp0_148m5", "clk148m5", TOP_CLK_GATE2, 22, 0, 0),
491 GATE(LSP0_99M, "lsp0_99m", "clk99m", TOP_CLK_GATE2, 21, 0, 0),
492 GATE(LSP0_24M, "lsp0_24m", "osc24m", TOP_CLK_GATE2, 20, 0, 0),
493 GATE(AUDIO_99M, "audio_99m", "clk99m", TOP_CLK_GATE5, 27, 0, 0),
494 GATE(AUDIO_24M, "audio_24m", "osc24m", TOP_CLK_GATE5, 28, 0, 0),
495 GATE(AUDIO_16M384, "audio_16m384", "clk16m384", TOP_CLK_GATE5, 29, 0, 0),
496 GATE(AUDIO_32K, "audio_32k", "clk32k", TOP_CLK_GATE5, 30, 0, 0),
497 GATE(WDT_WCLK, "wdt_wclk", "wdt_mux", TOP_CLK_GATE6, 9, CLK_SET_RATE_PARENT, 0),
498 GATE(TIMER_WCLK, "timer_wclk", "timer_mux", TOP_CLK_GATE6, 5, CLK_SET_RATE_PARENT, 0),
499 GATE(VDE_ACLK, "vde_aclk", "vde_mux", TOP_CLK_GATE3, 0, CLK_SET_RATE_PARENT, 0),
500 GATE(VCE_ACLK, "vce_aclk", "vce_mux", TOP_CLK_GATE3, 4, CLK_SET_RATE_PARENT, 0),
501 GATE(HDE_ACLK, "hde_aclk", "hde_mux", TOP_CLK_GATE3, 8, CLK_SET_RATE_PARENT, 0),
502 GATE(GPU_ACLK, "gpu_aclk", "gpu_mux", TOP_CLK_GATE3, 16, CLK_SET_RATE_PARENT, 0),
503 GATE(SAPPU_ACLK, "sappu_aclk", "sappu_a_mux", TOP_CLK_GATE3, 20, CLK_SET_RATE_PARENT, 0),
504 GATE(SAPPU_WCLK, "sappu_wclk", "sappu_w_mux", TOP_CLK_GATE3, 22, CLK_SET_RATE_PARENT, 0),
505 GATE(VOU_ACLK, "vou_aclk", "vou_a_mux", TOP_CLK_GATE4, 16, CLK_SET_RATE_PARENT, 0),
506 GATE(VOU_MAIN_WCLK, "vou_main_wclk", "vou_main_w_mux", TOP_CLK_GATE4, 18, CLK_SET_RATE_PARENT, 0),
507 GATE(VOU_AUX_WCLK, "vou_aux_wclk", "vou_aux_w_mux", TOP_CLK_GATE4, 19, CLK_SET_RATE_PARENT, 0),
508 GATE(VOU_PPU_WCLK, "vou_ppu_wclk", "vou_ppu_w_mux", TOP_CLK_GATE4, 20, CLK_SET_RATE_PARENT, 0),
509 GATE(MIPI_CFG_CLK, "mipi_cfg_clk", "osc24m", TOP_CLK_GATE4, 21, 0, 0),
510 GATE(VGA_I2C_WCLK, "vga_i2c_wclk", "vga_i2c_mux", TOP_CLK_GATE4, 23, CLK_SET_RATE_PARENT, 0),
511 GATE(MIPI_REF_CLK, "mipi_ref_clk", "clk27m", TOP_CLK_GATE4, 24, 0, 0),
512 GATE(HDMI_OSC_CEC, "hdmi_osc_cec", "clk2m", TOP_CLK_GATE4, 22, 0, 0),
513 GATE(HDMI_OSC_CLK, "hdmi_osc_clk", "clk240m", TOP_CLK_GATE4, 25, 0, 0),
514 GATE(HDMI_XCLK, "hdmi_xclk", "osc24m", TOP_CLK_GATE4, 26, 0, 0),
515 GATE(VIU_M0_ACLK, "viu_m0_aclk", "viu_m0_a_mux", TOP_CLK_GATE4, 0, CLK_SET_RATE_PARENT, 0),
516 GATE(VIU_M1_ACLK, "viu_m1_aclk", "viu_m1_a_mux", TOP_CLK_GATE4, 1, CLK_SET_RATE_PARENT, 0),
517 GATE(VIU_WCLK, "viu_wclk", "viu_w_mux", TOP_CLK_GATE4, 2, CLK_SET_RATE_PARENT, 0),
518 GATE(VIU_JPEG_WCLK, "viu_jpeg_wclk", "viu_jpeg_w_mux", TOP_CLK_GATE4, 3, CLK_SET_RATE_PARENT, 0),
519 GATE(VIU_CFG_CLK, "viu_cfg_clk", "osc24m", TOP_CLK_GATE4, 6, 0, 0),
520 GATE(TS_SYS_WCLK, "ts_sys_wclk", "ts_sys_mux", TOP_CLK_GATE5, 2, CLK_SET_RATE_PARENT, 0),
521 GATE(TS_SYS_108M, "ts_sys_108m", "clk108m", TOP_CLK_GATE5, 3, 0, 0),
522 GATE(USB20_HCLK, "usb20_hclk", "sys_noc_hclk", TOP_CLK_GATE2, 12, 0, 0),
523 GATE(USB20_PHY_CLK, "usb20_phy_clk", "usb_ref24m_mux", TOP_CLK_GATE2, 13, 0, 0),
524 GATE(USB21_HCLK, "usb21_hclk", "sys_noc_hclk", TOP_CLK_GATE2, 14, 0, 0),
525 GATE(USB21_PHY_CLK, "usb21_phy_clk", "usb_ref24m_mux", TOP_CLK_GATE2, 15, 0, 0),
526 GATE(GMAC_RMIICLK, "gmac_rmii_clk", "clk50m", TOP_CLK_GATE2, 3, 0, 0),
527 GATE(GMAC_PCLK, "gmac_pclk", "clk198m", TOP_CLK_GATE2, 1, 0, 0),
528 GATE(GMAC_ACLK, "gmac_aclk", "clk49m5", TOP_CLK_GATE2, 0, 0, 0),
529 GATE(GMAC_RFCLK, "gmac_refclk", "clk25m", TOP_CLK_GATE2, 4, 0, 0),
530 GATE(SD1_AHB, "sd1_hclk", "sys_noc_hclk", TOP_CLK_GATE1, 12, 0, 0),
531 GATE(SD0_AHB, "sd0_hclk", "sys_noc_hclk", TOP_CLK_GATE1, 8, 0, 0),
532 GATE(TEMPSENSOR_GATE, "tempsensor_gate", "clk4m", TOP_CLK_GATE5, 31, 0, 0),
533};
534
535static struct clk_hw_onecell_data top_hw_onecell_data = {
536 .num = TOP_NR_CLKS,
537 .hws = {
538 [TOP_NR_CLKS - 1] = NULL,
539 },
540};
541
542static int __init top_clocks_init(struct device_node *np)
543{
544 void __iomem *reg_base;
545 int i, ret;
546
547 reg_base = of_iomap(np, 0);
548 if (!reg_base) {
549 pr_err("%s: Unable to map clk base\n", __func__);
550 return -ENXIO;
551 }
552
553 for (i = 0; i < ARRAY_SIZE(zx296718_pll_clk); i++) {
554 zx296718_pll_clk[i].reg_base += (u64)reg_base;
555 ret = clk_hw_register(NULL, &zx296718_pll_clk[i].hw);
556 if (ret) {
557 pr_warn("top clk %s init error!\n",
558 zx296718_pll_clk[i].hw.init->name);
559 }
560 }
561
562 for (i = 0; i < ARRAY_SIZE(top_ffactor_clk); i++) {
563 if (top_ffactor_clk[i].id)
564 top_hw_onecell_data.hws[top_ffactor_clk[i].id] =
565 &top_ffactor_clk[i].factor.hw;
566
567 ret = clk_hw_register(NULL, &top_ffactor_clk[i].factor.hw);
568 if (ret) {
569 pr_warn("top clk %s init error!\n",
570 top_ffactor_clk[i].factor.hw.init->name);
571 }
572 }
573
574 for (i = 0; i < ARRAY_SIZE(top_mux_clk); i++) {
575 if (top_mux_clk[i].id)
576 top_hw_onecell_data.hws[top_mux_clk[i].id] =
577 &top_mux_clk[i].mux.hw;
578
579 top_mux_clk[i].mux.reg += (u64)reg_base;
580 ret = clk_hw_register(NULL, &top_mux_clk[i].mux.hw);
581 if (ret) {
582 pr_warn("top clk %s init error!\n",
583 top_mux_clk[i].mux.hw.init->name);
584 }
585 }
586
587 for (i = 0; i < ARRAY_SIZE(top_gate_clk); i++) {
588 if (top_gate_clk[i].id)
589 top_hw_onecell_data.hws[top_gate_clk[i].id] =
590 &top_gate_clk[i].gate.hw;
591
592 top_gate_clk[i].gate.reg += (u64)reg_base;
593 ret = clk_hw_register(NULL, &top_gate_clk[i].gate.hw);
594 if (ret) {
595 pr_warn("top clk %s init error!\n",
596 top_gate_clk[i].gate.hw.init->name);
597 }
598 }
599
600 for (i = 0; i < ARRAY_SIZE(top_div_clk); i++) {
601 if (top_div_clk[i].id)
602 top_hw_onecell_data.hws[top_div_clk[i].id] =
603 &top_div_clk[i].div.hw;
604
605 top_div_clk[i].div.reg += (u64)reg_base;
606 ret = clk_hw_register(NULL, &top_div_clk[i].div.hw);
607 if (ret) {
608 pr_warn("top clk %s init error!\n",
609 top_div_clk[i].div.hw.init->name);
610 }
611 }
612
613 if (of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &top_hw_onecell_data))
614 panic("could not register clk provider\n");
615 pr_info("top clk init over, nr:%d\n", TOP_NR_CLKS);
616
617 return 0;
618}
619
620static struct clk_div_table common_even_div_table[] = {
621 { .val = 0, .div = 1, },
622 { .val = 1, .div = 2, },
623 { .val = 3, .div = 4, },
624 { .val = 5, .div = 6, },
625 { .val = 7, .div = 8, },
626 { .val = 9, .div = 10, },
627 { .val = 11, .div = 12, },
628 { .val = 13, .div = 14, },
629 { .val = 15, .div = 16, },
630};
631
632static struct clk_div_table common_div_table[] = {
633 { .val = 0, .div = 1, },
634 { .val = 1, .div = 2, },
635 { .val = 2, .div = 3, },
636 { .val = 3, .div = 4, },
637 { .val = 4, .div = 5, },
638 { .val = 5, .div = 6, },
639 { .val = 6, .div = 7, },
640 { .val = 7, .div = 8, },
641 { .val = 8, .div = 9, },
642 { .val = 9, .div = 10, },
643 { .val = 10, .div = 11, },
644 { .val = 11, .div = 12, },
645 { .val = 12, .div = 13, },
646 { .val = 13, .div = 14, },
647 { .val = 14, .div = 15, },
648 { .val = 15, .div = 16, },
649};
650
651PNAME(lsp0_wclk_common_p) = {
652 "lsp0_24m",
653 "lsp0_99m",
654};
655
656PNAME(lsp0_wclk_timer3_p) = {
657 "timer3_div",
658 "lsp0_32k"
659};
660
661PNAME(lsp0_wclk_timer4_p) = {
662 "timer4_div",
663 "lsp0_32k"
664};
665
666PNAME(lsp0_wclk_timer5_p) = {
667 "timer5_div",
668 "lsp0_32k"
669};
670
671PNAME(lsp0_wclk_spifc0_p) = {
672 "lsp0_148m5",
673 "lsp0_24m",
674 "lsp0_99m",
675 "lsp0_74m25"
676};
677
678PNAME(lsp0_wclk_ssp_p) = {
679 "lsp0_148m5",
680 "lsp0_99m",
681 "lsp0_24m",
682};
683
684static struct zx_clk_mux lsp0_mux_clk[] = {
685 MUX(0, "timer3_wclk_mux", lsp0_wclk_timer3_p, LSP0_TIMER3_CLK, 4, 1),
686 MUX(0, "timer4_wclk_mux", lsp0_wclk_timer4_p, LSP0_TIMER4_CLK, 4, 1),
687 MUX(0, "timer5_wclk_mux", lsp0_wclk_timer5_p, LSP0_TIMER5_CLK, 4, 1),
688 MUX(0, "uart3_wclk_mux", lsp0_wclk_common_p, LSP0_UART3_CLK, 4, 1),
689 MUX(0, "uart1_wclk_mux", lsp0_wclk_common_p, LSP0_UART1_CLK, 4, 1),
690 MUX(0, "uart2_wclk_mux", lsp0_wclk_common_p, LSP0_UART2_CLK, 4, 1),
691 MUX(0, "spifc0_wclk_mux", lsp0_wclk_spifc0_p, LSP0_SPIFC0_CLK, 4, 2),
692 MUX(0, "i2c4_wclk_mux", lsp0_wclk_common_p, LSP0_I2C4_CLK, 4, 1),
693 MUX(0, "i2c5_wclk_mux", lsp0_wclk_common_p, LSP0_I2C5_CLK, 4, 1),
694 MUX(0, "ssp0_wclk_mux", lsp0_wclk_ssp_p, LSP0_SSP0_CLK, 4, 1),
695 MUX(0, "ssp1_wclk_mux", lsp0_wclk_ssp_p, LSP0_SSP1_CLK, 4, 1),
696 MUX(0, "i2c3_wclk_mux", lsp0_wclk_common_p, LSP0_I2C3_CLK, 4, 1),
697};
698
699static struct zx_clk_gate lsp0_gate_clk[] = {
700 GATE(LSP0_TIMER3_WCLK, "timer3_wclk", "timer3_wclk_mux", LSP0_TIMER3_CLK, 1, CLK_SET_RATE_PARENT, 0),
701 GATE(LSP0_TIMER4_WCLK, "timer4_wclk", "timer4_wclk_mux", LSP0_TIMER4_CLK, 1, CLK_SET_RATE_PARENT, 0),
702 GATE(LSP0_TIMER5_WCLK, "timer5_wclk", "timer5_wclk_mux", LSP0_TIMER5_CLK, 1, CLK_SET_RATE_PARENT, 0),
703 GATE(LSP0_UART3_WCLK, "uart3_wclk", "uart3_wclk_mux", LSP0_UART3_CLK, 1, CLK_SET_RATE_PARENT, 0),
704 GATE(LSP0_UART1_WCLK, "uart1_wclk", "uart1_wclk_mux", LSP0_UART1_CLK, 1, CLK_SET_RATE_PARENT, 0),
705 GATE(LSP0_UART2_WCLK, "uart2_wclk", "uart2_wclk_mux", LSP0_UART2_CLK, 1, CLK_SET_RATE_PARENT, 0),
706 GATE(LSP0_SPIFC0_WCLK, "spifc0_wclk", "spifc0_wclk_mux", LSP0_SPIFC0_CLK, 1, CLK_SET_RATE_PARENT, 0),
707 GATE(LSP0_I2C4_WCLK, "i2c4_wclk", "i2c4_wclk_mux", LSP0_I2C4_CLK, 1, CLK_SET_RATE_PARENT, 0),
708 GATE(LSP0_I2C5_WCLK, "i2c5_wclk", "i2c5_wclk_mux", LSP0_I2C5_CLK, 1, CLK_SET_RATE_PARENT, 0),
709 GATE(LSP0_SSP0_WCLK, "ssp0_wclk", "ssp0_div", LSP0_SSP0_CLK, 1, CLK_SET_RATE_PARENT, 0),
710 GATE(LSP0_SSP1_WCLK, "ssp1_wclk", "ssp1_div", LSP0_SSP1_CLK, 1, CLK_SET_RATE_PARENT, 0),
711 GATE(LSP0_I2C3_WCLK, "i2c3_wclk", "i2c3_wclk_mux", LSP0_I2C3_CLK, 1, CLK_SET_RATE_PARENT, 0),
712};
713
714static struct zx_clk_div lsp0_div_clk[] = {
715 DIV_T(0, "timer3_div", "lsp0_24m", LSP0_TIMER3_CLK, 12, 4, 0, common_even_div_table),
716 DIV_T(0, "timer4_div", "lsp0_24m", LSP0_TIMER4_CLK, 12, 4, 0, common_even_div_table),
717 DIV_T(0, "timer5_div", "lsp0_24m", LSP0_TIMER5_CLK, 12, 4, 0, common_even_div_table),
718 DIV_T(0, "ssp0_div", "ssp0_wclk_mux", LSP0_SSP0_CLK, 12, 4, 0, common_even_div_table),
719 DIV_T(0, "ssp1_div", "ssp1_wclk_mux", LSP0_SSP1_CLK, 12, 4, 0, common_even_div_table),
720};
721
722static struct clk_hw_onecell_data lsp0_hw_onecell_data = {
723 .num = LSP0_NR_CLKS,
724 .hws = {
725 [LSP0_NR_CLKS - 1] = NULL,
726 },
727};
728
729static int __init lsp0_clocks_init(struct device_node *np)
730{
731 void __iomem *reg_base;
732 int i, ret;
733
734 reg_base = of_iomap(np, 0);
735 if (!reg_base) {
736 pr_err("%s: Unable to map clk base\n", __func__);
737 return -ENXIO;
738 }
739
740 for (i = 0; i < ARRAY_SIZE(lsp0_mux_clk); i++) {
741 if (lsp0_mux_clk[i].id)
742 lsp0_hw_onecell_data.hws[lsp0_mux_clk[i].id] =
743 &lsp0_mux_clk[i].mux.hw;
744
745 lsp0_mux_clk[i].mux.reg += (u64)reg_base;
746 ret = clk_hw_register(NULL, &lsp0_mux_clk[i].mux.hw);
747 if (ret) {
748 pr_warn("lsp0 clk %s init error!\n",
749 lsp0_mux_clk[i].mux.hw.init->name);
750 }
751 }
752
753 for (i = 0; i < ARRAY_SIZE(lsp0_gate_clk); i++) {
754 if (lsp0_gate_clk[i].id)
755 lsp0_hw_onecell_data.hws[lsp0_gate_clk[i].id] =
756 &lsp0_gate_clk[i].gate.hw;
757
758 lsp0_gate_clk[i].gate.reg += (u64)reg_base;
759 ret = clk_hw_register(NULL, &lsp0_gate_clk[i].gate.hw);
760 if (ret) {
761 pr_warn("lsp0 clk %s init error!\n",
762 lsp0_gate_clk[i].gate.hw.init->name);
763 }
764 }
765
766 for (i = 0; i < ARRAY_SIZE(lsp0_div_clk); i++) {
767 if (lsp0_div_clk[i].id)
768 lsp0_hw_onecell_data.hws[lsp0_div_clk[i].id] =
769 &lsp0_div_clk[i].div.hw;
770
771 lsp0_div_clk[i].div.reg += (u64)reg_base;
772 ret = clk_hw_register(NULL, &lsp0_div_clk[i].div.hw);
773 if (ret) {
774 pr_warn("lsp0 clk %s init error!\n",
775 lsp0_div_clk[i].div.hw.init->name);
776 }
777 }
778
779 if (of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &lsp0_hw_onecell_data))
780 panic("could not register clk provider\n");
781 pr_info("lsp0-clk init over:%d\n", LSP0_NR_CLKS);
782
783 return 0;
784}
785
786PNAME(lsp1_wclk_common_p) = {
787 "lsp1_24m",
788 "lsp1_99m",
789};
790
791PNAME(lsp1_wclk_ssp_p) = {
792 "lsp1_148m5",
793 "lsp1_99m",
794 "lsp1_24m",
795};
796
797static struct zx_clk_mux lsp1_mux_clk[] = {
798 MUX(0, "uart4_wclk_mux", lsp1_wclk_common_p, LSP1_UART4_CLK, 4, 1),
799 MUX(0, "uart5_wclk_mux", lsp1_wclk_common_p, LSP1_UART5_CLK, 4, 1),
800 MUX(0, "pwm_wclk_mux", lsp1_wclk_common_p, LSP1_PWM_CLK, 4, 1),
801 MUX(0, "i2c2_wclk_mux", lsp1_wclk_common_p, LSP1_I2C2_CLK, 4, 1),
802 MUX(0, "ssp2_wclk_mux", lsp1_wclk_ssp_p, LSP1_SSP2_CLK, 4, 2),
803 MUX(0, "ssp3_wclk_mux", lsp1_wclk_ssp_p, LSP1_SSP3_CLK, 4, 2),
804 MUX(0, "ssp4_wclk_mux", lsp1_wclk_ssp_p, LSP1_SSP4_CLK, 4, 2),
805 MUX(0, "usim1_wclk_mux", lsp1_wclk_common_p, LSP1_USIM1_CLK, 4, 1),
806};
807
808static struct zx_clk_div lsp1_div_clk[] = {
809 DIV_T(0, "pwm_div", "pwm_wclk_mux", LSP1_PWM_CLK, 12, 4, CLK_SET_RATE_PARENT, common_div_table),
810 DIV_T(0, "ssp2_div", "ssp2_wclk_mux", LSP1_SSP2_CLK, 12, 4, CLK_SET_RATE_PARENT, common_even_div_table),
811 DIV_T(0, "ssp3_div", "ssp3_wclk_mux", LSP1_SSP3_CLK, 12, 4, CLK_SET_RATE_PARENT, common_even_div_table),
812 DIV_T(0, "ssp4_div", "ssp4_wclk_mux", LSP1_SSP4_CLK, 12, 4, CLK_SET_RATE_PARENT, common_even_div_table),
813};
814
815static struct zx_clk_gate lsp1_gate_clk[] = {
816 GATE(LSP1_UART4_WCLK, "lsp1_uart4_wclk", "uart4_wclk_mux", LSP1_UART4_CLK, 1, CLK_SET_RATE_PARENT, 0),
817 GATE(LSP1_UART5_WCLK, "lsp1_uart5_wclk", "uart5_wclk_mux", LSP1_UART5_CLK, 1, CLK_SET_RATE_PARENT, 0),
818 GATE(LSP1_PWM_WCLK, "lsp1_pwm_wclk", "pwm_div", LSP1_PWM_CLK, 1, CLK_SET_RATE_PARENT, 0),
819 GATE(LSP1_PWM_PCLK, "lsp1_pwm_pclk", "lsp1_pclk", LSP1_PWM_CLK, 0, 0, 0),
820 GATE(LSP1_I2C2_WCLK, "lsp1_i2c2_wclk", "i2c2_wclk_mux", LSP1_I2C2_CLK, 1, CLK_SET_RATE_PARENT, 0),
821 GATE(LSP1_SSP2_WCLK, "lsp1_ssp2_wclk", "ssp2_div", LSP1_SSP2_CLK, 1, CLK_SET_RATE_PARENT, 0),
822 GATE(LSP1_SSP3_WCLK, "lsp1_ssp3_wclk", "ssp3_div", LSP1_SSP3_CLK, 1, CLK_SET_RATE_PARENT, 0),
823 GATE(LSP1_SSP4_WCLK, "lsp1_ssp4_wclk", "ssp4_div", LSP1_SSP4_CLK, 1, CLK_SET_RATE_PARENT, 0),
824 GATE(LSP1_USIM1_WCLK, "lsp1_usim1_wclk", "usim1_wclk_mux", LSP1_USIM1_CLK, 1, CLK_SET_RATE_PARENT, 0),
825};
826
827static struct clk_hw_onecell_data lsp1_hw_onecell_data = {
828 .num = LSP1_NR_CLKS,
829 .hws = {
830 [LSP1_NR_CLKS - 1] = NULL,
831 },
832};
833
834static int __init lsp1_clocks_init(struct device_node *np)
835{
836 void __iomem *reg_base;
837 int i, ret;
838
839 reg_base = of_iomap(np, 0);
840 if (!reg_base) {
841 pr_err("%s: Unable to map clk base\n", __func__);
842 return -ENXIO;
843 }
844
845 for (i = 0; i < ARRAY_SIZE(lsp1_mux_clk); i++) {
846 if (lsp1_mux_clk[i].id)
847 lsp1_hw_onecell_data.hws[lsp1_mux_clk[i].id] =
848 &lsp0_mux_clk[i].mux.hw;
849
850 lsp1_mux_clk[i].mux.reg += (u64)reg_base;
851 ret = clk_hw_register(NULL, &lsp1_mux_clk[i].mux.hw);
852 if (ret) {
853 pr_warn("lsp1 clk %s init error!\n",
854 lsp1_mux_clk[i].mux.hw.init->name);
855 }
856 }
857
858 for (i = 0; i < ARRAY_SIZE(lsp1_gate_clk); i++) {
859 if (lsp1_gate_clk[i].id)
860 lsp1_hw_onecell_data.hws[lsp1_gate_clk[i].id] =
861 &lsp1_gate_clk[i].gate.hw;
862
863 lsp1_gate_clk[i].gate.reg += (u64)reg_base;
864 ret = clk_hw_register(NULL, &lsp1_gate_clk[i].gate.hw);
865 if (ret) {
866 pr_warn("lsp1 clk %s init error!\n",
867 lsp1_gate_clk[i].gate.hw.init->name);
868 }
869 }
870
871 for (i = 0; i < ARRAY_SIZE(lsp1_div_clk); i++) {
872 if (lsp1_div_clk[i].id)
873 lsp1_hw_onecell_data.hws[lsp1_div_clk[i].id] =
874 &lsp1_div_clk[i].div.hw;
875
876 lsp1_div_clk[i].div.reg += (u64)reg_base;
877 ret = clk_hw_register(NULL, &lsp1_div_clk[i].div.hw);
878 if (ret) {
879 pr_warn("lsp1 clk %s init error!\n",
880 lsp1_div_clk[i].div.hw.init->name);
881 }
882 }
883
884 if (of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &lsp1_hw_onecell_data))
885 panic("could not register clk provider\n");
886 pr_info("lsp1-clk init over, nr:%d\n", LSP1_NR_CLKS);
887
888 return 0;
889}
890
891static const struct of_device_id zx_clkc_match_table[] = {
892 { .compatible = "zte,zx296718-topcrm", .data = &top_clocks_init },
893 { .compatible = "zte,zx296718-lsp0crm", .data = &lsp0_clocks_init },
894 { .compatible = "zte,zx296718-lsp1crm", .data = &lsp1_clocks_init },
895 { }
896};
897
898static int zx_clkc_probe(struct platform_device *pdev)
899{
900 int (*init_fn)(struct device_node *np);
901 struct device_node *np = pdev->dev.of_node;
902
903 init_fn = of_device_get_match_data(&pdev->dev);
904 if (!init_fn) {
905 dev_err(&pdev->dev, "Error: No device match found\n");
906 return -ENODEV;
907 }
908
909 return init_fn(np);
910}
911
912static struct platform_driver zx_clk_driver = {
913 .probe = zx_clkc_probe,
914 .driver = {
915 .name = "zx296718-clkc",
916 .of_match_table = zx_clkc_match_table,
917 },
918};
919
920static int __init zx_clkc_init(void)
921{
922 return platform_driver_register(&zx_clk_driver);
923}
924device_initcall(zx_clkc_init);
diff --git a/drivers/clk/zte/clk.h b/drivers/clk/zte/clk.h
index 8f6b5f05bb7f..0df3474b2cf3 100644
--- a/drivers/clk/zte/clk.h
+++ b/drivers/clk/zte/clk.h
@@ -12,6 +12,26 @@
12#include <linux/clk-provider.h> 12#include <linux/clk-provider.h>
13#include <linux/spinlock.h> 13#include <linux/spinlock.h>
14 14
15#define PNAME(x) static const char *x[]
16
17#define CLK_HW_INIT(_name, _parent, _ops, _flags) \
18 &(struct clk_init_data) { \
19 .flags = _flags, \
20 .name = _name, \
21 .parent_names = (const char *[]) { _parent }, \
22 .num_parents = 1, \
23 .ops = _ops, \
24 }
25
26#define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
27 &(struct clk_init_data) { \
28 .flags = _flags, \
29 .name = _name, \
30 .parent_names = _parents, \
31 .num_parents = ARRAY_SIZE(_parents), \
32 .ops = _ops, \
33 }
34
15struct zx_pll_config { 35struct zx_pll_config {
16 unsigned long rate; 36 unsigned long rate;
17 u32 cfg0; 37 u32 cfg0;
@@ -28,6 +48,111 @@ struct clk_zx_pll {
28 u8 lock_bit; /* pll lock flag bit */ 48 u8 lock_bit; /* pll lock flag bit */
29}; 49};
30 50
51#define PLL_RATE(_rate, _cfg0, _cfg1) \
52{ \
53 .rate = _rate, \
54 .cfg0 = _cfg0, \
55 .cfg1 = _cfg1, \
56}
57
58#define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock) \
59{ \
60 .reg_base = (void __iomem *) _reg, \
61 .lookup_table = _table, \
62 .count = ARRAY_SIZE(_table), \
63 .pd_bit = _pd, \
64 .lock_bit = _lock, \
65 .hw.init = CLK_HW_INIT(_name, _parent, &zx_pll_ops, \
66 CLK_GET_RATE_NOCACHE), \
67}
68
69#define ZX296718_PLL(_name, _parent, _reg, _table) \
70ZX_PLL(_name, _parent, _reg, _table, 0, 30)
71
72struct zx_clk_gate {
73 struct clk_gate gate;
74 u16 id;
75};
76
77#define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \
78{ \
79 .gate = { \
80 .reg = (void __iomem *) _reg, \
81 .bit_idx = (_bit), \
82 .flags = _gflags, \
83 .lock = &clk_lock, \
84 .hw.init = CLK_HW_INIT(_name, \
85 _parent, \
86 &clk_gate_ops, \
87 _flag | CLK_IGNORE_UNUSED), \
88 }, \
89 .id = _id, \
90}
91
92struct zx_clk_fixed_factor {
93 struct clk_fixed_factor factor;
94 u16 id;
95};
96
97#define FFACTOR(_id, _name, _parent, _mult, _div, _flag) \
98{ \
99 .factor = { \
100 .div = _div, \
101 .mult = _mult, \
102 .hw.init = CLK_HW_INIT(_name, \
103 _parent, \
104 &clk_fixed_factor_ops, \
105 _flag), \
106 }, \
107 .id = _id, \
108}
109
110struct zx_clk_mux {
111 struct clk_mux mux;
112 u16 id;
113};
114
115#define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag) \
116{ \
117 .mux = { \
118 .reg = (void __iomem *) _reg, \
119 .mask = BIT(_width) - 1, \
120 .shift = _shift, \
121 .flags = _mflag, \
122 .lock = &clk_lock, \
123 .hw.init = CLK_HW_INIT_PARENTS(_name, \
124 _parent, \
125 &clk_mux_ops, \
126 _flag), \
127 }, \
128 .id = _id, \
129}
130
131#define MUX(_id, _name, _parent, _reg, _shift, _width) \
132MUX_F(_id, _name, _parent, _reg, _shift, _width, 0, 0)
133
134struct zx_clk_div {
135 struct clk_divider div;
136 u16 id;
137};
138
139#define DIV_T(_id, _name, _parent, _reg, _shift, _width, _flag, _table) \
140{ \
141 .div = { \
142 .reg = (void __iomem *) _reg, \
143 .shift = _shift, \
144 .width = _width, \
145 .flags = 0, \
146 .table = _table, \
147 .lock = &clk_lock, \
148 .hw.init = CLK_HW_INIT(_name, \
149 _parent, \
150 &clk_divider_ops, \
151 _flag), \
152 }, \
153 .id = _id, \
154}
155
31struct clk *clk_register_zx_pll(const char *name, const char *parent_name, 156struct clk *clk_register_zx_pll(const char *name, const char *parent_name,
32 unsigned long flags, void __iomem *reg_base, 157 unsigned long flags, void __iomem *reg_base,
33 const struct zx_pll_config *lookup_table, int count, spinlock_t *lock); 158 const struct zx_pll_config *lookup_table, int count, spinlock_t *lock);
diff --git a/include/dt-bindings/clock/zx296718-clock.h b/include/dt-bindings/clock/zx296718-clock.h
new file mode 100644
index 000000000000..822d52385080
--- /dev/null
+++ b/include/dt-bindings/clock/zx296718-clock.h
@@ -0,0 +1,163 @@
1/*
2 * Copyright (C) 2015 - 2016 ZTE Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8#ifndef __DT_BINDINGS_CLOCK_ZX296718_H
9#define __DT_BINDINGS_CLOCK_ZX296718_H
10
11/* PLL */
12#define ZX296718_PLL_CPU 1
13#define ZX296718_PLL_MAC 2
14#define ZX296718_PLL_MM0 3
15#define ZX296718_PLL_MM1 4
16#define ZX296718_PLL_VGA 5
17#define ZX296718_PLL_DDR 6
18#define ZX296718_PLL_AUDIO 7
19#define ZX296718_PLL_HSIC 8
20#define CPU_DBG_GATE 9
21#define A72_GATE 10
22#define CPU_PERI_GATE 11
23#define A53_GATE 12
24#define DDR1_GATE 13
25#define DDR0_GATE 14
26#define SD1_WCLK 15
27#define SD1_AHB 16
28#define SD0_WCLK 17
29#define SD0_AHB 18
30#define EMMC_WCLK 19
31#define EMMC_NAND_AXI 20
32#define NAND_WCLK 21
33#define EMMC_NAND_AHB 22
34#define LSP1_148M5 23
35#define LSP1_99M 24
36#define LSP1_24M 25
37#define LSP0_74M25 26
38#define LSP0_32K 27
39#define LSP0_148M5 28
40#define LSP0_99M 29
41#define LSP0_24M 30
42#define DEMUX_AXI 31
43#define DEMUX_APB 32
44#define DEMUX_148M5 33
45#define DEMUX_108M 34
46#define AUDIO_APB 35
47#define AUDIO_99M 36
48#define AUDIO_24M 37
49#define AUDIO_16M384 38
50#define AUDIO_32K 39
51#define WDT_WCLK 40
52#define TIMER_WCLK 41
53#define VDE_ACLK 42
54#define VCE_ACLK 43
55#define HDE_ACLK 44
56#define GPU_ACLK 45
57#define SAPPU_ACLK 46
58#define SAPPU_WCLK 47
59#define VOU_ACLK 48
60#define VOU_MAIN_WCLK 49
61#define VOU_AUX_WCLK 50
62#define VOU_PPU_WCLK 51
63#define MIPI_CFG_CLK 52
64#define VGA_I2C_WCLK 53
65#define MIPI_REF_CLK 54
66#define HDMI_OSC_CEC 55
67#define HDMI_OSC_CLK 56
68#define HDMI_XCLK 57
69#define VIU_M0_ACLK 58
70#define VIU_M1_ACLK 59
71#define VIU_WCLK 60
72#define VIU_JPEG_WCLK 61
73#define VIU_CFG_CLK 62
74#define TS_SYS_WCLK 63
75#define TS_SYS_108M 64
76#define USB20_HCLK 65
77#define USB20_PHY_CLK 66
78#define USB21_HCLK 67
79#define USB21_PHY_CLK 68
80#define GMAC_RMIICLK 69
81#define GMAC_PCLK 70
82#define GMAC_ACLK 71
83#define GMAC_RFCLK 72
84#define TEMPSENSOR_GATE 73
85
86#define TOP_NR_CLKS 74
87
88
89#define LSP0_TIMER3_PCLK 1
90#define LSP0_TIMER3_WCLK 2
91#define LSP0_TIMER4_PCLK 3
92#define LSP0_TIMER4_WCLK 4
93#define LSP0_TIMER5_PCLK 5
94#define LSP0_TIMER5_WCLK 6
95#define LSP0_UART3_PCLK 7
96#define LSP0_UART3_WCLK 8
97#define LSP0_UART1_PCLK 9
98#define LSP0_UART1_WCLK 10
99#define LSP0_UART2_PCLK 11
100#define LSP0_UART2_WCLK 12
101#define LSP0_SPIFC0_PCLK 13
102#define LSP0_SPIFC0_WCLK 14
103#define LSP0_I2C4_PCLK 15
104#define LSP0_I2C4_WCLK 16
105#define LSP0_I2C5_PCLK 17
106#define LSP0_I2C5_WCLK 18
107#define LSP0_SSP0_PCLK 19
108#define LSP0_SSP0_WCLK 20
109#define LSP0_SSP1_PCLK 21
110#define LSP0_SSP1_WCLK 22
111#define LSP0_USIM_PCLK 23
112#define LSP0_USIM_WCLK 24
113#define LSP0_GPIO_PCLK 25
114#define LSP0_GPIO_WCLK 26
115#define LSP0_I2C3_PCLK 27
116#define LSP0_I2C3_WCLK 28
117
118#define LSP0_NR_CLKS 29
119
120
121#define LSP1_UART4_PCLK 1
122#define LSP1_UART4_WCLK 2
123#define LSP1_UART5_PCLK 3
124#define LSP1_UART5_WCLK 4
125#define LSP1_PWM_PCLK 5
126#define LSP1_PWM_WCLK 6
127#define LSP1_I2C2_PCLK 7
128#define LSP1_I2C2_WCLK 8
129#define LSP1_SSP2_PCLK 9
130#define LSP1_SSP2_WCLK 10
131#define LSP1_SSP3_PCLK 11
132#define LSP1_SSP3_WCLK 12
133#define LSP1_SSP4_PCLK 13
134#define LSP1_SSP4_WCLK 14
135#define LSP1_USIM1_PCLK 15
136#define LSP1_USIM1_WCLK 16
137
138#define LSP1_NR_CLKS 17
139
140
141#define AUDIO_I2S0_WCLK 1
142#define AUDIO_I2S0_PCLK 2
143#define AUDIO_I2S1_WCLK 3
144#define AUDIO_I2S1_PCLK 4
145#define AUDIO_I2S2_WCLK 5
146#define AUDIO_I2S2_PCLK 6
147#define AUDIO_I2S3_WCLK 7
148#define AUDIO_I2S3_PCLK 8
149#define AUDIO_I2C0_WCLK 9
150#define AUDIO_I2C0_PCLK 10
151#define AUDIO_SPDIF0_WCLK 11
152#define AUDIO_SPDIF0_PCLK 12
153#define AUDIO_SPDIF1_WCLK 13
154#define AUDIO_SPDIF1_PCLK 14
155#define AUDIO_TIMER_WCLK 15
156#define AUDIO_TIMER_PCLK 16
157#define AUDIO_TDM_WCLK 17
158#define AUDIO_TDM_PCLK 18
159#define AUDIO_TS_PCLK 19
160
161#define AUDIO_NR_CLKS 20
162
163#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-11 09:43:38 -0400