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authorEric Huang <JinHuiEric.Huang@amd.com>2016-05-19 15:41:25 -0400
committerAlex Deucher <alexander.deucher@amd.com>2016-07-07 14:50:47 -0400
commitc85e299ff9a14fe43160fd8caada383d622354a1 (patch)
treeaba2cfe011ef41f5bd039191c4bf0c32997e55e0
parent9bf51b07196a8a53a71bea3c60ad0b5c01a446e6 (diff)
drm/amdgpu: add the new common pm code to select the clock levels
This extends dpm clock level selection to the non-powerplay code paths. This interface can be used to select individual clock levels. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c50
2 files changed, 34 insertions, 18 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 611d33d855ff..5252580621bc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1560,6 +1560,8 @@ struct amdgpu_dpm_funcs {
1560 u32 (*get_fan_control_mode)(struct amdgpu_device *adev); 1560 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1561 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); 1561 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1562 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); 1562 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1563 int (*force_clock_level)(struct amdgpu_device *adev, enum pp_clock_type type, uint32_t mask);
1564 int (*print_clock_levels)(struct amdgpu_device *adev, enum pp_clock_type type, char *buf);
1563}; 1565};
1564 1566
1565struct amdgpu_dpm { 1567struct amdgpu_dpm {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 191c28ff0d93..5ad2e7926328 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -347,6 +347,8 @@ static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
347 347
348 if (adev->pp_enabled) 348 if (adev->pp_enabled)
349 size = amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf); 349 size = amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
350 else if (adev->pm.funcs->print_clock_levels)
351 size = adev->pm.funcs->print_clock_levels(adev, PP_SCLK, buf);
350 352
351 return size; 353 return size;
352} 354}
@@ -377,6 +379,8 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
377 379
378 if (adev->pp_enabled) 380 if (adev->pp_enabled)
379 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask); 381 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
382 else if (adev->pm.funcs->force_clock_level)
383 adev->pm.funcs->force_clock_level(adev, PP_SCLK, mask);
380fail: 384fail:
381 return count; 385 return count;
382} 386}
@@ -391,6 +395,8 @@ static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
391 395
392 if (adev->pp_enabled) 396 if (adev->pp_enabled)
393 size = amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf); 397 size = amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
398 else if (adev->pm.funcs->print_clock_levels)
399 size = adev->pm.funcs->print_clock_levels(adev, PP_MCLK, buf);
394 400
395 return size; 401 return size;
396} 402}
@@ -421,6 +427,8 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
421 427
422 if (adev->pp_enabled) 428 if (adev->pp_enabled)
423 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask); 429 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
430 else if (adev->pm.funcs->force_clock_level)
431 adev->pm.funcs->force_clock_level(adev, PP_MCLK, mask);
424fail: 432fail:
425 return count; 433 return count;
426} 434}
@@ -435,6 +443,8 @@ static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
435 443
436 if (adev->pp_enabled) 444 if (adev->pp_enabled)
437 size = amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf); 445 size = amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
446 else if (adev->pm.funcs->print_clock_levels)
447 size = adev->pm.funcs->print_clock_levels(adev, PP_PCIE, buf);
438 448
439 return size; 449 return size;
440} 450}
@@ -465,6 +475,8 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
465 475
466 if (adev->pp_enabled) 476 if (adev->pp_enabled)
467 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask); 477 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
478 else if (adev->pm.funcs->force_clock_level)
479 adev->pm.funcs->force_clock_level(adev, PP_PCIE, mask);
468fail: 480fail:
469 return count; 481 return count;
470} 482}
@@ -1151,27 +1163,29 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
1151 DRM_ERROR("failed to create device file pp_table\n"); 1163 DRM_ERROR("failed to create device file pp_table\n");
1152 return ret; 1164 return ret;
1153 } 1165 }
1154 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
1155 if (ret) {
1156 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1157 return ret;
1158 }
1159 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
1160 if (ret) {
1161 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1162 return ret;
1163 }
1164 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
1165 if (ret) {
1166 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1167 return ret;
1168 }
1169 ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od); 1166 ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
1170 if (ret) { 1167 if (ret) {
1171 DRM_ERROR("failed to create device file pp_sclk_od\n"); 1168 DRM_ERROR("failed to create device file pp_sclk_od\n");
1172 return ret; 1169 return ret;
1173 } 1170 }
1174 } 1171 }
1172
1173 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
1174 if (ret) {
1175 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1176 return ret;
1177 }
1178 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
1179 if (ret) {
1180 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1181 return ret;
1182 }
1183 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
1184 if (ret) {
1185 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1186 return ret;
1187 }
1188
1175 ret = amdgpu_debugfs_pm_init(adev); 1189 ret = amdgpu_debugfs_pm_init(adev);
1176 if (ret) { 1190 if (ret) {
1177 DRM_ERROR("Failed to register debugfs file for dpm!\n"); 1191 DRM_ERROR("Failed to register debugfs file for dpm!\n");
@@ -1194,11 +1208,11 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
1194 device_remove_file(adev->dev, &dev_attr_pp_cur_state); 1208 device_remove_file(adev->dev, &dev_attr_pp_cur_state);
1195 device_remove_file(adev->dev, &dev_attr_pp_force_state); 1209 device_remove_file(adev->dev, &dev_attr_pp_force_state);
1196 device_remove_file(adev->dev, &dev_attr_pp_table); 1210 device_remove_file(adev->dev, &dev_attr_pp_table);
1197 device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
1198 device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
1199 device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
1200 device_remove_file(adev->dev, &dev_attr_pp_sclk_od); 1211 device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
1201 } 1212 }
1213 device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
1214 device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
1215 device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
1202} 1216}
1203 1217
1204void amdgpu_pm_compute_clocks(struct amdgpu_device *adev) 1218void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)