spi: meson: Add support for Amlogic Meson SPIFC

This is a driver for the Amlogic Meson SPIFC (SPI flash controller),
which is one of the two SPI controllers available on the SoC. It
doesn't support DMA and has a 64-byte unified transmit/receive buffer.

The device is optimized for interfacing with SPI NOR memories and
allows the execution of standard operations such as read, page
program, sector erase, etc. in a simplified way, toggling a bit in a
dedicated register. The driver doesn't use those predefined commands
and relies only on custom transfers.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

3 files changed, 470 insertions, 0 deletions

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 84e7c9e6ccef..70f20b99e5ff 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -301,6 +301,13 @@ config SPI_FSL_ESPI
           From MPC8536, 85xx platform uses the controller, and all P10xx,
           P20xx, P30xx,P40xx, P50xx uses this controller.
 
+config SPI_MESON_SPIFC
+        tristate "Amlogic Meson SPIFC controller"
+        depends on ARCH_MESON || COMPILE_TEST
+        help
+          This enables master mode support for the SPIFC (SPI flash
+          controller) available in Amlogic Meson SoCs.
+
 config SPI_OC_TINY
         tristate "OpenCores tiny SPI"
         depends on GPIOLIB
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 78f24ca36fcf..9b8a7472b5b8 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_SPI_FSL_SPI)		+= spi-fsl-spi.o
 obj-$(CONFIG_SPI_GPIO)                  += spi-gpio.o
 obj-$(CONFIG_SPI_IMX)                   += spi-imx.o
 obj-$(CONFIG_SPI_LM70_LLP)              += spi-lm70llp.o
+obj-$(CONFIG_SPI_MESON_SPIFC)           += spi-meson-spifc.o
 obj-$(CONFIG_SPI_MPC512x_PSC)           += spi-mpc512x-psc.o
 obj-$(CONFIG_SPI_MPC52xx_PSC)           += spi-mpc52xx-psc.o
 obj-$(CONFIG_SPI_MPC52xx)               += spi-mpc52xx.o
diff --git a/drivers/spi/spi-meson-spifc.c b/drivers/spi/spi-meson-spifc.c
new file mode 100644
index 000000000000..f536476710ad
--- /dev/null
+++ b/drivers/spi/spi-meson-spifc.c
@@ -0,0 +1,462 @@
+/*
+ * Driver for Amlogic Meson SPI flash controller (SPIFC)
+ *
+ * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/spi/spi.h>
+#include <linux/types.h>
+
+/* register map */
+#define REG_CMD                 0x00
+#define REG_ADDR                0x04
+#define REG_CTRL                0x08
+#define REG_CTRL1               0x0c
+#define REG_STATUS              0x10
+#define REG_CTRL2               0x14
+#define REG_CLOCK               0x18
+#define REG_USER                0x1c
+#define REG_USER1               0x20
+#define REG_USER2               0x24
+#define REG_USER3               0x28
+#define REG_USER4               0x2c
+#define REG_SLAVE               0x30
+#define REG_SLAVE1              0x34
+#define REG_SLAVE2              0x38
+#define REG_SLAVE3              0x3c
+#define REG_C0                  0x40
+#define REG_B8                  0x60
+#define REG_MAX                 0x7c
+
+/* register fields */
+#define CMD_USER                BIT(18)
+#define CTRL_ENABLE_AHB         BIT(17)
+#define CLOCK_SOURCE            BIT(31)
+#define CLOCK_DIV_SHIFT         12
+#define CLOCK_DIV_MASK          (0x3f << CLOCK_DIV_SHIFT)
+#define CLOCK_CNT_HIGH_SHIFT    6
+#define CLOCK_CNT_HIGH_MASK     (0x3f << CLOCK_CNT_HIGH_SHIFT)
+#define CLOCK_CNT_LOW_SHIFT     0
+#define CLOCK_CNT_LOW_MASK      (0x3f << CLOCK_CNT_LOW_SHIFT)
+#define USER_DIN_EN_MS          BIT(0)
+#define USER_CMP_MODE           BIT(2)
+#define USER_UC_DOUT_SEL        BIT(27)
+#define USER_UC_DIN_SEL         BIT(28)
+#define USER_UC_MASK            ((BIT(5) - 1) << 27)
+#define USER1_BN_UC_DOUT_SHIFT  17
+#define USER1_BN_UC_DOUT_MASK   (0xff << 16)
+#define USER1_BN_UC_DIN_SHIFT   8
+#define USER1_BN_UC_DIN_MASK    (0xff << 8)
+#define USER4_CS_ACT            BIT(30)
+#define SLAVE_TRST_DONE         BIT(4)
+#define SLAVE_OP_MODE           BIT(30)
+#define SLAVE_SW_RST            BIT(31)
+
+#define SPIFC_BUFFER_SIZE       64
+
+/**
+ * struct meson_spifc
+ * @master:     the SPI master
+ * @regmap:     regmap for device registers
+ * @clk:        input clock of the built-in baud rate generator
+ * @device:     the device structure
+ */
+struct meson_spifc {
+        struct spi_master *master;
+        struct regmap *regmap;
+        struct clk *clk;
+        struct device *dev;
+};
+
+static struct regmap_config spifc_regmap_config = {
+        .reg_bits = 32,
+        .val_bits = 32,
+        .reg_stride = 4,
+        .max_register = REG_MAX,
+};
+
+/**
+ * meson_spifc_wait_ready() - wait for the current operation to terminate
+ * @spifc:      the Meson SPI device
+ * Return:      0 on success, a negative value on error
+ */
+static int meson_spifc_wait_ready(struct meson_spifc *spifc)
+{
+        unsigned long deadline = jiffies + msecs_to_jiffies(5);
+        u32 data;
+
+        do {
+                regmap_read(spifc->regmap, REG_SLAVE, &data);
+                if (data & SLAVE_TRST_DONE)
+                        return 0;
+                cond_resched();
+        } while (!time_after(jiffies, deadline));
+
+        return -ETIMEDOUT;
+}
+
+/**
+ * meson_spifc_drain_buffer() - copy data from device buffer to memory
+ * @spifc:      the Meson SPI device
+ * @buf:        the destination buffer
+ * @len:        number of bytes to copy
+ */
+static void meson_spifc_drain_buffer(struct meson_spifc *spifc, u8 *buf,
+                                     int len)
+{
+        u32 data;
+        int i = 0;
+
+        while (i < len) {
+                regmap_read(spifc->regmap, REG_C0 + i, &data);
+
+                if (len - i >= 4) {
+                        *((u32 *)buf) = data;
+                        buf += 4;
+                } else {
+                        memcpy(buf, &data, len - i);
+                        break;
+                }
+                i += 4;
+        }
+}
+
+/**
+ * meson_spifc_fill_buffer() - copy data from memory to device buffer
+ * @spifc:      the Meson SPI device
+ * @buf:        the source buffer
+ * @len:        number of bytes to copy
+ */
+static void meson_spifc_fill_buffer(struct meson_spifc *spifc, const u8 *buf,
+                                    int len)
+{
+        u32 data;
+        int i = 0;
+
+        while (i < len) {
+                if (len - i >= 4)
+                        data = *(u32 *)buf;
+                else
+                        memcpy(&data, buf, len - i);
+
+                regmap_write(spifc->regmap, REG_C0 + i, data);
+
+                buf += 4;
+                i += 4;
+        }
+}
+
+/**
+ * meson_spifc_setup_speed() - program the clock divider
+ * @spifc:      the Meson SPI device
+ * @speed:      desired speed in Hz
+ */
+void meson_spifc_setup_speed(struct meson_spifc *spifc, u32 speed)
+{
+        unsigned long parent, value;
+        int n;
+
+        parent = clk_get_rate(spifc->clk);
+        n = max_t(int, parent / speed - 1, 1);
+