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authorAnton Blanchard <anton@samba.org>2015-02-09 17:51:22 -0500
committerMichael Ellerman <mpe@ellerman.id.au>2015-03-16 03:32:11 -0400
commitc2ce6f9f3dc00daca5714ef070a9a2d4e78eb336 (patch)
treec008f72ced83ffd950f0920566c378b4809780cf
parent06e5801b8cb3fc057d88cb4dc03c0b64b2744cda (diff)
powerpc: Change vrX register defines to vX to match gcc and glibc
As our various loops (copy, string, crypto etc) get more complicated, we want to share implementations between userspace (eg glibc) and the kernel. We also want to write userspace test harnesses to put in tools/testing/selftest. One gratuitous difference between userspace and the kernel is the VMX register definitions - the kernel uses vrX whereas both gcc and glibc use vX. Change the kernel to match userspace. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat
-rw-r--r--arch/powerpc/include/asm/ppc_asm.h64
-rw-r--r--arch/powerpc/include/uapi/asm/ptrace.h2
-rw-r--r--arch/powerpc/kernel/tm.S8
-rw-r--r--arch/powerpc/kernel/vector.S24
-rw-r--r--arch/powerpc/lib/copypage_power7.S32
-rw-r--r--arch/powerpc/lib/copyuser_power7.S226
-rw-r--r--arch/powerpc/lib/crtsavres.S96
-rw-r--r--arch/powerpc/lib/ldstfp.S26
-rw-r--r--arch/powerpc/lib/memcpy_power7.S226
-rw-r--r--tools/testing/selftests/powerpc/copyloops/asm/ppc_asm.h33
10 files changed, 352 insertions, 385 deletions
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
index 7e4612528546..c7461032b469 100644
--- a/arch/powerpc/include/asm/ppc_asm.h
+++ b/arch/powerpc/include/asm/ppc_asm.h
@@ -637,38 +637,38 @@ END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,945)
637 637
638/* AltiVec Registers (VPRs) */ 638/* AltiVec Registers (VPRs) */
639 639
640#define vr0 0 640#define v0 0
641#define vr1 1 641#define v1 1
642#define vr2 2 642#define v2 2
643#define vr3 3 643#define v3 3
644#define vr4 4 644#define v4 4
645#define vr5 5 645#define v5 5
646#define vr6 6 646#define v6 6
647#define vr7 7 647#define v7 7
648#define vr8 8 648#define v8 8
649#define vr9 9 649#define v9 9
650#define vr10 10 650#define v10 10
651#define vr11 11 651#define v11 11
652#define vr12 12 652#define v12 12
653#define vr13 13 653#define v13 13
654#define vr14 14 654#define v14 14
655#define vr15 15 655#define v15 15
656#define vr16 16 656#define v16 16
657#define vr17 17 657#define v17 17
658#define vr18 18 658#define v18 18
659#define vr19 19 659#define v19 19
660#define vr20 20 660#define v20 20
661#define vr21 21 661#define v21 21
662#define vr22 22 662#define v22 22
663#define vr23 23 663#define v23 23
664#define vr24 24 664#define v24 24
665#define vr25 25 665#define v25 25
666#define vr26 26 666#define v26 26
667#define vr27 27 667#define v27 27
668#define vr28 28 668#define v28 28
669#define vr29 29 669#define v29 29
670#define vr30 30 670#define v30 30
671#define vr31 31 671#define v31 31
672 672
673/* VSX Registers (VSRs) */ 673/* VSX Registers (VSRs) */
674 674
diff --git a/arch/powerpc/include/uapi/asm/ptrace.h b/arch/powerpc/include/uapi/asm/ptrace.h
index 77d2ed35b111..8036b385417d 100644
--- a/arch/powerpc/include/uapi/asm/ptrace.h
+++ b/arch/powerpc/include/uapi/asm/ptrace.h
@@ -136,7 +136,7 @@ struct pt_regs {
136#endif /* __powerpc64__ */ 136#endif /* __powerpc64__ */
137 137
138/* 138/*
139 * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go. 139 * Get/set all the altivec registers v0..v31, vscr, vrsave, in one go.
140 * The transfer totals 34 quadword. Quadwords 0-31 contain the 140 * The transfer totals 34 quadword. Quadwords 0-31 contain the
141 * corresponding vector registers. Quadword 32 contains the vscr as the 141 * corresponding vector registers. Quadword 32 contains the vscr as the
142 * last word (offset 12) within that quadword. Quadword 33 contains the 142 * last word (offset 12) within that quadword. Quadword 33 contains the
diff --git a/arch/powerpc/kernel/tm.S b/arch/powerpc/kernel/tm.S
index 2a324f4cb1b9..5754b226da7e 100644
--- a/arch/powerpc/kernel/tm.S
+++ b/arch/powerpc/kernel/tm.S
@@ -152,9 +152,9 @@ _GLOBAL(tm_reclaim)
152 152
153 addi r7, r3, THREAD_TRANSACT_VRSTATE 153 addi r7, r3, THREAD_TRANSACT_VRSTATE
154 SAVE_32VRS(0, r6, r7) /* r6 scratch, r7 transact vr state */ 154 SAVE_32VRS(0, r6, r7) /* r6 scratch, r7 transact vr state */
155 mfvscr vr0 155 mfvscr v0
156 li r6, VRSTATE_VSCR 156 li r6, VRSTATE_VSCR
157 stvx vr0, r7, r6 157 stvx v0, r7, r6
158dont_backup_vec: 158dont_backup_vec:
159 mfspr r0, SPRN_VRSAVE 159 mfspr r0, SPRN_VRSAVE
160 std r0, THREAD_TRANSACT_VRSAVE(r3) 160 std r0, THREAD_TRANSACT_VRSAVE(r3)
@@ -359,8 +359,8 @@ _GLOBAL(__tm_recheckpoint)
359 359
360 addi r8, r3, THREAD_VRSTATE 360 addi r8, r3, THREAD_VRSTATE
361 li r5, VRSTATE_VSCR 361 li r5, VRSTATE_VSCR
362 lvx vr0, r8, r5 362 lvx v0, r8, r5
363 mtvscr vr0 363 mtvscr v0
364 REST_32VRS(0, r5, r8) /* r5 scratch, r8 ptr */ 364 REST_32VRS(0, r5, r8) /* r5 scratch, r8 ptr */
365dont_restore_vec: 365dont_restore_vec:
366 ld r5, THREAD_VRSAVE(r3) 366 ld r5, THREAD_VRSAVE(r3)
diff --git a/arch/powerpc/kernel/vector.S b/arch/powerpc/kernel/vector.S
index 74f8050518d6..f5c80d567d8d 100644
--- a/arch/powerpc/kernel/vector.S
+++ b/arch/powerpc/kernel/vector.S
@@ -24,8 +24,8 @@ _GLOBAL(do_load_up_transact_altivec)
24 stw r4,THREAD_USED_VR(r3) 24 stw r4,THREAD_USED_VR(r3)
25 25
26 li r10,THREAD_TRANSACT_VRSTATE+VRSTATE_VSCR 26 li r10,THREAD_TRANSACT_VRSTATE+VRSTATE_VSCR
27 lvx vr0,r10,r3 27 lvx v0,r10,r3
28 mtvscr vr0 28 mtvscr v0
29 addi r10,r3,THREAD_TRANSACT_VRSTATE 29 addi r10,r3,THREAD_TRANSACT_VRSTATE
30 REST_32VRS(0,r4,r10) 30 REST_32VRS(0,r4,r10)
31 31
@@ -52,8 +52,8 @@ _GLOBAL(vec_enable)
52 */ 52 */
53_GLOBAL(load_vr_state) 53_GLOBAL(load_vr_state)
54 li r4,VRSTATE_VSCR 54 li r4,VRSTATE_VSCR
55 lvx vr0,r4,r3 55 lvx v0,r4,r3
56 mtvscr vr0 56 mtvscr v0
57 REST_32VRS(0,r4,r3) 57 REST_32VRS(0,r4,r3)
58 blr 58 blr
59 59
@@ -63,9 +63,9 @@ _GLOBAL(load_vr_state)
63 */ 63 */
64_GLOBAL(store_vr_state) 64_GLOBAL(store_vr_state)
65 SAVE_32VRS(0, r4, r3) 65 SAVE_32VRS(0, r4, r3)
66 mfvscr vr0 66 mfvscr v0
67 li r4, VRSTATE_VSCR 67 li r4, VRSTATE_VSCR
68 stvx vr0, r4, r3 68 stvx v0, r4, r3
69 blr 69 blr
70 70
71/* 71/*
@@ -104,9 +104,9 @@ _GLOBAL(load_up_altivec)
104 addi r4,r4,THREAD 104 addi r4,r4,THREAD
105 addi r6,r4,THREAD_VRSTATE 105 addi r6,r4,THREAD_VRSTATE
106 SAVE_32VRS(0,r5,r6) 106 SAVE_32VRS(0,r5,r6)
107 mfvscr vr0 107 mfvscr v0
108 li r10,VRSTATE_VSCR 108 li r10,VRSTATE_VSCR
109 stvx vr0,r10,r6 109 stvx v0,r10,r6
110 /* Disable VMX for last_task_used_altivec */ 110 /* Disable VMX for last_task_used_altivec */
111 PPC_LL r5,PT_REGS(r4) 111 PPC_LL r5,PT_REGS(r4)
112 toreal(r5) 112 toreal(r5)
@@ -142,8 +142,8 @@ _GLOBAL(load_up_altivec)
142 li r4,1 142 li r4,1
143 li r10,VRSTATE_VSCR 143 li r10,VRSTATE_VSCR
144 stw r4,THREAD_USED_VR(r5) 144 stw r4,THREAD_USED_VR(r5)
145 lvx vr0,r10,r6 145 lvx v0,r10,r6
146 mtvscr vr0 146 mtvscr v0
147 REST_32VRS(0,r4,r6) 147 REST_32VRS(0,r4,r6)
148#ifndef CONFIG_SMP 148#ifndef CONFIG_SMP
149 /* Update last_task_used_altivec to 'current' */ 149 /* Update last_task_used_altivec to 'current' */
@@ -186,9 +186,9 @@ _GLOBAL(giveup_altivec)
186 addi r7,r3,THREAD_VRSTATE 186 addi r7,r3,THREAD_VRSTATE
1872: PPC_LCMPI 0,r5,0 1872: PPC_LCMPI 0,r5,0
188 SAVE_32VRS(0,r4,r7) 188 SAVE_32VRS(0,r4,r7)
189 mfvscr vr0 189 mfvscr v0
190 li r4,VRSTATE_VSCR 190 li r4,VRSTATE_VSCR
191 stvx vr0,r4,r7 191 stvx v0,r4,r7
192 beq 1f 192 beq 1f
193 PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 193 PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
194#ifdef CONFIG_VSX 194#ifdef CONFIG_VSX
diff --git a/arch/powerpc/lib/copypage_power7.S b/arch/powerpc/lib/copypage_power7.S
index d7dafb3777ac..a84d333ecb09 100644
--- a/arch/powerpc/lib/copypage_power7.S
+++ b/arch/powerpc/lib/copypage_power7.S
@@ -83,23 +83,23 @@ _GLOBAL(copypage_power7)
83 li r12,112 83 li r12,112
84 84
85 .align 5 85 .align 5
861: lvx vr7,r0,r4 861: lvx v7,r0,r4
87 lvx vr6,r4,r6 87 lvx v6,r4,r6
88 lvx vr5,r4,r7 88 lvx v5,r4,r7
89 lvx vr4,r4,r8 89 lvx v4,r4,r8
90 lvx vr3,r4,r9 90 lvx v3,r4,r9
91 lvx vr2,r4,r10 91 lvx v2,r4,r10
92 lvx vr1,r4,r11 92 lvx v1,r4,r11
93 lvx vr0,r4,r12 93 lvx v0,r4,r12
94 addi r4,r4,128 94 addi r4,r4,128
95 stvx vr7,r0,r3 95 stvx v7,r0,r3
96 stvx vr6,r3,r6 96 stvx v6,r3,r6
97 stvx vr5,r3,r7 97 stvx v5,r3,r7
98 stvx vr4,r3,r8 98 stvx v4,r3,r8
99 stvx vr3,r3,r9 99 stvx v3,r3,r9
100 stvx vr2,r3,r10 100 stvx v2,r3,r10
101 stvx vr1,r3,r11 101 stvx v1,r3,r11
102 stvx vr0,r3,r12 102 stvx v0,r3,r12
103 addi r3,r3,128 103 addi r3,r3,128
104 bdnz 1b 104 bdnz 1b
105 105
diff --git a/arch/powerpc/lib/copyuser_power7.S b/arch/powerpc/lib/copyuser_power7.S
index 92ee840529bc..da0c568d18c4 100644
--- a/arch/powerpc/lib/copyuser_power7.S
+++ b/arch/powerpc/lib/copyuser_power7.S
@@ -388,29 +388,29 @@ err3; std r0,0(r3)
388 li r11,48 388 li r11,48
389 389
390 bf cr7*4+3,5f 390 bf cr7*4+3,5f
391err3; lvx vr1,r0,r4 391err3; lvx v1,r0,r4
392 addi r4,r4,16 392 addi r4,r4,16
393err3; stvx vr1,r0,r3 393err3; stvx v1,r0,r3
394 addi r3,r3,16 394 addi r3,r3,16
395 395
3965: bf cr7*4+2,6f 3965: bf cr7*4+2,6f
397err3; lvx vr1,r0,r4 397err3; lvx v1,r0,r4
398err3; lvx vr0,r4,r9 398err3; lvx v0,r4,r9
399 addi r4,r4,32 399 addi r4,r4,32
400err3; stvx vr1,r0,r3 400err3; stvx v1,r0,r3
401err3; stvx vr0,r3,r9 401err3; stvx v0,r3,r9
402 addi r3,r3,32 402 addi r3,r3,32
403 403
4046: bf cr7*4+1,7f 4046: bf cr7*4+1,7f
405err3; lvx vr3,r0,r4 405err3; lvx v3,r0,r4
406err3; lvx vr2,r4,r9 406err3; lvx v2,r4,r9
407err3; lvx vr1,r4,r10 407err3; lvx v1,r4,r10
408err3; lvx vr0,r4,r11 408err3; lvx v0,r4,r11
409 addi r4,r4,64 409 addi r4,r4,64
410err3; stvx vr3,r0,r3 410err3; stvx v3,r0,r3
411err3; stvx vr2,r3,r9 411err3; stvx v2,r3,r9
412err3; stvx vr1,r3,r10 412err3; stvx v1,r3,r10
413err3; stvx vr0,r3,r11 413err3; stvx v0,r3,r11
414 addi r3,r3,64 414 addi r3,r3,64
415 415
4167: sub r5,r5,r6 4167: sub r5,r5,r6
@@ -433,23 +433,23 @@ err3; stvx vr0,r3,r11
433 */ 433 */
434 .align 5 434 .align 5
4358: 4358:
436err4; lvx vr7,r0,r4 436err4; lvx v7,r0,r4
437err4; lvx vr6,r4,r9 437err4; lvx v6,r4,r9
438err4; lvx vr5,r4,r10 438err4; lvx v5,r4,r10
439err4; lvx vr4,r4,r11 439err4; lvx v4,r4,r11
440err4; lvx vr3,r4,r12 440err4; lvx v3,r4,r12
441err4; lvx vr2,r4,r14 441err4; lvx v2,r4,r14
442err4; lvx vr1,r4,r15 442err4; lvx v1,r4,r15
443err4; lvx vr0,r4,r16 443err4; lvx v0,r4,r16
444 addi r4,r4,128 444 addi r4,r4,128
445err4; stvx vr7,r0,r3 445err4; stvx v7,r0,r3
446err4; stvx vr6,r3,r9 446err4; stvx v6,r3,r9
447err4; stvx vr5,r3,r10 447err4; stvx v5,r3,r10
448err4; stvx vr4,r3,r11 448err4; stvx v4,r3,r11
449err4; stvx vr3,r3,r12 449err4; stvx v3,r3,r12
450err4; stvx vr2,r3,r14 450err4; stvx v2,r3,r14
451err4; stvx vr1,r3,r15 451err4; stvx v1,r3,r15
452err4; stvx vr0,r3,r16 452err4; stvx v0,r3,r16
453 addi r3,r3,128 453 addi r3,r3,128
454 bdnz 8b 454 bdnz 8b
455 455
@@ -463,29 +463,29 @@ err4; stvx vr0,r3,r16
463 mtocrf 0x01,r6 463 mtocrf 0x01,r6
464 464
465 bf cr7*4+1,9f 465 bf cr7*4+1,9f
466err3; lvx vr3,r0,r4 466err3; lvx v3,r0,r4
467err3; lvx vr2,r4,r9 467err3; lvx v2,r4,r9
468err3; lvx vr1,r4,r10 468err3; lvx v1,r4,r10
469err3; lvx vr0,r4,r11 469err3; lvx v0,r4,r11
470 addi r4,r4,64 470 addi r4,r4,64
471err3; stvx vr3,r0,r3 471err3; stvx v3,r0,r3
472err3; stvx vr2,r3,r9 472err3; stvx v2,r3,r9
473err3; stvx vr1,r3,r10 473err3; stvx v1,r3,r10
474err3; stvx vr0,r3,r11 474err3; stvx v0,r3,r11
475 addi r3,r3,64 475 addi r3,r3,64
476 476
4779: bf cr7*4+2,10f 4779: bf cr7*4+2,10f
478err3; lvx vr1,r0,r4 478err3; lvx v1,r0,r4
479err3; lvx vr0,r4,r9 479err3; lvx v0,r4,r9
480 addi r4,r4,32 480 addi r4,r4,32
481err3; stvx vr1,r0,r3 481err3; stvx v1,r0,r3
482err3; stvx vr0,r3,r9 482err3; stvx v0,r3,r9
483 addi r3,r3,32 483 addi r3,r3,32
484 484
48510: bf cr7*4+3,11f 48510: bf cr7*4+3,11f
486err3; lvx vr1,r0,r4 486err3; lvx v1,r0,r4
487 addi r4,r4,16 487 addi r4,r4,16
488err3; stvx vr1,r0,r3 488err3; stvx v1,r0,r3
489 addi r3,r3,16 489 addi r3,r3,16
490 490
491 /* Up to 15B to go */ 491 /* Up to 15B to go */
@@ -560,42 +560,42 @@ err3; stw r7,4(r3)
560 li r10,32 560 li r10,32
561 li r11,48 561 li r11,48
562 562
563 LVS(vr16,0,r4) /* Setup permute control vector */ 563 LVS(v16,0,r4) /* Setup permute control vector */
564err3; lvx vr0,0,r4 564err3; lvx v0,0,r4
565 addi r4,r4,16 565 addi r4,r4,16
566 566
567 bf cr7*4+3,5f 567 bf cr7*4+3,5f
568err3; lvx vr1,r0,r4 568err3; lvx v1,r0,r4
569 VPERM(vr8,vr0,vr1,vr16) 569 VPERM(v8,v0,v1,v16)
570 addi r4,r4,16 570 addi r4,r4,16
571err3; stvx vr8,r0,r3 571err3; stvx v8,r0,r3
572 addi r3,r3,16 572 addi r3,r3,16
573 vor vr0,vr1,vr1 573 vor v0,v1,v1
574 574
5755: bf cr7*4+2,6f 5755: bf cr7*4+2,6f
576err3; lvx vr1,r0,r4 576err3; lvx v1,r0,r4
577 VPERM(vr8,vr0,vr1,vr16) 577 VPERM(v8,v0,v1,v16)
578err3; lvx vr0,r4,r9 578err3; lvx v0,r4,r9
579 VPERM(vr9,vr1,vr0,vr16) 579 VPERM(v9,v1,v0,v16)
580 addi r4,r4,32 580 addi r4,r4,32
581err3; stvx vr8,r0,r3 581err3; stvx v8,r0,r3
582err3; stvx vr9,r3,r9 582err3; stvx v9,r3,r9
583 addi r3,r3,32 583 addi r3,r3,32
584 584
5856: bf cr7*4+1,7f 5856: bf cr7*4+1,7f
586err3; lvx vr3,r0,r4 586err3; lvx v3,r0,r4
587 VPERM(vr8,vr0,vr3,vr16) 587 VPERM(v8,v0,v3,v16)
588err3; lvx vr2,r4,r9 588err3; lvx v2,r4,r9
589 VPERM(vr9,vr3,vr2,vr16) 589 VPERM(v9,v3,v2,v16)
590err3; lvx vr1,r4,r10 590err3; lvx v1,r4,r10
591 VPERM(vr10,vr2,vr1,vr16) 591 VPERM(v10,v2,v1,v16)
592err3; lvx vr0,r4,r11 592err3; lvx v0,r4,r11
593 VPERM(vr11,vr1,vr0,vr16) 593 VPERM(v11,v1,v0,v16)
594 addi r4,r4,64 594 addi r4,r4,64
595err3; stvx vr8,r0,r3 595err3; stvx v8,r0,r3
596err3; stvx vr9,r3,r9 596err3; stvx v9,r3,r9
597err3; stvx vr10,r3,r10 597err3; stvx v10,r3,r10
598err3; stvx vr11,r3,r11 598err3; stvx v11,r3,r11
599 addi r3,r3,64 599 addi r3,r3,64
600 600
6017: sub r5,r5,r6 6017: sub r5,r5,r6
@@ -618,31 +618,31 @@ err3; stvx vr11,r3,r11
618 */ 618 */
619 .align 5 619 .align 5
6208: 6208:
621err4; lvx vr7,r0,r4 621err4; lvx v7,r0,r4
622 VPERM(vr8,vr0,vr7,vr16) 622 VPERM(v8,v0,v7,v16)
623err4; lvx vr6,r4,r9 623err4; lvx v6,r4,r9
624 VPERM(vr9,vr7,vr6,vr16) 624 VPERM(v9,v7,v6,v16)
625err4; lvx vr5,r4,r10 625err4; lvx v5,r4,r10
626 VPERM(vr10,vr6,vr5,vr16) 626 VPERM(v10,v6,v5,v16)
627err4; lvx vr4,r4,r11 627err4; lvx v4,r4,r11
628 VPERM(vr11,vr5,vr4,vr16) 628 VPERM(v11,v5,v4,v16)
629err4; lvx vr3,r4,r12 629err4; lvx v3,r4,r12
630 VPERM(vr12,vr4,vr3,vr16) 630 VPERM(v12,v4,v3,v16)
631err4; lvx vr2,r4,r14 631err4; lvx v2,r4,r14
632 VPERM(vr13,vr3,vr2,vr16) 632 VPERM(v13,v3,v2,v16)
633err4; lvx vr1,r4,r15 633err4; lvx v1,r4,r15
634 VPERM(vr14,vr2,vr1,vr16) 634 VPERM(v14,v2,v1,v16)
635err4; lvx vr0,r4,r16 635err4; lvx v0,r4,r16
636 VPERM(vr15,vr1,vr0,vr16) 636 VPERM(v15,v1,v0,v16)
637 addi r4,r4,128 637 addi r4,r4,128
638err4; stvx vr8,r0,r3 638err4; stvx v8,r0,r3
639err4; stvx vr9,r3,r9 639err4; stvx v9,r3,r9
640err4; stvx vr10,r3,r10 640err4; stvx v10,r3,r10
641err4; stvx vr11,r3,r11 641err4; stvx v11,r3,r11
642err4; stvx vr12,r3,r12 642err4; stvx v12,r3,r12
643err4; stvx vr13,r3,r14 643err4; stvx v13,r3,r14
644err4; stvx vr14,r3,r15 644err4; stvx v14,r3,r15
645err4; stvx vr15,r3,r16 645err4; stvx v15,r3,r16
646 addi r3,r3,128 646 addi r3,r3,128
647 bdnz 8b 647 bdnz 8b
648 648
@@ -656,36 +656,36 @@ err4; stvx vr15,r3,r16
656 mtocrf 0x01,r6 656 mtocrf 0x01,r6
657 657
658 bf cr7*4+1,9f 658 bf cr7*4+1,9f
659err3; lvx vr3,r0,r4 659err3; lvx v3,r0,r4
660 VPERM(vr8,vr0,vr3,vr16) 660 VPERM(v8,v0,v3,v16)
661err3; lvx vr2,r4,r9 661err3; lvx v2,r4,r9
662 VPERM(vr9,vr3,vr2,vr16) 662 VPERM(v9,v3,v2,v16)
663err3; lvx vr1,r4,r10 663err3; lvx v1,r4,r10
664 VPERM(vr10,vr2,vr1,vr16) 664 VPERM(v10,v2,v1,v16)
665err3; lvx vr0,r4,r11 665err3; lvx v0,r4,r11
666 VPERM(vr11,vr1,vr0,vr16) 666 VPERM(v11,v1,v0,v16)
667 addi r4,r4,64 667 addi r4,r4,64
668err3; stvx vr8,r0,r3 668err3; stvx v8,r0,r3
669err3; stvx vr9,r3,r9 669err3; stvx v9,r3,r9
670err3; stvx vr10,r3,r10 670err3; stvx v10,r3,r10
671err3; stvx vr11,r3,r11 671err3; stvx v11,r3,r11
672 addi r3,r3,64 672 addi r3,r3,64
673 673
6749: bf cr7*4+2,10f 6749: bf cr7*4+2,10f
675err3; lvx vr1,r0,r4 675err3; lvx v1,r0,r4
676 VPERM(vr8,vr0,vr1,vr16) 676 VPERM(v8,v0,v1,v16)
677err3; lvx vr0,r4,r9 677err3; lvx v0,r4,r9
678 VPERM(vr9,vr1,vr0,vr16) 678 VPERM(v9,v1,v0,v16)
679 addi r4,r4,32 679 addi r4,r4,32
680err3; stvx vr8,r0,r3 680err3; stvx v8,r0,r3
681err3; stvx vr9,r3,r9 681err3; stvx v9,r3,r9
682 addi r3,r3,32 682 addi r3,r3,32
683 683
68410: bf cr7*4+3,11f 68410: bf cr7*4+3,11f
685err3; lvx vr1,r0,r4 685err3; lvx v1,r0,r4
686 VPERM(vr8,vr0,vr1,vr16) 686 VPERM(v8,v0,v1,v16)
687 addi r4,r4,16 687 addi r4,r4,16
688err3; stvx vr8,r0,r3 688err3; stvx v8,r0,r3
689 addi r3,r3,16 689 addi r3,r3,16
690 690
691 /* Up to 15B to go */ 691 /* Up to 15B to go */
diff --git a/arch/powerpc/lib/crtsavres.S b/arch/powerpc/lib/crtsavres.S
index a5b30c71a8d3..18af0b3d3eb2 100644
--- a/arch/powerpc/lib/crtsavres.S
+++ b/arch/powerpc/lib/crtsavres.S
@@ -236,78 +236,78 @@ _GLOBAL(_rest32gpr_31_x)
236 236
237_GLOBAL(_savevr_20) 237_GLOBAL(_savevr_20)
238 li r11,-192 238 li r11,-192
239 stvx vr20,r11,r0 239 stvx v20,r11,r0
240_GLOBAL(_savevr_21) 240_GLOBAL(_savevr_21)
241 li r11,-176 241 li r11,-176
242 stvx vr21,r11,r0 242 stvx v21,r11,r0
243_GLOBAL(_savevr_22) 243_GLOBAL(_savevr_22)
244 li r11,-160 244 li r11,-160
245 stvx vr22,r11,r0 245 stvx v22,r11,r0
246_GLOBAL(_savevr_23) 246_GLOBAL(_savevr_23)
247 li r11,-144 247 li r11,-144
248 stvx vr23,r11,r0 248 stvx v23,r11,r0
249_GLOBAL(_savevr_24) 249_GLOBAL(_savevr_24)
250 li r11,-128 250 li r11,-128
251 stvx vr24,r11,r0 251 stvx v24,r11,r0
252_GLOBAL(_savevr_25) 252_GLOBAL(_savevr_25)
253 li r11,-112 253 li r11,-112
254 stvx vr25,r11,r0 254 stvx v25,r11,r0
255_GLOBAL(_savevr_26) 255_GLOBAL(_savevr_26)
256 li r11,-96 256 li r11,-96
257 stvx vr26,r11,r0 257 stvx v26,r11,r0
258_GLOBAL(_savevr_27) 258_GLOBAL(_savevr_27)
259 li r11,-80 259 li r11,-80
260 stvx vr27,r11,r0 260 stvx v27,r11,r0
261_GLOBAL(_savevr_28) 261_GLOBAL(_savevr_28)
262 li r11,-64 262 li r11,-64
263 stvx vr28,r11,r0 263 stvx v28,r11,r0
264_GLOBAL(_savevr_29) 264_GLOBAL(_savevr_29)
265 li r11,-48 265 li r11,-48
266 stvx vr29,r11,r0 266 stvx v29,r11,r0
267_GLOBAL(_savevr_30) 267_GLOBAL(_savevr_30)
268 li r11,-32 268 li r11,-32
269 stvx vr30,r11,r0 269 stvx v30,r11,r0
270_GLOBAL(_savevr_31) 270_GLOBAL(_savevr_31)
271 li r11,-16 271 li r11,-16
272 stvx vr31,r11,r0 272 stvx v31,r11,r0
273 blr 273 blr
274 274
275_GLOBAL(_restvr_20) 275_GLOBAL(_restvr_20)
276 li r11,-192 276 li r11,-192
277 lvx vr20,r11,r0 277 lvx v20,r11,r0
278_GLOBAL(_restvr_21) 278_GLOBAL(_restvr_21)
279 li r11,-176 279 li r11,-176
280 lvx vr21,r11,r0 280 lvx v21,r11,r0
281_GLOBAL(_restvr_22) 281_GLOBAL(_restvr_22)
282 li r11,-160 282 li r11,-160
283 lvx vr22,r11,r0 283 lvx v22,r11,r0
284_GLOBAL(_restvr_23) 284_GLOBAL(_restvr_23)
285 li r11,-144 285 li r11,-144
286 lvx vr23,r11,r0 286 lvx v23,r11,r0
287_GLOBAL(_restvr_24) 287_GLOBAL(_restvr_24)
288 li r11,-128 288 li r11,-128
289 lvx vr24,r11,r0 289 lvx v24,r11,r0
290_GLOBAL(_restvr_25) 290_GLOBAL(_restvr_25)
291 li r11,-112 291 li r11,-112
292 lvx vr25,r11,r0 292 lvx v25,r11,r0
293_GLOBAL(_restvr_26) 293_GLOBAL(_restvr_26)
294 li r11,-96 294 li r11,-96
295 lvx vr26,r11,r0 295 lvx v26,r11,r0
296_GLOBAL(_restvr_27) 296_GLOBAL(_restvr_27)
297 li r11,-80 297 li r11,-80
298 lvx vr27,r11,r0 298 lvx v27,r11,r0
299_GLOBAL(_restvr_28) 299_GLOBAL(_restvr_28)
300 li r11,-64 300 li r11,-64
301 lvx vr28,r11,r0 301 lvx v28,r11,r0
302_GLOBAL(_restvr_29) 302_GLOBAL(_restvr_29)
303 li r11,-48 303 li r11,-48
304 lvx vr29,r11,r0 304 lvx v29,r11,r0
305_GLOBAL(_restvr_30) 305_GLOBAL(_restvr_30)
306 li r11,-32 306 li r11,-32
307 lvx vr30,r11,r0 307 lvx v30,r11,r0
308_GLOBAL(_restvr_31) 308_GLOBAL(_restvr_31)
309 li r11,-16 309 li r11,-16
310 lvx vr31,r11,r0 310 lvx v31,r11,r0
311 blr 311 blr
312 312
313#endif /* CONFIG_ALTIVEC */ 313#endif /* CONFIG_ALTIVEC */
@@ -443,101 +443,101 @@ _restgpr0_31:
443.globl _savevr_20 443.globl _savevr_20
444_savevr_20: 444_savevr_20:
445 li r12,-192 445 li r12,-192
446 stvx vr20,r12,r0 446 stvx v20,r12,r0
447.globl _savevr_21 447.globl _savevr_21
448_savevr_21: 448_savevr_21:
449 li r12,-176 449 li r12,-176
450 stvx vr21,r12,r0 450 stvx v21,r12,r0
451.globl _savevr_22 451.globl _savevr_22
452_savevr_22: 452_savevr_22:
453 li r12,-160 453 li r12,-160
454 stvx vr22,r12,r0 454 stvx v22,r12,r0
455.globl _savevr_23 455.globl _savevr_23
456_savevr_23: 456_savevr_23:
457 li r12,-144 457 li r12,-144
458 stvx vr23,r12,r0 458 stvx v23,r12,r0
459.globl _savevr_24 459.globl _savevr_24
460_savevr_24: 460_savevr_24:
461 li r12,-128 461 li r12,-128
462 stvx vr24,r12,r0 462 stvx v24,r12,r0
463.globl _savevr_25 463.globl _savevr_25
464_savevr_25: 464_savevr_25:
465 li r12,-112 465 li r12,-112
466 stvx vr25,r12,r0 466 stvx v25,r12,r0
467.globl _savevr_26 467.globl _savevr_26
468_savevr_26: 468_savevr_26:
469 li r12,-96 469 li r12,-96
470 stvx vr26,r12,r0 470 stvx v26,r12,r0
471.globl _savevr_27 471.globl _savevr_27
472_savevr_27: 472_savevr_27:
473 li r12,-80 473 li r12,-80
474 stvx vr27,r12,r0 474 stvx v27,r12,r0
475.globl _savevr_28 475.globl _savevr_28
476_savevr_28: 476_savevr_28:
477 li r12,-64 477 li r12,-64
478 stvx vr28,r12,r0 478 stvx v28,r12,r0
479.globl _savevr_29 479.globl _savevr_29
480_savevr_29: 480_savevr_29:
481 li r12,-48 481 li r12,-48
482 stvx vr29,r12,r0 482 stvx v29,r12,r0
483.globl _savevr_30 483.globl _savevr_30
484_savevr_30: 484_savevr_30:
485 li r12,-32 485 li r12,-32
486 stvx vr30,r12,r0 486 stvx v30,r12,r0
487.globl _savevr_31 487.globl _savevr_31
488_savevr_31: 488_savevr_31:
489 li r12,-16 489 li r12,-16
490 stvx vr31,r12,r0 490 stvx v31,r12,r0
491 blr 491 blr
492 492
493.globl _restvr_20 493.globl _restvr_20
494_restvr_20: 494_restvr_20:
495 li r12,-192 495 li r12,-192
496 lvx vr20,r12,r0 496 lvx v20,r12,r0
497.globl _restvr_21 497.globl _restvr_21
498_restvr_21: 498_restvr_21:
499 li r12,-176 499 li r12,-176
500 lvx vr21,r12,r0 500 lvx v21,r12,r0
501.globl _restvr_22 501.globl _restvr_22
502_restvr_22: 502_restvr_22:
503 li r12,-160 503 li r12,-160
504 lvx vr22,r12,r0 504 lvx v22,r12,r0
505.globl _restvr_23 505.globl _restvr_23
506_restvr_23: 506_restvr_23:
507 li r12,-144 507 li r12,-144
508 lvx vr23,r12,r0 508 lvx v23,r12,r0
509.globl _restvr_24 509.globl _restvr_24
510_restvr_24: 510_restvr_24:
511 li r12,-128 511 li r12,-128
512 lvx vr24,r12,r0 512 lvx v24,r12,r0
513.globl _restvr_25 513.globl _restvr_25
514_restvr_25: 514_restvr_25:
515 li r12,-112 515 li r12,-112
516 lvx vr25,r12,r0 516 lvx v25,r12,r0
517.globl _restvr_26 517.globl _restvr_26
518_restvr_26: 518_restvr_26:
519 li r12,-96 519 li r12,-96
520 lvx vr26,r12,r0 520 lvx v26,r12,r0
521.globl _restvr_27 521.globl _restvr_27
522_restvr_27: 522_restvr_27:
523 li r12,-80 523 li r12,-80
524 lvx vr27,r12,r0 524 lvx v27,r12,r0
525.globl _restvr_28 525.globl _restvr_28
526_restvr_28: 526_restvr_28:
527 li r12,-64 527 li r12,-64
528 lvx vr28,r12,r0 528 lvx v28,r12,r0
529.globl _restvr_29 529.globl _restvr_29
530_restvr_29: 530_restvr_29:
531 li r12,-48 531 li r12,-48
532 lvx vr29,r12,r0 532 lvx v29,r12,r0
533.globl _restvr_30 533.globl _restvr_30
534_restvr_30: 534_restvr_30:
535 li r12,-32 535 li r12,-32
536 lvx vr30,r12,r0 536 lvx v30,r12,r0
537.globl _restvr_31 537.globl _restvr_31
538_restvr_31: 538_restvr_31:
539 li r12,-16 539 li r12,-16
540 lvx vr31,r12,r0 540 lvx v31,r12,r0
541 blr 541 blr
542 542
543#endif /* CONFIG_ALTIVEC */ 543#endif /* CONFIG_ALTIVEC */
diff --git a/arch/powerpc/lib/ldstfp.S b/arch/powerpc/lib/ldstfp.S
index 85aec08ab234..659c7ca1f4f2 100644
--- a/arch/powerpc/lib/ldstfp.S
+++ b/arch/powerpc/lib/ldstfp.S
@@ -184,16 +184,16 @@ _GLOBAL(do_stfd)
184 extab 2b,3b 184 extab 2b,3b
185 185
186#ifdef CONFIG_ALTIVEC 186#ifdef CONFIG_ALTIVEC
187/* Get the contents of vrN into vr0; N is in r3. */ 187/* Get the contents of vrN into v0; N is in r3. */
188_GLOBAL(get_vr) 188_GLOBAL(get_vr)
189 mflr r0 189 mflr r0
190 rlwinm r3,r3,3,0xf8 190 rlwinm r3,r3,3,0xf8
191 bcl 20,31,1f 191 bcl 20,31,1f
192 blr /* vr0 is already in vr0 */ 192 blr /* v0 is already in v0 */
193 nop 193 nop
194reg = 1 194reg = 1
195 .rept 31 195 .rept 31
196 vor vr0,reg,reg /* assembler doesn't know vmr? */ 196 vor v0,reg,reg /* assembler doesn't know vmr? */
197 blr 197 blr
198reg = reg + 1 198reg = reg + 1
199 .endr 199 .endr
@@ -203,16 +203,16 @@ reg = reg + 1
203 mtlr r0 203 mtlr r0
204 bctr 204 bctr
205 205
206/* Put the contents of vr0 into vrN; N is in r3. */ 206/* Put the contents of v0 into vrN; N is in r3. */
207_GLOBAL(put_vr) 207_GLOBAL(put_vr)
208 mflr r0 208 mflr r0
209 rlwinm r3,r3,3,0xf8 209 rlwinm r3,r3,3,0xf8
210 bcl 20,31,1f 210 bcl 20,31,1f
211 blr /* vr0 is already in vr0 */ 211 blr /* v0 is already in v0 */
212 nop 212 nop
213reg = 1 213reg = 1
214 .rept 31 214 .rept 31
215 vor reg,vr0,vr0 215 vor reg,v0,v0
216 blr 216 blr
217reg = reg + 1 217reg = reg + 1
218 .endr 218 .endr
@@ -234,13 +234,13 @@ _GLOBAL(do_lvx)
234 MTMSRD(r7) 234 MTMSRD(r7)
235 isync 235 isync
236 beq cr7,1f 236 beq cr7,1f
237 stvx vr0,r1,r8 237 stvx v0,r1,r8
2381: li r9,-EFAULT 2381: li r9,-EFAULT
2392: lvx vr0,0,r4 2392: lvx v0,0,r4
240 li r9,0 240 li r9,0
2413: beq cr7,4f 2413: beq cr7,4f
242 bl put_vr 242 bl put_vr
243 lvx vr0,r1,r8 243 lvx v0,r1,r8
2444: PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1) 2444: PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1)
245 mtlr r0 245 mtlr r0
246 MTMSRD(r6) 246 MTMSRD(r6)
@@ -262,13 +262,13 @@ _GLOBAL(do_stvx)
262 MTMSRD(r7) 262 MTMSRD(r7)
263 isync 263 isync
264 beq cr7,1f 264 beq cr7,1f
265 stvx vr0,r1,r8 265 stvx v0,r1,r8
266 bl get_vr 266 bl get_vr
2671: li r9,-EFAULT 2671: li r9,-EFAULT
2682: stvx vr0,0,r4 2682: stvx v0,0,r4
269 li r9,0 269 li r9,0
2703: beq cr7,4f 2703: beq cr7,4f
271 lvx vr0,r1,r8 271 lvx v0,r1,r8
2724: PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1) 2724: PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1)
273 mtlr r0 273 mtlr r0
274 MTMSRD(r6) 274 MTMSRD(r6)
@@ -304,7 +304,7 @@ _GLOBAL(put_vsr)
304 mflr r0 304 mflr r0
305 rlwinm r3,r3,3,0x1f8 305 rlwinm r3,r3,3,0x1f8
306 bcl 20,31,1f 306 bcl 20,31,1f
307 blr /* vr0 is already in vr0 */ 307 blr /* v0 is already in v0 */
308 nop 308 nop
309reg = 1 309reg = 1
310 .rept 63 310 .rept 63
diff --git a/arch/powerpc/lib/memcpy_power7.S b/arch/powerpc/lib/memcpy_power7.S
index 0830587df16e..786234fd4e91 100644
--- a/arch/powerpc/lib/memcpy_power7.S
+++ b/arch/powerpc/lib/memcpy_power7.S
@@ -321,29 +321,29 @@ _GLOBAL(memcpy_power7)
321 li r11,48 321 li r11,48
322 322
323 bf cr7*4+3,5f 323 bf cr7*4+3,5f
324 lvx vr1,r0,r4 324 lvx v1,r0,r4
325 addi r4,r4,16 325 addi r4,r4,16
326 stvx vr1,r0,r3 326 stvx v1,r0,r3
327 addi r3,r3,16 327 addi r3,r3,16
328 328
3295: bf cr7*4+2,6f 3295: bf cr7*4+2,6f
330 lvx vr1,r0,r4 330 lvx v1,r0,r4
331 lvx vr0,r4,r9 331 lvx v0,r4,r9
332 addi r4,r4,32 332 addi r4,r4,32
333 stvx vr1,r0,r3 333 stvx v1,r0,r3
334 stvx vr0,r3,r9 334 stvx v0,r3,r9
335 addi r3,r3,32 335 addi r3,r3,32
336 336
3376: bf cr7*4+1,7f 3376: bf cr7*4+1,7f
338 lvx vr3,r0,r4 338 lvx v3,r0,r4
339 lvx vr2,r4,r9 339 lvx v2,r4,r9
340 lvx vr1,r4,r10 340 lvx v1,r4,r10
341 lvx vr0,r4,r11 341 lvx v0,r4,r11
342 addi r4,r4,64 342 addi r4,r4,64
343 stvx vr3,r0,r3 343 stvx v3,r0,r3
344 stvx vr2,r3,r9 344 stvx v2,r3,r9
345 stvx vr1,r3,r10 345 stvx v1,r3,r10
346 stvx vr0,r3,r11 346 stvx v0,r3,r11
347 addi r3,r3,64 347 addi r3,r3,64
348 348
3497: sub r5,r5,r6 3497: sub r5,r5,r6
@@ -366,23 +366,23 @@ _GLOBAL(memcpy_power7)
366 */ 366 */
367 .align 5 367 .align 5
3688: 3688:
369 lvx vr7,r0,r4 369 lvx v7,r0,r4
370 lvx vr6,r4,r9 370 lvx v6,r4,r9
371 lvx vr5,r4,r10 371 lvx v5,r4,r10
372 lvx vr4,r4,r11 372 lvx v4,r4,r11
373 lvx vr3,r4,r12 373 lvx v3,r4,r12
374 lvx vr2,r4,r14 374 lvx v2,r4,r14
375 lvx vr1,r4,r15 375 lvx v1,r4,r15
376 lvx vr0,r4,r16 376 lvx v0,r4,r16
377 addi r4,r4,128 377 addi r4,r4,128
378 stvx vr7,r0,r3 378 stvx v7,r0,r3
379 stvx vr6,r3,r9 379 stvx v6,r3,r9
380 stvx vr5,r3,r10 380 stvx v5,r3,r10
381 stvx vr4,r3,r11 381 stvx v4,r3,r11
382 stvx vr3,r3,r12 382 stvx v3,r3,r12
383 stvx vr2,r3,r14 383 stvx v2,r3,r14
384 stvx vr1,r3,r15 384 stvx v1,r3,r15
385 stvx vr0,r3,r16 385 stvx v0,r3,r16
386 addi r3,r3,128 386 addi r3,r3,128
387 bdnz 8b 387 bdnz 8b
388 388
@@ -396,29 +396,29 @@ _GLOBAL(memcpy_power7)
396 mtocrf 0x01,r6 396 mtocrf 0x01,r6
397 397
398 bf cr7*4+1,9f 398 bf cr7*4+1,9f
399 lvx vr3,r0,r4 399 lvx v3,r0,r4
400 lvx vr2,r4,r9 400 lvx v2,r4,r9
401 lvx vr1,r4,r10 401 lvx v1,r4,r10
402 lvx vr0,r4,r11 402 lvx v0,r4,r11
403 addi r4,r4,64 403 addi r4,r4,64
404 stvx vr3,r0,r3 404 stvx v3,r0,r3
405 stvx vr2,r3,r9 405 stvx v2,r3,r9
406 stvx vr1,r3,r10 406 stvx v1,r3,r10
407 stvx vr0,r3,r11 407 stvx v0,r3,r11
408 addi r3,r3,64 408 addi r3,r3,64
409 409
4109: bf cr7*4+2,10f 4109: bf cr7*4+2,10f
411 lvx vr1,r0,r4 411 lvx v1,r0,r4
412 lvx vr0,r4,r9 412 lvx v0,r4,r9
413 addi r4,r4,32 413 addi r4,r4,32
414 stvx vr1,r0,r3 414 stvx v1,r0,r3
415 stvx vr0,r3,r9 415 stvx v0,r3,r9
416 addi r3,r3,32 416 addi r3,r3,32
417 417
41810: bf cr7*4+3,11f 41810: bf cr7*4+3,11f
419 lvx vr1,r0,r4 419 lvx v1,r0,r4
420 addi r4,r4,16 420 addi r4,r4,16
421 stvx vr1,r0,r3 421 stvx v1,r0,r3
422 addi r3,r3,16 422 addi r3,r3,16
423 423
424 /* Up to 15B to go */ 424 /* Up to 15B to go */
@@ -494,42 +494,42 @@ _GLOBAL(memcpy_power7)
494 li r10,32 494 li r10,32
495 li r11,48 495 li r11,48
496 496
497 LVS(vr16,0,r4) /* Setup permute control vector */ 497 LVS(v16,0,r4) /* Setup permute control vector */
498 lvx vr0,0,r4 498 lvx v0,0,r4
499 addi r4,r4,16 499 addi r4,r4,16
500 500
501 bf cr7*4+3,5f 501 bf cr7*4+3,5f
502 lvx vr1,r0,r4 502 lvx v1,r0,r4
503 VPERM(vr8,vr0,vr1,vr16) 503 VPERM(v8,v0,v1,v16)
504 addi r4,r4,16 504 addi r4,r4,16
505 stvx vr8,r0,r3 505 stvx v8,r0,r3
506 addi r3,r3,16 506 addi r3,r3,16
507 vor vr0,vr1,vr1 507 vor v0,v1,v1
508 508
5095: bf cr7*4+2,6f 5095: bf cr7*4+2,6f
510 lvx vr1,r0,r4 510 lvx v1,r0,r4
511 VPERM(vr8,vr0,vr1,vr16) 511 VPERM(v8,v0,v1,v16)
512 lvx vr0,r4,r9 512 lvx v0,r4,r9
513 VPERM(vr9,vr1,vr0,vr16) 513 VPERM(v9,v1,v0,v16)
514 addi r4,r4,32 514 addi r4,r4,32
515 stvx vr8,r0,r3 515 stvx v8,r0,r3
516 stvx vr9,r3,r9 516 stvx v9,r3,r9
517 addi r3,r3,32 517 addi r3,r3,32
518 518
5196: bf cr7*4+1,7f 5196: bf cr7*4+1,7f
520 lvx vr3,r0,r4 520 lvx v3,r0,r4
521 VPERM(vr8,vr0,vr3,vr16) 521 VPERM(v8,v0,v3,v16)
522 lvx vr2,r4,r9 522 lvx v2,r4,r9
523 VPERM(vr9,vr3,vr2,vr16) 523 VPERM(v9,v3,v2,v16)
524 lvx vr1,r4,r10 524 lvx v1,r4,r10
525 VPERM(vr10,vr2,vr1,vr16) 525 VPERM(v10,v2,v1,v16)
526 lvx vr0,r4,r11 526 lvx v0,r4,r11
527 VPERM(vr11,vr1,vr0,vr16) 527 VPERM(v11,v1,v0,v16)
528 addi r4,r4,64 528 addi r4,r4,64
529 stvx vr8,r0,r3 529 stvx v8,r0,r3
530 stvx vr9,r3,r9 530 stvx v9,r3,r9
531 stvx vr10,r3,r10 531 stvx v10,r3,r10
532 stvx vr11,r3,r11 532 stvx v11,r3,r11
533 addi r3,r3,64 533 addi r3,r3,64
534 534
5357: sub r5,r5,r6 5357: sub r5,r5,r6
@@ -552,31 +552,31 @@ _GLOBAL(memcpy_power7)
552 */ 552 */
553 .align 5 553 .align 5
5548: 5548:
555 lvx vr7,r0,r4 555 lvx v7,r0,r4
556 VPERM(vr8,vr0,vr7,vr16) 556 VPERM(v8,v0,v7,v16)
557 lvx vr6,r4,r9 557 lvx v6,r4,r9
558 VPERM(vr9,vr7,vr6,vr16) 558 VPERM(v9,v7,v6,v16)
559 lvx vr5,r4,r10 559 lvx v5,r4,r10
560 VPERM(vr10,vr6,vr5,vr16) 560 VPERM(v10,v6,v5,v16)
561 lvx vr4,r4,r11 561 lvx v4,r4,r11
562 VPERM(vr11,vr5,vr4,vr16) 562 VPERM(v11,v5,v4,v16)
563 lvx vr3,r4,r12 563 lvx v3,r4,r12
564 VPERM(vr12,vr4,vr3,vr16) 564 VPERM(v12,v4,v3,v16)
565 lvx vr2,r4,r14 565 lvx v2,r4,r14
566 VPERM(vr13,vr3,vr2,vr16) 566 VPERM(v13,v3,v2,v16)
567 lvx vr1,r4,r15 567 lvx v1,r4,r15
568 VPERM(vr14,vr2,vr1,vr16) 568 VPERM(v14,v2,v1,v16)
569 lvx vr0,r4,r16 569 lvx v0,r4,r16
570 VPERM(vr15,vr1,vr0,vr16) 570 VPERM(v15,v1,v0,v16)
571 addi r4,r4,128 571 addi r4,r4,128
572 stvx vr8,r0,r3 572 stvx v8,r0,r3
573 stvx vr9,r3,r9 573 stvx v9,r3,r9
574 stvx vr10,r3,r10 574 stvx v10,r3,r10
575 stvx vr11,r3,r11 575 stvx v11,r3,r11
576 stvx vr12,r3,r12 576 stvx v12,r3,r12
577 stvx vr13,r3,r14 577 stvx v13,r3,r14
578 stvx vr14,r3,r15 578 stvx v14,r3,r15
579 stvx vr15,r3,r16 579 stvx v15,r3,r16
580 addi r3,r3,128 580 addi r3,r3,128
581 bdnz 8b 581 bdnz 8b
582 582
@@ -590,36 +590,36 @@ _GLOBAL(memcpy_power7)
590 mtocrf 0x01,r6 590 mtocrf 0x01,r6
591 591
592 bf cr7*4+1,9f 592 bf cr7*4+1,9f
593 lvx vr3,r0,r4 593 lvx v3,r0,r4
594 VPERM(vr8,vr0,vr3,vr16) 594 VPERM(v8,v0,v3,v16)
595 lvx vr2,r4,r9 595 lvx v2,r4,r9
596 VPERM(vr9,vr3,vr2,vr16) 596 VPERM(v9,v3,v2,v16)
597 lvx vr1,r4,r10 597 lvx v1,r4,r10
598 VPERM(vr10,vr2,vr1,vr16) 598 VPERM(v10,v2,v1,v16)
599 lvx vr0,r4,r11 599 lvx v0,r4,r11
600 VPERM(vr11,vr1,vr0,vr16) 600 VPERM(v11,v1,v0,v16)
601 addi r4,r4,64 601 addi r4,r4,64
602 stvx vr8,r0,r3 602 stvx v8,r0,r3
603 stvx vr9,r3,r9 603 stvx v9,r3,r9
604 stvx vr10,r3,r10 604 stvx v10,r3,r10
605 stvx vr11,r3,r11 605 stvx v11,r3,r11
606 addi r3,r3,64 606 addi r3,r3,64
607 607
6089: bf cr7*4+2,10f 6089: bf cr7*4+2,10f
609 lvx vr1,r0,r4 609 lvx v1,r0,r4
610 VPERM(vr8,vr0,vr1,vr16) 610 VPERM(v8,v0,v1,v16)
611 lvx vr0,r4,r9 611 lvx v0,r4,r9
612 VPERM(vr9,vr1,vr0,vr16) 612 VPERM(v9,v1,v0,v16)
613 addi r4,r4,32 613 addi r4,r4,32
614 stvx vr8,r0,r3 614 stvx v8,r0,r3
615 stvx vr9,r3,r9 615 stvx v9,r3,r9
616 addi r3,r3,32 616 addi r3,r3,32
617 617
61810: bf cr7*4+3,11f 61810: bf cr7*4+3,11f
619 lvx vr1,r0,r4 619 lvx v1,r0,r4
620 VPERM(vr8,vr0,vr1,vr16) 620 VPERM(v8,v0,v1,v16)
621 addi r4,r4,16 621 addi r4,r4,16
622 stvx vr8,r0,r3 622 stvx v8,r0,r3
623 addi r3,r3,16 623 addi r3,r3,16
624 624
625 /* Up to 15B to go */ 625 /* Up to 15B to go */
diff --git a/tools/testing/selftests/powerpc/copyloops/asm/ppc_asm.h b/tools/testing/selftests/powerpc/copyloops/asm/ppc_asm.h
index d1dc37425510..50ae7d2091ce 100644
--- a/tools/testing/selftests/powerpc/copyloops/asm/ppc_asm.h
+++ b/tools/testing/selftests/powerpc/copyloops/asm/ppc_asm.h
@@ -4,39 +4,6 @@
4 4
5#define r1 1 5#define r1 1
6 6
7#define vr0 0
8#define vr1 1
9#define vr2 2
10#define vr3 3
11#define vr4 4
12#define vr5 5
13#define vr6 6
14#define vr7 7
15#define vr8 8
16#define vr9 9
17#define vr10 10
18#define vr11 11
19#define vr12 12
20#define vr13 13
21#define vr14 14
22#define vr15 15
23#define vr16 16
24#define vr17 17
25#define vr18 18
26#define vr19 19
27#define vr20 20
28#define vr21 21
29#define vr22 22
30#define vr23 23
31#define vr24 24
32#define vr25 25
33#define vr26 26
34#define vr27 27
35#define vr28 28
36#define vr29 29
37#define vr30 30
38#define vr31 31
39
40#define R14 r14 7#define R14 r14
41#define R15 r15 8#define R15 r15
42#define R16 r16 9#define R16 r16
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-12 22:02:21 -0400