x86/cpufeature: Remove cpu_has_pge

Use static_cpu_has() in __flush_tlb_all() due to the time-sensitivity of
this one.

Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1459266123-21878-10-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>

8 files changed, 11 insertions, 12 deletions

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 5e02bc2e8444..f97b53417d44 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -121,7 +121,6 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
 #define cpu_has_fpu             boot_cpu_has(X86_FEATURE_FPU)
 #define cpu_has_pse             boot_cpu_has(X86_FEATURE_PSE)
 #define cpu_has_tsc             boot_cpu_has(X86_FEATURE_TSC)
-#define cpu_has_pge             boot_cpu_has(X86_FEATURE_PGE)
 #define cpu_has_apic            boot_cpu_has(X86_FEATURE_APIC)
 #define cpu_has_fxsr            boot_cpu_has(X86_FEATURE_FXSR)
 #define cpu_has_xmm             boot_cpu_has(X86_FEATURE_XMM)
diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
index c24b4224d439..3628e6c5ebf4 100644
--- a/arch/x86/include/asm/tlbflush.h
+++ b/arch/x86/include/asm/tlbflush.h
@@ -181,7 +181,7 @@ static inline void __native_flush_tlb_single(unsigned long addr)
 
 static inline void __flush_tlb_all(void)
 {
-        if (cpu_has_pge)
+        if (static_cpu_has(X86_FEATURE_PGE))
                 __flush_tlb_global();
         else
                 __flush_tlb();
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 1dba36fe73e5..f71a34944b56 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -152,9 +152,9 @@ static void early_init_intel(struct cpuinfo_x86 *c)
          *  the TLB when any changes are made to any of the page table entries.
          *  The operating system must reload CR3 to cause the TLB to be flushed"
          *
-         * As a result cpu_has_pge() in arch/x86/include/asm/tlbflush.h should
-         * be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE
-         * to be modified
+         * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h
+         * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE
+         * to be modified.
          */
         if (c->x86 == 5 && c->x86_model == 9) {
                 pr_info("Disabling PGE capability bit\n");
diff --git a/arch/x86/kernel/cpu/mtrr/cyrix.c b/arch/x86/kernel/cpu/mtrr/cyrix.c
index f8c81ba0b465..b1086f79e57e 100644
--- a/arch/x86/kernel/cpu/mtrr/cyrix.c
+++ b/arch/x86/kernel/cpu/mtrr/cyrix.c
@@ -137,7 +137,7 @@ static void prepare_set(void)
         u32 cr0;
 
         /*  Save value of CR4 and clear Page Global Enable (bit 7)  */
-        if (cpu_has_pge) {
+        if (boot_cpu_has(X86_FEATURE_PGE)) {
                 cr4 = __read_cr4();
                 __write_cr4(cr4 & ~X86_CR4_PGE);
         }
@@ -170,7 +170,7 @@ static void post_set(void)
         write_cr0(read_cr0() & ~X86_CR0_CD);
 
         /* Restore value of CR4 */
-        if (cpu_has_pge)
+        if (boot_cpu_has(X86_FEATURE_PGE))
                 __write_cr4(cr4);
 }
 
diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c
index 19f57360dfd2..f1bed301bdb2 100644
--- a/arch/x86/kernel/cpu/mtrr/generic.c
+++ b/arch/x86/kernel/cpu/mtrr/generic.c
@@ -741,7 +741,7 @@ static void prepare_set(void) __acquires(set_atomicity_lock)
         wbinvd();
 
         /* Save value of CR4 and clear Page Global Enable (bit 7) */
-        if (cpu_has_pge) {
+        if (boot_cpu_has(X86_FEATURE_PGE)) {
                 cr4 = __read_cr4();
                 __write_cr4(cr4 & ~X86_CR4_PGE);
         }
@@ -771,7 +771,7 @@ static void post_set(void) __releases(set_atomicity_lock)
         write_cr0(read_cr0() & ~X86_CR0_CD);
 
         /* Restore value of CR4 */
-        if (cpu_has_pge)
+        if (boot_cpu_has(X86_FEATURE_PGE))
                 __write_cr4(cr4);
         raw_spin_unlock(&set_atomicity_lock);
 }
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index 14377e98f279..05ff46a9c261 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -166,7 +166,7 @@ static void __init probe_page_size_mask(void)
                 cr4_set_bits_and_update_boot(X86_CR4_PSE);
 
         /* Enable PGE if available */
-        if (cpu_has_pge) {
+        if (boot_cpu_has(X86_FEATURE_PGE)) {
                 cr4_set_bits_and_update_boot(X86_CR4_PGE);
                 __supported_pte_mask |= _PAGE_GLOBAL;
         } else
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index 880862c7d9dd..055f48ddb03c 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -1472,7 +1472,7 @@ static void xen_pvh_set_cr_flags(int cpu)
         if (cpu_has_pse)
                 cr4_set_bits_and_update_boot(X86_CR4_PSE);
 
-        if (cpu_has_pge)
+        if (boot_cpu_has(X86_FEATURE_PGE))
                 cr4_set_bits_and_update_boot(X86_CR4_PGE);
 }
 
diff --git a/drivers/lguest/x86/core.c b/drivers/lguest/x86/core.c
index 6a4cd771a2be..65f22debf3c6 100644
--- a/drivers/lguest/x86/core.c
+++ b/drivers/lguest/x86/core.c
@@ -599,7 +599,7 @@ void __init lguest_arch_host_init(void)
          * doing this.
          */
         get_online_cpus();
-        if (cpu_has_pge) { /* We have a broader idea of "global". */
+        if (boot_cpu_has(X86_FEATURE_PGE)) { /* We have a broader idea of "global". */
                 /* Remember that this was originally set (for cleanup). */
                 cpu_had_pge = 1;
                 /*