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authorAlex Deucher <alexander.deucher@amd.com>2016-09-27 14:57:35 -0400
committerAlex Deucher <alexander.deucher@amd.com>2016-09-28 16:13:17 -0400
commitbdbdb571c807b927867bd391159c9872a952533f (patch)
tree0621b34a22cc3da4e1415840ea6e8eb8cab7e170
parent427920292b00474d978d632bc03a8e4e50029af3 (diff)
drm/amdgpu/si/dpm: fix phase shedding setup
Used the wrong index to setup the phase shedding mask. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si_dpm.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sislands_smc.h1
2 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 73ccf33d84d5..8bd08925b370 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -4593,7 +4593,7 @@ static int si_populate_smc_voltage_tables(struct amdgpu_device *adev,
4593 &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 4593 &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4594 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table); 4594 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);
4595 4595
4596 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4596 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4597 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 4597 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4598 4598
4599 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 4599 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
diff --git a/drivers/gpu/drm/amd/amdgpu/sislands_smc.h b/drivers/gpu/drm/amd/amdgpu/sislands_smc.h
index ee4b846e58fa..d2930eceaf3c 100644
--- a/drivers/gpu/drm/amd/amdgpu/sislands_smc.h
+++ b/drivers/gpu/drm/amd/amdgpu/sislands_smc.h
@@ -194,6 +194,7 @@ typedef struct SISLANDS_SMC_SWSTATE SISLANDS_SMC_SWSTATE;
194#define SISLANDS_SMC_VOLTAGEMASK_VDDC 0 194#define SISLANDS_SMC_VOLTAGEMASK_VDDC 0
195#define SISLANDS_SMC_VOLTAGEMASK_MVDD 1 195#define SISLANDS_SMC_VOLTAGEMASK_MVDD 1
196#define SISLANDS_SMC_VOLTAGEMASK_VDDCI 2 196#define SISLANDS_SMC_VOLTAGEMASK_VDDCI 2
197#define SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING 3
197#define SISLANDS_SMC_VOLTAGEMASK_MAX 4 198#define SISLANDS_SMC_VOLTAGEMASK_MAX 4
198 199
199struct SISLANDS_SMC_VOLTAGEMASKTABLE 200struct SISLANDS_SMC_VOLTAGEMASKTABLE