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authorAlexandre Belloni <alexandre.belloni@free-electrons.com>2015-03-16 07:44:36 -0400
committerAlexandre Belloni <alexandre.belloni@free-electrons.com>2015-05-20 10:37:24 -0400
commitb8ccd9c39a3a4d8c816f323ac201f96bcc111f26 (patch)
tree0dd9c2370db8c7675c75ebd92d26a66a36a4c175
parent5a90f8d3b193407dfa8c2e47163f569d5343b3ee (diff)
ARM: at91: drop sam9_smc.c
sam9_smc.c has no users anymore, remove it along with both sam9_smc.h and mach/at91sam9_smc.h Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat
-rw-r--r--arch/arm/mach-at91/Makefile2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_smc.h98
-rw-r--r--arch/arm/mach-at91/sam9_smc.c136
-rw-r--r--arch/arm/mach-at91/sam9_smc.h11
4 files changed, 0 insertions, 247 deletions
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 4fa8b4541e64..f472704c3546 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -6,8 +6,6 @@ asflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
6 6
7obj-y := soc.o 7obj-y := soc.o
8 8
9obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o
10
11# CPU-specific support 9# CPU-specific support
12obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o 10obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o
13obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o 11obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
deleted file mode 100644
index ff54a0ce90e3..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h
+++ /dev/null
@@ -1,98 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91sam9_smc.h
3 *
4 * Copyright (C) 2007 Andrew Victor
5 * Copyright (C) 2007 Atmel Corporation.
6 *
7 * Static Memory Controllers (SMC) - System peripherals registers.
8 * Based on AT91SAM9261 datasheet revision D.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91SAM9_SMC_H
17#define AT91SAM9_SMC_H
18
19#ifndef __ASSEMBLY__
20struct sam9_smc_config {
21 /* Setup register */
22 u8 ncs_read_setup;
23 u8 nrd_setup;
24 u8 ncs_write_setup;
25 u8 nwe_setup;
26
27 /* Pulse register */
28 u8 ncs_read_pulse;
29 u8 nrd_pulse;
30 u8 ncs_write_pulse;
31 u8 nwe_pulse;
32
33 /* Cycle register */
34 u16 read_cycle;
35 u16 write_cycle;
36
37 /* Mode register */
38 u32 mode;
39 u8 tdf_cycles:4;
40};
41
42extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config);
43extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config);
44extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config);
45extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config);
46#endif
47
48#define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */
49#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
50#define AT91_SMC_NWESETUP_(x) ((x) << 0)
51#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
52#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
53#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
54#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
55#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
56#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
57
58#define AT91_SMC_PULSE 0x04 /* Pulse Register for CS n */
59#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
60#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
61#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
62#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
63#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
64#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
65#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
66#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
67
68#define AT91_SMC_CYCLE 0x08 /* Cycle Register for CS n */
69#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
70#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
71#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
72#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
73
74#define AT91_SMC_MODE 0x0c /* Mode Register for CS n */
75#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
76#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
77#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
78#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
79#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
80#define AT91_SMC_EXNWMODE_READY (3 << 4)
81#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
82#define AT91_SMC_BAT_SELECT (0 << 8)
83#define AT91_SMC_BAT_WRITE (1 << 8)
84#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
85#define AT91_SMC_DBW_8 (0 << 12)
86#define AT91_SMC_DBW_16 (1 << 12)
87#define AT91_SMC_DBW_32 (2 << 12)
88#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
89#define AT91_SMC_TDF_(x) ((x) << 16)
90#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
91#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
92#define AT91_SMC_PS (3 << 28) /* Page Size */
93#define AT91_SMC_PS_4 (0 << 28)
94#define AT91_SMC_PS_8 (1 << 28)
95#define AT91_SMC_PS_16 (2 << 28)
96#define AT91_SMC_PS_32 (3 << 28)
97
98#endif
diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
deleted file mode 100644
index 826315af6d11..000000000000
--- a/arch/arm/mach-at91/sam9_smc.c
+++ /dev/null
@@ -1,136 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/sam9_smc.c
3 *
4 * Copyright (C) 2008 Andrew Victor
5 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/io.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16
17#include <mach/at91sam9_smc.h>
18
19#include "sam9_smc.h"
20
21
22#define AT91_SMC_CS(id, n) (smc_base_addr[id] + ((n) * 0x10))
23
24static void __iomem *smc_base_addr[2];
25
26static void sam9_smc_cs_write_mode(void __iomem *base,
27 struct sam9_smc_config *config)
28{
29 __raw_writel(config->mode
30 | AT91_SMC_TDF_(config->tdf_cycles),
31 base + AT91_SMC_MODE);
32}
33
34void sam9_smc_write_mode(int id, int cs,
35 struct sam9_smc_config *config)
36{
37 sam9_smc_cs_write_mode(AT91_SMC_CS(id, cs), config);
38}
39EXPORT_SYMBOL_GPL(sam9_smc_write_mode);
40
41static void sam9_smc_cs_configure(void __iomem *base,
42 struct sam9_smc_config *config)
43{
44
45 /* Setup register */
46 __raw_writel(AT91_SMC_NWESETUP_(config->nwe_setup)
47 | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup)
48 | AT91_SMC_NRDSETUP_(config->nrd_setup)
49 | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup),
50 base + AT91_SMC_SETUP);
51
52 /* Pulse register */
53 __raw_writel(AT91_SMC_NWEPULSE_(config->nwe_pulse)
54 | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse)
55 | AT91_SMC_NRDPULSE_(config->nrd_pulse)
56 | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse),
57 base + AT91_SMC_PULSE);
58
59 /* Cycle register */
60 __raw_writel(AT91_SMC_NWECYCLE_(config->write_cycle)
61 | AT91_SMC_NRDCYCLE_(config->read_cycle),
62 base + AT91_SMC_CYCLE);
63
64 /* Mode register */
65 sam9_smc_cs_write_mode(base, config);
66}
67
68void sam9_smc_configure(int id, int cs,
69 struct sam9_smc_config *config)
70{
71 sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config);
72}
73EXPORT_SYMBOL_GPL(sam9_smc_configure);
74
75static void sam9_smc_cs_read_mode(void __iomem *base,
76 struct sam9_smc_config *config)
77{
78 u32 val = __raw_readl(base + AT91_SMC_MODE);
79
80 config->mode = (val & ~AT91_SMC_NWECYCLE);
81 config->tdf_cycles = (val & AT91_SMC_NWECYCLE) >> 16 ;
82}
83
84void sam9_smc_read_mode(int id, int cs,
85 struct sam9_smc_config *config)
86{
87 sam9_smc_cs_read_mode(AT91_SMC_CS(id, cs), config);
88}
89EXPORT_SYMBOL_GPL(sam9_smc_read_mode);
90
91static void sam9_smc_cs_read(void __iomem *base,
92 struct sam9_smc_config *config)
93{
94 u32 val;
95
96 /* Setup register */
97 val = __raw_readl(base + AT91_SMC_SETUP);
98
99 config->nwe_setup = val & AT91_SMC_NWESETUP;
100 config->ncs_write_setup = (val & AT91_SMC_NCS_WRSETUP) >> 8;
101 config->nrd_setup = (val & AT91_SMC_NRDSETUP) >> 16;
102 config->ncs_read_setup = (val & AT91_SMC_NCS_RDSETUP) >> 24;
103
104 /* Pulse register */
105 val = __raw_readl(base + AT91_SMC_PULSE);
106
107 config->nwe_pulse = val & AT91_SMC_NWEPULSE;
108 config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8;
109 config->nrd_pulse = (val & AT91_SMC_NRDPULSE) >> 16;
110 config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24;
111
112 /* Cycle register */
113 val = __raw_readl(base + AT91_SMC_CYCLE);
114
115 config->write_cycle = val & AT91_SMC_NWECYCLE;
116 config->read_cycle = (val & AT91_SMC_NRDCYCLE) >> 16;
117
118 /* Mode register */
119 sam9_smc_cs_read_mode(base, config);
120}
121
122void sam9_smc_read(int id, int cs, struct sam9_smc_config *config)
123{
124 sam9_smc_cs_read(AT91_SMC_CS(id, cs), config);
125}
126
127void __init at91sam9_ioremap_smc(int id, u32 addr)
128{
129 if (id > 1) {
130 pr_warn("%s: id > 2\n", __func__);
131 return;
132 }
133 smc_base_addr[id] = ioremap(addr, 512);
134 if (!smc_base_addr[id])
135 pr_warn("Impossible to ioremap smc.%d 0x%x\n", id, addr);
136}
diff --git a/arch/arm/mach-at91/sam9_smc.h b/arch/arm/mach-at91/sam9_smc.h
deleted file mode 100644
index 3e52dcd4a59f..000000000000
--- a/arch/arm/mach-at91/sam9_smc.h
+++ /dev/null
@@ -1,11 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/sam9_smc.
3 *
4 * Copyright (C) 2008 Andrew Victor
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11extern void __init at91sam9_ioremap_smc(int id, u32 addr);
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 09:28:23 -0400