MIPS: mm: scache: Add secondary cache support for MIPS R6 cores

The secondary cache initialization and configuration code is processor
specific so we need to handle MIPS R6 cores as well.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>

2 files changed, 4 insertions, 2 deletions

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 7ecee761ae2d..3f8059602765 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1473,7 +1473,8 @@ static void setup_scache(void)
 
         default:
                 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
-                                    MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
+                                    MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 |
+                                    MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)) {
 #ifdef CONFIG_MIPS_CPU_SCACHE
                         if (mips_sc_init ()) {
                                 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index fd9b5d45e91b..4ceafd13870c 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -105,7 +105,8 @@ static inline int __init mips_sc_probe(void)
 
         /* Ignore anything but MIPSxx processors */
         if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
-                              MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)))
+                              MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 |
+                              MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)))
                 return 0;
 
         /* Does this MIPS32/MIPS64 CPU have a config2 register? */