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authorStephen Boyd <sboyd@codeaurora.org>2015-11-30 20:31:40 -0500
committerStephen Boyd <sboyd@codeaurora.org>2015-11-30 21:24:27 -0500
commitb1e010c0730ab8861ef5a259ff5be7c78ccfb8ac (patch)
tree45ff1d4fa305a4d4536450abecefe20da4181077
parent8ff1f4c4c47676dfccd56b55104a15dcd4650a8f (diff)
clk: qcom: Add MSM8996 Global Clock Control (GCC) driver
Add support for the global clock controller found on MSM8996 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc.txt1
-rw-r--r--drivers/clk/qcom/Kconfig8
-rw-r--r--drivers/clk/qcom/Makefile1
-rw-r--r--drivers/clk/qcom/gcc-msm8996.c3422
-rw-r--r--include/dt-bindings/clock/qcom,gcc-msm8996.h339
5 files changed, 3771 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 152dfaab2575..72f82f444091 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -13,6 +13,7 @@ Required properties :
13 "qcom,gcc-msm8974" 13 "qcom,gcc-msm8974"
14 "qcom,gcc-msm8974pro" 14 "qcom,gcc-msm8974pro"
15 "qcom,gcc-msm8974pro-ac" 15 "qcom,gcc-msm8974pro-ac"
16 "qcom,gcc-msm8996"
16 17
17- reg : shall contain base register location and length 18- reg : shall contain base register location and length
18- #clock-cells : shall contain 1 19- #clock-cells : shall contain 1
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index ee4c83aab4f4..fb2b499c647d 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -106,3 +106,11 @@ config MSM_MMCC_8974
106 Support for the multimedia clock controller on msm8974 devices. 106 Support for the multimedia clock controller on msm8974 devices.
107 Say Y if you want to support multimedia devices such as display, 107 Say Y if you want to support multimedia devices such as display,
108 graphics, video encode/decode, camera, etc. 108 graphics, video encode/decode, camera, etc.
109
110config MSM_GCC_8996
111 tristate "MSM8996 Global Clock Controller"
112 depends on COMMON_CLK_QCOM
113 help
114 Support for the global clock controller on msm8996 devices.
115 Say Y if you want to use peripheral devices such as UART, SPI,
116 i2c, USB, UFS, SD/eMMC, PCIe, etc.
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 472200040788..42dca6799414 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -21,5 +21,6 @@ obj-$(CONFIG_MSM_GCC_8916) += gcc-msm8916.o
21obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o 21obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
22obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o 22obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
23obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o 23obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
24obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o
24obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o 25obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
25obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o 26obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
new file mode 100644
index 000000000000..16d7c323db49
--- /dev/null
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -0,0 +1,3422 @@
1/*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/clk-provider.h>
22#include <linux/regmap.h>
23#include <linux/reset-controller.h>
24
25#include <dt-bindings/clock/qcom,gcc-msm8996.h>
26
27#include "common.h"
28#include "clk-regmap.h"
29#include "clk-alpha-pll.h"
30#include "clk-rcg.h"
31#include "clk-branch.h"
32#include "reset.h"
33
34#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
35
36enum {
37 P_XO,
38 P_GPLL0,
39 P_GPLL2,
40 P_GPLL3,
41 P_GPLL1,
42 P_GPLL2_EARLY,
43 P_GPLL0_EARLY_DIV,
44 P_SLEEP_CLK,
45 P_GPLL4,
46 P_AUD_REF_CLK,
47 P_GPLL1_EARLY_DIV
48};
49
50static const struct parent_map gcc_sleep_clk_map[] = {
51 { P_SLEEP_CLK, 5 }
52};
53
54static const char * const gcc_sleep_clk[] = {
55 "sleep_clk"
56};
57
58static const struct parent_map gcc_xo_gpll0_map[] = {
59 { P_XO, 0 },
60 { P_GPLL0, 1 }
61};
62
63static const char * const gcc_xo_gpll0[] = {
64 "xo",
65 "gpll0"
66};
67
68static const struct parent_map gcc_xo_sleep_clk_map[] = {
69 { P_XO, 0 },
70 { P_SLEEP_CLK, 5 }
71};
72
73static const char * const gcc_xo_sleep_clk[] = {
74 "xo",
75 "sleep_clk"
76};
77
78static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
79 { P_XO, 0 },
80 { P_GPLL0, 1 },
81 { P_GPLL0_EARLY_DIV, 6 }
82};
83
84static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
85 "xo",
86 "gpll0",
87 "gpll0_early_div"
88};
89
90static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
91 { P_XO, 0 },
92 { P_GPLL0, 1 },
93 { P_GPLL4, 5 }
94};
95
96static const char * const gcc_xo_gpll0_gpll4[] = {
97 "xo",
98 "gpll0",
99 "gpll4"
100};
101
102static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
103 { P_XO, 0 },
104 { P_GPLL0, 1 },
105 { P_AUD_REF_CLK, 2 }
106};
107
108static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
109 "xo",
110 "gpll0",
111 "aud_ref_clk"
112};
113
114static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
115 { P_XO, 0 },
116 { P_GPLL0, 1 },
117 { P_SLEEP_CLK, 5 },
118 { P_GPLL0_EARLY_DIV, 6 }
119};
120
121static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
122 "xo",
123 "gpll0",
124 "sleep_clk",
125 "gpll0_early_div"
126};
127
128static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
129 { P_XO, 0 },
130 { P_GPLL0, 1 },
131 { P_GPLL4, 5 },
132 { P_GPLL0_EARLY_DIV, 6 }
133};
134
135static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
136 "xo",
137 "gpll0",
138 "gpll4",
139 "gpll0_early_div"
140};
141
142static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div_map[] = {
143 { P_XO, 0 },
144 { P_GPLL0, 1 },
145 { P_GPLL2, 2 },
146 { P_GPLL3, 3 },
147 { P_GPLL0_EARLY_DIV, 6 }
148};
149
150static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div[] = {
151 "xo",
152 "gpll0",
153 "gpll2",
154 "gpll3",
155 "gpll0_early_div"
156};
157
158static const struct parent_map gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map[] = {
159 { P_XO, 0 },
160 { P_GPLL0, 1 },
161 { P_GPLL1_EARLY_DIV, 3 },
162 { P_GPLL1, 4 },
163 { P_GPLL4, 5 },
164 { P_GPLL0_EARLY_DIV, 6 }
165};
166
167static const char * const gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div[] = {
168 "xo",
169 "gpll0",
170 "gpll1_early_div",
171 "gpll1",
172 "gpll4",
173 "gpll0_early_div"
174};
175
176static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map[] = {
177 { P_XO, 0 },
178 { P_GPLL0, 1 },
179 { P_GPLL2, 2 },
180 { P_GPLL3, 3 },
181 { P_GPLL1, 4 },
182 { P_GPLL2_EARLY, 5 },
183 { P_GPLL0_EARLY_DIV, 6 }
184};
185
186static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div[] = {
187 "xo",
188 "gpll0",
189 "gpll2",
190 "gpll3",
191 "gpll1",
192 "gpll2_early",
193 "gpll0_early_div"
194};
195
196static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div_map[] = {
197 { P_XO, 0 },
198 { P_GPLL0, 1 },
199 { P_GPLL2, 2 },
200 { P_GPLL3, 3 },
201 { P_GPLL1, 4 },
202 { P_GPLL4, 5 },
203 { P_GPLL0_EARLY_DIV, 6 }
204};
205
206static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div[] = {
207 "xo",
208 "gpll0",
209 "gpll2",
210 "gpll3",
211 "gpll1",
212 "gpll4",
213 "gpll0_early_div"
214};
215
216static struct clk_fixed_factor xo = {
217 .mult = 1,
218 .div = 1,
219 .hw.init = &(struct clk_init_data){
220 .name = "xo",
221 .parent_names = (const char *[]){ "xo_board" },
222 .num_parents = 1,
223 .ops = &clk_fixed_factor_ops,
224 },
225};
226
227static struct clk_alpha_pll gpll0_early = {
228 .offset = 0x00000,
229 .clkr = {
230 .enable_reg = 0x52000,
231 .enable_mask = BIT(0),
232 .hw.init = &(struct clk_init_data){
233 .name = "gpll0_early",
234 .parent_names = (const char *[]){ "xo" },
235 .num_parents = 1,
236 .ops = &clk_alpha_pll_ops,
237 },
238 },
239};
240
241static struct clk_fixed_factor gpll0_early_div = {
242 .mult = 1,
243 .div = 2,
244 .hw.init = &(struct clk_init_data){
245 .name = "gpll0_early_div",
246 .parent_names = (const char *[]){ "gpll0_early" },
247 .num_parents = 1,
248 .ops = &clk_fixed_factor_ops,
249 },
250};
251
252static struct clk_alpha_pll_postdiv gpll0 = {
253 .offset = 0x00000,
254 .clkr.hw.init = &(struct clk_init_data){
255 .name = "gpll0",
256 .parent_names = (const char *[]){ "gpll0_early" },
257 .num_parents = 1,
258 .ops = &clk_alpha_pll_postdiv_ops,
259 },
260};
261
262static struct clk_alpha_pll gpll4_early = {
263 .offset = 0x77000,
264 .clkr = {
265 .enable_reg = 0x52000,
266 .enable_mask = BIT(4),
267 .hw.init = &(struct clk_init_data){
268 .name = "gpll4_early",
269 .parent_names = (const char *[]){ "xo" },
270 .num_parents = 1,
271 .ops = &clk_alpha_pll_ops,
272 },
273 },
274};
275
276static struct clk_alpha_pll_postdiv gpll4 = {
277 .offset = 0x77000,
278 .clkr.hw.init = &(struct clk_init_data){
279 .name = "gpll4",
280 .parent_names = (const char *[]){ "gpll4_early" },
281 .num_parents = 1,
282 .ops = &clk_alpha_pll_postdiv_ops,
283 },
284};
285
286static const struct freq_tbl ftbl_system_noc_clk_src[] = {
287 F(19200000, P_XO, 1, 0, 0),
288 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
289 F(100000000, P_GPLL0, 6, 0, 0),
290 F(150000000, P_GPLL0, 4, 0, 0),
291 F(200000000, P_GPLL0, 3, 0, 0),
292 F(240000000, P_GPLL0, 2.5, 0, 0),
293 { }
294};
295
296static struct clk_rcg2 system_noc_clk_src = {
297 .cmd_rcgr = 0x0401c,
298 .hid_width = 5,
299 .parent_map = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map,
300 .freq_tbl = ftbl_system_noc_clk_src,
301 .clkr.hw.init = &(struct clk_init_data){
302 .name = "system_noc_clk_src",
303 .parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div,
304 .num_parents = 7,
305 .ops = &clk_rcg2_ops,
306 },
307};
308
309static const struct freq_tbl ftbl_config_noc_clk_src[] = {
310 F(19200000, P_XO, 1, 0, 0),
311 F(37500000, P_GPLL0, 16, 0, 0),
312 F(75000000, P_GPLL0, 8, 0, 0),
313 { }
314};
315
316static struct clk_rcg2 config_noc_clk_src = {
317 .cmd_rcgr = 0x0500c,
318 .hid_width = 5,
319 .parent_map = gcc_xo_gpll0_map,
320 .freq_tbl = ftbl_config_noc_clk_src,
321 .clkr.hw.init = &(struct clk_init_data){
322 .name = "config_noc_clk_src",
323 .parent_names = gcc_xo_gpll0,
324 .num_parents = 2,
325 .ops = &clk_rcg2_ops,
326 },
327};
328
329static const struct freq_tbl ftbl_periph_noc_clk_src[] = {
330 F(19200000, P_XO, 1, 0, 0),
331 F(37500000, P_GPLL0, 16, 0, 0),
332 F(50000000, P_GPLL0, 12, 0, 0),
333 F(75000000, P_GPLL0, 8, 0, 0),
334 F(100000000, P_GPLL0, 6, 0, 0),
335 { }
336};
337
338static struct clk_rcg2 periph_noc_clk_src = {
339 .cmd_rcgr = 0x06014,
340 .hid_width = 5,
341 .parent_map = gcc_xo_gpll0_map,
342 .freq_tbl = ftbl_periph_noc_clk_src,
343 .clkr.hw.init = &(struct clk_init_data){
344 .name = "periph_noc_clk_src",
345 .parent_names = gcc_xo_gpll0,
346 .num_parents = 2,
347 .ops = &clk_rcg2_ops,
348 },
349};
350
351static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
352 F(19200000, P_XO, 1, 0, 0),
353 F(120000000, P_GPLL0, 5, 0, 0),
354 F(150000000, P_GPLL0, 4, 0, 0),
355 { }
356};
357
358static struct clk_rcg2 usb30_master_clk_src = {
359 .cmd_rcgr = 0x0f014,
360 .mnd_width = 8,
361 .hid_width = 5,
362 .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
363 .freq_tbl = ftbl_usb30_master_clk_src,
364 .clkr.hw.init = &(struct clk_init_data){
365 .name = "usb30_master_clk_src",
366 .parent_names = gcc_xo_gpll0_gpll0_early_div,
367 .num_parents = 3,
368 .ops = &clk_rcg2_ops,
369 },
370};
371
372static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
373 F(19200000, P_XO, 1, 0, 0),
374 { }
375};
376
377static struct clk_rcg2 usb30_mock_utmi_clk_src = {
378 .cmd_rcgr = 0x0f028,
379 .hid_width = 5,
380 .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
381 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
382 .clkr.hw.init = &(struct clk_init_data){
383 .name = "usb30_mock_utmi_clk_src",
384 .parent_names = gcc_xo_gpll0_gpll0_early_div,
385 .num_parents = 3,
386 .ops = &clk_rcg2_ops,
387 },
388};
389
390static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
391 F(1200000, P_XO, 16, 0, 0),
392 { }
393};
394
395static struct clk_rcg2 usb3_phy_aux_clk_src = {
396 .cmd_rcgr = 0x5000c,
397 .hid_width = 5,
398 .parent_map = gcc_xo_sleep_clk_map,
399 .freq_tbl = ftbl_usb3_phy_aux_clk_src,
400 .clkr.hw.init = &(struct clk_init_data){
401 .name = "usb3_phy_aux_clk_src",
402 .parent_names = gcc_xo_sleep_clk,
403 .num_parents = 2,
404 .ops = &clk_rcg2_ops,
405 },
406};
407
408static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
409 F(120000000, P_GPLL0, 5, 0, 0),
410 { }
411};
412
413static struct clk_rcg2 usb20_master_clk_src = {
414 .cmd_rcgr = 0x12010,
415 .mnd_width = 8,
416 .hid_width = 5,
417 .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
418 .freq_tbl = ftbl_usb20_master_clk_src,
419 .clkr.hw.init = &(struct clk_init_data){
420 .name = "usb20_master_clk_src",
421 .parent_names = gcc_xo_gpll0_gpll0_early_div,
422 .num_parents = 3,
423 .ops = &clk_rcg2_ops,
424 },
425};
426
427static struct clk_rcg2 usb20_mock_utmi_clk_src = {
428 .cmd_rcgr = 0x12024,
429 .hid_width = 5,
430 .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
431 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
432 .clkr.hw.init = &(struct clk_init_data){
433 .name = "usb20_mock_utmi_clk_src",
434 .parent_names = gcc_xo_gpll0_gpll0_early_div,
435 .num_parents = 3,
436 .ops = &clk_rcg2_ops,
437 },
438};
439
440static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
441 F(144000, P_XO, 16, 3, 25),
442 F(400000, P_XO, 12, 1, 4),
443 F(20000000, P_GPLL0, 15, 1, 2),
444 F(25000000, P_GPLL0, 12, 1, 2),
445 F(50000000, P_GPLL0, 12, 0, 0),
446 F(96000000, P_GPLL4, 4, 0, 0),
447 F(192000000, P_GPLL4, 2, 0, 0),
448 F(384000000, P_GPLL4, 1, 0, 0),
449 { }
450};
451
452static struct clk_rcg2 sdcc1_apps_clk_src = {
453 .cmd_rcgr = 0x13010,
454 .mnd_width = 8,
455 .hid_width = 5,
456 .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
457 .freq_tbl = ftbl_sdcc1_apps_clk_src,
458 .clkr.hw.init = &(struct clk_init_data){
459 .name = "sdcc1_apps_clk_src",
460 .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
461 .num_parents = 4,
462 .ops = &clk_rcg2_ops,
463 },
464};
465
466static struct clk_rcg2 sdcc1_ice_core_clk_src = {
467 .cmd_rcgr = 0x13024,
468 .hid_width = 5,
469 .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
470 .clkr.hw.init = &(struct clk_init_data){
471 .name = "sdcc1_ice_core_clk_src",
472 .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
473 .num_parents = 4,
474 .ops = &clk_rcg2_ops,
475 },
476};
477
478static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
479 F(144000, P_XO, 16, 3, 25),
480 F(400000, P_XO, 12, 1, 4),
481 F(20000000, P_GPLL0, 15, 1, 2),
482 F(25000000, P_GPLL0, 12, 1, 2),
483 F(50000000, P_GPLL0, 12, 0, 0),
484 F(100000000, P_GPLL0, 6, 0, 0),
485 F(200000000, P_GPLL0, 3, 0, 0),
486 { }
487};
488
489static struct clk_rcg2 sdcc2_apps_clk_src = {
490 .cmd_rcgr = 0x14010,
491 .mnd_width = 8,
492 .hid_width = 5,
493 .parent_map = gcc_xo_gpll0_gpll4_map,
494 .freq_tbl = ftbl_sdcc2_apps_clk_src,
495 .clkr.hw.init = &(struct clk_init_data){
496 .name = "sdcc2_apps_clk_src",
497 .parent_names = gcc_xo_gpll0_gpll4,
498 .num_parents = 3,
499 .ops = &clk_rcg2_ops,
500 },
501};
502
503static struct clk_rcg2 sdcc3_apps_clk_src = {
504 .cmd_rcgr = 0x15010,
505 .mnd_width = 8,
506 .hid_width = 5,
507 .parent_map = gcc_xo_gpll0_gpll4_map,
508 .freq_tbl = ftbl_sdcc2_apps_clk_src,
509 .clkr.hw.init = &(struct clk_init_data){
510 .name = "sdcc3_apps_clk_src",
511 .parent_names = gcc_xo_gpll0_gpll4,
512 .num_parents = 3,
513 .ops = &clk_rcg2_ops,
514 },
515};
516
517static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
518 F(144000, P_XO, 16, 3, 25),
519 F(400000, P_XO, 12, 1, 4),
520 F(20000000, P_GPLL0, 15, 1, 2),
521 F(25000000, P_GPLL0, 12, 1, 2),
522 F(50000000, P_GPLL0, 12, 0, 0),
523 F(100000000, P_GPLL0, 6, 0, 0),
524 { }
525};
526
527static struct clk_rcg2 sdcc4_apps_clk_src = {
528 .cmd_rcgr = 0x16010,
529 .mnd_width = 8,
530 .hid_width = 5,
531 .parent_map = gcc_xo_gpll0_map,
532 .freq_tbl = ftbl_sdcc4_apps_clk_src,
533 .clkr.hw.init = &(struct clk_init_data){
534 .name = "sdcc4_apps_clk_src",
535 .parent_names = gcc_xo_gpll0,
536 .num_parents = 2,
537 .ops = &clk_rcg2_ops,
538 },
539};
540
541static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
542 F(960000, P_XO, 10, 1, 2),
543 F(4800000, P_XO, 4, 0, 0),
544 F(9600000, P_XO, 2, 0, 0),
545 F(15000000, P_GPLL0, 10, 1, 4),
546 F(19200000, P_XO, 1, 0, 0),
547 F(25000000, P_GPLL0, 12, 1, 2),
548 F(50000000, P_GPLL0, 12, 0, 0),
549 { }
550};
551
552static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
553 .cmd_rcgr = 0x1900c,
554 .mnd_width = 8,
555 .hid_width = 5,
556 .parent_map = gcc_xo_gpll0_map,
557 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
558 .clkr.hw.init = &(struct clk_init_data){
559 .name = "blsp1_qup1_spi_apps_clk_src",
560 .parent_names = gcc_xo_gpll0,
561 .num_parents = 2,
562 .ops = &clk_rcg2_ops,
563 },
564};
565
566static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
567 F(19200000, P_XO, 1, 0, 0),
568 F(50000000, P_GPLL0, 12, 0, 0),
569 { }
570};
571
572static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
573 .cmd_rcgr = 0x19020,
574 .hid_width = 5,
575 .parent_map = gcc_xo_gpll0_map,
576 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
577 .clkr.hw.init = &(struct clk_init_data){
578 .name = "blsp1_qup1_i2c_apps_clk_src",
579 .parent_names = gcc_xo_gpll0,
580 .num_parents = 2,
581 .ops = &clk_rcg2_ops,
582 },
583};
584
585static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
586 F(3686400, P_GPLL0, 1, 96, 15625),
587 F(7372800, P_GPLL0, 1, 192, 15625),
588 F(14745600, P_GPLL0, 1, 384, 15625),
589 F(16000000, P_GPLL0, 5, 2, 15),
590 F(19200000, P_XO, 1, 0, 0),
591 F(24000000, P_GPLL0, 5, 1, 5),
592 F(32000000, P_GPLL0, 1, 4, 75),
593 F(40000000, P_GPLL0, 15, 0, 0),
594 F(46400000, P_GPLL0, 1, 29, 375),
595 F(48000000, P_GPLL0, 12.5, 0, 0),
596 F(51200000, P_GPLL0, 1, 32, 375),
597 F(56000000, P_GPLL0, 1, 7, 75),
598 F(58982400, P_GPLL0, 1, 1536, 15625),
599 F(60000000, P_GPLL0, 10, 0, 0),
600 F(63157895, P_GPLL0, 9.5, 0, 0),
601 { }
602};
603
604static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
605 .cmd_rcgr = 0x1a00c,
606 .mnd_width = 16,
607 .hid_width = 5,
608 .parent_map = gcc_xo_gpll0_map,
609 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
610 .clkr.hw.init = &(struct clk_init_data){
611 .name = "blsp1_uart1_apps_clk_src",
612 .parent_names = gcc_xo_gpll0,
613 .num_parents = 2,
614 .ops = &clk_rcg2_ops,
615 },
616};
617
618static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
619 .cmd_rcgr = 0x1b00c,
620 .mnd_width = 8,
621 .hid_width = 5,
622 .parent_map = gcc_xo_gpll0_map,
623 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
624 .clkr.hw.init = &(struct clk_init_data){
625 .name = "blsp1_qup2_spi_apps_clk_src",
626 .parent_names = gcc_xo_gpll0,
627 .num_parents = 2,
628 .ops = &clk_rcg2_ops,
629 },
630};
631
632static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
633 .cmd_rcgr = 0x1b020,
634 .hid_width = 5,
635 .parent_map = gcc_xo_gpll0_map,
636 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
637 .clkr.hw.init = &(struct clk_init_data){
638 .name = "blsp1_qup2_i2c_apps_clk_src",
639 .parent_names = gcc_xo_gpll0,
640 .num_parents = 2,
641 .ops = &clk_rcg2_ops,
642 },
643};
644
645static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
646 .cmd_rcgr = 0x1c00c,
647 .mnd_width = 16,
648 .hid_width = 5,
649 .parent_map = gcc_xo_gpll0_map,
650 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
651 .clkr.hw.init = &(struct clk_init_data){
652 .name = "blsp1_uart2_apps_clk_src",
653 .parent_names = gcc_xo_gpll0,
654 .num_parents = 2,
655 .ops = &clk_rcg2_ops,
656 },
657};
658
659static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
660 .cmd_rcgr = 0x1d00c,
661 .mnd_width = 8,
662 .hid_width = 5,
663 .parent_map = gcc_xo_gpll0_map,
664 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
665 .clkr.hw.init = &(struct clk_init_data){
666 .name = "blsp1_qup3_spi_apps_clk_src",
667 .parent_names = gcc_xo_gpll0,
668 .num_parents = 2,
669 .ops = &clk_rcg2_ops,
670 },
671};
672
673static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
674 .cmd_rcgr = 0x1d020,
675 .hid_width = 5,
676 .parent_map = gcc_xo_gpll0_map,
677 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
678 .clkr.hw.init = &(struct clk_init_data){
679 .name = "blsp1_qup3_i2c_apps_clk_src",
680 .parent_names = gcc_xo_gpll0,
681 .num_parents = 2,
682 .ops = &clk_rcg2_ops,
683 },
684};
685
686static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
687 .cmd_rcgr = 0x1e00c,
688 .mnd_width = 16,
689 .hid_width = 5,
690 .parent_map = gcc_xo_gpll0_map,
691 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
692 .clkr.hw.init = &(struct clk_init_data){
693 .name = "blsp1_uart3_apps_clk_src",
694 .parent_names = gcc_xo_gpll0,
695 .num_parents = 2,
696 .ops = &clk_rcg2_ops,
697 },
698};
699
700static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
701 .cmd_rcgr = 0x1f00c,
702 .mnd_width = 8,
703 .hid_width = 5,
704 .parent_map = gcc_xo_gpll0_map,
705 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
706 .clkr.hw.init = &(struct clk_init_data){
707 .name = "blsp1_qup4_spi_apps_clk_src",
708 .parent_names = gcc_xo_gpll0,
709 .num_parents = 2,
710 .ops = &clk_rcg2_ops,
711 },
712};
713
714static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
715 .cmd_rcgr = 0x1f020,
716 .hid_width = 5,
717 .parent_map = gcc_xo_gpll0_map,
718 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
719 .clkr.hw.init = &(struct clk_init_data){
720 .name = "blsp1_qup4_i2c_apps_clk_src",
721 .parent_names = gcc_xo_gpll0,
722 .num_parents = 2,
723 .ops = &clk_rcg2_ops,
724 },
725};
726
727static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
728 .cmd_rcgr = 0x2000c,
729 .mnd_width = 16,
730 .hid_width = 5,
731 .parent_map = gcc_xo_gpll0_map,
732 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
733 .clkr.hw.init = &(struct clk_init_data){
734 .name = "blsp1_uart4_apps_clk_src",
735 .parent_names = gcc_xo_gpll0,
736 .num_parents = 2,
737 .ops = &clk_rcg2_ops,
738 },
739};
740
741static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
742 .cmd_rcgr = 0x2100c,
743 .mnd_width = 8,
744 .hid_width = 5,
745 .parent_map = gcc_xo_gpll0_map,
746 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
747 .clkr.hw.init = &(struct clk_init_data){
748 .name = "blsp1_qup5_spi_apps_clk_src",
749 .parent_names = gcc_xo_gpll0,
750 .num_parents = 2,
751 .ops = &clk_rcg2_ops,
752 },
753};
754
755static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
756 .cmd_rcgr = 0x21020,
757 .hid_width = 5,
758 .parent_map = gcc_xo_gpll0_map,
759 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
760 .clkr.hw.init = &(struct clk_init_data){
761 .name = "blsp1_qup5_i2c_apps_clk_src",
762 .parent_names = gcc_xo_gpll0,
763 .num_parents = 2,
764 .ops = &clk_rcg2_ops,
765 },
766};
767
768static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
769 .cmd_rcgr = 0x2200c,
770 .mnd_width = 16,
771 .hid_width = 5,
772 .parent_map = gcc_xo_gpll0_map,
773 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
774 .clkr.hw.init = &(struct clk_init_data){
775 .name = "blsp1_uart5_apps_clk_src",
776 .parent_names = gcc_xo_gpll0,
777 .num_parents = 2,
778 .ops = &clk_rcg2_ops,
779 },
780};
781
782static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
783 .cmd_rcgr = 0x2300c,
784 .mnd_width = 8,
785 .hid_width = 5,
786 .parent_map = gcc_xo_gpll0_map,
787 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
788 .clkr.hw.init = &(struct clk_init_data){
789 .name = "blsp1_qup6_spi_apps_clk_src",
790 .parent_names = gcc_xo_gpll0,
791 .num_parents = 2,
792 .ops = &clk_rcg2_ops,
793 },
794};
795
796static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
797 .cmd_rcgr = 0x23020,
798 .hid_width = 5,
799 .parent_map = gcc_xo_gpll0_map,
800 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
801 .clkr.hw.init = &(struct clk_init_data){
802 .name = "blsp1_qup6_i2c_apps_clk_src",
803 .parent_names = gcc_xo_gpll0,
804 .num_parents = 2,
805 .ops = &clk_rcg2_ops,
806 },
807};
808
809static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
810 .cmd_rcgr = 0x2400c,
811 .mnd_width = 16,
812 .hid_width = 5,
813 .parent_map = gcc_xo_gpll0_map,
814 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
815 .clkr.hw.init = &(struct clk_init_data){
816 .name = "blsp1_uart6_apps_clk_src",
817 .parent_names = gcc_xo_gpll0,
818 .num_parents = 2,
819 .ops = &clk_rcg2_ops,
820 },
821};
822
823static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
824 .cmd_rcgr = 0x2600c,
825 .mnd_width = 8,
826 .hid_width = 5,
827 .parent_map = gcc_xo_gpll0_map,
828 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
829 .clkr.hw.init = &(struct clk_init_data){
830 .name = "blsp2_qup1_spi_apps_clk_src",
831 .parent_names = gcc_xo_gpll0,
832 .num_parents = 2,
833 .ops = &clk_rcg2_ops,
834 },
835};
836
837static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
838 .cmd_rcgr = 0x26020,
839 .hid_width = 5,
840 .parent_map = gcc_xo_gpll0_map,
841 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
842 .clkr.hw.init = &(struct clk_init_data){
843 .name = "blsp2_qup1_i2c_apps_clk_src",
844 .parent_names = gcc_xo_gpll0,
845 .num_parents = 2,
846 .ops = &clk_rcg2_ops,
847 },
848};
849
850static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
851 .cmd_rcgr = 0x2700c,
852 .mnd_width = 16,
853 .hid_width = 5,
854 .parent_map = gcc_xo_gpll0_map,
855 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
856 .clkr.hw.init = &(struct clk_init_data){
857 .name = "blsp2_uart1_apps_clk_src",
858 .parent_names = gcc_xo_gpll0,
859 .num_parents = 2,
860 .ops = &clk_rcg2_ops,
861 },
862};
863
864static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
865 .cmd_rcgr = 0x2800c,
866 .mnd_width = 8,
867 .hid_width = 5,
868 .parent_map = gcc_xo_gpll0_map,
869 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
870 .clkr.hw.init = &(struct clk_init_data){
871 .name = "blsp2_qup2_spi_apps_clk_src",
872 .parent_names = gcc_xo_gpll0,
873 .num_parents = 2,
874 .ops = &clk_rcg2_ops,
875 },
876};
877
878static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
879 .cmd_rcgr = 0x28020,
880 .hid_width = 5,
881 .parent_map = gcc_xo_gpll0_map,
882 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
883 .clkr.hw.init = &(struct clk_init_data){
884 .name = "blsp2_qup2_i2c_apps_clk_src",
885 .parent_names = gcc_xo_gpll0,
886 .num_parents = 2,
887 .ops = &clk_rcg2_ops,
888 },
889};
890
891static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
892 .cmd_rcgr = 0x2900c,
893 .mnd_width = 16,
894 .hid_width = 5,
895 .parent_map = gcc_xo_gpll0_map,
896 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
897 .clkr.hw.init = &(struct clk_init_data){
898 .name = "blsp2_uart2_apps_clk_src",
899 .parent_names = gcc_xo_gpll0,
900 .num_parents = 2,
901 .ops = &clk_rcg2_ops,
902 },
903};
904
905static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
906 .cmd_rcgr = 0x2a00c,
907 .mnd_width = 8,
908 .hid_width = 5,
909 .parent_map = gcc_xo_gpll0_map,
910 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
911 .clkr.hw.init = &(struct clk_init_data){
912 .name = "blsp2_qup3_spi_apps_clk_src",
913 .parent_names = gcc_xo_gpll0,
914 .num_parents = 2,
915 .ops = &clk_rcg2_ops,
916 },
917};
918
919static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
920 .cmd_rcgr = 0x2a020,
921 .hid_width = 5,
922 .parent_map = gcc_xo_gpll0_map,
923 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
924 .clkr.hw.init = &(struct clk_init_data){
925 .name = "blsp2_qup3_i2c_apps_clk_src",
926 .parent_names = gcc_xo_gpll0,
927 .num_parents = 2,
928 .ops = &clk_rcg2_ops,
929 },
930};
931
932static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
933 .cmd_rcgr = 0x2b00c,
934 .mnd_width = 16,
935 .hid_width = 5,
936 .parent_map = gcc_xo_gpll0_map,
937 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
938 .clkr.hw.init = &(struct clk_init_data){
939 .name = "blsp2_uart3_apps_clk_src",
940 .parent_names = gcc_xo_gpll0,
941 .num_parents = 2,
942 .ops = &clk_rcg2_ops,
943 },
944};
945
946static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
947 .cmd_rcgr = 0x2c00c,
948 .mnd_width = 8,
949 .hid_width = 5,
950 .parent_map = gcc_xo_gpll0_map,
951 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
952 .clkr.hw.init = &(struct clk_init_data){
953 .name = "blsp2_qup4_spi_apps_clk_src",
954 .parent_names = gcc_xo_gpll0,
955 .num_parents = 2,
956 .ops = &clk_rcg2_ops,
957 },
958};
959
960static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
961 .cmd_rcgr = 0x2c020,
962 .hid_width = 5,
963 .parent_map = gcc_xo_gpll0_map,
964 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
965 .clkr.hw.init = &(struct clk_init_data){
966 .name = "blsp2_qup4_i2c_apps_clk_src",
967 .parent_names = gcc_xo_gpll0,
968 .num_parents = 2,
969 .ops = &clk_rcg2_ops,
970 },
971};
972
973static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
974 .cmd_rcgr = 0x2d00c,
975 .mnd_width = 16,
976 .hid_width = 5,
977 .parent_map = gcc_xo_gpll0_map,
978 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
979 .clkr.hw.init = &(struct clk_init_data){
980 .name = "blsp2_uart4_apps_clk_src",
981 .parent_names = gcc_xo_gpll0,
982 .num_parents = 2,
983 .ops = &clk_rcg2_ops,
984 },
985};
986
987static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
988 .cmd_rcgr = 0x2e00c,
989 .mnd_width = 8,
990 .hid_width = 5,
991 .parent_map = gcc_xo_gpll0_map,
992 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
993 .clkr.hw.init = &(struct clk_init_data){
994 .name = "blsp2_qup5_spi_apps_clk_src",
995 .parent_names = gcc_xo_gpll0,
996 .num_parents = 2,
997 .ops = &clk_rcg2_ops,
998 },
999};
1000
1001static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
1002 .cmd_rcgr = 0x2e020,
1003 .hid_width = 5,
1004 .parent_map = gcc_xo_gpll0_map,
1005 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
1006 .clkr.hw.init = &(struct clk_init_data){
1007 .name = "blsp2_qup5_i2c_apps_clk_src",
1008 .parent_names = gcc_xo_gpll0,
1009 .num_parents = 2,
1010 .ops = &clk_rcg2_ops,
1011 },
1012};
1013
1014static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
1015 .cmd_rcgr = 0x2f00c,
1016 .mnd_width = 16,
1017 .hid_width = 5,
1018 .parent_map = gcc_xo_gpll0_map,
1019 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
1020 .clkr.hw.init = &(struct clk_init_data){
1021 .name = "blsp2_uart5_apps_clk_src",
1022 .parent_names = gcc_xo_gpll0,
1023 .num_parents = 2,
1024 .ops = &clk_rcg2_ops,
1025 },
1026};
1027
1028static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
1029 .cmd_rcgr = 0x3000c,
1030 .mnd_width = 8,
1031 .hid_width = 5,
1032 .parent_map = gcc_xo_gpll0_map,
1033 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
1034 .clkr.hw.init = &(struct clk_init_data){
1035 .name = "blsp2_qup6_spi_apps_clk_src",
1036 .parent_names = gcc_xo_gpll0,
1037 .num_parents = 2,
1038 .ops = &clk_rcg2_ops,
1039 },
1040};
1041
1042static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
1043 .cmd_rcgr = 0x30020,
1044 .hid_width = 5,
1045 .parent_map = gcc_xo_gpll0_map,
1046 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
1047 .clkr.hw.init = &(struct clk_init_data){
1048 .name = "blsp2_qup6_i2c_apps_clk_src",
1049 .parent_names = gcc_xo_gpll0,
1050 .num_parents = 2,
1051 .ops = &clk_rcg2_ops,
1052 },
1053};
1054
1055static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
1056 .cmd_rcgr = 0x3100c,
1057 .mnd_width = 16,
1058 .hid_width = 5,
1059 .parent_map = gcc_xo_gpll0_map,
1060 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
1061 .clkr.hw.init = &(struct clk_init_data){
1062 .name = "blsp2_uart6_apps_clk_src",
1063 .parent_names = gcc_xo_gpll0,
1064 .num_parents = 2,
1065 .ops = &clk_rcg2_ops,
1066 },
1067};
1068
1069static const struct freq_tbl ftbl_pdm2_clk_src[] = {
1070 F(60000000, P_GPLL0, 10, 0, 0),
1071 { }
1072};
1073
1074static struct clk_rcg2 pdm2_clk_src = {
1075 .cmd_rcgr = 0x33010,
1076 .hid_width = 5,
1077 .parent_map = gcc_xo_gpll0_map,
1078 .freq_tbl = ftbl_pdm2_clk_src,
1079 .clkr.hw.init = &(struct clk_init_data){
1080 .name = "pdm2_clk_src",
1081 .parent_names = gcc_xo_gpll0,
1082 .num_parents = 2,
1083 .ops = &clk_rcg2_ops,
1084 },
1085};
1086
1087static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
1088 F(105495, P_XO, 1, 1, 182),
1089 { }
1090};
1091
1092static struct clk_rcg2 tsif_ref_clk_src = {
1093 .cmd_rcgr = 0x36010,
1094 .mnd_width = 8,
1095 .hid_width = 5,
1096 .parent_map = gcc_xo_gpll0_aud_ref_clk_map,
1097 .freq_tbl = ftbl_tsif_ref_clk_src,
1098 .clkr.hw.init = &(struct clk_init_data){
1099 .name = "tsif_ref_clk_src",
1100 .parent_names = gcc_xo_gpll0_aud_ref_clk,
1101 .num_parents = 3,
1102 .ops = &clk_rcg2_ops,
1103 },
1104};
1105
1106static struct clk_rcg2 gcc_sleep_clk_src = {
1107 .cmd_rcgr = 0x43014,
1108 .hid_width = 5,
1109 .parent_map = gcc_sleep_clk_map,
1110 .clkr.hw.init = &(struct clk_init_data){
1111 .name = "gcc_sleep_clk_src",
1112 .parent_names = gcc_sleep_clk,
1113 .num_parents = 1,
1114 .ops = &clk_rcg2_ops,
1115 },
1116};
1117
1118static struct clk_rcg2 hmss_rbcpr_clk_src = {
1119 .cmd_rcgr = 0x48040,
1120 .hid_width = 5,
1121 .parent_map = gcc_xo_gpll0_map,
1122 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1123 .clkr.hw.init = &(struct clk_init_data){
1124 .name = "hmss_rbcpr_clk_src",
1125 .parent_names = gcc_xo_gpll0,
1126 .num_parents = 2,
1127 .ops = &clk_rcg2_ops,
1128 },
1129};
1130
1131static struct clk_rcg2 hmss_gpll0_clk_src = {
1132 .cmd_rcgr = 0x48058,
1133 .hid_width = 5,
1134 .parent_map = gcc_xo_gpll0_map,
1135 .clkr.hw.init = &(struct clk_init_data){
1136 .name = "hmss_gpll0_clk_src",
1137 .parent_names = gcc_xo_gpll0,
1138 .num_parents = 2,
1139 .ops = &clk_rcg2_ops,
1140 },
1141};
1142
1143static const struct freq_tbl ftbl_gp1_clk_src[] = {
1144 F(19200000, P_XO, 1, 0, 0),
1145 F(100000000, P_GPLL0, 6, 0, 0),
1146 F(200000000, P_GPLL0, 3, 0, 0),
1147 { }
1148};
1149
1150static struct clk_rcg2 gp1_clk_src = {
1151 .cmd_rcgr = 0x64004,
1152 .mnd_width = 8,
1153 .hid_width = 5,
1154 .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1155 .freq_tbl = ftbl_gp1_clk_src,
1156 .clkr.hw.init = &(struct clk_init_data){
1157 .name = "gp1_clk_src",
1158 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1159 .num_parents = 4,
1160 .ops = &clk_rcg2_ops,
1161 },
1162};
1163
1164static struct clk_rcg2 gp2_clk_src = {
1165 .cmd_rcgr = 0x65004,
1166 .mnd_width = 8,
1167 .hid_width = 5,
1168 .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1169 .freq_tbl = ftbl_gp1_clk_src,
1170 .clkr.hw.init = &(struct clk_init_data){
1171 .name = "gp2_clk_src",
1172 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1173 .num_parents = 4,
1174 .ops = &clk_rcg2_ops,
1175 },
1176};
1177
1178static struct clk_rcg2 gp3_clk_src = {
1179 .cmd_rcgr = 0x66004,
1180 .mnd_width = 8,
1181 .hid_width = 5,
1182 .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1183 .freq_tbl = ftbl_gp1_clk_src,
1184 .clkr.hw.init = &(struct clk_init_data){
1185 .name = "gp3_clk_src",
1186 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1187 .num_parents = 4,
1188 .ops = &clk_rcg2_ops,
1189 },
1190};
1191
1192static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
1193 F(1010526, P_XO, 1, 1, 19),
1194 { }
1195};
1196
1197static struct clk_rcg2 pcie_aux_clk_src = {
1198 .cmd_rcgr = 0x6c000,
1199 .mnd_width = 16,
1200 .hid_width = 5,
1201 .parent_map = gcc_xo_sleep_clk_map,
1202 .freq_tbl = ftbl_pcie_aux_clk_src,
1203 .clkr.hw.init = &(struct clk_init_data){
1204 .name = "pcie_aux_clk_src",
1205 .parent_names = gcc_xo_sleep_clk,
1206 .num_parents = 2,
1207 .ops = &clk_rcg2_ops,
1208 },
1209};
1210
1211static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
1212 F(100000000, P_GPLL0, 6, 0, 0),
1213 F(200000000, P_GPLL0, 3, 0, 0),
1214 F(240000000, P_GPLL0, 2.5, 0, 0),
1215 { }
1216};
1217
1218static struct clk_rcg2 ufs_axi_clk_src = {
1219 .cmd_rcgr = 0x75024,
1220 .mnd_width = 8,
1221 .hid_width = 5,
1222 .parent_map = gcc_xo_gpll0_map,
1223 .freq_tbl = ftbl_ufs_axi_clk_src,
1224 .clkr.hw.init = &(struct clk_init_data){
1225 .name = "ufs_axi_clk_src",
1226 .parent_names = gcc_xo_gpll0,
1227 .num_parents = 2,
1228 .ops = &clk_rcg2_ops,
1229 },
1230};
1231
1232static struct clk_rcg2 ufs_ice_core_clk_src = {
1233 .cmd_rcgr = 0x76014,
1234 .hid_width = 5,
1235 .parent_map = gcc_xo_gpll0_map,
1236 .clkr.hw.init = &(struct clk_init_data){
1237 .name = "ufs_ice_core_clk_src",
1238 .parent_names = gcc_xo_gpll0,
1239 .num_parents = 2,
1240 .ops = &clk_rcg2_ops,
1241 },
1242};
1243
1244static struct clk_rcg2 qspi_ser_clk_src = {
1245 .cmd_rcgr = 0x8b00c,
1246 .hid_width = 5,
1247 .parent_map = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map,
1248 .clkr.hw.init = &(struct clk_init_data){
1249 .name = "qspi_ser_clk_src",
1250 .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,
1251 .num_parents = 6,
1252 .ops = &clk_rcg2_ops,
1253 },
1254};
1255
1256static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
1257 .halt_reg = 0x0f03c,
1258 .clkr = {
1259 .enable_reg = 0x0f03c,
1260 .enable_mask = BIT(0),
1261 .hw.init = &(struct clk_init_data){
1262 .name = "gcc_sys_noc_usb3_axi_clk",
1263 .parent_names = (const char *[]){ "usb30_master_clk_src" },
1264 .num_parents = 1,
1265 .flags = CLK_SET_RATE_PARENT,
1266 .ops = &clk_branch2_ops,
1267 },
1268 },
1269};
1270
1271static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
1272 .halt_reg = 0x75038,
1273 .clkr = {
1274 .enable_reg = 0x75038,
1275 .enable_mask = BIT(0),
1276 .hw.init = &(struct clk_init_data){
1277 .name = "gcc_sys_noc_ufs_axi_clk",
1278 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
1279 .num_parents = 1,
1280 .flags = CLK_SET_RATE_PARENT,
1281 .ops = &clk_branch2_ops,
1282 },
1283 },
1284};
1285
1286static struct clk_branch gcc_periph_noc_usb20_ahb_clk = {
1287 .halt_reg = 0x6010,
1288 .clkr = {
1289 .enable_reg = 0x6010,
1290 .enable_mask = BIT(0),
1291 .hw.init = &(struct clk_init_data){
1292 .name = "gcc_periph_noc_usb20_ahb_clk",
1293 .parent_names = (const char *[]){ "usb20_master_clk_src" },
1294 .num_parents = 1,
1295 .flags = CLK_SET_RATE_PARENT,
1296 .ops = &clk_branch2_ops,
1297 },
1298 },
1299};
1300
1301static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
1302 .halt_reg = 0x9008,
1303 .clkr = {
1304 .enable_reg = 0x9008,
1305 .enable_mask = BIT(0),
1306 .hw.init = &(struct clk_init_data){
1307 .name = "gcc_mmss_noc_cfg_ahb_clk",
1308 .parent_names = (const char *[]){ "config_noc_clk_src" },
1309 .num_parents = 1,
1310 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1311 .ops = &clk_branch2_ops,
1312 },
1313 },
1314};
1315
1316static struct clk_branch gcc_mmss_bimc_gfx_clk = {
1317 .halt_reg = 0x9010,
1318 .clkr = {
1319 .enable_reg = 0x9010,
1320 .enable_mask = BIT(0),
1321 .hw.init = &(struct clk_init_data){
1322 .name = "gcc_mmss_bimc_gfx_clk",
1323 .flags = CLK_SET_RATE_PARENT | CLK_IS_ROOT,
1324 .ops = &clk_branch2_ops,
1325 },
1326 },
1327};
1328
1329static struct clk_branch gcc_usb30_master_clk = {
1330 .halt_reg = 0x0f008,
1331 .clkr = {
1332 .enable_reg = 0x0f008,
1333 .enable_mask = BIT(0),
1334 .hw.init = &(struct clk_init_data){
1335 .name = "gcc_usb30_master_clk",
1336 .parent_names = (const char *[]){ "usb30_master_clk_src" },
1337 .num_parents = 1,
1338 .flags = CLK_SET_RATE_PARENT,
1339 .ops = &clk_branch2_ops,
1340 },
1341 },
1342};
1343
1344static struct clk_branch gcc_usb30_sleep_clk = {
1345 .halt_reg = 0x0f00c,
1346 .clkr = {
1347 .enable_reg = 0x0f00c,
1348 .enable_mask = BIT(0),
1349 .hw.init = &(struct clk_init_data){
1350 .name = "gcc_usb30_sleep_clk",
1351 .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1352 .num_parents = 1,
1353 .flags = CLK_SET_RATE_PARENT,
1354 .ops = &clk_branch2_ops,
1355 },
1356 },
1357};
1358
1359static struct clk_branch gcc_usb30_mock_utmi_clk = {
1360 .halt_reg = 0x0f010,
1361 .clkr = {
1362 .enable_reg = 0x0f010,
1363 .enable_mask = BIT(0),
1364 .hw.init = &(struct clk_init_data){
1365 .name = "gcc_usb30_mock_utmi_clk",
1366 .parent_names = (const char *[]){ "usb30_mock_utmi_clk_src" },
1367 .num_parents = 1,
1368 .flags = CLK_SET_RATE_PARENT,
1369 .ops = &clk_branch2_ops,
1370 },
1371 },
1372};
1373
1374static struct clk_branch gcc_usb3_phy_aux_clk = {
1375 .halt_reg = 0x50000,
1376 .clkr = {
1377 .enable_reg = 0x50000,
1378 .enable_mask = BIT(0),
1379 .hw.init = &(struct clk_init_data){
1380 .name = "gcc_usb3_phy_aux_clk",
1381 .parent_names = (const char *[]){ "usb3_phy_aux_clk_src" },
1382 .num_parents = 1,
1383 .flags = CLK_SET_RATE_PARENT,
1384 .ops = &clk_branch2_ops,
1385 },
1386 },
1387};
1388
1389static struct clk_branch gcc_usb3_phy_pipe_clk = {
1390 .halt_reg = 0x50004,
1391 .clkr = {
1392 .enable_reg = 0x50004,
1393 .enable_mask = BIT(0),
1394 .hw.init = &(struct clk_init_data){
1395 .name = "gcc_usb3_phy_pipe_clk",
1396 .parent_names = (const char *[]){ "usb3_phy_pipe_clk_src" },
1397 .num_parents = 1,
1398 .flags = CLK_SET_RATE_PARENT,
1399 .ops = &clk_branch2_ops,
1400 },
1401 },
1402};
1403
1404static struct clk_branch gcc_usb20_master_clk = {
1405 .halt_reg = 0x12004,
1406 .clkr = {
1407 .enable_reg = 0x12004,
1408 .enable_mask = BIT(0),
1409 .hw.init = &(struct clk_init_data){
1410 .name = "gcc_usb20_master_clk",
1411 .parent_names = (const char *[]){ "usb20_master_clk_src" },
1412 .num_parents = 1,
1413 .flags = CLK_SET_RATE_PARENT,
1414 .ops = &clk_branch2_ops,
1415 },
1416 },
1417};
1418
1419static struct clk_branch gcc_usb20_sleep_clk = {
1420 .halt_reg = 0x12008,
1421 .clkr = {
1422 .enable_reg = 0x12008,
1423 .enable_mask = BIT(0),
1424 .hw.init = &(struct clk_init_data){
1425 .name = "gcc_usb20_sleep_clk",
1426 .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1427 .num_parents = 1,
1428 .flags = CLK_SET_RATE_PARENT,
1429 .ops = &clk_branch2_ops,
1430 },
1431 },
1432};
1433
1434static struct clk_branch gcc_usb20_mock_utmi_clk = {
1435 .halt_reg = 0x1200c,
1436 .clkr = {
1437 .enable_reg = 0x1200c,
1438 .enable_mask = BIT(0),
1439 .hw.init = &(struct clk_init_data){
1440 .name = "gcc_usb20_mock_utmi_clk",
1441 .parent_names = (const char *[]){ "usb20_mock_utmi_clk_src" },
1442 .num_parents = 1,
1443 .flags = CLK_SET_RATE_PARENT,
1444 .ops = &clk_branch2_ops,
1445 },
1446 },
1447};
1448
1449static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
1450 .halt_reg = 0x6a004,
1451 .clkr = {
1452 .enable_reg = 0x6a004,
1453 .enable_mask = BIT(0),
1454 .hw.init = &(struct clk_init_data){
1455 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
1456 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1457 .num_parents = 1,
1458 .flags = CLK_SET_RATE_PARENT,
1459 .ops = &clk_branch2_ops,
1460 },
1461 },
1462};
1463
1464static struct clk_branch gcc_sdcc1_apps_clk = {
1465 .halt_reg = 0x13004,
1466 .clkr = {
1467 .enable_reg = 0x13004,
1468 .enable_mask = BIT(0),
1469 .hw.init = &(struct clk_init_data){
1470 .name = "gcc_sdcc1_apps_clk",
1471 .parent_names = (const char *[]){ "sdcc1_apps_clk_src" },
1472 .num_parents = 1,
1473 .flags = CLK_SET_RATE_PARENT,
1474 .ops = &clk_branch2_ops,
1475 },
1476 },
1477};
1478
1479static struct clk_branch gcc_sdcc1_ahb_clk = {
1480 .halt_reg = 0x13008,
1481 .clkr = {
1482 .enable_reg = 0x13008,
1483 .enable_mask = BIT(0),
1484 .hw.init = &(struct clk_init_data){
1485 .name = "gcc_sdcc1_ahb_clk",
1486 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1487 .num_parents = 1,
1488 .flags = CLK_SET_RATE_PARENT,
1489 .ops = &clk_branch2_ops,
1490 },
1491 },
1492};
1493
1494static struct clk_branch gcc_sdcc1_ice_core_clk = {
1495 .halt_reg = 0x13038,
1496 .clkr = {
1497 .enable_reg = 0x13038,
1498 .enable_mask = BIT(0),
1499 .hw.init = &(struct clk_init_data){
1500 .name = "gcc_sdcc1_ice_core_clk",
1501 .parent_names = (const char *[]){ "sdcc1_ice_core_clk_src" },
1502 .num_parents = 1,
1503 .flags = CLK_SET_RATE_PARENT,
1504 .ops = &clk_branch2_ops,
1505 },
1506 },
1507};
1508
1509static struct clk_branch gcc_sdcc2_apps_clk = {
1510 .halt_reg = 0x14004,
1511 .clkr = {
1512 .enable_reg = 0x14004,
1513 .enable_mask = BIT(0),
1514 .hw.init = &(struct clk_init_data){
1515 .name = "gcc_sdcc2_apps_clk",
1516 .parent_names = (const char *[]){ "sdcc2_apps_clk_src" },
1517 .num_parents = 1,
1518 .flags = CLK_SET_RATE_PARENT,
1519 .ops = &clk_branch2_ops,
1520 },
1521 },
1522};
1523
1524static struct clk_branch gcc_sdcc2_ahb_clk = {
1525 .halt_reg = 0x14008,
1526 .clkr = {
1527 .enable_reg = 0x14008,
1528 .enable_mask = BIT(0),
1529 .hw.init = &(struct clk_init_data){
1530 .name = "gcc_sdcc2_ahb_clk",
1531 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1532 .num_parents = 1,
1533 .flags = CLK_SET_RATE_PARENT,
1534 .ops = &clk_branch2_ops,
1535 },
1536 },
1537};
1538
1539static struct clk_branch gcc_sdcc3_apps_clk = {
1540 .halt_reg = 0x15004,
1541 .clkr = {
1542 .enable_reg = 0x15004,
1543 .enable_mask = BIT(0),
1544 .hw.init = &(struct clk_init_data){
1545 .name = "gcc_sdcc3_apps_clk",
1546 .parent_names = (const char *[]){ "sdcc3_apps_clk_src" },
1547 .num_parents = 1,
1548 .flags = CLK_SET_RATE_PARENT,
1549 .ops = &clk_branch2_ops,
1550 },
1551 },
1552};
1553
1554static struct clk_branch gcc_sdcc3_ahb_clk = {
1555 .halt_reg = 0x15008,
1556 .clkr = {
1557 .enable_reg = 0x15008,
1558 .enable_mask = BIT(0),
1559 .hw.init = &(struct clk_init_data){
1560 .name = "gcc_sdcc3_ahb_clk",
1561 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1562 .num_parents = 1,
1563 .flags = CLK_SET_RATE_PARENT,
1564 .ops = &clk_branch2_ops,
1565 },
1566 },
1567};
1568
1569static struct clk_branch gcc_sdcc4_apps_clk = {
1570 .halt_reg = 0x16004,
1571 .clkr = {
1572 .enable_reg = 0x16004,
1573 .enable_mask = BIT(0),
1574 .hw.init = &(struct clk_init_data){
1575 .name = "gcc_sdcc4_apps_clk",
1576 .parent_names = (const char *[]){ "sdcc4_apps_clk_src" },
1577 .num_parents = 1,
1578 .flags = CLK_SET_RATE_PARENT,
1579 .ops = &clk_branch2_ops,
1580 },
1581 },
1582};
1583
1584static struct clk_branch gcc_sdcc4_ahb_clk = {
1585 .halt_reg = 0x16008,
1586 .clkr = {
1587 .enable_reg = 0x16008,
1588 .enable_mask = BIT(0),
1589 .hw.init = &(struct clk_init_data){
1590 .name = "gcc_sdcc4_ahb_clk",
1591 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1592 .num_parents = 1,
1593 .flags = CLK_SET_RATE_PARENT,
1594 .ops = &clk_branch2_ops,
1595 },
1596 },
1597};
1598
1599static struct clk_branch gcc_blsp1_ahb_clk = {
1600 .halt_reg = 0x17004,
1601 .halt_check = BRANCH_HALT_VOTED,
1602 .clkr = {
1603 .enable_reg = 0x52004,
1604 .enable_mask = BIT(17),
1605 .hw.init = &(struct clk_init_data){
1606 .name = "gcc_blsp1_ahb_clk",
1607 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1608 .num_parents = 1,
1609 .flags = CLK_SET_RATE_PARENT,
1610 .ops = &clk_branch2_ops,
1611 },
1612 },
1613};
1614
1615static struct clk_branch gcc_blsp1_sleep_clk = {
1616 .halt_reg = 0x17008,
1617 .halt_check = BRANCH_HALT_VOTED,
1618 .clkr = {
1619 .enable_reg = 0x52004,
1620 .enable_mask = BIT(16),
1621 .hw.init = &(struct clk_init_data){
1622 .name = "gcc_blsp1_sleep_clk",
1623 .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1624 .num_parents = 1,
1625 .flags = CLK_SET_RATE_PARENT,
1626 .ops = &clk_branch2_ops,
1627 },
1628 },
1629};
1630
1631static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1632 .halt_reg = 0x19004,
1633 .clkr = {
1634 .enable_reg = 0x19004,
1635 .enable_mask = BIT(0),
1636 .hw.init = &(struct clk_init_data){
1637 .name = "gcc_blsp1_qup1_spi_apps_clk",
1638 .parent_names = (const char *[]){ "blsp1_qup1_spi_apps_clk_src" },
1639 .num_parents = 1,
1640 .flags = CLK_SET_RATE_PARENT,
1641 .ops = &clk_branch2_ops,
1642 },
1643 },
1644};
1645
1646static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1647 .halt_reg = 0x19008,
1648 .clkr = {
1649 .enable_reg = 0x19008,
1650 .enable_mask = BIT(0),
1651 .hw.init = &(struct clk_init_data){
1652 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1653 .parent_names = (const char *[]){ "blsp1_qup1_i2c_apps_clk_src" },
1654 .num_parents = 1,
1655 .flags = CLK_SET_RATE_PARENT,
1656 .ops = &clk_branch2_ops,
1657 },
1658 },
1659};
1660
1661static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1662 .halt_reg = 0x1a004,
1663 .clkr = {
1664 .enable_reg = 0x1a004,
1665 .enable_mask = BIT(0),
1666 .hw.init = &(struct clk_init_data){
1667 .name = "gcc_blsp1_uart1_apps_clk",
1668 .parent_names = (const char *[]){ "blsp1_uart1_apps_clk_src" },
1669 .num_parents = 1,
1670 .flags = CLK_SET_RATE_PARENT,
1671 .ops = &clk_branch2_ops,
1672 },
1673 },
1674};
1675
1676static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1677 .halt_reg = 0x1b004,
1678 .clkr = {
1679 .enable_reg = 0x1b004,
1680 .enable_mask = BIT(0),
1681 .hw.init = &(struct clk_init_data){
1682 .name = "gcc_blsp1_qup2_spi_apps_clk",
1683 .parent_names = (const char *[]){ "blsp1_qup2_spi_apps_clk_src" },
1684 .num_parents = 1,
1685 .flags = CLK_SET_RATE_PARENT,
1686 .ops = &clk_branch2_ops,
1687 },
1688 },
1689};
1690
1691static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1692 .halt_reg = 0x1b008,
1693 .clkr = {
1694 .enable_reg = 0x1b008,
1695 .enable_mask = BIT(0),
1696 .hw.init = &(struct clk_init_data){
1697 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1698 .parent_names = (const char *[]){ "blsp1_qup2_i2c_apps_clk_src" },
1699 .num_parents = 1,
1700 .flags = CLK_SET_RATE_PARENT,
1701 .ops = &clk_branch2_ops,
1702 },
1703 },
1704};
1705
1706static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1707 .halt_reg = 0x1c004,
1708 .clkr = {
1709 .enable_reg = 0x1c004,
1710 .enable_mask = BIT(0),
1711 .hw.init = &(struct clk_init_data){
1712 .name = "gcc_blsp1_uart2_apps_clk",
1713 .parent_names = (const char *[]){ "blsp1_uart2_apps_clk_src" },
1714 .num_parents = 1,
1715 .flags = CLK_SET_RATE_PARENT,
1716 .ops = &clk_branch2_ops,
1717 },
1718 },
1719};
1720
1721static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1722 .halt_reg = 0x1d004,
1723 .clkr = {
1724 .enable_reg = 0x1d004,
1725 .enable_mask = BIT(0),
1726 .hw.init = &(struct clk_init_data){
1727 .name = "gcc_blsp1_qup3_spi_apps_clk",
1728 .parent_names = (const char *[]){ "blsp1_qup3_spi_apps_clk_src" },
1729 .num_parents = 1,
1730 .flags = CLK_SET_RATE_PARENT,
1731 .ops = &clk_branch2_ops,
1732 },
1733 },
1734};
1735
1736static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1737 .halt_reg = 0x1d008,
1738 .clkr = {
1739 .enable_reg = 0x1d008,
1740 .enable_mask = BIT(0),
1741 .hw.init = &(struct clk_init_data){
1742 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1743 .parent_names = (const char *[]){ "blsp1_qup3_i2c_apps_clk_src" },
1744 .num_parents = 1,
1745 .flags = CLK_SET_RATE_PARENT,
1746 .ops = &clk_branch2_ops,
1747 },
1748 },
1749};
1750
1751static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1752 .halt_reg = 0x1e004,
1753 .clkr = {
1754 .enable_reg = 0x1e004,
1755 .enable_mask = BIT(0),
1756 .hw.init = &(struct clk_init_data){
1757 .name = "gcc_blsp1_uart3_apps_clk",
1758 .parent_names = (const char *[]){ "blsp1_uart3_apps_clk_src" },
1759 .num_parents = 1,
1760 .flags = CLK_SET_RATE_PARENT,
1761 .ops = &clk_branch2_ops,
1762 },
1763 },
1764};
1765
1766static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1767 .halt_reg = 0x1f004,
1768 .clkr = {
1769 .enable_reg = 0x1f004,
1770 .enable_mask = BIT(0),
1771 .hw.init = &(struct clk_init_data){
1772 .name = "gcc_blsp1_qup4_spi_apps_clk",
1773 .parent_names = (const char *[]){ "blsp1_qup4_spi_apps_clk_src" },
1774 .num_parents = 1,
1775 .flags = CLK_SET_RATE_PARENT,
1776 .ops = &clk_branch2_ops,
1777 },
1778 },
1779};
1780
1781static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1782 .halt_reg = 0x1f008,
1783 .clkr = {
1784 .enable_reg = 0x1f008,
1785 .enable_mask = BIT(0),
1786 .hw.init = &(struct clk_init_data){
1787 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1788 .parent_names = (const char *[]){ "blsp1_qup4_i2c_apps_clk_src" },
1789 .num_parents = 1,
1790 .flags = CLK_SET_RATE_PARENT,
1791 .ops = &clk_branch2_ops,
1792 },
1793 },
1794};
1795
1796static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1797 .halt_reg = 0x20004,
1798 .clkr = {
1799 .enable_reg = 0x20004,
1800 .enable_mask = BIT(0),
1801 .hw.init = &(struct clk_init_data){
1802 .name = "gcc_blsp1_uart4_apps_clk",
1803 .parent_names = (const char *[]){ "blsp1_uart4_apps_clk_src" },
1804 .num_parents = 1,
1805 .flags = CLK_SET_RATE_PARENT,
1806 .ops = &clk_branch2_ops,
1807 },
1808 },
1809};
1810
1811static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1812 .halt_reg = 0x21004,
1813 .clkr = {
1814 .enable_reg = 0x21004,
1815 .enable_mask = BIT(0),
1816 .hw.init = &(struct clk_init_data){
1817 .name = "gcc_blsp1_qup5_spi_apps_clk",
1818 .parent_names = (const char *[]){ "blsp1_qup5_spi_apps_clk_src" },
1819 .num_parents = 1,
1820 .flags = CLK_SET_RATE_PARENT,
1821 .ops = &clk_branch2_ops,
1822 },
1823 },
1824};
1825
1826static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1827 .halt_reg = 0x21008,
1828 .clkr = {
1829 .enable_reg = 0x21008,
1830 .enable_mask = BIT(0),
1831 .hw.init = &(struct clk_init_data){
1832 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1833 .parent_names = (const char *[]){ "blsp1_qup5_i2c_apps_clk_src" },
1834 .num_parents = 1,
1835 .flags = CLK_SET_RATE_PARENT,
1836 .ops = &clk_branch2_ops,
1837 },
1838 },
1839};
1840
1841static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1842 .halt_reg = 0x22004,
1843 .clkr = {
1844 .enable_reg = 0x22004,
1845 .enable_mask = BIT(0),
1846 .hw.init = &(struct clk_init_data){
1847 .name = "gcc_blsp1_uart5_apps_clk",
1848 .parent_names = (const char *[]){ "blsp1_uart5_apps_clk_src" },
1849 .num_parents = 1,
1850 .flags = CLK_SET_RATE_PARENT,
1851 .ops = &clk_branch2_ops,
1852 },
1853 },
1854};
1855
1856static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1857 .halt_reg = 0x23004,
1858 .clkr = {
1859 .enable_reg = 0x23004,
1860 .enable_mask = BIT(0),
1861 .hw.init = &(struct clk_init_data){
1862 .name = "gcc_blsp1_qup6_spi_apps_clk",
1863 .parent_names = (const char *[]){ "blsp1_qup6_spi_apps_clk_src" },
1864 .num_parents = 1,
1865 .flags = CLK_SET_RATE_PARENT,
1866 .ops = &clk_branch2_ops,
1867 },
1868 },
1869};
1870
1871static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1872 .halt_reg = 0x23008,
1873 .clkr = {
1874 .enable_reg = 0x23008,
1875 .enable_mask = BIT(0),
1876 .hw.init = &(struct clk_init_data){
1877 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1878 .parent_names = (const char *[]){ "blsp1_qup6_i2c_apps_clk_src" },
1879 .num_parents = 1,
1880 .flags = CLK_SET_RATE_PARENT,
1881 .ops = &clk_branch2_ops,
1882 },
1883 },
1884};
1885
1886static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1887 .halt_reg = 0x24004,
1888 .clkr = {
1889 .enable_reg = 0x24004,
1890 .enable_mask = BIT(0),
1891 .hw.init = &(struct clk_init_data){
1892 .name = "gcc_blsp1_uart6_apps_clk",
1893 .parent_names = (const char *[]){ "blsp1_uart6_apps_clk_src" },
1894 .num_parents = 1,
1895 .flags = CLK_SET_RATE_PARENT,
1896 .ops = &clk_branch2_ops,
1897 },
1898 },
1899};
1900
1901static struct clk_branch gcc_blsp2_ahb_clk = {
1902 .halt_reg = 0x25004,
1903 .halt_check = BRANCH_HALT_VOTED,
1904 .clkr = {
1905 .enable_reg = 0x52004,
1906 .enable_mask = BIT(15),
1907 .hw.init = &(struct clk_init_data){
1908 .name = "gcc_blsp2_ahb_clk",
1909 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1910 .num_parents = 1,
1911 .flags = CLK_SET_RATE_PARENT,
1912 .ops = &clk_branch2_ops,
1913 },
1914 },
1915};
1916
1917static struct clk_branch gcc_blsp2_sleep_clk = {
1918 .halt_reg = 0x25008,
1919 .halt_check = BRANCH_HALT_VOTED,
1920 .clkr = {
1921 .enable_reg = 0x52004,
1922 .enable_mask = BIT(14),
1923 .hw.init = &(struct clk_init_data){
1924 .name = "gcc_blsp2_sleep_clk",
1925 .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1926 .num_parents = 1,
1927 .flags = CLK_SET_RATE_PARENT,
1928 .ops = &clk_branch2_ops,
1929 },
1930 },
1931};
1932
1933static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1934 .halt_reg = 0x26004,
1935 .clkr = {
1936 .enable_reg = 0x26004,
1937 .enable_mask = BIT(0),
1938 .hw.init = &(struct clk_init_data){
1939 .name = "gcc_blsp2_qup1_spi_apps_clk",
1940 .parent_names = (const char *[]){ "blsp2_qup1_spi_apps_clk_src" },
1941 .num_parents = 1,
1942 .flags = CLK_SET_RATE_PARENT,
1943 .ops = &clk_branch2_ops,
1944 },
1945 },
1946};
1947
1948static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1949 .halt_reg = 0x26008,
1950 .clkr = {
1951 .enable_reg = 0x26008,
1952 .enable_mask = BIT(0),
1953 .hw.init = &(struct clk_init_data){
1954 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1955 .parent_names = (const char *[]){ "blsp2_qup1_i2c_apps_clk_src" },
1956 .num_parents = 1,
1957 .flags = CLK_SET_RATE_PARENT,
1958 .ops = &clk_branch2_ops,
1959 },
1960 },
1961};
1962
1963static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1964 .halt_reg = 0x27004,
1965 .clkr = {
1966 .enable_reg = 0x27004,
1967 .enable_mask = BIT(0),
1968 .hw.init = &(struct clk_init_data){
1969 .name = "gcc_blsp2_uart1_apps_clk",
1970 .parent_names = (const char *[]){ "blsp2_uart1_apps_clk_src" },
1971 .num_parents = 1,
1972 .flags = CLK_SET_RATE_PARENT,
1973 .ops = &clk_branch2_ops,
1974 },
1975 },
1976};
1977
1978static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1979 .halt_reg = 0x28004,
1980 .clkr = {
1981 .enable_reg = 0x28004,
1982 .enable_mask = BIT(0),
1983 .hw.init = &(struct clk_init_data){
1984 .name = "gcc_blsp2_qup2_spi_apps_clk",
1985 .parent_names = (const char *[]){ "blsp2_qup2_spi_apps_clk_src" },
1986 .num_parents = 1,
1987 .flags = CLK_SET_RATE_PARENT,
1988 .ops = &clk_branch2_ops,
1989 },
1990 },
1991};
1992
1993static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1994 .halt_reg = 0x28008,
1995 .clkr = {
1996 .enable_reg = 0x28008,
1997 .enable_mask = BIT(0),
1998 .hw.init = &(struct clk_init_data){
1999 .name = "gcc_blsp2_qup2_i2c_apps_clk",
2000 .parent_names = (const char *[]){ "blsp2_qup2_i2c_apps_clk_src" },
2001 .num_parents = 1,
2002 .flags = CLK_SET_RATE_PARENT,
2003 .ops = &clk_branch2_ops,
2004 },
2005 },
2006};
2007
2008static struct clk_branch gcc_blsp2_uart2_apps_clk = {
2009 .halt_reg = 0x29004,
2010 .clkr = {
2011 .enable_reg = 0x29004,
2012 .enable_mask = BIT(0),
2013 .hw.init = &(struct clk_init_data){
2014 .name = "gcc_blsp2_uart2_apps_clk",
2015 .parent_names = (const char *[]){ "blsp2_uart2_apps_clk_src" },
2016 .num_parents = 1,
2017 .flags = CLK_SET_RATE_PARENT,
2018 .ops = &clk_branch2_ops,
2019 },
2020 },
2021};
2022
2023static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
2024 .halt_reg = 0x2a004,
2025 .clkr = {
2026 .enable_reg = 0x2a004,
2027 .enable_mask = BIT(0),
2028 .hw.init = &(struct clk_init_data){
2029 .name = "gcc_blsp2_qup3_spi_apps_clk",
2030 .parent_names = (const char *[]){ "blsp2_qup3_spi_apps_clk_src" },
2031 .num_parents = 1,
2032 .flags = CLK_SET_RATE_PARENT,
2033 .ops = &clk_branch2_ops,
2034 },
2035 },
2036};
2037
2038static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
2039 .halt_reg = 0x2a008,
2040 .clkr = {
2041 .enable_reg = 0x2a008,
2042 .enable_mask = BIT(0),
2043 .hw.init = &(struct clk_init_data){
2044 .name = "gcc_blsp2_qup3_i2c_apps_clk",
2045 .parent_names = (const char *[]){ "blsp2_qup3_i2c_apps_clk_src" },
2046 .num_parents = 1,
2047 .flags = CLK_SET_RATE_PARENT,
2048 .ops = &clk_branch2_ops,
2049 },
2050 },
2051};
2052
2053static struct clk_branch gcc_blsp2_uart3_apps_clk = {
2054 .halt_reg = 0x2b004,
2055 .clkr = {
2056 .enable_reg = 0x2b004,
2057 .enable_mask = BIT(0),
2058 .hw.init = &(struct clk_init_data){
2059 .name = "gcc_blsp2_uart3_apps_clk",
2060 .parent_names = (const char *[]){ "blsp2_uart3_apps_clk_src" },
2061 .num_parents = 1,
2062 .flags = CLK_SET_RATE_PARENT,
2063 .ops = &clk_branch2_ops,
2064 },
2065 },
2066};
2067
2068static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
2069 .halt_reg = 0x2c004,
2070 .clkr = {
2071 .enable_reg = 0x2c004,
2072 .enable_mask = BIT(0),
2073 .hw.init = &(struct clk_init_data){
2074 .name = "gcc_blsp2_qup4_spi_apps_clk",
2075 .parent_names = (const char *[]){ "blsp2_qup4_spi_apps_clk_src" },
2076 .num_parents = 1,
2077 .flags = CLK_SET_RATE_PARENT,
2078 .ops = &clk_branch2_ops,
2079 },
2080 },
2081};
2082
2083static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
2084 .halt_reg = 0x2c008,
2085 .clkr = {
2086 .enable_reg = 0x2c008,
2087 .enable_mask = BIT(0),
2088 .hw.init = &(struct clk_init_data){
2089 .name = "gcc_blsp2_qup4_i2c_apps_clk",
2090 .parent_names = (const char *[]){ "blsp2_qup4_i2c_apps_clk_src" },
2091 .num_parents = 1,
2092 .flags = CLK_SET_RATE_PARENT,
2093 .ops = &clk_branch2_ops,
2094 },
2095 },
2096};
2097
2098static struct clk_branch gcc_blsp2_uart4_apps_clk = {
2099 .halt_reg = 0x2d004,
2100 .clkr = {
2101 .enable_reg = 0x2d004,
2102 .enable_mask = BIT(0),
2103 .hw.init = &(struct clk_init_data){
2104 .name = "gcc_blsp2_uart4_apps_clk",
2105 .parent_names = (const char *[]){ "blsp2_uart4_apps_clk_src" },
2106 .num_parents = 1,
2107 .flags = CLK_SET_RATE_PARENT,
2108 .ops = &clk_branch2_ops,
2109 },
2110 },
2111};
2112
2113static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
2114 .halt_reg = 0x2e004,
2115 .clkr = {
2116 .enable_reg = 0x2e004,
2117 .enable_mask = BIT(0),
2118 .hw.init = &(struct clk_init_data){
2119 .name = "gcc_blsp2_qup5_spi_apps_clk",
2120 .parent_names = (const char *[]){ "blsp2_qup5_spi_apps_clk_src" },
2121 .num_parents = 1,
2122 .flags = CLK_SET_RATE_PARENT,
2123 .ops = &clk_branch2_ops,
2124 },
2125 },
2126};
2127
2128static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
2129 .halt_reg = 0x2e008,
2130 .clkr = {
2131 .enable_reg = 0x2e008,
2132 .enable_mask = BIT(0),
2133 .hw.init = &(struct clk_init_data){
2134 .name = "gcc_blsp2_qup5_i2c_apps_clk",
2135 .parent_names = (const char *[]){ "blsp2_qup5_i2c_apps_clk_src" },
2136 .num_parents = 1,
2137 .flags = CLK_SET_RATE_PARENT,
2138 .ops = &clk_branch2_ops,
2139 },
2140 },
2141};
2142
2143static struct clk_branch gcc_blsp2_uart5_apps_clk = {
2144 .halt_reg = 0x2f004,
2145 .clkr = {
2146 .enable_reg = 0x2f004,
2147 .enable_mask = BIT(0),
2148 .hw.init = &(struct clk_init_data){
2149 .name = "gcc_blsp2_uart5_apps_clk",
2150 .parent_names = (const char *[]){ "blsp2_uart5_apps_clk_src" },
2151 .num_parents = 1,
2152 .flags = CLK_SET_RATE_PARENT,
2153 .ops = &clk_branch2_ops,
2154 },
2155 },
2156};
2157
2158static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
2159 .halt_reg = 0x30004,
2160 .clkr = {
2161 .enable_reg = 0x30004,
2162 .enable_mask = BIT(0),
2163 .hw.init = &(struct clk_init_data){
2164 .name = "gcc_blsp2_qup6_spi_apps_clk",
2165 .parent_names = (const char *[]){ "blsp2_qup6_spi_apps_clk_src" },
2166 .num_parents = 1,
2167 .flags = CLK_SET_RATE_PARENT,
2168 .ops = &clk_branch2_ops,
2169 },
2170 },
2171};
2172
2173static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
2174 .halt_reg = 0x30008,
2175 .clkr = {
2176 .enable_reg = 0x30008,
2177 .enable_mask = BIT(0),
2178 .hw.init = &(struct clk_init_data){
2179 .name = "gcc_blsp2_qup6_i2c_apps_clk",
2180 .parent_names = (const char *[]){ "blsp2_qup6_i2c_apps_clk_src" },
2181 .num_parents = 1,
2182 .flags = CLK_SET_RATE_PARENT,
2183 .ops = &clk_branch2_ops,
2184 },
2185 },
2186};
2187
2188static struct clk_branch gcc_blsp2_uart6_apps_clk = {
2189 .halt_reg = 0x31004,
2190 .clkr = {
2191 .enable_reg = 0x31004,
2192 .enable_mask = BIT(0),
2193 .hw.init = &(struct clk_init_data){
2194 .name = "gcc_blsp2_uart6_apps_clk",
2195 .parent_names = (const char *[]){ "blsp2_uart6_apps_clk_src" },
2196 .num_parents = 1,
2197 .flags = CLK_SET_RATE_PARENT,
2198 .ops = &clk_branch2_ops,
2199 },
2200 },
2201};
2202
2203static struct clk_branch gcc_pdm_ahb_clk = {
2204 .halt_reg = 0x33004,
2205 .clkr = {
2206 .enable_reg = 0x33004,
2207 .enable_mask = BIT(0),
2208 .hw.init = &(struct clk_init_data){
2209 .name = "gcc_pdm_ahb_clk",
2210 .parent_names = (const char *[]){ "periph_noc_clk_src" },
2211 .num_parents = 1,
2212 .flags = CLK_SET_RATE_PARENT,
2213 .ops = &clk_branch2_ops,
2214 },
2215 },
2216};
2217
2218static struct clk_branch gcc_pdm2_clk = {
2219 .halt_reg = 0x3300c,
2220 .clkr = {
2221 .enable_reg = 0x3300c,
2222 .enable_mask = BIT(0),
2223 .hw.init = &(struct clk_init_data){
2224 .name = "gcc_pdm2_clk",
2225 .parent_names = (const char *[]){ "pdm2_clk_src" },
2226 .num_parents = 1,
2227 .flags = CLK_SET_RATE_PARENT,
2228 .ops = &clk_branch2_ops,
2229 },
2230 },
2231};
2232
2233static struct clk_branch gcc_prng_ahb_clk = {
2234 .halt_reg = 0x34004,
2235 .halt_check = BRANCH_HALT_VOTED,
2236 .clkr = {
2237 .enable_reg = 0x52004,
2238 .enable_mask = BIT(13),
2239 .hw.init = &(struct clk_init_data){
2240 .name = "gcc_prng_ahb_clk",
2241 .parent_names = (const char *[]){ "config_noc_clk_src" },
2242 .num_parents = 1,
2243 .flags = CLK_SET_RATE_PARENT,
2244 .ops = &clk_branch2_ops,
2245 },
2246 },
2247};
2248
2249static struct clk_branch gcc_tsif_ahb_clk = {
2250 .halt_reg = 0x36004,
2251 .clkr = {
2252 .enable_reg = 0x36004,
2253 .enable_mask = BIT(0),
2254 .hw.init = &(struct clk_init_data){
2255 .name = "gcc_tsif_ahb_clk",
2256 .parent_names = (const char *[]){ "periph_noc_clk_src" },
2257 .num_parents = 1,
2258 .flags = CLK_SET_RATE_PARENT,
2259 .ops = &clk_branch2_ops,
2260 },
2261 },
2262};
2263
2264static struct clk_branch gcc_tsif_ref_clk = {
2265 .halt_reg = 0x36008,
2266 .clkr = {
2267 .enable_reg = 0x36008,
2268 .enable_mask = BIT(0),
2269 .hw.init = &(struct clk_init_data){
2270 .name = "gcc_tsif_ref_clk",
2271 .parent_names = (const char *[]){ "tsif_ref_clk_src" },
2272 .num_parents = 1,
2273 .flags = CLK_SET_RATE_PARENT,
2274 .ops = &clk_branch2_ops,
2275 },
2276 },
2277};
2278
2279static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2280 .halt_reg = 0x3600c,
2281 .clkr = {
2282 .enable_reg = 0x3600c,
2283 .enable_mask = BIT(0),
2284 .hw.init = &(struct clk_init_data){
2285 .name = "gcc_tsif_inactivity_timers_clk",
2286 .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
2287 .num_parents = 1,
2288 .flags = CLK_SET_RATE_PARENT,
2289 .ops = &clk_branch2_ops,
2290 },
2291 },
2292};
2293
2294static struct clk_branch gcc_boot_rom_ahb_clk = {
2295 .halt_reg = 0x38004,
2296 .halt_check = BRANCH_HALT_VOTED,
2297 .clkr = {
2298 .enable_reg = 0x52004,
2299 .enable_mask = BIT(10),
2300 .hw.init = &(struct clk_init_data){
2301 .name = "gcc_boot_rom_ahb_clk",
2302 .parent_names = (const char *[]){ "config_noc_clk_src" },
2303 .num_parents = 1,
2304 .flags = CLK_SET_RATE_PARENT,
2305 .ops = &clk_branch2_ops,
2306 },
2307 },
2308};
2309
2310static struct clk_branch gcc_bimc_gfx_clk = {
2311 .halt_reg = 0x46018,
2312 .clkr = {
2313 .enable_reg = 0x46018,
2314 .enable_mask = BIT(0),
2315 .hw.init = &(struct clk_init_data){
2316 .name = "gcc_bimc_gfx_clk",
2317 .flags = CLK_SET_RATE_PARENT | CLK_IS_ROOT,
2318 .ops = &clk_branch2_ops,
2319 },
2320 },
2321};
2322
2323static struct clk_branch gcc_hmss_rbcpr_clk = {
2324 .halt_reg = 0x4800c,
2325 .clkr = {
2326 .enable_reg = 0x4800c,
2327 .enable_mask = BIT(0),
2328 .hw.init = &(struct clk_init_data){
2329 .name = "gcc_hmss_rbcpr_clk",
2330 .parent_names = (const char *[]){ "hmss_rbcpr_clk_src" },
2331 .num_parents = 1,
2332 .flags = CLK_SET_RATE_PARENT,
2333 .ops = &clk_branch2_ops,
2334 },
2335 },
2336};
2337
2338static struct clk_branch gcc_gp1_clk = {
2339 .halt_reg = 0x64000,
2340 .clkr = {
2341 .enable_reg = 0x64000,
2342 .enable_mask = BIT(0),
2343 .hw.init = &(struct clk_init_data){
2344 .name = "gcc_gp1_clk",
2345 .parent_names = (const char *[]){ "gp1_clk_src" },
2346 .num_parents = 1,
2347 .flags = CLK_SET_RATE_PARENT,
2348 .ops = &clk_branch2_ops,
2349 },
2350 },
2351};
2352
2353static struct clk_branch gcc_gp2_clk = {
2354 .halt_reg = 0x65000,
2355 .clkr = {
2356 .enable_reg = 0x65000,
2357 .enable_mask = BIT(0),
2358 .hw.init = &(struct clk_init_data){
2359 .name = "gcc_gp2_clk",
2360 .parent_names = (const char *[]){ "gp2_clk_src" },
2361 .num_parents = 1,
2362 .flags = CLK_SET_RATE_PARENT,
2363 .ops = &clk_branch2_ops,
2364 },
2365 },
2366};
2367
2368static struct clk_branch gcc_gp3_clk = {
2369 .halt_reg = 0x66000,
2370 .clkr = {
2371 .enable_reg = 0x66000,
2372 .enable_mask = BIT(0),
2373 .hw.init = &(struct clk_init_data){
2374 .name = "gcc_gp3_clk",
2375 .parent_names = (const char *[]){ "gp3_clk_src" },
2376 .num_parents = 1,
2377 .flags = CLK_SET_RATE_PARENT,
2378 .ops = &clk_branch2_ops,
2379 },
2380 },
2381};
2382
2383static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2384 .halt_reg = 0x6b008,
2385 .clkr = {
2386 .enable_reg = 0x6b008,
2387 .enable_mask = BIT(0),
2388 .hw.init = &(struct clk_init_data){
2389 .name = "gcc_pcie_0_slv_axi_clk",
2390 .parent_names = (const char *[]){ "system_noc_clk_src" },
2391 .num_parents = 1,
2392 .flags = CLK_SET_RATE_PARENT,
2393 .ops = &clk_branch2_ops,
2394 },
2395 },
2396};
2397
2398static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2399 .halt_reg = 0x6b00c,
2400 .clkr = {
2401 .enable_reg = 0x6b00c,
2402 .enable_mask = BIT(0),
2403 .hw.init = &(struct clk_init_data){
2404 .name = "gcc_pcie_0_mstr_axi_clk",
2405 .parent_names = (const char *[]){ "system_noc_clk_src" },
2406 .num_parents = 1,
2407 .flags = CLK_SET_RATE_PARENT,
2408 .ops = &clk_branch2_ops,
2409 },
2410 },
2411};
2412
2413static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2414 .halt_reg = 0x6b010,
2415 .clkr = {
2416 .enable_reg = 0x6b010,
2417 .enable_mask = BIT(0),
2418 .hw.init = &(struct clk_init_data){
2419 .name = "gcc_pcie_0_cfg_ahb_clk",
2420 .parent_names = (const char *[]){ "config_noc_clk_src" },
2421 .num_parents = 1,
2422 .flags = CLK_SET_RATE_PARENT,
2423 .ops = &clk_branch2_ops,
2424 },
2425 },
2426};
2427
2428static struct clk_branch gcc_pcie_0_aux_clk = {
2429 .halt_reg = 0x6b014,
2430 .clkr = {
2431 .enable_reg = 0x6b014,
2432 .enable_mask = BIT(0),
2433 .hw.init = &(struct clk_init_data){
2434 .name = "gcc_pcie_0_aux_clk",
2435 .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2436 .num_parents = 1,
2437 .flags = CLK_SET_RATE_PARENT,
2438 .ops = &clk_branch2_ops,
2439 },
2440 },
2441};
2442
2443static struct clk_branch gcc_pcie_0_pipe_clk = {
2444 .halt_reg = 0x6b018,
2445 .clkr = {
2446 .enable_reg = 0x6b018,
2447 .enable_mask = BIT(0),
2448 .hw.init = &(struct clk_init_data){
2449 .name = "gcc_pcie_0_pipe_clk",
2450 .parent_names = (const char *[]){ "pcie_0_pipe_clk_src" },
2451 .num_parents = 1,
2452 .flags = CLK_SET_RATE_PARENT,
2453 .ops = &clk_branch2_ops,
2454 },
2455 },
2456};
2457
2458static struct clk_branch gcc_pcie_1_slv_axi_clk = {
2459 .halt_reg = 0x6d008,
2460 .clkr = {
2461 .enable_reg = 0x6d008,
2462 .enable_mask = BIT(0),
2463 .hw.init = &(struct clk_init_data){
2464 .name = "gcc_pcie_1_slv_axi_clk",
2465 .parent_names = (const char *[]){ "system_noc_clk_src" },
2466 .num_parents = 1,
2467 .flags = CLK_SET_RATE_PARENT,
2468 .ops = &clk_branch2_ops,
2469 },
2470 },
2471};
2472
2473static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
2474 .halt_reg = 0x6d00c,
2475 .clkr = {
2476 .enable_reg = 0x6d00c,
2477 .enable_mask = BIT(0),
2478 .hw.init = &(struct clk_init_data){
2479 .name = "gcc_pcie_1_mstr_axi_clk",
2480 .parent_names = (const char *[]){ "system_noc_clk_src" },
2481 .num_parents = 1,
2482 .flags = CLK_SET_RATE_PARENT,
2483 .ops = &clk_branch2_ops,
2484 },
2485 },
2486};
2487
2488static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
2489 .halt_reg = 0x6d010,
2490 .clkr = {
2491 .enable_reg = 0x6d010,
2492 .enable_mask = BIT(0),
2493 .hw.init = &(struct clk_init_data){
2494 .name = "gcc_pcie_1_cfg_ahb_clk",
2495 .parent_names = (const char *[]){ "config_noc_clk_src" },
2496 .num_parents = 1,
2497 .flags = CLK_SET_RATE_PARENT,
2498 .ops = &clk_branch2_ops,
2499 },
2500 },
2501};
2502
2503static struct clk_branch gcc_pcie_1_aux_clk = {
2504 .halt_reg = 0x6d014,
2505 .clkr = {
2506 .enable_reg = 0x6d014,
2507 .enable_mask = BIT(0),
2508 .hw.init = &(struct clk_init_data){
2509 .name = "gcc_pcie_1_aux_clk",
2510 .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2511 .num_parents = 1,
2512 .flags = CLK_SET_RATE_PARENT,
2513 .ops = &clk_branch2_ops,
2514 },
2515 },
2516};
2517
2518static struct clk_branch gcc_pcie_1_pipe_clk = {
2519 .halt_reg = 0x6d018,
2520 .clkr = {
2521 .enable_reg = 0x6d018,
2522 .enable_mask = BIT(0),
2523 .hw.init = &(struct clk_init_data){
2524 .name = "gcc_pcie_1_pipe_clk",
2525 .parent_names = (const char *[]){ "pcie_1_pipe_clk_src" },
2526 .num_parents = 1,
2527 .flags = CLK_SET_RATE_PARENT,
2528 .ops = &clk_branch2_ops,
2529 },
2530 },
2531};
2532
2533static struct clk_branch gcc_pcie_2_slv_axi_clk = {
2534 .halt_reg = 0x6e008,
2535 .clkr = {
2536 .enable_reg = 0x6e008,
2537 .enable_mask = BIT(0),
2538 .hw.init = &(struct clk_init_data){
2539 .name = "gcc_pcie_2_slv_axi_clk",
2540 .parent_names = (const char *[]){ "system_noc_clk_src" },
2541 .num_parents = 1,
2542 .flags = CLK_SET_RATE_PARENT,
2543 .ops = &clk_branch2_ops,
2544 },
2545 },
2546};
2547
2548static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
2549 .halt_reg = 0x6e00c,
2550 .clkr = {
2551 .enable_reg = 0x6e00c,
2552 .enable_mask = BIT(0),
2553 .hw.init = &(struct clk_init_data){
2554 .name = "gcc_pcie_2_mstr_axi_clk",
2555 .parent_names = (const char *[]){ "system_noc_clk_src" },
2556 .num_parents = 1,
2557 .flags = CLK_SET_RATE_PARENT,
2558 .ops = &clk_branch2_ops,
2559 },
2560 },
2561};
2562
2563static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
2564 .halt_reg = 0x6e010,
2565 .clkr = {
2566 .enable_reg = 0x6e010,
2567 .enable_mask = BIT(0),
2568 .hw.init = &(struct clk_init_data){
2569 .name = "gcc_pcie_2_cfg_ahb_clk",
2570 .parent_names = (const char *[]){ "config_noc_clk_src" },
2571 .num_parents = 1,
2572 .flags = CLK_SET_RATE_PARENT,
2573 .ops = &clk_branch2_ops,
2574 },
2575 },
2576};
2577
2578static struct clk_branch gcc_pcie_2_aux_clk = {
2579 .halt_reg = 0x6e014,
2580 .clkr = {
2581 .enable_reg = 0x6e014,
2582 .enable_mask = BIT(0),
2583 .hw.init = &(struct clk_init_data){
2584 .name = "gcc_pcie_2_aux_clk",
2585 .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2586 .num_parents = 1,
2587 .flags = CLK_SET_RATE_PARENT,
2588 .ops = &clk_branch2_ops,
2589 },
2590 },
2591};
2592
2593static struct clk_branch gcc_pcie_2_pipe_clk = {
2594 .halt_reg = 0x6e108,
2595 .clkr = {
2596 .enable_reg = 0x6e108,
2597 .enable_mask = BIT(0),
2598 .hw.init = &(struct clk_init_data){
2599 .name = "gcc_pcie_2_pipe_clk",
2600 .parent_names = (const char *[]){ "pcie_2_pipe_clk_src" },
2601 .num_parents = 1,
2602 .flags = CLK_SET_RATE_PARENT,
2603 .ops = &clk_branch2_ops,
2604 },
2605 },
2606};
2607
2608static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
2609 .halt_reg = 0x6f004,
2610 .clkr = {
2611 .enable_reg = 0x6f004,
2612 .enable_mask = BIT(0),
2613 .hw.init = &(struct clk_init_data){
2614 .name = "gcc_pcie_phy_cfg_ahb_clk",
2615 .parent_names = (const char *[]){ "config_noc_clk_src" },
2616 .num_parents = 1,
2617 .flags = CLK_SET_RATE_PARENT,
2618 .ops = &clk_branch2_ops,
2619 },
2620 },
2621};
2622
2623static struct clk_branch gcc_pcie_phy_aux_clk = {
2624 .halt_reg = 0x6f008,
2625 .clkr = {
2626 .enable_reg = 0x6f008,
2627 .enable_mask = BIT(0),
2628 .hw.init = &(struct clk_init_data){
2629 .name = "gcc_pcie_phy_aux_clk",
2630 .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2631 .num_parents = 1,
2632 .flags = CLK_SET_RATE_PARENT,
2633 .ops = &clk_branch2_ops,
2634 },
2635 },
2636};
2637
2638static struct clk_branch gcc_ufs_axi_clk = {
2639 .halt_reg = 0x75008,
2640 .clkr = {
2641 .enable_reg = 0x75008,
2642 .enable_mask = BIT(0),
2643 .hw.init = &(struct clk_init_data){
2644 .name = "gcc_ufs_axi_clk",
2645 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2646 .num_parents = 1,
2647 .flags = CLK_SET_RATE_PARENT,
2648 .ops = &clk_branch2_ops,
2649 },
2650 },
2651};
2652
2653static struct clk_branch gcc_ufs_ahb_clk = {
2654 .halt_reg = 0x7500c,
2655 .clkr = {
2656 .enable_reg = 0x7500c,
2657 .enable_mask = BIT(0),
2658 .hw.init = &(struct clk_init_data){
2659 .name = "gcc_ufs_ahb_clk",
2660 .parent_names = (const char *[]){ "config_noc_clk_src" },
2661 .num_parents = 1,
2662 .flags = CLK_SET_RATE_PARENT,
2663 .ops = &clk_branch2_ops,
2664 },
2665 },
2666};
2667
2668static struct clk_fixed_factor ufs_tx_cfg_clk_src = {
2669 .mult = 1,
2670 .div = 16,
2671 .hw.init = &(struct clk_init_data){
2672 .name = "ufs_tx_cfg_clk_src",
2673 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2674 .num_parents = 1,
2675 .flags = CLK_SET_RATE_PARENT,
2676 .ops = &clk_fixed_factor_ops,
2677 },
2678};
2679
2680static struct clk_branch gcc_ufs_tx_cfg_clk = {
2681 .halt_reg = 0x75010,
2682 .clkr = {
2683 .enable_reg = 0x75010,
2684 .enable_mask = BIT(0),
2685 .hw.init = &(struct clk_init_data){
2686 .name = "gcc_ufs_tx_cfg_clk",
2687 .parent_names = (const char *[]){ "ufs_tx_cfg_clk_src" },
2688 .num_parents = 1,
2689 .flags = CLK_SET_RATE_PARENT,
2690 .ops = &clk_branch2_ops,
2691 },
2692 },
2693};
2694
2695static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
2696 .mult = 1,
2697 .div = 16,
2698 .hw.init = &(struct clk_init_data){
2699 .name = "ufs_rx_cfg_clk_src",
2700 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2701 .num_parents = 1,
2702 .flags = CLK_SET_RATE_PARENT,
2703 .ops = &clk_fixed_factor_ops,
2704 },
2705};
2706
2707static struct clk_branch gcc_ufs_rx_cfg_clk = {
2708 .halt_reg = 0x75014,
2709 .clkr = {
2710 .enable_reg = 0x75014,
2711 .enable_mask = BIT(0),
2712 .hw.init = &(struct clk_init_data){
2713 .name = "gcc_ufs_rx_cfg_clk",
2714 .parent_names = (const char *[]){ "ufs_rx_cfg_clk_src" },
2715 .num_parents = 1,
2716 .flags = CLK_SET_RATE_PARENT,
2717 .ops = &clk_branch2_ops,
2718 },
2719 },
2720};
2721
2722static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2723 .halt_reg = 0x75018,
2724 .clkr = {
2725 .enable_reg = 0x75018,
2726 .enable_mask = BIT(0),
2727 .hw.init = &(struct clk_init_data){
2728 .name = "gcc_ufs_tx_symbol_0_clk",
2729 .parent_names = (const char *[]){ "ufs_tx_symbol_0_clk_src" },
2730 .num_parents = 1,
2731 .flags = CLK_SET_RATE_PARENT,
2732 .ops = &clk_branch2_ops,
2733 },
2734 },
2735};
2736
2737static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2738 .halt_reg = 0x7501c,
2739 .clkr = {
2740 .enable_reg = 0x7501c,
2741 .enable_mask = BIT(0),
2742 .hw.init = &(struct clk_init_data){
2743 .name = "gcc_ufs_rx_symbol_0_clk",
2744 .parent_names = (const char *[]){ "ufs_rx_symbol_0_clk_src" },
2745 .num_parents = 1,
2746 .flags = CLK_SET_RATE_PARENT,
2747 .ops = &clk_branch2_ops,
2748 },
2749 },
2750};
2751
2752static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2753 .halt_reg = 0x75020,
2754 .clkr = {
2755 .enable_reg = 0x75020,
2756 .enable_mask = BIT(0),
2757 .hw.init = &(struct clk_init_data){
2758 .name = "gcc_ufs_rx_symbol_1_clk",
2759 .parent_names = (const char *[]){ "ufs_rx_symbol_1_clk_src" },
2760 .num_parents = 1,
2761 .flags = CLK_SET_RATE_PARENT,
2762 .ops = &clk_branch2_ops,
2763 },
2764 },
2765};
2766
2767static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = {
2768 .mult = 1,
2769 .div = 2,
2770 .hw.init = &(struct clk_init_data){
2771 .name = "ufs_ice_core_postdiv_clk_src",
2772 .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
2773 .num_parents = 1,
2774 .flags = CLK_SET_RATE_PARENT,
2775 .ops = &clk_fixed_factor_ops,
2776 },
2777};
2778
2779static struct clk_branch gcc_ufs_unipro_core_clk = {
2780 .halt_reg = 0x7600c,
2781 .clkr = {
2782 .enable_reg = 0x7600c,
2783 .enable_mask = BIT(0),
2784 .hw.init = &(struct clk_init_data){
2785 .name = "gcc_ufs_unipro_core_clk",
2786 .parent_names = (const char *[]){ "ufs_ice_core_postdiv_clk_src" },
2787 .num_parents = 1,
2788 .flags = CLK_SET_RATE_PARENT,
2789 .ops = &clk_branch2_ops,
2790 },
2791 },
2792};
2793
2794static struct clk_branch gcc_ufs_ice_core_clk = {
2795 .halt_reg = 0x76010,
2796 .clkr = {
2797 .enable_reg = 0x76010,
2798 .enable_mask = BIT(0),
2799 .hw.init = &(struct clk_init_data){
2800 .name = "gcc_ufs_ice_core_clk",
2801 .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
2802 .num_parents = 1,
2803 .flags = CLK_SET_RATE_PARENT,
2804 .ops = &clk_branch2_ops,
2805 },
2806 },
2807};
2808
2809static struct clk_branch gcc_ufs_sys_clk_core_clk = {
2810 .halt_check = BRANCH_HALT_DELAY,
2811 .clkr = {
2812 .enable_reg = 0x76030,
2813 .enable_mask = BIT(0),
2814 .hw.init = &(struct clk_init_data){
2815 .name = "gcc_ufs_sys_clk_core_clk",
2816 .ops = &clk_branch2_ops,
2817 .flags = CLK_IS_ROOT,
2818 },
2819 },
2820};
2821
2822static struct clk_branch gcc_ufs_tx_symbol_clk_core_clk = {
2823 .halt_check = BRANCH_HALT_DELAY,
2824 .clkr = {
2825 .enable_reg = 0x76034,
2826 .enable_mask = BIT(0),
2827 .hw.init = &(struct clk_init_data){
2828 .name = "gcc_ufs_tx_symbol_clk_core_clk",
2829 .ops = &clk_branch2_ops,
2830 .flags = CLK_IS_ROOT,
2831 },
2832 },
2833};
2834
2835static struct clk_branch gcc_aggre0_snoc_axi_clk = {
2836 .halt_reg = 0x81008,
2837 .clkr = {
2838 .enable_reg = 0x81008,
2839 .enable_mask = BIT(0),
2840 .hw.init = &(struct clk_init_data){
2841 .name = "gcc_aggre0_snoc_axi_clk",
2842 .parent_names = (const char *[]){ "system_noc_clk_src" },
2843 .num_parents = 1,
2844 .flags = CLK_SET_RATE_PARENT,
2845 .ops = &clk_branch2_ops,
2846 },
2847 },
2848};
2849
2850static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
2851 .halt_reg = 0x8100c,
2852 .clkr = {
2853 .enable_reg = 0x8100c,
2854 .enable_mask = BIT(0),
2855 .hw.init = &(struct clk_init_data){
2856 .name = "gcc_aggre0_cnoc_ahb_clk",
2857 .parent_names = (const char *[]){ "config_noc_clk_src" },
2858 .num_parents = 1,
2859 .flags = CLK_SET_RATE_PARENT,
2860 .ops = &clk_branch2_ops,
2861 },
2862 },
2863};
2864
2865static struct clk_branch gcc_smmu_aggre0_axi_clk = {
2866 .halt_reg = 0x81014,
2867 .clkr = {
2868 .enable_reg = 0x81014,
2869 .enable_mask = BIT(0),
2870 .hw.init = &(struct clk_init_data){
2871 .name = "gcc_smmu_aggre0_axi_clk",
2872 .parent_names = (const char *[]){ "system_noc_clk_src" },
2873 .num_parents = 1,
2874 .flags = CLK_SET_RATE_PARENT,
2875 .ops = &clk_branch2_ops,
2876 },
2877 },
2878};
2879
2880static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
2881 .halt_reg = 0x81018,
2882 .clkr = {
2883 .enable_reg = 0x81018,
2884 .enable_mask = BIT(0),
2885 .hw.init = &(struct clk_init_data){
2886 .name = "gcc_smmu_aggre0_ahb_clk",
2887 .parent_names = (const char *[]){ "config_noc_clk_src" },
2888 .num_parents = 1,
2889 .flags = CLK_SET_RATE_PARENT,
2890 .ops = &clk_branch2_ops,
2891 },
2892 },
2893};
2894
2895static struct clk_branch gcc_aggre1_pnoc_ahb_clk = {
2896 .halt_reg = 0x82014,
2897 .clkr = {
2898 .enable_reg = 0x82014,
2899 .enable_mask = BIT(0),
2900 .hw.init = &(struct clk_init_data){
2901 .name = "gcc_aggre1_pnoc_ahb_clk",
2902 .parent_names = (const char *[]){ "periph_noc_clk_src" },
2903 .num_parents = 1,
2904 .flags = CLK_SET_RATE_PARENT,
2905 .ops = &clk_branch2_ops,
2906 },
2907 },
2908};
2909
2910static struct clk_branch gcc_aggre2_ufs_axi_clk = {
2911 .halt_reg = 0x83014,
2912 .clkr = {
2913 .enable_reg = 0x83014,
2914 .enable_mask = BIT(0),
2915 .hw.init = &(struct clk_init_data){
2916 .name = "gcc_aggre2_ufs_axi_clk",
2917 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2918 .num_parents = 1,
2919 .flags = CLK_SET_RATE_PARENT,
2920 .ops = &clk_branch2_ops,
2921 },
2922 },
2923};
2924
2925static struct clk_branch gcc_aggre2_usb3_axi_clk = {
2926 .halt_reg = 0x83018,
2927 .clkr = {
2928 .enable_reg = 0x83018,
2929 .enable_mask = BIT(0),
2930 .hw.init = &(struct clk_init_data){
2931 .name = "gcc_aggre2_usb3_axi_clk",
2932 .parent_names = (const char *[]){ "usb30_master_clk_src" },
2933 .num_parents = 1,
2934 .flags = CLK_SET_RATE_PARENT,
2935 .ops = &clk_branch2_ops,
2936 },
2937 },
2938};
2939
2940static struct clk_branch gcc_qspi_ahb_clk = {
2941 .halt_reg = 0x8b004,
2942 .clkr = {
2943 .enable_reg = 0x8b004,
2944 .enable_mask = BIT(0),
2945 .hw.init = &(struct clk_init_data){
2946 .name = "gcc_qspi_ahb_clk",
2947 .parent_names = (const char *[]){ "periph_noc_clk_src" },
2948 .num_parents = 1,
2949 .flags = CLK_SET_RATE_PARENT,
2950 .ops = &clk_branch2_ops,
2951 },
2952 },
2953};
2954
2955static struct clk_branch gcc_qspi_ser_clk = {
2956 .halt_reg = 0x8b008,
2957 .clkr = {
2958 .enable_reg = 0x8b008,
2959 .enable_mask = BIT(0),
2960 .hw.init = &(struct clk_init_data){
2961 .name = "gcc_qspi_ser_clk",
2962 .parent_names = (const char *[]){ "qspi_ser_clk_src" },
2963 .num_parents = 1,
2964 .flags = CLK_SET_RATE_PARENT,
2965 .ops = &clk_branch2_ops,
2966 },
2967 },
2968};
2969
2970static struct clk_branch gcc_usb3_clkref_clk = {
2971 .halt_reg = 0x8800C,
2972 .clkr = {
2973 .enable_reg = 0x8800C,
2974 .enable_mask = BIT(0),
2975 .hw.init = &(struct clk_init_data){
2976 .name = "gcc_usb3_clkref_clk",
2977 .parent_names = (const char *[]){ "xo" },
2978 .num_parents = 1,
2979 .ops = &clk_branch2_ops,
2980 },
2981 },
2982};
2983
2984static struct clk_branch gcc_hdmi_clkref_clk = {
2985 .halt_reg = 0x88000,
2986 .clkr = {
2987 .enable_reg = 0x88000,
2988 .enable_mask = BIT(0),
2989 .hw.init = &(struct clk_init_data){
2990 .name = "gcc_hdmi_clkref_clk",
2991 .parent_names = (const char *[]){ "xo" },
2992 .num_parents = 1,
2993 .ops = &clk_branch2_ops,
2994 },
2995 },
2996};
2997
2998static struct clk_branch gcc_ufs_clkref_clk = {
2999 .halt_reg = 0x88008,
3000 .clkr = {
3001 .enable_reg = 0x88008,
3002 .enable_mask = BIT(0),
3003 .hw.init = &(struct clk_init_data){
3004 .name = "gcc_ufs_clkref_clk",
3005 .parent_names = (const char *[]){ "xo" },
3006 .num_parents = 1,
3007 .ops = &clk_branch2_ops,
3008 },
3009 },
3010};
3011
3012static struct clk_branch gcc_pcie_clkref_clk = {
3013 .halt_reg = 0x88010,
3014 .clkr = {
3015 .enable_reg = 0x88010,
3016 .enable_mask = BIT(0),
3017 .hw.init = &(struct clk_init_data){
3018 .name = "gcc_pcie_clkref_clk",
3019 .parent_names = (const char *[]){ "xo" },
3020 .num_parents = 1,
3021 .ops = &clk_branch2_ops,
3022 },
3023 },
3024};
3025
3026static struct clk_branch gcc_rx2_usb2_clkref_clk = {
3027 .halt_reg = 0x88014,
3028 .clkr = {
3029 .enable_reg = 0x88014,
3030 .enable_mask = BIT(0),
3031 .hw.init = &(struct clk_init_data){
3032 .name = "gcc_rx2_usb2_clkref_clk",
3033 .parent_names = (const char *[]){ "xo" },
3034 .num_parents = 1,
3035 .ops = &clk_branch2_ops,
3036 },
3037 },
3038};
3039
3040static struct clk_branch gcc_rx1_usb2_clkref_clk = {
3041 .halt_reg = 0x88018,
3042 .clkr = {
3043 .enable_reg = 0x88018,
3044 .enable_mask = BIT(0),
3045 .hw.init = &(struct clk_init_data){
3046 .name = "gcc_rx1_usb2_clkref_clk",
3047 .parent_names = (const char *[]){ "xo" },
3048 .num_parents = 1,
3049 .ops = &clk_branch2_ops,
3050 },
3051 },
3052};
3053
3054static struct clk_hw *gcc_msm8996_hws[] = {
3055 &xo.hw,
3056 &gpll0_early_div.hw,
3057 &ufs_tx_cfg_clk_src.hw,
3058 &ufs_rx_cfg_clk_src.hw,
3059 &ufs_ice_core_postdiv_clk_src.hw,
3060};
3061
3062static struct clk_regmap *gcc_msm8996_clocks[] = {
3063 [GPLL0_EARLY] = &gpll0_early.clkr,
3064 [GPLL0] = &gpll0.clkr,
3065 [GPLL4_EARLY] = &gpll4_early.clkr,
3066 [GPLL4] = &gpll4.clkr,
3067 [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
3068 [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
3069 [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
3070 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
3071 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
3072 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
3073 [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
3074 [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
3075 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3076 [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
3077 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3078 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
3079 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
3080 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3081 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3082 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3083 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3084 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3085 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3086 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3087 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3088 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
3089 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3090 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3091 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
3092 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3093 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3094 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
3095 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3096 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3097 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
3098 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
3099 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
3100 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
3101 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
3102 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
3103 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
3104 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
3105 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
3106 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
3107 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
3108 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
3109 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
3110 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
3111 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
3112 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
3113 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
3114 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
3115 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
3116 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3117 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
3118 [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
3119 [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
3120 [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
3121 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3122 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3123 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3124 [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
3125 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
3126 [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
3127 [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
3128 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
3129 [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
3130 [GCC_PERIPH_NOC_USB20_AHB_CLK] = &gcc_periph_noc_usb20_ahb_clk.clkr,
3131 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
3132 [GCC_MMSS_BIMC_GFX_CLK] = &gcc_mmss_bimc_gfx_clk.clkr,
3133 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
3134 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
3135 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
3136 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
3137 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
3138 [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
3139 [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
3140 [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
3141 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
3142 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3143 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3144 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3145 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3146 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3147 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
3148 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
3149 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3150 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3151 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3152 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
3153 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3154 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3155 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3156 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3157 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3158 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3159 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3160 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3161 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
3162 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3163 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3164 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
3165 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3166 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3167 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
3168 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3169 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3170 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
3171 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
3172 [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
3173 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
3174 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
3175 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
3176 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
3177 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
3178 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
3179 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
3180 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
3181 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
3182 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
3183 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
3184 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
3185 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
3186 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
3187 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
3188 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
3189 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
3190 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
3191 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3192 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3193 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3194 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3195 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3196 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3197 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3198 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3199 [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
3200 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3201 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3202 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3203 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3204 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3205 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3206 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3207 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3208 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3209 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3210 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3211 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3212 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3213 [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
3214 [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
3215 [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
3216 [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
3217 [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
3218 [GCC_PCIE_PHY_CFG_AHB_CLK] = &gcc_pcie_phy_cfg_ahb_clk.clkr,
3219 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3220 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
3221 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
3222 [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
3223 [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
3224 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
3225 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
3226 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
3227 [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
3228 [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
3229 [GCC_UFS_SYS_CLK_CORE_CLK] = &gcc_ufs_sys_clk_core_clk.clkr,
3230 [GCC_UFS_TX_SYMBOL_CLK_CORE_CLK] = &gcc_ufs_tx_symbol_clk_core_clk.clkr,
3231 [GCC_AGGRE0_SNOC_AXI_CLK] = &gcc_aggre0_snoc_axi_clk.clkr,
3232 [GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
3233 [GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
3234 [GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
3235 [GCC_AGGRE1_PNOC_AHB_CLK] = &gcc_aggre1_pnoc_ahb_clk.clkr,
3236 [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
3237 [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
3238 [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
3239 [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
3240 [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
3241 [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,
3242 [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
3243 [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
3244 [GCC_RX2_USB2_CLKREF_CLK] = &gcc_rx2_usb2_clkref_clk.clkr,
3245 [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
3246};
3247
3248static const struct qcom_reset_map gcc_msm8996_resets[] = {
3249 [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
3250 [GCC_CONFIG_NOC_BCR] = { 0x5000 },
3251 [GCC_PERIPH_NOC_BCR] = { 0x6000 },
3252 [GCC_IMEM_BCR] = { 0x8000 },
3253 [GCC_MMSS_BCR] = { 0x9000 },
3254 [GCC_PIMEM_BCR] = { 0x0a000 },
3255 [GCC_QDSS_BCR] = { 0x0c000 },
3256 [GCC_USB_30_BCR] = { 0x0f000 },
3257 [GCC_USB_20_BCR] = { 0x12000 },
3258 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12038 },
3259 [GCC_QUSB2PHY_SEC_BCR] = { 0x1203c },
3260 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3261 [GCC_SDCC1_BCR] = { 0x13000 },
3262 [GCC_SDCC2_BCR] = { 0x14000 },
3263 [GCC_SDCC3_BCR] = { 0x15000 },
3264 [GCC_SDCC4_BCR] = { 0x16000 },
3265 [GCC_BLSP1_BCR] = { 0x17000 },
3266 [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
3267 [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
3268 [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
3269 [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
3270 [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
3271 [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
3272 [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
3273 [GCC_BLSP1_UART4_BCR] = { 0x20000 },
3274 [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
3275 [GCC_BLSP1_UART5_BCR] = { 0x22000 },
3276 [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
3277 [GCC_BLSP1_UART6_BCR] = { 0x24000 },
3278 [GCC_BLSP2_BCR] = { 0x25000 },
3279 [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
3280 [GCC_BLSP2_UART1_BCR] = { 0x27000 },
3281 [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
3282 [GCC_BLSP2_UART2_BCR] = { 0x29000 },
3283 [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
3284 [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
3285 [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
3286 [GCC_BLSP2_UART4_BCR] = { 0x2d000 },
3287 [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
3288 [GCC_BLSP2_UART5_BCR] = { 0x2f000 },
3289 [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
3290 [GCC_BLSP2_UART6_BCR] = { 0x31000 },
3291 [GCC_PDM_BCR] = { 0x33000 },
3292 [GCC_PRNG_BCR] = { 0x34000 },
3293 [GCC_TSIF_BCR] = { 0x36000 },
3294 [GCC_TCSR_BCR] = { 0x37000 },
3295 [GCC_BOOT_ROM_BCR] = { 0x38000 },
3296 [GCC_MSG_RAM_BCR] = { 0x39000 },
3297 [GCC_TLMM_BCR] = { 0x3a000 },
3298 [GCC_MPM_BCR] = { 0x3b000 },
3299 [GCC_SEC_CTRL_BCR] = { 0x3d000 },
3300 [GCC_SPMI_BCR] = { 0x3f000 },
3301 [GCC_SPDM_BCR] = { 0x40000 },
3302 [GCC_CE1_BCR] = { 0x41000 },
3303 [GCC_BIMC_BCR] = { 0x44000 },
3304 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
3305 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x49008 },
3306 [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49010 },
3307 [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49018 },
3308 [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49020 },
3309 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
3310 [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x4a008 },
3311 [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x4a010 },
3312 [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x4a018 },
3313 [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x4a020 },
3314 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
3315 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
3316 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
3317 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
3318 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
3319 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
3320 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
3321 [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
3322 [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
3323 [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
3324 [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80010 },
3325 [GCC_APB2JTAG_BCR] = { 0x4c000 },
3326 [GCC_RBCPR_CX_BCR] = { 0x4e000 },
3327 [GCC_RBCPR_MX_BCR] = { 0x4f000 },
3328 [GCC_PCIE_0_BCR] = { 0x6b000 },
3329 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3330 [GCC_PCIE_1_BCR] = { 0x6d000 },
3331 [GCC_PCIE_1_PHY_BCR] = { 0x6d038 },
3332 [GCC_PCIE_2_BCR] = { 0x6e000 },
3333 [GCC_PCIE_2_PHY_BCR] = { 0x6e038 },
3334 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3335 [GCC_DCD_BCR] = { 0x70000 },
3336 [GCC_OBT_ODT_BCR] = { 0x73000 },
3337 [GCC_UFS_BCR] = { 0x75000 },
3338 [GCC_SSC_BCR] = { 0x63000 },
3339 [GCC_VS_BCR] = { 0x7a000 },
3340 [GCC_AGGRE0_NOC_BCR] = { 0x81000 },
3341 [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
3342 [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
3343 [GCC_DCC_BCR] = { 0x84000 },
3344 [GCC_IPA_BCR] = { 0x89000 },
3345 [GCC_QSPI_BCR] = { 0x8b000 },
3346 [GCC_SKL_BCR] = { 0x8c000 },
3347 [GCC_MSMPU_BCR] = { 0x8d000 },
3348 [GCC_MSS_Q6_BCR] = { 0x8e000 },
3349 [GCC_QREFS_VBG_CAL_BCR] = { 0x88020 },
3350};
3351
3352static const struct regmap_config gcc_msm8996_regmap_config = {
3353 .reg_bits = 32,
3354 .reg_stride = 4,
3355 .val_bits = 32,
3356 .max_register = 0x8f010,
3357 .fast_io = true,
3358};
3359
3360static const struct qcom_cc_desc gcc_msm8996_desc = {
3361 .config = &gcc_msm8996_regmap_config,
3362 .clks = gcc_msm8996_clocks,
3363 .num_clks = ARRAY_SIZE(gcc_msm8996_clocks),
3364 .resets = gcc_msm8996_resets,
3365 .num_resets = ARRAY_SIZE(gcc_msm8996_resets),
3366};
3367
3368static const struct of_device_id gcc_msm8996_match_table[] = {
3369 { .compatible = "qcom,gcc-msm8996" },
3370 { }
3371};
3372MODULE_DEVICE_TABLE(of, gcc_msm8996_match_table);
3373
3374static int gcc_msm8996_probe(struct platform_device *pdev)
3375{
3376 struct clk *clk;
3377 struct device *dev = &pdev->dev;
3378 int i;
3379 struct regmap *regmap;
3380
3381 regmap = qcom_cc_map(pdev, &gcc_msm8996_desc);
3382 if (IS_ERR(regmap))
3383 return PTR_ERR(regmap);
3384
3385 /*
3386 * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
3387 * turned off by hardware during certain apps low power modes.
3388 */
3389 regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
3390
3391 for (i = 0; i < ARRAY_SIZE(gcc_msm8996_hws); i++) {
3392 clk = devm_clk_register(dev, gcc_msm8996_hws[i]);
3393 if (IS_ERR(clk))
3394 return PTR_ERR(clk);
3395 }
3396
3397 return qcom_cc_really_probe(pdev, &gcc_msm8996_desc, regmap);
3398}
3399
3400static struct platform_driver gcc_msm8996_driver = {
3401 .probe = gcc_msm8996_probe,
3402 .driver = {
3403 .name = "gcc-msm8996",
3404 .of_match_table = gcc_msm8996_match_table,
3405 },
3406};
3407
3408static int __init gcc_msm8996_init(void)
3409{
3410 return platform_driver_register(&gcc_msm8996_driver);
3411}
3412core_initcall(gcc_msm8996_init);
3413
3414static void __exit gcc_msm8996_exit(void)
3415{
3416 platform_driver_unregister(&gcc_msm8996_driver);
3417}
3418module_exit(gcc_msm8996_exit);
3419
3420MODULE_DESCRIPTION("QCOM GCC MSM8996 Driver");
3421MODULE_LICENSE("GPL v2");
3422MODULE_ALIAS("platform:gcc-msm8996");
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h b/include/dt-bindings/clock/qcom,gcc-msm8996.h
new file mode 100644
index 000000000000..888e75ce8fec
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-msm8996.h
@@ -0,0 +1,339 @@
1/*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H
15#define _DT_BINDINGS_CLK_MSM_GCC_8996_H
16
17#define GPLL0_EARLY 0
18#define GPLL0 1
19#define GPLL1_EARLY 2
20#define GPLL1 3
21#define GPLL2_EARLY 4
22#define GPLL2 5
23#define GPLL3_EARLY 6
24#define GPLL3 7
25#define GPLL4_EARLY 8
26#define GPLL4 9
27#define SYSTEM_NOC_CLK_SRC 10
28#define CONFIG_NOC_CLK_SRC 11
29#define PERIPH_NOC_CLK_SRC 12
30#define MMSS_BIMC_GFX_CLK_SRC 13
31#define USB30_MASTER_CLK_SRC 14
32#define USB30_MOCK_UTMI_CLK_SRC 15
33#define USB3_PHY_AUX_CLK_SRC 16
34#define USB20_MASTER_CLK_SRC 17
35#define USB20_MOCK_UTMI_CLK_SRC 18
36#define SDCC1_APPS_CLK_SRC 19
37#define SDCC1_ICE_CORE_CLK_SRC 20
38#define SDCC2_APPS_CLK_SRC 21
39#define SDCC3_APPS_CLK_SRC 22
40#define SDCC4_APPS_CLK_SRC 23
41#define BLSP1_QUP1_SPI_APPS_CLK_SRC 24
42#define BLSP1_QUP1_I2C_APPS_CLK_SRC 25
43#define BLSP1_UART1_APPS_CLK_SRC 26
44#define BLSP1_QUP2_SPI_APPS_CLK_SRC 27
45#define BLSP1_QUP2_I2C_APPS_CLK_SRC 28
46#define BLSP1_UART2_APPS_CLK_SRC 29
47#define BLSP1_QUP3_SPI_APPS_CLK_SRC 30
48#define BLSP1_QUP3_I2C_APPS_CLK_SRC 31
49#define BLSP1_UART3_APPS_CLK_SRC 32
50#define BLSP1_QUP4_SPI_APPS_CLK_SRC 33
51#define BLSP1_QUP4_I2C_APPS_CLK_SRC 34
52#define BLSP1_UART4_APPS_CLK_SRC 35
53#define BLSP1_QUP5_SPI_APPS_CLK_SRC 36
54#define BLSP1_QUP5_I2C_APPS_CLK_SRC 37
55#define BLSP1_UART5_APPS_CLK_SRC 38
56#define BLSP1_QUP6_SPI_APPS_CLK_SRC 39
57#define BLSP1_QUP6_I2C_APPS_CLK_SRC 40
58#define BLSP1_UART6_APPS_CLK_SRC 41
59#define BLSP2_QUP1_SPI_APPS_CLK_SRC 42
60#define BLSP2_QUP1_I2C_APPS_CLK_SRC 43
61#define BLSP2_UART1_APPS_CLK_SRC 44
62#define BLSP2_QUP2_SPI_APPS_CLK_SRC 45
63#define BLSP2_QUP2_I2C_APPS_CLK_SRC 46
64#define BLSP2_UART2_APPS_CLK_SRC 47
65#define BLSP2_QUP3_SPI_APPS_CLK_SRC 48
66#define BLSP2_QUP3_I2C_APPS_CLK_SRC 49
67#define BLSP2_UART3_APPS_CLK_SRC 50
68#define BLSP2_QUP4_SPI_APPS_CLK_SRC 51
69#define BLSP2_QUP4_I2C_APPS_CLK_SRC 52
70#define BLSP2_UART4_APPS_CLK_SRC 53
71#define BLSP2_QUP5_SPI_APPS_CLK_SRC 54
72#define BLSP2_QUP5_I2C_APPS_CLK_SRC 55
73#define BLSP2_UART5_APPS_CLK_SRC 56
74#define BLSP2_QUP6_SPI_APPS_CLK_SRC 57
75#define BLSP2_QUP6_I2C_APPS_CLK_SRC 58
76#define BLSP2_UART6_APPS_CLK_SRC 59
77#define PDM2_CLK_SRC 60
78#define TSIF_REF_CLK_SRC 61
79#define CE1_CLK_SRC 62
80#define GCC_SLEEP_CLK_SRC 63
81#define BIMC_CLK_SRC 64
82#define HMSS_AHB_CLK_SRC 65
83#define BIMC_HMSS_AXI_CLK_SRC 66
84#define HMSS_RBCPR_CLK_SRC 67
85#define HMSS_GPLL0_CLK_SRC 68
86#define GP1_CLK_SRC 69
87#define GP2_CLK_SRC 70
88#define GP3_CLK_SRC 71
89#define PCIE_AUX_CLK_SRC 72
90#define UFS_AXI_CLK_SRC 73
91#define UFS_ICE_CORE_CLK_SRC 74
92#define QSPI_SER_CLK_SRC 75
93#define GCC_SYS_NOC_AXI_CLK 76
94#define GCC_SYS_NOC_HMSS_AHB_CLK 77
95#define GCC_SNOC_CNOC_AHB_CLK 78
96#define GCC_SNOC_PNOC_AHB_CLK 79
97#define GCC_SYS_NOC_AT_CLK 80
98#define GCC_SYS_NOC_USB3_AXI_CLK 81
99#define GCC_SYS_NOC_UFS_AXI_CLK 82
100#define GCC_CFG_NOC_AHB_CLK 83
101#define GCC_PERIPH_NOC_AHB_CLK 84
102#define GCC_PERIPH_NOC_USB20_AHB_CLK 85
103#define GCC_TIC_CLK 86
104#define GCC_IMEM_AXI_CLK 87
105#define GCC_MMSS_SYS_NOC_AXI_CLK 88
106#define GCC_MMSS_NOC_CFG_AHB_CLK 89
107#define GCC_MMSS_BIMC_GFX_CLK 90
108#define GCC_USB30_MASTER_CLK 91
109#define GCC_USB30_SLEEP_CLK 92
110#define GCC_USB30_MOCK_UTMI_CLK 93
111#define GCC_USB3_PHY_AUX_CLK 94
112#define GCC_USB3_PHY_PIPE_CLK 95
113#define GCC_USB20_MASTER_CLK 96
114#define GCC_USB20_SLEEP_CLK 97
115#define GCC_USB20_MOCK_UTMI_CLK 98
116#define GCC_USB_PHY_CFG_AHB2PHY_CLK 99
117#define GCC_SDCC1_APPS_CLK 100
118#define GCC_SDCC1_AHB_CLK 101
119#define GCC_SDCC1_ICE_CORE_CLK 102
120#define GCC_SDCC2_APPS_CLK 103
121#define GCC_SDCC2_AHB_CLK 104
122#define GCC_SDCC3_APPS_CLK 105
123#define GCC_SDCC3_AHB_CLK 106
124#define GCC_SDCC4_APPS_CLK 107
125#define GCC_SDCC4_AHB_CLK 108
126#define GCC_BLSP1_AHB_CLK 109
127#define GCC_BLSP1_SLEEP_CLK 110
128#define GCC_BLSP1_QUP1_SPI_APPS_CLK 111
129#define GCC_BLSP1_QUP1_I2C_APPS_CLK 112
130#define GCC_BLSP1_UART1_APPS_CLK 113
131#define GCC_BLSP1_QUP2_SPI_APPS_CLK 114
132#define GCC_BLSP1_QUP2_I2C_APPS_CLK 115
133#define GCC_BLSP1_UART2_APPS_CLK 116
134#define GCC_BLSP1_QUP3_SPI_APPS_CLK 117
135#define GCC_BLSP1_QUP3_I2C_APPS_CLK 118
136#define GCC_BLSP1_UART3_APPS_CLK 119
137#define GCC_BLSP1_QUP4_SPI_APPS_CLK 120
138#define GCC_BLSP1_QUP4_I2C_APPS_CLK 121
139#define GCC_BLSP1_UART4_APPS_CLK 122
140#define GCC_BLSP1_QUP5_SPI_APPS_CLK 123
141#define GCC_BLSP1_QUP5_I2C_APPS_CLK 124
142#define GCC_BLSP1_UART5_APPS_CLK 125
143#define GCC_BLSP1_QUP6_SPI_APPS_CLK 126
144#define GCC_BLSP1_QUP6_I2C_APPS_CLK 127
145#define GCC_BLSP1_UART6_APPS_CLK 128
146#define GCC_BLSP2_AHB_CLK 129
147#define GCC_BLSP2_SLEEP_CLK 130
148#define GCC_BLSP2_QUP1_SPI_APPS_CLK 131
149#define GCC_BLSP2_QUP1_I2C_APPS_CLK 132
150#define GCC_BLSP2_UART1_APPS_CLK 133
151#define GCC_BLSP2_QUP2_SPI_APPS_CLK 134
152#define GCC_BLSP2_QUP2_I2C_APPS_CLK 135
153#define GCC_BLSP2_UART2_APPS_CLK 136
154#define GCC_BLSP2_QUP3_SPI_APPS_CLK 137
155#define GCC_BLSP2_QUP3_I2C_APPS_CLK 138
156#define GCC_BLSP2_UART3_APPS_CLK 139
157#define GCC_BLSP2_QUP4_SPI_APPS_CLK 140
158#define GCC_BLSP2_QUP4_I2C_APPS_CLK 141
159#define GCC_BLSP2_UART4_APPS_CLK 142
160#define GCC_BLSP2_QUP5_SPI_APPS_CLK 143
161#define GCC_BLSP2_QUP5_I2C_APPS_CLK 144
162#define GCC_BLSP2_UART5_APPS_CLK 145
163#define GCC_BLSP2_QUP6_SPI_APPS_CLK 146
164#define GCC_BLSP2_QUP6_I2C_APPS_CLK 147
165#define GCC_BLSP2_UART6_APPS_CLK 148
166#define GCC_PDM_AHB_CLK 149
167#define GCC_PDM_XO4_CLK 150
168#define GCC_PDM2_CLK 151
169#define GCC_PRNG_AHB_CLK 152
170#define GCC_TSIF_AHB_CLK 153
171#define GCC_TSIF_REF_CLK 154
172#define GCC_TSIF_INACTIVITY_TIMERS_CLK 155
173#define GCC_TCSR_AHB_CLK 156
174#define GCC_BOOT_ROM_AHB_CLK 157
175#define GCC_MSG_RAM_AHB_CLK 158
176#define GCC_TLMM_AHB_CLK 159
177#define GCC_TLMM_CLK 160
178#define GCC_MPM_AHB_CLK 161
179#define GCC_SPMI_SER_CLK 162
180#define GCC_SPMI_CNOC_AHB_CLK 163
181#define GCC_CE1_CLK 164
182#define GCC_CE1_AXI_CLK 165
183#define GCC_CE1_AHB_CLK 166
184#define GCC_BIMC_HMSS_AXI_CLK 167
185#define GCC_BIMC_GFX_CLK 168
186#define GCC_HMSS_AHB_CLK 169
187#define GCC_HMSS_SLV_AXI_CLK 170
188#define GCC_HMSS_MSTR_AXI_CLK 171
189#define GCC_HMSS_RBCPR_CLK 172
190#define GCC_GP1_CLK 173
191#define GCC_GP2_CLK 174
192#define GCC_GP3_CLK 175
193#define GCC_PCIE_0_SLV_AXI_CLK 176
194#define GCC_PCIE_0_MSTR_AXI_CLK 177
195#define GCC_PCIE_0_CFG_AHB_CLK 178
196#define GCC_PCIE_0_AUX_CLK 179
197#define GCC_PCIE_0_PIPE_CLK 180
198#define GCC_PCIE_1_SLV_AXI_CLK 181
199#define GCC_PCIE_1_MSTR_AXI_CLK 182
200#define GCC_PCIE_1_CFG_AHB_CLK 183
201#define GCC_PCIE_1_AUX_CLK 184
202#define GCC_PCIE_1_PIPE_CLK 185
203#define GCC_PCIE_2_SLV_AXI_CLK 186
204#define GCC_PCIE_2_MSTR_AXI_CLK 187
205#define GCC_PCIE_2_CFG_AHB_CLK 188
206#define GCC_PCIE_2_AUX_CLK 189
207#define GCC_PCIE_2_PIPE_CLK 190
208#define GCC_PCIE_PHY_CFG_AHB_CLK 191
209#define GCC_PCIE_PHY_AUX_CLK 192
210#define GCC_UFS_AXI_CLK 193
211#define GCC_UFS_AHB_CLK 194
212#define GCC_UFS_TX_CFG_CLK 195
213#define GCC_UFS_RX_CFG_CLK 196
214#define GCC_UFS_TX_SYMBOL_0_CLK 197
215#define GCC_UFS_RX_SYMBOL_0_CLK 198
216#define GCC_UFS_RX_SYMBOL_1_CLK 199
217#define GCC_UFS_UNIPRO_CORE_CLK 200
218#define GCC_UFS_ICE_CORE_CLK 201
219#define GCC_UFS_SYS_CLK_CORE_CLK 202
220#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK 203
221#define GCC_AGGRE0_SNOC_AXI_CLK 204
222#define GCC_AGGRE0_CNOC_AHB_CLK 205
223#define GCC_SMMU_AGGRE0_AXI_CLK 206
224#define GCC_SMMU_AGGRE0_AHB_CLK 207
225#define GCC_AGGRE1_PNOC_AHB_CLK 208
226#define GCC_AGGRE2_UFS_AXI_CLK 209
227#define GCC_AGGRE2_USB3_AXI_CLK 210
228#define GCC_QSPI_AHB_CLK 211
229#define GCC_QSPI_SER_CLK 212
230#define GCC_USB3_CLKREF_CLK 213
231#define GCC_HDMI_CLKREF_CLK 214
232#define GCC_UFS_CLKREF_CLK 215
233#define GCC_PCIE_CLKREF_CLK 216
234#define GCC_RX2_USB2_CLKREF_CLK 217
235#define GCC_RX1_USB2_CLKREF_CLK 218
236
237#define GCC_SYSTEM_NOC_BCR 0
238#define GCC_CONFIG_NOC_BCR 1
239#define GCC_PERIPH_NOC_BCR 2
240#define GCC_IMEM_BCR 3
241#define GCC_MMSS_BCR 4
242#define GCC_PIMEM_BCR 5
243#define GCC_QDSS_BCR 6
244#define GCC_USB_30_BCR 7
245#define GCC_USB_20_BCR 8
246#define GCC_QUSB2PHY_PRIM_BCR 9
247#define GCC_QUSB2PHY_SEC_BCR 10
248#define GCC_USB_PHY_CFG_AHB2PHY_BCR 11
249#define GCC_SDCC1_BCR 12
250#define GCC_SDCC2_BCR 13
251#define GCC_SDCC3_BCR 14
252#define GCC_SDCC4_BCR 15
253#define GCC_BLSP1_BCR 16
254#define GCC_BLSP1_QUP1_BCR 17
255#define GCC_BLSP1_UART1_BCR 18
256#define GCC_BLSP1_QUP2_BCR 19
257#define GCC_BLSP1_UART2_BCR 20
258#define GCC_BLSP1_QUP3_BCR 21
259#define GCC_BLSP1_UART3_BCR 22
260#define GCC_BLSP1_QUP4_BCR 23
261#define GCC_BLSP1_UART4_BCR 24
262#define GCC_BLSP1_QUP5_BCR 25
263#define GCC_BLSP1_UART5_BCR 26
264#define GCC_BLSP1_QUP6_BCR 27
265#define GCC_BLSP1_UART6_BCR 28
266#define GCC_BLSP2_BCR 29
267#define GCC_BLSP2_QUP1_BCR 30
268#define GCC_BLSP2_UART1_BCR 31
269#define GCC_BLSP2_QUP2_BCR 32
270#define GCC_BLSP2_UART2_BCR 33
271#define GCC_BLSP2_QUP3_BCR 34
272#define GCC_BLSP2_UART3_BCR 35
273#define GCC_BLSP2_QUP4_BCR 36
274#define GCC_BLSP2_UART4_BCR 37
275#define GCC_BLSP2_QUP5_BCR 38
276#define GCC_BLSP2_UART5_BCR 39
277#define GCC_BLSP2_QUP6_BCR 40
278#define GCC_BLSP2_UART6_BCR 41
279#define GCC_PDM_BCR 42
280#define GCC_PRNG_BCR 43
281#define GCC_TSIF_BCR 44
282#define GCC_TCSR_BCR 45
283#define GCC_BOOT_ROM_BCR 46
284#define GCC_MSG_RAM_BCR 47
285#define GCC_TLMM_BCR 48
286#define GCC_MPM_BCR 49
287#define GCC_SEC_CTRL_BCR 50
288#define GCC_SPMI_BCR 51
289#define GCC_SPDM_BCR 52
290#define GCC_CE1_BCR 53
291#define GCC_BIMC_BCR 54
292#define GCC_SNOC_BUS_TIMEOUT0_BCR 55
293#define GCC_SNOC_BUS_TIMEOUT2_BCR 56
294#define GCC_SNOC_BUS_TIMEOUT1_BCR 57
295#define GCC_SNOC_BUS_TIMEOUT3_BCR 58
296#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 59
297#define GCC_PNOC_BUS_TIMEOUT0_BCR 60
298#define GCC_PNOC_BUS_TIMEOUT1_BCR 61
299#define GCC_PNOC_BUS_TIMEOUT2_BCR 62
300#define GCC_PNOC_BUS_TIMEOUT3_BCR 63
301#define GCC_PNOC_BUS_TIMEOUT4_BCR 64
302#define GCC_CNOC_BUS_TIMEOUT0_BCR 65
303#define GCC_CNOC_BUS_TIMEOUT1_BCR 66
304#define GCC_CNOC_BUS_TIMEOUT2_BCR 67
305#define GCC_CNOC_BUS_TIMEOUT3_BCR 68
306#define GCC_CNOC_BUS_TIMEOUT4_BCR 69
307#define GCC_CNOC_BUS_TIMEOUT5_BCR 70
308#define GCC_CNOC_BUS_TIMEOUT6_BCR 71
309#define GCC_CNOC_BUS_TIMEOUT7_BCR 72
310#define GCC_CNOC_BUS_TIMEOUT8_BCR 73
311#define GCC_CNOC_BUS_TIMEOUT9_BCR 74
312#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 75
313#define GCC_APB2JTAG_BCR 76
314#define GCC_RBCPR_CX_BCR 77
315#define GCC_RBCPR_MX_BCR 78
316#define GCC_PCIE_0_BCR 79
317#define GCC_PCIE_0_PHY_BCR 80
318#define GCC_PCIE_1_BCR 81
319#define GCC_PCIE_1_PHY_BCR 82
320#define GCC_PCIE_2_BCR 83
321#define GCC_PCIE_2_PHY_BCR 84
322#define GCC_PCIE_PHY_BCR 85
323#define GCC_DCD_BCR 86
324#define GCC_OBT_ODT_BCR 87
325#define GCC_UFS_BCR 88
326#define GCC_SSC_BCR 89
327#define GCC_VS_BCR 90
328#define GCC_AGGRE0_NOC_BCR 91
329#define GCC_AGGRE1_NOC_BCR 92
330#define GCC_AGGRE2_NOC_BCR 93
331#define GCC_DCC_BCR 94
332#define GCC_IPA_BCR 95
333#define GCC_QSPI_BCR 96
334#define GCC_SKL_BCR 97
335#define GCC_MSMPU_BCR 98
336#define GCC_MSS_Q6_BCR 99
337#define GCC_QREFS_VBG_CAL_BCR 100
338
339#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-25 00:30:08 -0500