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authorChris Wilson <chris@chris-wilson.co.uk>2016-08-18 12:16:51 -0400
committerChris Wilson <chris@chris-wilson.co.uk>2016-08-18 17:36:46 -0400
commitb0dc465f9540a8659ae06be08c6fcfc04c874777 (patch)
tree26838239c004c66ae1883ab120aa47d642a962c1
parent9764951e7f517717bc7ecc3f1a9711816646ebf7 (diff)
drm/i915: Tidy up flush cpu/gtt write domains
Since we know the write domain, we can drop the local variable and make the code look a tiny bit simpler. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20160818161718.27187-12-chris@chris-wilson.co.uk
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c15
1 files changed, 4 insertions, 11 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c5d5dfe3e0ef..cfec2ff4fc7c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3182,7 +3182,6 @@ static void
3182i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) 3182i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3183{ 3183{
3184 struct drm_i915_private *dev_priv = to_i915(obj->base.dev); 3184 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3185 uint32_t old_write_domain;
3186 3185
3187 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) 3186 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3188 return; 3187 return;
@@ -3206,36 +3205,30 @@ i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3206 if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) 3205 if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv))
3207 POSTING_READ(RING_ACTHD(dev_priv->engine[RCS].mmio_base)); 3206 POSTING_READ(RING_ACTHD(dev_priv->engine[RCS].mmio_base));
3208 3207
3209 old_write_domain = obj->base.write_domain;
3210 obj->base.write_domain = 0;
3211
3212 intel_fb_obj_flush(obj, false, write_origin(obj, I915_GEM_DOMAIN_GTT)); 3208 intel_fb_obj_flush(obj, false, write_origin(obj, I915_GEM_DOMAIN_GTT));
3213 3209
3210 obj->base.write_domain = 0;
3214 trace_i915_gem_object_change_domain(obj, 3211 trace_i915_gem_object_change_domain(obj,
3215 obj->base.read_domains, 3212 obj->base.read_domains,
3216 old_write_domain); 3213 I915_GEM_DOMAIN_GTT);
3217} 3214}
3218 3215
3219/** Flushes the CPU write domain for the object if it's dirty. */ 3216/** Flushes the CPU write domain for the object if it's dirty. */
3220static void 3217static void
3221i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) 3218i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3222{ 3219{
3223 uint32_t old_write_domain;
3224
3225 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) 3220 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3226 return; 3221 return;
3227 3222
3228 if (i915_gem_clflush_object(obj, obj->pin_display)) 3223 if (i915_gem_clflush_object(obj, obj->pin_display))
3229 i915_gem_chipset_flush(to_i915(obj->base.dev)); 3224 i915_gem_chipset_flush(to_i915(obj->base.dev));
3230 3225
3231 old_write_domain = obj->base.write_domain;
3232 obj->base.write_domain = 0;
3233
3234 intel_fb_obj_flush(obj, false, ORIGIN_CPU); 3226 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
3235 3227
3228 obj->base.write_domain = 0;
3236 trace_i915_gem_object_change_domain(obj, 3229 trace_i915_gem_object_change_domain(obj,
3237 obj->base.read_domains, 3230 obj->base.read_domains,
3238 old_write_domain); 3231 I915_GEM_DOMAIN_CPU);
3239} 3232}
3240 3233
3241/** 3234/**