diff options
author | Vivien Didelot <vivien.didelot@savoirfairelinux.com> | 2016-09-29 12:22:01 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2016-09-30 01:26:00 -0400 |
commit | b073d4e2b16a42f7d5b01814307ff41012c2e1ea (patch) | |
tree | e85fb8120b21246c9ce7953c90f9ae4d46380950 | |
parent | b3469dd8adade11e8234854d79b43daf8ce478c9 (diff) |
net: dsa: mv88e6xxx: add set_switch_mac to ops
Add a set_switch_mac chip-wide function to mv88e6xxx_ops and remove
MV88E6XXX_FLAG_G2_SWITCH_MAC flags.
Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r-- | drivers/net/dsa/mv88e6xxx/chip.c | 28 | ||||
-rw-r--r-- | drivers/net/dsa/mv88e6xxx/mv88e6xxx.h | 8 |
2 files changed, 23 insertions, 13 deletions
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index 83a37693a8db..e40b71ba871c 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c | |||
@@ -2909,14 +2909,11 @@ static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr) | |||
2909 | struct mv88e6xxx_chip *chip = ds->priv; | 2909 | struct mv88e6xxx_chip *chip = ds->priv; |
2910 | int err; | 2910 | int err; |
2911 | 2911 | ||
2912 | mutex_lock(&chip->reg_lock); | 2912 | if (!chip->info->ops->set_switch_mac) |
2913 | 2913 | return -EOPNOTSUPP; | |
2914 | /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */ | ||
2915 | if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC)) | ||
2916 | err = mv88e6xxx_g2_set_switch_mac(chip, addr); | ||
2917 | else | ||
2918 | err = mv88e6xxx_g1_set_switch_mac(chip, addr); | ||
2919 | 2914 | ||
2915 | mutex_lock(&chip->reg_lock); | ||
2916 | err = chip->info->ops->set_switch_mac(chip, addr); | ||
2920 | mutex_unlock(&chip->reg_lock); | 2917 | mutex_unlock(&chip->reg_lock); |
2921 | 2918 | ||
2922 | return err; | 2919 | return err; |
@@ -3210,86 +3207,103 @@ static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, | |||
3210 | } | 3207 | } |
3211 | 3208 | ||
3212 | static const struct mv88e6xxx_ops mv88e6085_ops = { | 3209 | static const struct mv88e6xxx_ops mv88e6085_ops = { |
3210 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, | ||
3213 | .phy_read = mv88e6xxx_phy_ppu_read, | 3211 | .phy_read = mv88e6xxx_phy_ppu_read, |
3214 | .phy_write = mv88e6xxx_phy_ppu_write, | 3212 | .phy_write = mv88e6xxx_phy_ppu_write, |
3215 | }; | 3213 | }; |
3216 | 3214 | ||
3217 | static const struct mv88e6xxx_ops mv88e6095_ops = { | 3215 | static const struct mv88e6xxx_ops mv88e6095_ops = { |
3216 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, | ||
3218 | .phy_read = mv88e6xxx_phy_ppu_read, | 3217 | .phy_read = mv88e6xxx_phy_ppu_read, |
3219 | .phy_write = mv88e6xxx_phy_ppu_write, | 3218 | .phy_write = mv88e6xxx_phy_ppu_write, |
3220 | }; | 3219 | }; |
3221 | 3220 | ||
3222 | static const struct mv88e6xxx_ops mv88e6123_ops = { | 3221 | static const struct mv88e6xxx_ops mv88e6123_ops = { |
3222 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, | ||
3223 | .phy_read = mv88e6xxx_read, | 3223 | .phy_read = mv88e6xxx_read, |
3224 | .phy_write = mv88e6xxx_write, | 3224 | .phy_write = mv88e6xxx_write, |
3225 | }; | 3225 | }; |
3226 | 3226 | ||
3227 | static const struct mv88e6xxx_ops mv88e6131_ops = { | 3227 | static const struct mv88e6xxx_ops mv88e6131_ops = { |
3228 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, | ||
3228 | .phy_read = mv88e6xxx_phy_ppu_read, | 3229 | .phy_read = mv88e6xxx_phy_ppu_read, |
3229 | .phy_write = mv88e6xxx_phy_ppu_write, | 3230 | .phy_write = mv88e6xxx_phy_ppu_write, |
3230 | }; | 3231 | }; |
3231 | 3232 | ||
3232 | static const struct mv88e6xxx_ops mv88e6161_ops = { | 3233 | static const struct mv88e6xxx_ops mv88e6161_ops = { |
3234 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, | ||
3233 | .phy_read = mv88e6xxx_read, | 3235 | .phy_read = mv88e6xxx_read, |
3234 | .phy_write = mv88e6xxx_write, | 3236 | .phy_write = mv88e6xxx_write, |
3235 | }; | 3237 | }; |
3236 | 3238 | ||
3237 | static const struct mv88e6xxx_ops mv88e6165_ops = { | 3239 | static const struct mv88e6xxx_ops mv88e6165_ops = { |
3240 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, | ||
3238 | .phy_read = mv88e6xxx_read, | 3241 | .phy_read = mv88e6xxx_read, |
3239 | .phy_write = mv88e6xxx_write, | 3242 | .phy_write = mv88e6xxx_write, |
3240 | }; | 3243 | }; |
3241 | 3244 | ||
3242 | static const struct mv88e6xxx_ops mv88e6171_ops = { | 3245 | static const struct mv88e6xxx_ops mv88e6171_ops = { |
3246 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, | ||
3243 | .phy_read = mv88e6xxx_g2_smi_phy_read, | 3247 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3244 | .phy_write = mv88e6xxx_g2_smi_phy_write, | 3248 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
3245 | }; | 3249 | }; |
3246 | 3250 | ||
3247 | static const struct mv88e6xxx_ops mv88e6172_ops = { | 3251 | static const struct mv88e6xxx_ops mv88e6172_ops = { |
3252 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, | ||
3248 | .phy_read = mv88e6xxx_g2_smi_phy_read, | 3253 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3249 | .phy_write = mv88e6xxx_g2_smi_phy_write, | 3254 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
3250 | }; | 3255 | }; |
3251 | 3256 | ||
3252 | static const struct mv88e6xxx_ops mv88e6175_ops = { | 3257 | static const struct mv88e6xxx_ops mv88e6175_ops = { |
3258 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, | ||
3253 | .phy_read = mv88e6xxx_g2_smi_phy_read, | 3259 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3254 | .phy_write = mv88e6xxx_g2_smi_phy_write, | 3260 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
3255 | }; | 3261 | }; |
3256 | 3262 | ||
3257 | static const struct mv88e6xxx_ops mv88e6176_ops = { | 3263 | static const struct mv88e6xxx_ops mv88e6176_ops = { |
3264 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, | ||
3258 | .phy_read = mv88e6xxx_g2_smi_phy_read, | 3265 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3259 | .phy_write = mv88e6xxx_g2_smi_phy_write, | 3266 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
3260 | }; | 3267 | }; |
3261 | 3268 | ||
3262 | static const struct mv88e6xxx_ops mv88e6185_ops = { | 3269 | static const struct mv88e6xxx_ops mv88e6185_ops = { |
3270 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, | ||
3263 | .phy_read = mv88e6xxx_phy_ppu_read, | 3271 | .phy_read = mv88e6xxx_phy_ppu_read, |
3264 | .phy_write = mv88e6xxx_phy_ppu_write, | 3272 | .phy_write = mv88e6xxx_phy_ppu_write, |
3265 | }; | 3273 | }; |
3266 | 3274 | ||
3267 | static const struct mv88e6xxx_ops mv88e6240_ops = { | 3275 | static const struct mv88e6xxx_ops mv88e6240_ops = { |
3276 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, | ||
3268 | .phy_read = mv88e6xxx_g2_smi_phy_read, | 3277 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3269 | .phy_write = mv88e6xxx_g2_smi_phy_write, | 3278 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
3270 | }; | 3279 | }; |
3271 | 3280 | ||
3272 | static const struct mv88e6xxx_ops mv88e6320_ops = { | 3281 | static const struct mv88e6xxx_ops mv88e6320_ops = { |
3282 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, | ||
3273 | .phy_read = mv88e6xxx_g2_smi_phy_read, | 3283 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3274 | .phy_write = mv88e6xxx_g2_smi_phy_write, | 3284 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
3275 | }; | 3285 | }; |
3276 | 3286 | ||
3277 | static const struct mv88e6xxx_ops mv88e6321_ops = { | 3287 | static const struct mv88e6xxx_ops mv88e6321_ops = { |
3288 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, | ||
3278 | .phy_read = mv88e6xxx_g2_smi_phy_read, | 3289 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3279 | .phy_write = mv88e6xxx_g2_smi_phy_write, | 3290 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
3280 | }; | 3291 | }; |
3281 | 3292 | ||
3282 | static const struct mv88e6xxx_ops mv88e6350_ops = { | 3293 | static const struct mv88e6xxx_ops mv88e6350_ops = { |
3294 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, | ||
3283 | .phy_read = mv88e6xxx_g2_smi_phy_read, | 3295 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3284 | .phy_write = mv88e6xxx_g2_smi_phy_write, | 3296 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
3285 | }; | 3297 | }; |
3286 | 3298 | ||
3287 | static const struct mv88e6xxx_ops mv88e6351_ops = { | 3299 | static const struct mv88e6xxx_ops mv88e6351_ops = { |
3300 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, | ||
3288 | .phy_read = mv88e6xxx_g2_smi_phy_read, | 3301 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3289 | .phy_write = mv88e6xxx_g2_smi_phy_write, | 3302 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
3290 | }; | 3303 | }; |
3291 | 3304 | ||
3292 | static const struct mv88e6xxx_ops mv88e6352_ops = { | 3305 | static const struct mv88e6xxx_ops mv88e6352_ops = { |
3306 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, | ||
3293 | .phy_read = mv88e6xxx_g2_smi_phy_read, | 3307 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3294 | .phy_write = mv88e6xxx_g2_smi_phy_write, | 3308 | .phy_write = mv88e6xxx_g2_smi_phy_write, |
3295 | }; | 3309 | }; |
diff --git a/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h b/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h index 8e1290278ef6..d04184c7e068 100644 --- a/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h +++ b/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h | |||
@@ -423,7 +423,6 @@ enum mv88e6xxx_cap { | |||
423 | MV88E6XXX_CAP_G2_IRL_DATA, /* (0x0a) Ingress Rate Data */ | 423 | MV88E6XXX_CAP_G2_IRL_DATA, /* (0x0a) Ingress Rate Data */ |
424 | MV88E6XXX_CAP_G2_PVT_ADDR, /* (0x0b) Cross Chip Port VLAN Addr */ | 424 | MV88E6XXX_CAP_G2_PVT_ADDR, /* (0x0b) Cross Chip Port VLAN Addr */ |
425 | MV88E6XXX_CAP_G2_PVT_DATA, /* (0x0c) Cross Chip Port VLAN Data */ | 425 | MV88E6XXX_CAP_G2_PVT_DATA, /* (0x0c) Cross Chip Port VLAN Data */ |
426 | MV88E6XXX_CAP_G2_SWITCH_MAC, /* (0x0d) Switch MAC/WoL/WoF */ | ||
427 | MV88E6XXX_CAP_G2_POT, /* (0x0f) Priority Override Table */ | 426 | MV88E6XXX_CAP_G2_POT, /* (0x0f) Priority Override Table */ |
428 | MV88E6XXX_CAP_G2_EEPROM_CMD, /* (0x14) EEPROM Command */ | 427 | MV88E6XXX_CAP_G2_EEPROM_CMD, /* (0x14) EEPROM Command */ |
429 | MV88E6XXX_CAP_G2_EEPROM_DATA, /* (0x15) EEPROM Data */ | 428 | MV88E6XXX_CAP_G2_EEPROM_DATA, /* (0x15) EEPROM Data */ |
@@ -473,7 +472,6 @@ enum mv88e6xxx_cap { | |||
473 | #define MV88E6XXX_FLAG_G2_IRL_DATA BIT_ULL(MV88E6XXX_CAP_G2_IRL_DATA) | 472 | #define MV88E6XXX_FLAG_G2_IRL_DATA BIT_ULL(MV88E6XXX_CAP_G2_IRL_DATA) |
474 | #define MV88E6XXX_FLAG_G2_PVT_ADDR BIT_ULL(MV88E6XXX_CAP_G2_PVT_ADDR) | 473 | #define MV88E6XXX_FLAG_G2_PVT_ADDR BIT_ULL(MV88E6XXX_CAP_G2_PVT_ADDR) |
475 | #define MV88E6XXX_FLAG_G2_PVT_DATA BIT_ULL(MV88E6XXX_CAP_G2_PVT_DATA) | 474 | #define MV88E6XXX_FLAG_G2_PVT_DATA BIT_ULL(MV88E6XXX_CAP_G2_PVT_DATA) |
476 | #define MV88E6XXX_FLAG_G2_SWITCH_MAC BIT_ULL(MV88E6XXX_CAP_G2_SWITCH_MAC) | ||
477 | #define MV88E6XXX_FLAG_G2_POT BIT_ULL(MV88E6XXX_CAP_G2_POT) | 475 | #define MV88E6XXX_FLAG_G2_POT BIT_ULL(MV88E6XXX_CAP_G2_POT) |
478 | #define MV88E6XXX_FLAG_G2_EEPROM_CMD BIT_ULL(MV88E6XXX_CAP_G2_EEPROM_CMD) | 476 | #define MV88E6XXX_FLAG_G2_EEPROM_CMD BIT_ULL(MV88E6XXX_CAP_G2_EEPROM_CMD) |
479 | #define MV88E6XXX_FLAG_G2_EEPROM_DATA BIT_ULL(MV88E6XXX_CAP_G2_EEPROM_DATA) | 477 | #define MV88E6XXX_FLAG_G2_EEPROM_DATA BIT_ULL(MV88E6XXX_CAP_G2_EEPROM_DATA) |
@@ -537,7 +535,6 @@ enum mv88e6xxx_cap { | |||
537 | MV88E6XXX_FLAG_GLOBAL2 | \ | 535 | MV88E6XXX_FLAG_GLOBAL2 | \ |
538 | MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ | 536 | MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ |
539 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ | 537 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ |
540 | MV88E6XXX_FLAG_G2_SWITCH_MAC | \ | ||
541 | MV88E6XXX_FLAG_G2_POT | \ | 538 | MV88E6XXX_FLAG_G2_POT | \ |
542 | MV88E6XXX_FLAG_STU | \ | 539 | MV88E6XXX_FLAG_STU | \ |
543 | MV88E6XXX_FLAG_TEMP | \ | 540 | MV88E6XXX_FLAG_TEMP | \ |
@@ -559,7 +556,6 @@ enum mv88e6xxx_cap { | |||
559 | MV88E6XXX_FLAG_GLOBAL2 | \ | 556 | MV88E6XXX_FLAG_GLOBAL2 | \ |
560 | MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ | 557 | MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ |
561 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ | 558 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ |
562 | MV88E6XXX_FLAG_G2_SWITCH_MAC | \ | ||
563 | MV88E6XXX_FLAG_G2_POT | \ | 559 | MV88E6XXX_FLAG_G2_POT | \ |
564 | MV88E6XXX_FLAG_PPU_ACTIVE | \ | 560 | MV88E6XXX_FLAG_PPU_ACTIVE | \ |
565 | MV88E6XXX_FLAG_TEMP | \ | 561 | MV88E6XXX_FLAG_TEMP | \ |
@@ -577,7 +573,6 @@ enum mv88e6xxx_cap { | |||
577 | MV88E6XXX_FLAG_GLOBAL2 | \ | 573 | MV88E6XXX_FLAG_GLOBAL2 | \ |
578 | MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ | 574 | MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ |
579 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ | 575 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ |
580 | MV88E6XXX_FLAG_G2_SWITCH_MAC | \ | ||
581 | MV88E6XXX_FLAG_G2_POT | \ | 576 | MV88E6XXX_FLAG_G2_POT | \ |
582 | MV88E6XXX_FLAG_PPU_ACTIVE | \ | 577 | MV88E6XXX_FLAG_PPU_ACTIVE | \ |
583 | MV88E6XXX_FLAG_STU | \ | 578 | MV88E6XXX_FLAG_STU | \ |
@@ -595,7 +590,6 @@ enum mv88e6xxx_cap { | |||
595 | MV88E6XXX_FLAG_GLOBAL2 | \ | 590 | MV88E6XXX_FLAG_GLOBAL2 | \ |
596 | MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ | 591 | MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ |
597 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ | 592 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ |
598 | MV88E6XXX_FLAG_G2_SWITCH_MAC | \ | ||
599 | MV88E6XXX_FLAG_G2_POT | \ | 593 | MV88E6XXX_FLAG_G2_POT | \ |
600 | MV88E6XXX_FLAG_PPU_ACTIVE | \ | 594 | MV88E6XXX_FLAG_PPU_ACTIVE | \ |
601 | MV88E6XXX_FLAG_STU | \ | 595 | MV88E6XXX_FLAG_STU | \ |
@@ -702,6 +696,8 @@ struct mv88e6xxx_bus_ops { | |||
702 | }; | 696 | }; |
703 | 697 | ||
704 | struct mv88e6xxx_ops { | 698 | struct mv88e6xxx_ops { |
699 | int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); | ||
700 | |||
705 | int (*phy_read)(struct mv88e6xxx_chip *chip, int addr, int reg, | 701 | int (*phy_read)(struct mv88e6xxx_chip *chip, int addr, int reg, |
706 | u16 *val); | 702 | u16 *val); |
707 | int (*phy_write)(struct mv88e6xxx_chip *chip, int addr, int reg, | 703 | int (*phy_write)(struct mv88e6xxx_chip *chip, int addr, int reg, |