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authorLinus Torvalds <torvalds@linux-foundation.org>2016-10-08 00:16:16 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2016-10-08 00:16:16 -0400
commita771151a8323a5ca81f443a9a439851b8a872c85 (patch)
treee1cd1a77beae03bb03ec238c227ae26199998dc7
parent997b611baf7591ea5119539ee821a3e2f4fcf24e (diff)
parente13688fe618881dd407a68dfbd2295d70b21a445 (diff)
Merge tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanups from Arnd Bergmann: "The cleanups for v4.9 are a little larger that usual, but thankfully that is almost exclusively due to removing a significant number of files that have become obsolete after the still ongoing conversion of old board files to devicetree. - for mach-omap2, which is still the largest platform in arch/arm/, the conversion to DT is finally complete after the Nokia N900 is now fully supported there, along with the omap3 LDP, and we can remove those two board files. If no regressions are found, another large cleanup for the platform will happen as a follow-up, removing dead code and restructuring the platform based on being DT-only. - In mach-imx, similar work is ongoing, but has not come that far. This time, we remove the obsolete board file for the i.MX1 generation, which like i.MX25, i.MX5, i.MX6, and i.MX7 is now DT-only. The remaining board files are for i.MX2 and i.MX3 machines based on old ARM926 or ARM1136 cores that should work with DT in principle. - realview has just been converted from board files to DT, and a lot of code gets removed in the process. This is the last ARM/Keil/Versatile derived platform that was still using board files, the other ones being integrator, versatile and vexpress. We can probably merge the remaining code into a single directory in the near future. - clps711x had completed the conversion in v4.8, but we accidentally left the files in place that should have been deleted then" * tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (21 commits) ARM: select PCI_DOMAINS config from ARCH_MULTIPLATFORM ARM: stop *MIGHT_HAVE_PCI* config from being selected redundantly ARM: imx: (trivial) fix typo and grammar ARM: clps711x: remove extraneous files ARM: imx: use IS_ENABLED() instead of checking for built-in or module ARM: OMAP2+: use IS_ENABLED() instead of checking for built-in or module ARM: OMAP1: use IS_ENABLED() instead of checking for built-in or module ARM: imx: remove platform-mxc_rnga ARM: realview: imply device tree boot ARM: realview: no need to select SMP_ON_UP explicitly ARM: realview: delete the RealView board files ARM: imx: no need to select SMP_ON_UP explicitly ARM: i.MX: Move SOC_IMX1 into 'Device tree only' ARM: i.MX: Remove i.MX1 non-DT support ARM: i.MX: Remove i.MX1 Synertronixx SCB9328 board support ARM: i.MX: Remove i.MX1 Armadeus APF9328 board support ARM: mxs: remove obsolete startup code for TX28 ARM: i.MX31 iomux: remove duplicates with alternate name ARM: i.MX31 iomux: remove plain duplicates ARM: OMAP2+: Drop legacy board file for LDP ...
Diffstat
-rw-r--r--arch/arm/Kconfig4
-rw-r--r--arch/arm/configs/imx_v4_v5_defconfig3
-rw-r--r--arch/arm/configs/multi_v4t_defconfig4
-rw-r--r--arch/arm/mach-at91/Kconfig1
-rw-r--r--arch/arm/mach-axxia/Kconfig2
-rw-r--r--arch/arm/mach-clps711x/Makefile.boot0
-rw-r--r--arch/arm/mach-clps711x/board-autcpu12.c275
-rw-r--r--arch/arm/mach-clps711x/board-cdb89712.c147
-rw-r--r--arch/arm/mach-clps711x/board-clep7312.c45
-rw-r--r--arch/arm/mach-clps711x/board-edb7211.c188
-rw-r--r--arch/arm/mach-clps711x/board-p720t.c373
-rw-r--r--arch/arm/mach-clps711x/common.c65
-rw-r--r--arch/arm/mach-clps711x/common.h23
-rw-r--r--arch/arm/mach-clps711x/devices.c149
-rw-r--r--arch/arm/mach-clps711x/devices.h12
-rw-r--r--arch/arm/mach-cns3xxx/Kconfig1
-rw-r--r--arch/arm/mach-exynos/Kconfig2
-rw-r--r--arch/arm/mach-imx/Kconfig52
-rw-r--r--arch/arm/mach-imx/Makefile7
-rw-r--r--arch/arm/mach-imx/common.h5
-rw-r--r--arch/arm/mach-imx/devices-imx1.h30
-rw-r--r--arch/arm/mach-imx/devices/Makefile1
-rw-r--r--arch/arm/mach-imx/devices/devices-common.h12
-rw-r--r--arch/arm/mach-imx/devices/platform-imx-fb.c5
-rw-r--r--arch/arm/mach-imx/devices/platform-imx-i2c.c5
-rw-r--r--arch/arm/mach-imx/devices/platform-imx-uart.c37
-rw-r--r--arch/arm/mach-imx/devices/platform-spi_imx.c9
-rw-r--r--arch/arm/mach-imx/hardware.h3
-rw-r--r--arch/arm/mach-imx/iomux-mx1.h155
-rw-r--r--arch/arm/mach-imx/iomux-mx3.h34
-rw-r--r--arch/arm/mach-imx/mach-apf9328.c148
-rw-r--r--arch/arm/mach-imx/mach-imx1.c (renamed from arch/arm/mach-imx/imx1-dt.c)23
-rw-r--r--arch/arm/mach-imx/mach-kzm_arm11_01.c6
-rw-r--r--arch/arm/mach-imx/mach-pcm037.c2
-rw-r--r--arch/arm/mach-imx/mach-scb9328.c143
-rw-r--r--arch/arm/mach-imx/mm-imx1.c67
-rw-r--r--arch/arm/mach-imx/mx1.h172
-rw-r--r--arch/arm/mach-integrator/Kconfig1
-rw-r--r--arch/arm/mach-keystone/Kconfig2
-rw-r--r--arch/arm/mach-mxs/mach-mxs.c77
-rw-r--r--arch/arm/mach-omap1/board-h2-mmc.c2
-rw-r--r--arch/arm/mach-omap1/board-h2.c2
-rw-r--r--arch/arm/mach-omap1/board-h3-mmc.c2
-rw-r--r--arch/arm/mach-omap1/board-h3.c2
-rw-r--r--arch/arm/mach-omap1/board-htcherald.c4
-rw-r--r--arch/arm/mach-omap1/board-innovator.c4
-rw-r--r--arch/arm/mach-omap1/board-nokia770.c4
-rw-r--r--arch/arm/mach-omap1/board-sx1-mmc.c2
-rw-r--r--arch/arm/mach-omap1/devices.c10
-rw-r--r--arch/arm/mach-omap1/fb.c2
-rw-r--r--arch/arm/mach-omap1/include/mach/usb.h2
-rw-r--r--arch/arm/mach-omap1/mmc.h2
-rw-r--r--arch/arm/mach-omap1/usb.c6
-rw-r--r--arch/arm/mach-omap2/Kconfig12
-rw-r--r--arch/arm/mach-omap2/Makefile4
-rw-r--r--arch/arm/mach-omap2/board-flash.c10
-rw-r--r--arch/arm/mach-omap2/board-flash.h11
-rw-r--r--arch/arm/mach-omap2/board-ldp.c430
-rw-r--r--arch/arm/mach-omap2/board-n8x0.c5
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c1313
-rw-r--r--arch/arm/mach-omap2/board-rx51-video.c67
-rw-r--r--arch/arm/mach-omap2/board-rx51.c141
-rw-r--r--arch/arm/mach-omap2/board-rx51.h11
-rw-r--r--arch/arm/mach-omap2/common-board-devices.c3
-rw-r--r--arch/arm/mach-omap2/devices.c7
-rw-r--r--arch/arm/mach-omap2/drm.c2
-rw-r--r--arch/arm/mach-omap2/fb.c2
-rw-r--r--arch/arm/mach-omap2/gpmc-smsc911x.h2
-rw-r--r--arch/arm/mach-omap2/hsmmc.c2
-rw-r--r--arch/arm/mach-omap2/hsmmc.h2
-rw-r--r--arch/arm/mach-omap2/twl-common.c3
-rw-r--r--arch/arm/mach-realview/Kconfig72
-rw-r--r--arch/arm/mach-realview/Makefile12
-rw-r--r--arch/arm/mach-realview/board-eb.h94
-rw-r--r--arch/arm/mach-realview/board-pb1176.h81
-rw-r--r--arch/arm/mach-realview/board-pb11mp.h96
-rw-r--r--arch/arm/mach-realview/board-pba8.h71
-rw-r--r--arch/arm/mach-realview/board-pbx.h106
-rw-r--r--arch/arm/mach-realview/core.c405
-rw-r--r--arch/arm/mach-realview/core.h58
-rw-r--r--arch/arm/mach-realview/hardware.h40
-rw-r--r--arch/arm/mach-realview/hotplug.h1
-rw-r--r--arch/arm/mach-realview/irqs-eb.h114
-rw-r--r--arch/arm/mach-realview/irqs-pb1176.h77
-rw-r--r--arch/arm/mach-realview/irqs-pb11mp.h97
-rw-r--r--arch/arm/mach-realview/irqs-pba8.h71
-rw-r--r--arch/arm/mach-realview/irqs-pbx.h87
-rw-r--r--arch/arm/mach-realview/platform.h247
-rw-r--r--arch/arm/mach-realview/platsmp-dt.c3
-rw-r--r--arch/arm/mach-realview/platsmp.c86
-rw-r--r--arch/arm/mach-realview/realview_eb.c492
-rw-r--r--arch/arm/mach-realview/realview_pb1176.c395
-rw-r--r--arch/arm/mach-realview/realview_pb11mp.c385
-rw-r--r--arch/arm/mach-realview/realview_pba8.c307
-rw-r--r--arch/arm/mach-realview/realview_pbx.c402
-rw-r--r--arch/arm/mach-shmobile/Kconfig1
-rw-r--r--arch/arm/mach-spear/Kconfig1
-rw-r--r--arch/arm/mach-versatile/Kconfig1
-rw-r--r--drivers/clk/imx/clk-imx1.c46
-rw-r--r--drivers/irqchip/Makefile2
-rw-r--r--drivers/mtd/maps/Kconfig2
101 files changed, 105 insertions, 8108 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3cd9042fbb62..125657b602a4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -279,10 +279,9 @@ config PHYS_OFFSET
279 ARCH_INTEGRATOR || \ 279 ARCH_INTEGRATOR || \
280 ARCH_IOP13XX || \ 280 ARCH_IOP13XX || \
281 ARCH_KS8695 || \ 281 ARCH_KS8695 || \
282 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET) 282 ARCH_REALVIEW
283 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 283 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
284 default 0x20000000 if ARCH_S5PV210 284 default 0x20000000 if ARCH_S5PV210
285 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
286 default 0xc0000000 if ARCH_SA1100 285 default 0xc0000000 if ARCH_SA1100
287 help 286 help
288 Please provide the physical address corresponding to the 287 Please provide the physical address corresponding to the
@@ -338,6 +337,7 @@ config ARCH_MULTIPLATFORM
338 select GENERIC_CLOCKEVENTS 337 select GENERIC_CLOCKEVENTS
339 select MIGHT_HAVE_PCI 338 select MIGHT_HAVE_PCI
340 select MULTI_IRQ_HANDLER 339 select MULTI_IRQ_HANDLER
340 select PCI_DOMAINS if PCI
341 select SPARSE_IRQ 341 select SPARSE_IRQ
342 select USE_OF 342 select USE_OF
343 343
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index 9083399a8ab1..5f013c9fc1ed 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -22,14 +22,13 @@ CONFIG_ARCH_MULTI_V4T=y
22CONFIG_ARCH_MULTI_V5=y 22CONFIG_ARCH_MULTI_V5=y
23# CONFIG_ARCH_MULTI_V7 is not set 23# CONFIG_ARCH_MULTI_V7 is not set
24CONFIG_ARCH_MXC=y 24CONFIG_ARCH_MXC=y
25CONFIG_MACH_SCB9328=y
26CONFIG_MACH_APF9328=y
27CONFIG_MACH_MX21ADS=y 25CONFIG_MACH_MX21ADS=y
28CONFIG_MACH_MX27ADS=y 26CONFIG_MACH_MX27ADS=y
29CONFIG_MACH_MX27_3DS=y 27CONFIG_MACH_MX27_3DS=y
30CONFIG_MACH_IMX27_VISSTRIM_M10=y 28CONFIG_MACH_IMX27_VISSTRIM_M10=y
31CONFIG_MACH_PCA100=y 29CONFIG_MACH_PCA100=y
32CONFIG_MACH_IMX27_DT=y 30CONFIG_MACH_IMX27_DT=y
31CONFIG_SOC_IMX1=y
33CONFIG_SOC_IMX25=y 32CONFIG_SOC_IMX25=y
34CONFIG_PREEMPT=y 33CONFIG_PREEMPT=y
35CONFIG_AEABI=y 34CONFIG_AEABI=y
diff --git a/arch/arm/configs/multi_v4t_defconfig b/arch/arm/configs/multi_v4t_defconfig
index 433eebb4103f..9a6390c172d6 100644
--- a/arch/arm/configs/multi_v4t_defconfig
+++ b/arch/arm/configs/multi_v4t_defconfig
@@ -20,9 +20,7 @@ CONFIG_INTEGRATOR_CM720T=y
20CONFIG_INTEGRATOR_CM920T=y 20CONFIG_INTEGRATOR_CM920T=y
21CONFIG_INTEGRATOR_CM922T_XA10=y 21CONFIG_INTEGRATOR_CM922T_XA10=y
22CONFIG_ARCH_MXC=y 22CONFIG_ARCH_MXC=y
23CONFIG_MACH_SCB9328=y 23CONFIG_SOC_IMX1=y
24CONFIG_MACH_APF9328=y
25CONFIG_MACH_IMX1_DT=y
26CONFIG_ARCH_NSPIRE=y 24CONFIG_ARCH_NSPIRE=y
27CONFIG_AEABI=y 25CONFIG_AEABI=y
28# CONFIG_ATAGS is not set 26# CONFIG_ATAGS is not set
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 5204395efda8..841e924143f9 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -55,7 +55,6 @@ config SOC_AT91RM9200
55 select ATMEL_ST 55 select ATMEL_ST
56 select CPU_ARM920T 56 select CPU_ARM920T
57 select HAVE_AT91_USB_CLK 57 select HAVE_AT91_USB_CLK
58 select MIGHT_HAVE_PCI
59 select PINCTRL_AT91 58 select PINCTRL_AT91
60 select SOC_SAM_V4_V5 59 select SOC_SAM_V4_V5
61 select SRAM if PM 60 select SRAM if PM
diff --git a/arch/arm/mach-axxia/Kconfig b/arch/arm/mach-axxia/Kconfig
index 6c6d5e76565b..fe627cbcfdc5 100644
--- a/arch/arm/mach-axxia/Kconfig
+++ b/arch/arm/mach-axxia/Kconfig
@@ -7,8 +7,6 @@ config ARCH_AXXIA
7 select ARM_TIMER_SP804 7 select ARM_TIMER_SP804
8 select HAVE_ARM_ARCH_TIMER 8 select HAVE_ARM_ARCH_TIMER
9 select MFD_SYSCON 9 select MFD_SYSCON
10 select MIGHT_HAVE_PCI
11 select PCI_DOMAINS if PCI
12 select ZONE_DMA 10 select ZONE_DMA
13 help 11 help
14 This enables support for the LSI Axxia devices. 12 This enables support for the LSI Axxia devices.
diff --git a/arch/arm/mach-clps711x/Makefile.boot b/arch/arm/mach-clps711x/Makefile.boot
deleted file mode 100644
index e69de29bb2d1..000000000000
--- a/arch/arm/mach-clps711x/Makefile.boot
+++ /dev/null
diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c
deleted file mode 100644
index ba3d7d1b28f8..000000000000
--- a/arch/arm/mach-clps711x/board-autcpu12.c
+++ /dev/null
@@ -1,275 +0,0 @@
1/*
2 * linux/arch/arm/mach-clps711x/autcpu12.c
3 *
4 * (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/types.h>
23#include <linux/string.h>
24#include <linux/mm.h>
25#include <linux/io.h>
26#include <linux/gpio.h>
27#include <linux/ioport.h>
28#include <linux/interrupt.h>
29#include <linux/mtd/physmap.h>
30#include <linux/mtd/plat-ram.h>
31#include <linux/mtd/partitions.h>
32#include <linux/mtd/nand-gpio.h>
33#include <linux/platform_device.h>
34#include <linux/gpio/driver.h>
35
36#include <mach/hardware.h>
37#include <asm/sizes.h>
38#include <asm/setup.h>
39#include <asm/mach-types.h>
40#include <asm/mach/arch.h>
41#include <asm/pgtable.h>
42#include <asm/page.h>
43
44#include <asm/mach/map.h>
45
46#include "common.h"
47#include "devices.h"
48
49/* NOR flash */
50#define AUTCPU12_FLASH_BASE (CS0_PHYS_BASE)
51
52/* Board specific hardware definitions */
53#define AUTCPU12_CHAR_LCD_BASE (CS1_PHYS_BASE + 0x00000000)
54#define AUTCPU12_CSAUX1_BASE (CS1_PHYS_BASE + 0x04000000)
55#define AUTCPU12_CAN_BASE (CS1_PHYS_BASE + 0x08000000)
56#define AUTCPU12_TOUCH_BASE (CS1_PHYS_BASE + 0x0a000000)
57#define AUTCPU12_IO_BASE (CS1_PHYS_BASE + 0x0c000000)
58#define AUTCPU12_LPT_BASE (CS1_PHYS_BASE + 0x0e000000)
59
60/* NVRAM */
61#define AUTCPU12_NVRAM_BASE (CS1_PHYS_BASE + 0x02000000)
62
63/* SmartMedia flash */
64#define AUTCPU12_SMC_BASE (CS1_PHYS_BASE + 0x06000000)
65#define AUTCPU12_SMC_SEL_BASE (AUTCPU12_SMC_BASE + 0x10)
66
67/* Ethernet */
68#define AUTCPU12_CS8900_BASE (CS2_PHYS_BASE + 0x300)
69#define AUTCPU12_CS8900_IRQ (IRQ_EINT3)
70
71/* NAND flash */
72#define AUTCPU12_MMGPIO_BASE (CLPS711X_NR_GPIO)
73#define AUTCPU12_SMC_NCE (AUTCPU12_MMGPIO_BASE + 0) /* Bit 0 */
74#define AUTCPU12_SMC_RDY CLPS711X_GPIO(1, 2)
75#define AUTCPU12_SMC_ALE CLPS711X_GPIO(1, 3)
76#define AUTCPU12_SMC_CLE CLPS711X_GPIO(1, 4)
77
78/* LCD contrast digital potentiometer */
79#define AUTCPU12_DPOT_CS CLPS711X_GPIO(4, 0)
80#define AUTCPU12_DPOT_CLK CLPS711X_GPIO(4, 1)
81#define AUTCPU12_DPOT_UD CLPS711X_GPIO(4, 2)
82
83static struct resource autcpu12_cs8900_resource[] __initdata = {
84 DEFINE_RES_MEM(AUTCPU12_CS8900_BASE, SZ_1K),
85 DEFINE_RES_IRQ(AUTCPU12_CS8900_IRQ),
86};
87
88static struct resource autcpu12_nand_resource[] __initdata = {
89 DEFINE_RES_MEM(AUTCPU12_SMC_BASE, SZ_16),
90};
91
92static struct mtd_partition autcpu12_nand_parts[] __initdata = {
93 {
94 .name = "Flash partition 1",
95 .offset = 0,
96 .size = SZ_8M,
97 },
98 {
99 .name = "Flash partition 2",
100 .offset = MTDPART_OFS_APPEND,
101 .size = MTDPART_SIZ_FULL,
102 },
103};
104
105static void __init autcpu12_adjust_parts(struct gpio_nand_platdata *pdata,
106 size_t sz)
107{
108 switch (sz) {
109 case SZ_16M:
110 case SZ_32M:
111 break;
112 case SZ_64M:
113 case SZ_128M:
114 pdata->parts[0].size = SZ_16M;
115 break;
116 default:
117 pr_warn("Unsupported SmartMedia device size %u\n", sz);
118 break;
119 }
120}
121
122static struct gpio_nand_platdata autcpu12_nand_pdata __initdata = {
123 .gpio_rdy = AUTCPU12_SMC_RDY,
124 .gpio_nce = AUTCPU12_SMC_NCE,
125 .gpio_ale = AUTCPU12_SMC_ALE,
126 .gpio_cle = AUTCPU12_SMC_CLE,
127 .gpio_nwp = -1,
128 .chip_delay = 20,
129 .parts = autcpu12_nand_parts,
130 .num_parts = ARRAY_SIZE(autcpu12_nand_parts),
131 .adjust_parts = autcpu12_adjust_parts,
132};
133
134static struct platform_device autcpu12_nand_pdev __initdata = {
135 .name = "gpio-nand",
136 .id = -1,
137 .resource = autcpu12_nand_resource,
138 .num_resources = ARRAY_SIZE(autcpu12_nand_resource),
139 .dev = {
140 .platform_data = &autcpu12_nand_pdata,
141 },
142};
143
144static struct resource autcpu12_mmgpio_resource[] __initdata = {
145 DEFINE_RES_MEM_NAMED(AUTCPU12_SMC_SEL_BASE, SZ_1, "dat"),
146};
147
148static struct bgpio_pdata autcpu12_mmgpio_pdata __initdata = {
149 .base = AUTCPU12_MMGPIO_BASE,
150 .ngpio = 8,
151};
152
153static struct platform_device autcpu12_mmgpio_pdev __initdata = {
154 .name = "basic-mmio-gpio",
155 .id = -1,
156 .resource = autcpu12_mmgpio_resource,
157 .num_resources = ARRAY_SIZE(autcpu12_mmgpio_resource),
158 .dev = {
159 .platform_data = &autcpu12_mmgpio_pdata,
160 },
161};
162
163static const struct gpio const autcpu12_gpios[] __initconst = {
164 { AUTCPU12_DPOT_CS, GPIOF_OUT_INIT_HIGH, "DPOT CS" },
165 { AUTCPU12_DPOT_CLK, GPIOF_OUT_INIT_LOW, "DPOT CLK" },
166 { AUTCPU12_DPOT_UD, GPIOF_OUT_INIT_LOW, "DPOT UD" },
167};
168
169static struct mtd_partition autcpu12_flash_partitions[] = {
170 {
171 .name = "NOR.0",
172 .offset = 0,
173 .size = MTDPART_SIZ_FULL,
174 },
175};
176
177static struct physmap_flash_data autcpu12_flash_pdata = {
178 .width = 4,
179 .parts = autcpu12_flash_partitions,
180 .nr_parts = ARRAY_SIZE(autcpu12_flash_partitions),
181};
182
183static struct resource autcpu12_flash_resources[] __initdata = {
184 DEFINE_RES_MEM(AUTCPU12_FLASH_BASE, SZ_8M),
185};
186
187static struct platform_device autcpu12_flash_pdev __initdata = {
188 .name = "physmap-flash",
189 .id = 0,
190 .resource = autcpu12_flash_resources,
191 .num_resources = ARRAY_SIZE(autcpu12_flash_resources),
192 .dev = {
193 .platform_data = &autcpu12_flash_pdata,
194 },
195};
196
197static struct resource autcpu12_nvram_resource[] __initdata = {
198 DEFINE_RES_MEM(AUTCPU12_NVRAM_BASE, 0),
199};
200
201static struct platdata_mtd_ram autcpu12_nvram_pdata = {
202 .bankwidth = 4,
203};
204
205static struct platform_device autcpu12_nvram_pdev __initdata = {
206 .name = "mtd-ram",
207 .id = 0,
208 .resource = autcpu12_nvram_resource,
209 .num_resources = ARRAY_SIZE(autcpu12_nvram_resource),
210 .dev = {
211 .platform_data = &autcpu12_nvram_pdata,
212 },
213};
214
215static void __init autcpu12_nvram_init(void)
216{
217 void __iomem *nvram;
218 unsigned int save[2];
219 resource_size_t nvram_size = SZ_128K;
220
221 /*
222 * Check for 32K/128K
223 * Read ofs 0K
224 * Read ofs 64K
225 * Write complement to ofs 64K
226 * Read and check result on ofs 0K
227 * Restore contents
228 */
229 nvram = ioremap(autcpu12_nvram_resource[0].start, SZ_128K);
230 if (nvram) {
231 save[0] = readl(nvram + 0);
232 save[1] = readl(nvram + SZ_64K);
233 writel(~save[0], nvram + SZ_64K);
234 if (readl(nvram + 0) != save[0]) {
235 writel(save[0], nvram + 0);
236 nvram_size = SZ_32K;
237 } else
238 writel(save[1], nvram + SZ_64K);
239 iounmap(nvram);
240
241 autcpu12_nvram_resource[0].end =
242 autcpu12_nvram_resource[0].start + nvram_size - 1;
243 platform_device_register(&autcpu12_nvram_pdev);
244 } else
245 pr_err("Failed to remap NVRAM resource\n");
246}
247
248static void __init autcpu12_init(void)
249{
250 clps711x_devices_init();
251 platform_device_register(&autcpu12_flash_pdev);
252 platform_device_register_simple("video-clps711x", 0, NULL, 0);
253 platform_device_register_simple("cs89x0", 0, autcpu12_cs8900_resource,
254 ARRAY_SIZE(autcpu12_cs8900_resource));
255 platform_device_register(&autcpu12_mmgpio_pdev);
256 autcpu12_nvram_init();
257}
258
259static void __init autcpu12_init_late(void)
260{
261 gpio_request_array(autcpu12_gpios, ARRAY_SIZE(autcpu12_gpios));
262 platform_device_register(&autcpu12_nand_pdev);
263}
264
265MACHINE_START(AUTCPU12, "autronix autcpu12")
266 /* Maintainer: Thomas Gleixner */
267 .atag_offset = 0x20000,
268 .map_io = clps711x_map_io,
269 .init_irq = clps711x_init_irq,
270 .init_time = clps711x_timer_init,
271 .init_machine = autcpu12_init,
272 .init_late = autcpu12_init_late,
273 .restart = clps711x_restart,
274MACHINE_END
275
diff --git a/arch/arm/mach-clps711x/board-cdb89712.c b/arch/arm/mach-clps711x/board-cdb89712.c
deleted file mode 100644
index 972abdb10028..000000000000
--- a/arch/arm/mach-clps711x/board-cdb89712.c
+++ /dev/null
@@ -1,147 +0,0 @@
1/*
2 * linux/arch/arm/mach-clps711x/cdb89712.c
3 *
4 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/types.h>
23#include <linux/string.h>
24#include <linux/mm.h>
25#include <linux/io.h>
26#include <linux/interrupt.h>
27#include <linux/platform_device.h>
28
29#include <linux/mtd/physmap.h>
30#include <linux/mtd/plat-ram.h>
31#include <linux/mtd/partitions.h>
32
33#include <mach/hardware.h>
34#include <asm/pgtable.h>
35#include <asm/page.h>
36#include <asm/setup.h>
37#include <asm/mach-types.h>
38#include <asm/mach/arch.h>
39#include <asm/mach/map.h>
40
41#include "common.h"
42#include "devices.h"
43
44#define CDB89712_CS8900_BASE (CS2_PHYS_BASE + 0x300)
45#define CDB89712_CS8900_IRQ (IRQ_EINT3)
46
47static struct resource cdb89712_cs8900_resource[] __initdata = {
48 DEFINE_RES_MEM(CDB89712_CS8900_BASE, SZ_1K),
49 DEFINE_RES_IRQ(CDB89712_CS8900_IRQ),
50};
51
52static struct mtd_partition cdb89712_flash_partitions[] __initdata = {
53 {
54 .name = "Flash",
55 .offset = 0,
56 .size = MTDPART_SIZ_FULL,
57 },
58};
59
60static struct physmap_flash_data cdb89712_flash_pdata __initdata = {
61 .width = 4,
62 .probe_type = "map_rom",
63 .parts = cdb89712_flash_partitions,
64 .nr_parts = ARRAY_SIZE(cdb89712_flash_partitions),
65};
66
67static struct resource cdb89712_flash_resources[] __initdata = {
68 DEFINE_RES_MEM(CS0_PHYS_BASE, SZ_8M),
69};
70
71static struct platform_device cdb89712_flash_pdev __initdata = {
72 .name = "physmap-flash",
73 .id = 0,
74 .resource = cdb89712_flash_resources,
75 .num_resources = ARRAY_SIZE(cdb89712_flash_resources),
76 .dev = {
77 .platform_data = &cdb89712_flash_pdata,
78 },
79};
80
81static struct mtd_partition cdb89712_bootrom_partitions[] __initdata = {
82 {
83 .name = "BootROM",
84 .offset = 0,
85 .size = MTDPART_SIZ_FULL,
86 },
87};
88
89static struct physmap_flash_data cdb89712_bootrom_pdata __initdata = {
90 .width = 4,
91 .probe_type = "map_rom",
92 .parts = cdb89712_bootrom_partitions,
93 .nr_parts = ARRAY_SIZE(cdb89712_bootrom_partitions),
94};
95
96static struct resource cdb89712_bootrom_resources[] __initdata = {
97 DEFINE_RES_NAMED(CS7_PHYS_BASE, SZ_128, "BOOTROM", IORESOURCE_MEM |
98 IORESOURCE_READONLY),
99};
100
101static struct platform_device cdb89712_bootrom_pdev __initdata = {
102 .name = "physmap-flash",
103 .id = 1,
104 .resource = cdb89712_bootrom_resources,
105 .num_resources = ARRAY_SIZE(cdb89712_bootrom_resources),
106 .dev = {
107 .platform_data = &cdb89712_bootrom_pdata,
108 },
109};
110
111static struct platdata_mtd_ram cdb89712_sram_pdata __initdata = {
112 .bankwidth = 4,
113};
114
115static struct resource cdb89712_sram_resources[] __initdata = {
116 DEFINE_RES_MEM(CLPS711X_SRAM_BASE, CLPS711X_SRAM_SIZE),
117};
118
119static struct platform_device cdb89712_sram_pdev __initdata = {
120 .name = "mtd-ram",
121 .id = 0,
122 .resource = cdb89712_sram_resources,
123 .num_resources = ARRAY_SIZE(cdb89712_sram_resources),
124 .dev = {
125 .platform_data = &cdb89712_sram_pdata,
126 },
127};
128
129static void __init cdb89712_init(void)
130{
131 clps711x_devices_init();
132 platform_device_register(&cdb89712_flash_pdev);
133 platform_device_register(&cdb89712_bootrom_pdev);
134 platform_device_register(&cdb89712_sram_pdev);
135 platform_device_register_simple("cs89x0", 0, cdb89712_cs8900_resource,
136 ARRAY_SIZE(cdb89712_cs8900_resource));
137}
138
139MACHINE_START(CDB89712, "Cirrus-CDB89712")
140 /* Maintainer: Ray Lehtiniemi */
141 .atag_offset = 0x100,
142 .map_io = clps711x_map_io,
143 .init_irq = clps711x_init_irq,
144 .init_time = clps711x_timer_init,
145 .init_machine = cdb89712_init,
146 .restart = clps711x_restart,
147MACHINE_END
diff --git a/arch/arm/mach-clps711x/board-clep7312.c b/arch/arm/mach-clps711x/board-clep7312.c
deleted file mode 100644
index f9ca22b646bf..000000000000
--- a/arch/arm/mach-clps711x/board-clep7312.c
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * linux/arch/arm/mach-clps711x/clep7312.c
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18#include <linux/init.h>
19#include <linux/types.h>
20#include <linux/string.h>
21#include <linux/memblock.h>
22
23#include <asm/setup.h>
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h>
26
27#include "common.h"
28#include "devices.h"
29
30static void __init
31fixup_clep7312(struct tag *tags, char **cmdline)
32{
33 memblock_add(0xc0000000, 0x01000000);
34}
35
36MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312")
37 /* Maintainer: Nobody */
38 .atag_offset = 0x0100,
39 .fixup = fixup_clep7312,
40 .map_io = clps711x_map_io,
41 .init_irq = clps711x_init_irq,
42 .init_time = clps711x_timer_init,
43 .init_machine = clps711x_devices_init,
44 .restart = clps711x_restart,
45MACHINE_END
diff --git a/arch/arm/mach-clps711x/board-edb7211.c b/arch/arm/mach-clps711x/board-edb7211.c
deleted file mode 100644
index f33979784f38..000000000000
--- a/arch/arm/mach-clps711x/board-edb7211.c
+++ /dev/null
@@ -1,188 +0,0 @@
1/*
2 * Copyright (C) 2000, 2001 Blue Mug, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include <linux/init.h>
11#include <linux/gpio.h>
12#include <linux/delay.h>
13#include <linux/memblock.h>
14#include <linux/types.h>
15#include <linux/i2c-gpio.h>
16#include <linux/interrupt.h>
17#include <linux/platform_device.h>
18#include <linux/pwm.h>
19#include <linux/pwm_backlight.h>
20#include <linux/memblock.h>
21
22#include <linux/mtd/physmap.h>
23#include <linux/mtd/partitions.h>
24
25#include <asm/setup.h>
26#include <asm/mach/map.h>
27#include <asm/mach/arch.h>
28#include <asm/mach-types.h>
29
30#include <video/platform_lcd.h>
31
32#include <mach/hardware.h>
33
34#include "common.h"
35#include "devices.h"
36
37#define VIDEORAM_SIZE SZ_128K
38
39#define EDB7211_LCD_DC_DC_EN CLPS711X_GPIO(3, 1)
40#define EDB7211_LCDEN CLPS711X_GPIO(3, 2)
41#define EDB7211_LCDBL CLPS711X_GPIO(3, 3)
42
43#define EDB7211_I2C_SDA CLPS711X_GPIO(3, 4)
44#define EDB7211_I2C_SCL CLPS711X_GPIO(3, 5)
45
46#define EDB7211_FLASH0_BASE (CS0_PHYS_BASE)
47#define EDB7211_FLASH1_BASE (CS1_PHYS_BASE)
48
49#define EDB7211_CS8900_BASE (CS2_PHYS_BASE + 0x300)
50#define EDB7211_CS8900_IRQ (IRQ_EINT3)
51
52/* The extra 8 lines of the keyboard matrix */
53#define EDB7211_EXTKBD_BASE (CS3_PHYS_BASE)
54
55static struct i2c_gpio_platform_data edb7211_i2c_pdata __initdata = {
56 .sda_pin = EDB7211_I2C_SDA,
57 .scl_pin = EDB7211_I2C_SCL,
58 .scl_is_output_only = 1,
59};
60
61static struct resource edb7211_cs8900_resource[] __initdata = {
62 DEFINE_RES_MEM(EDB7211_CS8900_BASE, SZ_1K),
63 DEFINE_RES_IRQ(EDB7211_CS8900_IRQ),
64};
65
66static struct mtd_partition edb7211_flash_partitions[] __initdata = {
67 {
68 .name = "Flash",
69 .offset = 0,
70 .size = MTDPART_SIZ_FULL,
71 },
72};
73
74static struct physmap_flash_data edb7211_flash_pdata __initdata = {
75 .width = 4,
76 .parts = edb7211_flash_partitions,
77 .nr_parts = ARRAY_SIZE(edb7211_flash_partitions),
78};
79
80static struct resource edb7211_flash_resources[] __initdata = {
81 DEFINE_RES_MEM(EDB7211_FLASH0_BASE, SZ_8M),
82 DEFINE_RES_MEM(EDB7211_FLASH1_BASE, SZ_8M),
83};
84
85static struct platform_device edb7211_flash_pdev __initdata = {
86 .name = "physmap-flash",
87 .id = 0,
88 .resource = edb7211_flash_resources,
89 .num_resources = ARRAY_SIZE(edb7211_flash_resources),
90 .dev = {
91 .platform_data = &edb7211_flash_pdata,
92 },
93};
94
95static void edb7211_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
96{
97 if (power) {
98 gpio_set_value(EDB7211_LCDEN, 1);
99 udelay(100);
100 gpio_set_value(EDB7211_LCD_DC_DC_EN, 1);
101 } else {
102 gpio_set_value(EDB7211_LCD_DC_DC_EN, 0);
103 udelay(100);
104 gpio_set_value(EDB7211_LCDEN, 0);
105 }
106}
107
108static struct plat_lcd_data edb7211_lcd_power_pdata = {
109 .set_power = edb7211_lcd_power_set,
110};
111
112static struct pwm_lookup edb7211_pwm_lookup[] = {
113 PWM_LOOKUP("clps711x-pwm", 0, "pwm-backlight.0", NULL,
114 0, PWM_POLARITY_NORMAL),
115};
116
117static struct platform_pwm_backlight_data pwm_bl_pdata = {
118 .dft_brightness = 0x01,
119 .max_brightness = 0x0f,
120 .enable_gpio = EDB7211_LCDBL,
121};
122
123static struct resource clps711x_pwm_res =
124 DEFINE_RES_MEM(CLPS711X_PHYS_BASE + PMPCON, SZ_4);
125
126static struct gpio edb7211_gpios[] __initconst = {
127 { EDB7211_LCD_DC_DC_EN, GPIOF_OUT_INIT_LOW, "LCD DC-DC" },
128 { EDB7211_LCDEN, GPIOF_OUT_INIT_LOW, "LCD POWER" },
129};
130
131/* Reserve screen memory region at the start of main system memory. */
132static void __init edb7211_reserve(void)
133{
134 memblock_reserve(PHYS_OFFSET, VIDEORAM_SIZE);
135}
136
137static void __init
138fixup_edb7211(struct tag *tags, char **cmdline)
139{
140 /*
141 * Bank start addresses are not present in the information
142 * passed in from the boot loader. We could potentially
143 * detect them, but instead we hard-code them.
144 *
145 * Banks sizes _are_ present in the param block, but we're
146 * not using that information yet.
147 */
148 memblock_add(0xc0000000, SZ_8M);
149 memblock_add(0xc1000000, SZ_8M);
150}
151
152static void __init edb7211_init_late(void)
153{
154 gpio_request_array(edb7211_gpios, ARRAY_SIZE(edb7211_gpios));
155
156 platform_device_register(&edb7211_flash_pdev);
157
158 platform_device_register_data(NULL, "platform-lcd", 0,
159 &edb7211_lcd_power_pdata,
160 sizeof(edb7211_lcd_power_pdata));
161
162 platform_device_register_simple("clps711x-pwm", PLATFORM_DEVID_NONE,
163 &clps711x_pwm_res, 1);
164 pwm_add_table(edb7211_pwm_lookup, ARRAY_SIZE(edb7211_pwm_lookup));
165
166 platform_device_register_data(&platform_bus, "pwm-backlight", 0,
167 &pwm_bl_pdata, sizeof(pwm_bl_pdata));
168
169 platform_device_register_simple("video-clps711x", 0, NULL, 0);
170 platform_device_register_simple("cs89x0", 0, edb7211_cs8900_resource,
171 ARRAY_SIZE(edb7211_cs8900_resource));
172 platform_device_register_data(NULL, "i2c-gpio", 0,
173 &edb7211_i2c_pdata,
174 sizeof(edb7211_i2c_pdata));
175}
176
177MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
178 /* Maintainer: Jon McClintock */
179 .atag_offset = VIDEORAM_SIZE + 0x100,
180 .fixup = fixup_edb7211,
181 .reserve = edb7211_reserve,
182 .map_io = clps711x_map_io,
183 .init_irq = clps711x_init_irq,
184 .init_time = clps711x_timer_init,
185 .init_machine = clps711x_devices_init,
186 .init_late = edb7211_init_late,
187 .restart = clps711x_restart,
188MACHINE_END
diff --git a/arch/arm/mach-clps711x/board-p720t.c b/arch/arm/mach-clps711x/board-p720t.c
deleted file mode 100644
index 80a16a8b3776..000000000000
--- a/arch/arm/mach-clps711x/board-p720t.c
+++ /dev/null
@@ -1,373 +0,0 @@
1/*
2 * linux/arch/arm/mach-clps711x/p720t.c
3 *
4 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/types.h>
23#include <linux/string.h>
24#include <linux/mm.h>
25#include <linux/io.h>
26#include <linux/gpio.h>
27#include <linux/slab.h>
28#include <linux/leds.h>
29#include <linux/sizes.h>
30#include <linux/backlight.h>
31#include <linux/gpio/driver.h>
32#include <linux/platform_device.h>
33#include <linux/mtd/partitions.h>
34#include <linux/mtd/nand-gpio.h>
35
36#include <mach/hardware.h>
37#include <asm/pgtable.h>
38#include <asm/page.h>
39#include <asm/setup.h>
40#include <asm/mach-types.h>
41#include <asm/mach/arch.h>
42#include <asm/mach/map.h>
43
44#include <video/platform_lcd.h>
45
46#include "common.h"
47#include "devices.h"
48
49#define P720T_USERLED CLPS711X_GPIO(3, 0)
50#define P720T_NAND_CLE CLPS711X_GPIO(4, 0)
51#define P720T_NAND_ALE CLPS711X_GPIO(4, 1)
52#define P720T_NAND_NCE CLPS711X_GPIO(4, 2)
53
54#define P720T_NAND_BASE (CLPS711X_SDRAM1_BASE)
55
56#define P720T_MMGPIO_BASE (CLPS711X_NR_GPIO)
57
58#define SYSPLD_PHYS_BASE IOMEM(CS1_PHYS_BASE)
59
60#define PLD_INT (SYSPLD_PHYS_BASE + 0x000000)
61#define PLD_INT_MMGPIO_BASE (P720T_MMGPIO_BASE + 0)
62#define PLD_INT_PENIRQ (PLD_INT_MMGPIO_BASE + 5)
63#define PLD_INT_UCB_IRQ (PLD_INT_MMGPIO_BASE + 1)
64#define PLD_INT_KBD_ATN (PLD_INT_MMGPIO_BASE + 0) /* EINT1 */
65
66#define PLD_PWR (SYSPLD_PHYS_BASE + 0x000004)
67#define PLD_PWR_MMGPIO_BASE (P720T_MMGPIO_BASE + 8)
68#define PLD_PWR_EXT (PLD_PWR_MMGPIO_BASE + 5)
69#define PLD_PWR_MODE (PLD_PWR_MMGPIO_BASE + 4) /* 1 = PWM, 0 = PFM */
70#define PLD_S4_ON (PLD_PWR_MMGPIO_BASE + 3) /* LCD bias voltage enable */
71#define PLD_S3_ON (PLD_PWR_MMGPIO_BASE + 2) /* LCD backlight enable */
72#define PLD_S2_ON (PLD_PWR_MMGPIO_BASE + 1) /* LCD 3V3 supply enable */
73#define PLD_S1_ON (PLD_PWR_MMGPIO_BASE + 0) /* LCD 3V supply enable */
74
75#define PLD_KBD (SYSPLD_PHYS_BASE + 0x000008)
76#define PLD_KBD_MMGPIO_BASE (P720T_MMGPIO_BASE + 16)
77#define PLD_KBD_WAKE (PLD_KBD_MMGPIO_BASE + 1)
78#define PLD_KBD_EN (PLD_KBD_MMGPIO_BASE + 0)
79
80#define PLD_SPI (SYSPLD_PHYS_BASE + 0x00000c)
81#define PLD_SPI_MMGPIO_BASE (P720T_MMGPIO_BASE + 24)
82#define PLD_SPI_EN (PLD_SPI_MMGPIO_BASE + 0)
83
84#define PLD_IO (SYSPLD_PHYS_BASE + 0x000010)
85#define PLD_IO_MMGPIO_BASE (P720T_MMGPIO_BASE + 32)
86#define PLD_IO_BOOTSEL (PLD_IO_MMGPIO_BASE + 6) /* Boot sel switch */
87#define PLD_IO_USER (PLD_IO_MMGPIO_BASE + 5) /* User defined switch */
88#define PLD_IO_LED3 (PLD_IO_MMGPIO_BASE + 4)
89#define PLD_IO_LED2 (PLD_IO_MMGPIO_BASE + 3)
90#define PLD_IO_LED1 (PLD_IO_MMGPIO_BASE + 2)
91#define PLD_IO_LED0 (PLD_IO_MMGPIO_BASE + 1)
92#define PLD_IO_LEDEN (PLD_IO_MMGPIO_BASE + 0)
93
94#define PLD_IRDA (SYSPLD_PHYS_BASE + 0x000014)
95#define PLD_IRDA_MMGPIO_BASE (P720T_MMGPIO_BASE + 40)
96#define PLD_IRDA_EN (PLD_IRDA_MMGPIO_BASE + 0)
97
98#define PLD_COM2 (SYSPLD_PHYS_BASE + 0x000018)
99#define PLD_COM2_MMGPIO_BASE (P720T_MMGPIO_BASE + 48)
100#define PLD_COM2_EN (PLD_COM2_MMGPIO_BASE + 0)
101
102#define PLD_COM1 (SYSPLD_PHYS_BASE + 0x00001c)
103#define PLD_COM1_MMGPIO_BASE (P720T_MMGPIO_BASE + 56)
104#define PLD_COM1_EN (PLD_COM1_MMGPIO_BASE + 0)
105
106#define PLD_AUD (SYSPLD_PHYS_BASE + 0x000020)
107#define PLD_AUD_MMGPIO_BASE (P720T_MMGPIO_BASE + 64)
108#define PLD_AUD_DIV1 (PLD_AUD_MMGPIO_BASE + 6)
109#define PLD_AUD_DIV0 (PLD_AUD_MMGPIO_BASE + 5)
110#define PLD_AUD_CLK_SEL1 (PLD_AUD_MMGPIO_BASE + 4)
111#define PLD_AUD_CLK_SEL0 (PLD_AUD_MMGPIO_BASE + 3)
112#define PLD_AUD_MIC_PWR (PLD_AUD_MMGPIO_BASE + 2)
113#define PLD_AUD_MIC_GAIN (PLD_AUD_MMGPIO_BASE + 1)
114#define PLD_AUD_CODEC_EN (PLD_AUD_MMGPIO_BASE + 0)
115
116#define PLD_CF (SYSPLD_PHYS_BASE + 0x000024)
117#define PLD_CF_MMGPIO_BASE (P720T_MMGPIO_BASE + 72)
118#define PLD_CF2_SLEEP (PLD_CF_MMGPIO_BASE + 5)
119#define PLD_CF1_SLEEP (PLD_CF_MMGPIO_BASE + 4)
120#define PLD_CF2_nPDREQ (PLD_CF_MMGPIO_BASE + 3)
121#define PLD_CF1_nPDREQ (PLD_CF_MMGPIO_BASE + 2)
122#define PLD_CF2_nIRQ (PLD_CF_MMGPIO_BASE + 1)
123#define PLD_CF1_nIRQ (PLD_CF_MMGPIO_BASE + 0)
124
125#define PLD_SDC (SYSPLD_PHYS_BASE + 0x000028)
126#define PLD_SDC_MMGPIO_BASE (P720T_MMGPIO_BASE + 80)
127#define PLD_SDC_INT_EN (PLD_SDC_MMGPIO_BASE + 2)
128#define PLD_SDC_WP (PLD_SDC_MMGPIO_BASE + 1)
129#define PLD_SDC_CD (PLD_SDC_MMGPIO_BASE + 0)
130
131#define PLD_CODEC (SYSPLD_PHYS_BASE + 0x400000)
132#define PLD_CODEC_MMGPIO_BASE (P720T_MMGPIO_BASE + 88)
133#define PLD_CODEC_IRQ3 (PLD_CODEC_MMGPIO_BASE + 4)
134#define PLD_CODEC_IRQ2 (PLD_CODEC_MMGPIO_BASE + 3)
135#define PLD_CODEC_IRQ1 (PLD_CODEC_MMGPIO_BASE + 2)
136#define PLD_CODEC_EN (PLD_CODEC_MMGPIO_BASE + 0)
137
138#define PLD_BRITE (SYSPLD_PHYS_BASE + 0x400004)
139#define PLD_BRITE_MMGPIO_BASE (P720T_MMGPIO_BASE + 96)
140#define PLD_BRITE_UP (PLD_BRITE_MMGPIO_BASE + 1)
141#define PLD_BRITE_DN (PLD_BRITE_MMGPIO_BASE + 0)
142
143#define PLD_LCDEN (SYSPLD_PHYS_BASE + 0x400008)
144#define PLD_LCDEN_MMGPIO_BASE (P720T_MMGPIO_BASE + 104)
145#define PLD_LCDEN_EN (PLD_LCDEN_MMGPIO_BASE + 0)
146
147#define PLD_TCH (SYSPLD_PHYS_BASE + 0x400010)
148#define PLD_TCH_MMGPIO_BASE (P720T_MMGPIO_BASE + 112)
149#define PLD_TCH_PENIRQ (PLD_TCH_MMGPIO_BASE + 1)
150#define PLD_TCH_EN (PLD_TCH_MMGPIO_BASE + 0)
151
152#define PLD_GPIO (SYSPLD_PHYS_BASE + 0x400014)
153#define PLD_GPIO_MMGPIO_BASE (P720T_MMGPIO_BASE + 120)
154#define PLD_GPIO2 (PLD_GPIO_MMGPIO_BASE + 2)
155#define PLD_GPIO1 (PLD_GPIO_MMGPIO_BASE + 1)
156#define PLD_GPIO0 (PLD_GPIO_MMGPIO_BASE + 0)
157
158static struct gpio p720t_gpios[] __initconst = {
159 { PLD_S1_ON, GPIOF_OUT_INIT_LOW, "PLD_S1_ON" },
160 { PLD_S2_ON, GPIOF_OUT_INIT_LOW, "PLD_S2_ON" },
161 { PLD_S3_ON, GPIOF_OUT_INIT_LOW, "PLD_S3_ON" },
162 { PLD_S4_ON, GPIOF_OUT_INIT_LOW, "PLD_S4_ON" },
163 { PLD_KBD_EN, GPIOF_OUT_INIT_LOW, "PLD_KBD_EN" },
164 { PLD_SPI_EN, GPIOF_OUT_INIT_LOW, "PLD_SPI_EN" },
165 { PLD_IO_USER, GPIOF_OUT_INIT_LOW, "PLD_IO_USER" },
166 { PLD_IO_LED0, GPIOF_OUT_INIT_LOW, "PLD_IO_LED0" },
167 { PLD_IO_LED1, GPIOF_OUT_INIT_LOW, "PLD_IO_LED1" },
168 { PLD_IO_LED2, GPIOF_OUT_INIT_LOW, "PLD_IO_LED2" },
169 { PLD_IO_LED3, GPIOF_OUT_INIT_LOW, "PLD_IO_LED3" },
170 { PLD_IO_LEDEN, GPIOF_OUT_INIT_LOW, "PLD_IO_LEDEN" },
171 { PLD_IRDA_EN, GPIOF_OUT_INIT_LOW, "PLD_IRDA_EN" },
172 { PLD_COM1_EN, GPIOF_OUT_INIT_HIGH, "PLD_COM1_EN" },
173 { PLD_COM2_EN, GPIOF_OUT_INIT_HIGH, "PLD_COM2_EN" },
174 { PLD_CODEC_EN, GPIOF_OUT_INIT_LOW, "PLD_CODEC_EN" },
175 { PLD_LCDEN_EN, GPIOF_OUT_INIT_LOW, "PLD_LCDEN_EN" },
176 { PLD_TCH_EN, GPIOF_OUT_INIT_LOW, "PLD_TCH_EN" },
177 { P720T_USERLED,GPIOF_OUT_INIT_LOW, "USER_LED" },
178};
179
180static struct resource p720t_mmgpio_resource[] __initdata = {
181 DEFINE_RES_MEM_NAMED(0, 4, "dat"),
182};
183
184static struct bgpio_pdata p720t_mmgpio_pdata = {
185 .ngpio = 8,
186};
187
188static struct platform_device p720t_mmgpio __initdata = {
189 .name = "basic-mmio-gpio",
190 .id = -1,
191 .resource = p720t_mmgpio_resource,
192 .num_resources = ARRAY_SIZE(p720t_mmgpio_resource),
193 .dev = {
194 .platform_data = &p720t_mmgpio_pdata,
195 },
196};
197
198static void __init p720t_mmgpio_init(void __iomem *addrbase, int gpiobase)
199{
200 p720t_mmgpio_resource[0].start = (unsigned long)addrbase;
201 p720t_mmgpio_pdata.base = gpiobase;
202
203 platform_device_register(&p720t_mmgpio);
204}
205
206static struct {
207 void __iomem *addrbase;
208 int gpiobase;
209} mmgpios[] __initconst = {
210 { PLD_INT, PLD_INT_MMGPIO_BASE },
211 { PLD_PWR, PLD_PWR_MMGPIO_BASE },
212 { PLD_KBD, PLD_KBD_MMGPIO_BASE },
213 { PLD_SPI, PLD_SPI_MMGPIO_BASE },
214 { PLD_IO, PLD_IO_MMGPIO_BASE },
215 { PLD_IRDA, PLD_IRDA_MMGPIO_BASE },
216 { PLD_COM2, PLD_COM2_MMGPIO_BASE },
217 { PLD_COM1, PLD_COM1_MMGPIO_BASE },
218 { PLD_AUD, PLD_AUD_MMGPIO_BASE },
219 { PLD_CF, PLD_CF_MMGPIO_BASE },
220 { PLD_SDC, PLD_SDC_MMGPIO_BASE },
221 { PLD_CODEC, PLD_CODEC_MMGPIO_BASE },
222 { PLD_BRITE, PLD_BRITE_MMGPIO_BASE },
223 { PLD_LCDEN, PLD_LCDEN_MMGPIO_BASE },
224 { PLD_TCH, PLD_TCH_MMGPIO_BASE },
225 { PLD_GPIO, PLD_GPIO_MMGPIO_BASE },
226};
227
228static struct resource p720t_nand_resource[] __initdata = {
229 DEFINE_RES_MEM(P720T_NAND_BASE, SZ_4),
230};
231
232static struct mtd_partition p720t_nand_parts[] __initdata = {
233 {
234 .name = "Flash partition 1",
235 .offset = 0,
236 .size = SZ_2M,
237 },
238 {
239 .name = "Flash partition 2",
240 .offset = MTDPART_OFS_APPEND,
241 .size = MTDPART_SIZ_FULL,
242 },
243};
244
245static struct gpio_nand_platdata p720t_nand_pdata __initdata = {
246 .gpio_rdy = -1,
247 .gpio_nce = P720T_NAND_NCE,
248 .gpio_ale = P720T_NAND_ALE,
249 .gpio_cle = P720T_NAND_CLE,
250 .gpio_nwp = -1,
251 .chip_delay = 15,
252 .parts = p720t_nand_parts,
253 .num_parts = ARRAY_SIZE(p720t_nand_parts),
254};
255
256static struct platform_device p720t_nand_pdev __initdata = {
257 .name = "gpio-nand",
258 .id = -1,
259 .resource = p720t_nand_resource,
260 .num_resources = ARRAY_SIZE(p720t_nand_resource),
261 .dev = {
262 .platform_data = &p720t_nand_pdata,
263 },
264};
265
266static void p720t_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
267{
268 if (power) {
269 gpio_set_value(PLD_LCDEN_EN, 1);
270 gpio_set_value(PLD_S1_ON, 1);
271 gpio_set_value(PLD_S2_ON, 1);
272 gpio_set_value(PLD_S4_ON, 1);
273 } else {
274 gpio_set_value(PLD_S1_ON, 0);
275 gpio_set_value(PLD_S2_ON, 0);
276 gpio_set_value(PLD_S4_ON, 0);
277 gpio_set_value(PLD_LCDEN_EN, 0);
278 }
279}
280
281static struct plat_lcd_data p720t_lcd_power_pdata = {
282 .set_power = p720t_lcd_power_set,
283};
284
285static void p720t_lcd_backlight_set_intensity(int intensity)
286{
287 gpio_set_value(PLD_S3_ON, intensity);
288}
289
290static struct generic_bl_info p720t_lcd_backlight_pdata = {
291 .name = "lcd-backlight.0",
292 .default_intensity = 0x01,
293 .max_intensity = 0x01,
294 .set_bl_intensity = p720t_lcd_backlight_set_intensity,
295};
296
297static void __init
298fixup_p720t(struct tag *tag, char **cmdline)
299{
300 /*
301 * Our bootloader doesn't setup any tags (yet).
302 */
303 if (tag->hdr.tag != ATAG_CORE) {
304 tag->hdr.tag = ATAG_CORE;
305 tag->hdr.size = tag_size(tag_core);
306 tag->u.core.flags = 0;
307 tag->u.core.pagesize = PAGE_SIZE;
308 tag->u.core.rootdev = 0x0100;
309
310 tag = tag_next(tag);
311 tag->hdr.tag = ATAG_MEM;
312 tag->hdr.size = tag_size(tag_mem32);
313 tag->u.mem.size = 4096;
314 tag->u.mem.start = PHYS_OFFSET;
315
316 tag = tag_next(tag);
317 tag->hdr.tag = ATAG_NONE;
318 tag->hdr.size = 0;
319 }
320}
321
322static struct gpio_led p720t_gpio_leds[] = {
323 {
324 .name = "User LED",
325 .default_trigger = "heartbeat",
326 .gpio = P720T_USERLED,
327 },
328};
329
330static struct gpio_led_platform_data p720t_gpio_led_pdata __initdata = {
331 .leds = p720t_gpio_leds,
332 .num_leds = ARRAY_SIZE(p720t_gpio_leds),
333};
334
335static void __init p720t_init(void)
336{
337 int i;
338
339 clps711x_devices_init();
340
341 for (i = 0; i < ARRAY_SIZE(mmgpios); i++)
342 p720t_mmgpio_init(mmgpios[i].addrbase, mmgpios[i].gpiobase);
343
344 platform_device_register(&p720t_nand_pdev);
345}
346
347static void __init p720t_init_late(void)
348{
349 WARN_ON(gpio_request_array(p720t_gpios, ARRAY_SIZE(p720t_gpios)));
350
351 platform_device_register_data(NULL, "platform-lcd", 0,
352 &p720t_lcd_power_pdata,
353 sizeof(p720t_lcd_power_pdata));
354 platform_device_register_data(NULL, "generic-bl", 0,
355 &p720t_lcd_backlight_pdata,
356 sizeof(p720t_lcd_backlight_pdata));
357 platform_device_register_simple("video-clps711x", 0, NULL, 0);
358 platform_device_register_data(NULL, "leds-gpio", 0,
359 &p720t_gpio_led_pdata,
360 sizeof(p720t_gpio_led_pdata));
361}
362
363MACHINE_START(P720T, "ARM-Prospector720T")
364 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
365 .atag_offset = 0x100,
366 .fixup = fixup_p720t,
367 .map_io = clps711x_map_io,
368 .init_irq = clps711x_init_irq,
369 .init_time = clps711x_timer_init,
370 .init_machine = p720t_init,
371 .init_late = p720t_init_late,
372 .restart = clps711x_restart,
373MACHINE_END
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
deleted file mode 100644
index 6466da8f3c11..000000000000
--- a/arch/arm/mach-clps711x/common.c
+++ /dev/null
@@ -1,65 +0,0 @@
1/*
2 * linux/arch/arm/mach-clps711x/core.c
3 *
4 * Core support for the CLPS711x-based machines.
5 *
6 * Copyright (C) 2001,2011 Deep Blue Solutions Ltd
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/init.h>
24#include <linux/sizes.h>
25
26#include <asm/mach/map.h>
27#include <asm/system_misc.h>
28
29#include <mach/hardware.h>
30
31#include "common.h"
32
33/*
34 * This maps the generic CLPS711x registers
35 */
36static struct map_desc clps711x_io_desc[] __initdata = {
37 {
38 .virtual = (unsigned long)CLPS711X_VIRT_BASE,
39 .pfn = __phys_to_pfn(CLPS711X_PHYS_BASE),
40 .length = 48 * SZ_1K,
41 .type = MT_DEVICE,
42 }
43};
44
45void __init clps711x_map_io(void)
46{
47 iotable_init(clps711x_io_desc, ARRAY_SIZE(clps711x_io_desc));
48}
49
50void __init clps711x_init_irq(void)
51{
52 clps711x_intc_init(CLPS711X_PHYS_BASE, SZ_16K);
53}
54
55void __init clps711x_timer_init(void)
56{
57 clps711x_clk_init(CLPS711X_VIRT_BASE);
58 clps711x_clksrc_init(CLPS711X_VIRT_BASE + TC1D,
59 CLPS711X_VIRT_BASE + TC2D, IRQ_TC2OI);
60}
61
62void clps711x_restart(enum reboot_mode mode, const char *cmd)
63{
64 soft_restart(0);
65}
diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h
deleted file mode 100644
index 370200b26333..000000000000
--- a/arch/arm/mach-clps711x/common.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * linux/arch/arm/mach-clps711x/common.h
3 *
4 * Common bits.
5 */
6
7#include <linux/reboot.h>
8
9#define CLPS711X_NR_GPIO (4 * 8 + 3)
10#define CLPS711X_GPIO(prt, bit) ((prt) * 8 + (bit))
11
12extern void clps711x_map_io(void);
13extern void clps711x_init_irq(void);
14extern void clps711x_timer_init(void);
15extern void clps711x_restart(enum reboot_mode mode, const char *cmd);
16
17/* drivers/irqchip/irq-clps711x.c */
18void clps711x_intc_init(phys_addr_t, resource_size_t);
19/* drivers/clk/clk-clps711x.c */
20void clps711x_clk_init(void __iomem *base);
21/* drivers/clocksource/clps711x-timer.c */
22void clps711x_clksrc_init(void __iomem *tc1_base, void __iomem *tc2_base,
23 unsigned int irq);
diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c
deleted file mode 100644
index 77a9617c216d..000000000000
--- a/arch/arm/mach-clps711x/devices.c
+++ /dev/null
@@ -1,149 +0,0 @@
1/*
2 * CLPS711X common devices definitions
3 *
4 * Author: Alexander Shiyan <shc_work@mail.ru>, 2013-2014
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/io.h>
13#include <linux/of_fdt.h>
14#include <linux/platform_device.h>
15#include <linux/random.h>
16#include <linux/sizes.h>
17#include <linux/slab.h>
18#include <linux/sys_soc.h>
19
20#include <asm/system_info.h>
21
22#include <mach/hardware.h>
23
24static const struct resource clps711x_cpuidle_res __initconst =
25 DEFINE_RES_MEM(CLPS711X_PHYS_BASE + HALT, SZ_128);
26
27static void __init clps711x_add_cpuidle(void)
28{
29 platform_device_register_simple("clps711x-cpuidle", PLATFORM_DEVID_NONE,
30 &clps711x_cpuidle_res, 1);
31}
32
33static const phys_addr_t clps711x_gpios[][2] __initconst = {
34 { PADR, PADDR },
35 { PBDR, PBDDR },
36 { PCDR, PCDDR },
37 { PDDR, PDDDR },
38 { PEDR, PEDDR },
39};
40
41static void __init clps711x_add_gpio(void)
42{
43 unsigned i;
44 struct resource gpio_res[2];
45
46 memset(gpio_res, 0, sizeof(gpio_res));
47
48 gpio_res[0].flags = IORESOURCE_MEM;
49 gpio_res[1].flags = IORESOURCE_MEM;
50
51 for (i = 0; i < ARRAY_SIZE(clps711x_gpios); i++) {
52 gpio_res[0].start = CLPS711X_PHYS_BASE + clps711x_gpios[i][0];
53 gpio_res[0].end = gpio_res[0].start;
54 gpio_res[1].start = CLPS711X_PHYS_BASE + clps711x_gpios[i][1];
55 gpio_res[1].end = gpio_res[1].start;
56
57 platform_device_register_simple("clps711x-gpio", i,
58 gpio_res, ARRAY_SIZE(gpio_res));
59 }
60}
61
62const struct resource clps711x_syscon_res[] __initconst = {
63 /* SYSCON1, SYSFLG1 */
64 DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON1, SZ_128),
65 /* SYSCON2, SYSFLG2 */
66 DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON2, SZ_128),
67 /* SYSCON3 */
68 DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON3, SZ_64),
69};
70
71static void __init clps711x_add_syscon(void)
72{
73 unsigned i;
74
75 for (i = 0; i < ARRAY_SIZE(clps711x_syscon_res); i++)
76 platform_device_register_simple("syscon", i + 1,
77 &clps711x_syscon_res[i], 1);
78}
79
80static const struct resource clps711x_uart1_res[] __initconst = {
81 DEFINE_RES_MEM(CLPS711X_PHYS_BASE + UARTDR1, SZ_128),
82 DEFINE_RES_IRQ(IRQ_UTXINT1),
83 DEFINE_RES_IRQ(IRQ_URXINT1),
84};
85
86static const struct resource clps711x_uart2_res[] __initconst = {
87 DEFINE_RES_MEM(CLPS711X_PHYS_BASE + UARTDR2, SZ_128),
88 DEFINE_RES_IRQ(IRQ_UTXINT2),
89 DEFINE_RES_IRQ(IRQ_URXINT2),
90};
91
92static void __init clps711x_add_uart(void)
93{
94 platform_device_register_simple("clps711x-uart", 0, clps711x_uart1_res,
95 ARRAY_SIZE(clps711x_uart1_res));
96 platform_device_register_simple("clps711x-uart", 1, clps711x_uart2_res,
97 ARRAY_SIZE(clps711x_uart2_res));
98};
99
100static void __init clps711x_soc_init(void)
101{
102 struct soc_device_attribute *soc_dev_attr;
103 struct soc_device *soc_dev;
104 void __iomem *base;
105 u32 id[5];
106
107 base = ioremap(CLPS711X_PHYS_BASE, SZ_32K);
108 if (!base)
109 return;
110
111 id[0] = readl(base + UNIQID);
112 id[1] = readl(base + RANDID0);
113 id[2] = readl(base + RANDID1);
114 id[3] = readl(base + RANDID2);
115 id[4] = readl(base + RANDID3);
116 system_rev = SYSFLG1_VERID(readl(base + SYSFLG1));
117
118 add_device_randomness(id, sizeof(id));
119
120 system_serial_low = id[0];
121
122 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
123 if (!soc_dev_attr)
124 goto out_unmap;
125
126 soc_dev_attr->machine = of_flat_dt_get_machine_name();
127 soc_dev_attr->family = "Cirrus Logic CLPS711X";
128 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%u", system_rev);
129 soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%08x", id[0]);
130
131 soc_dev = soc_device_register(soc_dev_attr);
132 if (IS_ERR(soc_dev)) {
133 kfree(soc_dev_attr->revision);
134 kfree(soc_dev_attr->soc_id);
135 kfree(soc_dev_attr);
136 }
137
138out_unmap:
139 iounmap(base);
140}
141
142void __init clps711x_devices_init(void)
143{
144 clps711x_add_cpuidle();
145 clps711x_add_gpio();
146 clps711x_add_syscon();
147 clps711x_add_uart();
148 clps711x_soc_init();
149}
diff --git a/arch/arm/mach-clps711x/devices.h b/arch/arm/mach-clps711x/devices.h
deleted file mode 100644
index a5efc1744b84..000000000000
--- a/arch/arm/mach-clps711x/devices.h
+++ /dev/null
@@ -1,12 +0,0 @@
1/*
2 * CLPS711X common devices definitions
3 *
4 * Copyright (C) 2013 Alexander Shiyan <shc_work@mail.ru>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12void clps711x_devices_init(void);
diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig
index eb14a0ff0093..5fd836be2701 100644
--- a/arch/arm/mach-cns3xxx/Kconfig
+++ b/arch/arm/mach-cns3xxx/Kconfig
@@ -2,7 +2,6 @@ menuconfig ARCH_CNS3XXX
2 bool "Cavium Networks CNS3XXX family" 2 bool "Cavium Networks CNS3XXX family"
3 depends on ARCH_MULTI_V6 3 depends on ARCH_MULTI_V6
4 select ARM_GIC 4 select ARM_GIC
5 select PCI_DOMAINS if PCI
6 help 5 help
7 Support for Cavium Networks CNS3XXX platform. 6 Support for Cavium Networks CNS3XXX platform.
8 7
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 8f820de890b4..18f0c856f290 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -126,8 +126,6 @@ config SOC_EXYNOS5440
126 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE 126 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
127 select HAVE_ARM_ARCH_TIMER 127 select HAVE_ARM_ARCH_TIMER
128 select AUTO_ZRELADDR 128 select AUTO_ZRELADDR
129 select MIGHT_HAVE_PCI
130 select PCI_DOMAINS if PCI
131 select PINCTRL_EXYNOS5440 129 select PINCTRL_EXYNOS5440
132 select PM_OPP 130 select PM_OPP
133 help 131 help
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index ee9a318cab31..9155b639c9aa 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -64,13 +64,6 @@ config IMX_HAVE_IOMUX_V1
64config ARCH_MXC_IOMUX_V3 64config ARCH_MXC_IOMUX_V3
65 bool 65 bool
66 66
67config SOC_IMX1
68 bool
69 select CPU_ARM920T
70 select IMX_HAVE_IOMUX_V1
71 select MXC_AVIC
72 select PINCTRL_IMX1
73
74config SOC_IMX21 67config SOC_IMX21
75 bool 68 bool
76 select CPU_ARM926T 69 select CPU_ARM926T
@@ -88,7 +81,6 @@ config SOC_IMX31
88 bool 81 bool
89 select CPU_V6 82 select CPU_V6
90 select MXC_AVIC 83 select MXC_AVIC
91 select SMP_ON_UP if SMP
92 84
93config SOC_IMX35 85config SOC_IMX35
94 bool 86 bool
@@ -96,35 +88,6 @@ config SOC_IMX35
96 select HAVE_EPIT 88 select HAVE_EPIT
97 select MXC_AVIC 89 select MXC_AVIC
98 select PINCTRL_IMX35 90 select PINCTRL_IMX35
99 select SMP_ON_UP if SMP
100
101if ARCH_MULTI_V4T
102
103comment "MX1 platforms:"
104
105config MACH_SCB9328
106 bool "Synertronixx scb9328"
107 select IMX_HAVE_PLATFORM_IMX_UART
108 select SOC_IMX1
109 help
110 Say Y here if you are using a Synertronixx scb9328 board
111
112config MACH_APF9328
113 bool "APF9328"
114 select IMX_HAVE_PLATFORM_IMX_I2C
115 select IMX_HAVE_PLATFORM_IMX_UART
116 select SOC_IMX1
117 help
118 Say Yes here if you are using the Armadeus APF9328 development board
119
120config MACH_IMX1_DT
121 bool "Support i.MX1 platforms from device tree"
122 select SOC_IMX1
123 help
124 Include support for Freescale i.MX1 based platforms
125 using the device tree for discovery.
126
127endif
128 91
129if ARCH_MULTI_V5 92if ARCH_MULTI_V5
130 93
@@ -461,6 +424,18 @@ endif
461 424
462comment "Device tree only" 425comment "Device tree only"
463 426
427if ARCH_MULTI_V4T
428
429config SOC_IMX1
430 bool "i.MX1 support"
431 select CPU_ARM920T
432 select MXC_AVIC
433 select PINCTRL_IMX1
434 help
435 This enables support for Freescale i.MX1 processor
436
437endif
438
464if ARCH_MULTI_V5 439if ARCH_MULTI_V5
465 440
466config SOC_IMX25 441config SOC_IMX25
@@ -523,7 +498,6 @@ config SOC_IMX6Q
523 select ARM_ERRATA_764369 if SMP 498 select ARM_ERRATA_764369 if SMP
524 select HAVE_ARM_SCU if SMP 499 select HAVE_ARM_SCU if SMP
525 select HAVE_ARM_TWD 500 select HAVE_ARM_TWD
526 select PCI_DOMAINS if PCI
527 select PINCTRL_IMX6Q 501 select PINCTRL_IMX6Q
528 select SOC_IMX6 502 select SOC_IMX6
529 503
@@ -569,7 +543,6 @@ config SOC_LS1021A
569 bool "Freescale LS1021A support" 543 bool "Freescale LS1021A support"
570 select ARM_GIC 544 select ARM_GIC
571 select HAVE_ARM_ARCH_TIMER 545 select HAVE_ARM_ARCH_TIMER
572 select PCI_DOMAINS if PCI
573 select ZONE_DMA if ARM_LPAE 546 select ZONE_DMA if ARM_LPAE
574 help 547 help
575 This enables support for Freescale LS1021A processor. 548 This enables support for Freescale LS1021A processor.
@@ -585,7 +558,6 @@ config SOC_VF610
585 select ARM_GIC if ARCH_MULTI_V7 558 select ARM_GIC if ARCH_MULTI_V7
586 select PINCTRL_VF610 559 select PINCTRL_VF610
587 select PL310_ERRATA_769419 if CACHE_L2X0 560 select PL310_ERRATA_769419 if CACHE_L2X0
588 select SMP_ON_UP if SMP
589 561
590 help 562 help
591 This enables support for Freescale Vybrid VF610 processor. 563 This enables support for Freescale Vybrid VF610 processor.
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 9f5fffd62702..2636adfcb999 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,6 +1,5 @@
1obj-y := cpu.o system.o irq-common.o 1obj-y := cpu.o system.o irq-common.o
2 2
3obj-$(CONFIG_SOC_IMX1) += mm-imx1.o
4obj-$(CONFIG_SOC_IMX21) += mm-imx21.o 3obj-$(CONFIG_SOC_IMX21) += mm-imx21.o
5 4
6obj-$(CONFIG_SOC_IMX25) += cpu-imx25.o mach-imx25.o pm-imx25.o 5obj-$(CONFIG_SOC_IMX25) += cpu-imx25.o mach-imx25.o pm-imx25.o
@@ -35,11 +34,6 @@ obj-y += ssi-fiq.o
35obj-y += ssi-fiq-ksym.o 34obj-y += ssi-fiq-ksym.o
36endif 35endif
37 36
38# i.MX1 based machines
39obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
40obj-$(CONFIG_MACH_APF9328) += mach-apf9328.o
41obj-$(CONFIG_MACH_IMX1_DT) += imx1-dt.o
42
43# i.MX21 based machines 37# i.MX21 based machines
44obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o 38obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
45 39
@@ -93,6 +87,7 @@ obj-$(CONFIG_SOC_IMX53) += suspend-imx53.o
93endif 87endif
94obj-$(CONFIG_SOC_IMX6) += pm-imx6.o 88obj-$(CONFIG_SOC_IMX6) += pm-imx6.o
95 89
90obj-$(CONFIG_SOC_IMX1) += mach-imx1.o
96obj-$(CONFIG_SOC_IMX50) += mach-imx50.o 91obj-$(CONFIG_SOC_IMX50) += mach-imx50.o
97obj-$(CONFIG_SOC_IMX51) += mach-imx51.o 92obj-$(CONFIG_SOC_IMX51) += mach-imx51.o
98obj-$(CONFIG_SOC_IMX53) += mach-imx53.o 93obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index a8f469333027..bcca48138933 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -21,29 +21,24 @@ struct device_node;
21enum mxc_cpu_pwr_mode; 21enum mxc_cpu_pwr_mode;
22struct of_device_id; 22struct of_device_id;
23 23
24void mx1_map_io(void);
25void mx21_map_io(void); 24void mx21_map_io(void);
26void mx27_map_io(void); 25void mx27_map_io(void);
27void mx31_map_io(void); 26void mx31_map_io(void);
28void mx35_map_io(void); 27void mx35_map_io(void);
29void imx1_init_early(void);
30void imx21_init_early(void); 28void imx21_init_early(void);
31void imx27_init_early(void); 29void imx27_init_early(void);
32void imx31_init_early(void); 30void imx31_init_early(void);
33void imx35_init_early(void); 31void imx35_init_early(void);
34void mxc_init_irq(void __iomem *); 32void mxc_init_irq(void __iomem *);
35void mx1_init_irq(void);
36void mx21_init_irq(void); 33void mx21_init_irq(void);
37void mx27_init_irq(void); 34void mx27_init_irq(void);
38void mx31_init_irq(void); 35void mx31_init_irq(void);
39void mx35_init_irq(void); 36void mx35_init_irq(void);
40void imx1_soc_init(void);
41void imx21_soc_init(void); 37void imx21_soc_init(void);
42void imx27_soc_init(void); 38void imx27_soc_init(void);
43void imx31_soc_init(void); 39void imx31_soc_init(void);
44void imx35_soc_init(void); 40void imx35_soc_init(void);
45void epit_timer_init(void __iomem *base, int irq); 41void epit_timer_init(void __iomem *base, int irq);
46int mx1_clocks_init(unsigned long fref);
47int mx21_clocks_init(unsigned long lref, unsigned long fref); 42int mx21_clocks_init(unsigned long lref, unsigned long fref);
48int mx27_clocks_init(unsigned long fref); 43int mx27_clocks_init(unsigned long fref);
49int mx31_clocks_init(unsigned long fref); 44int mx31_clocks_init(unsigned long fref);
diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h
deleted file mode 100644
index f9b5afc6bcd1..000000000000
--- a/arch/arm/mach-imx/devices-imx1.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include "devices/devices-common.h"
10
11extern const struct imx_imx_fb_data imx1_imx_fb_data;
12#define imx1_add_imx_fb(pdata) \
13 imx_add_imx_fb(&imx1_imx_fb_data, pdata)
14
15extern const struct imx_imx_i2c_data imx1_imx_i2c_data;
16#define imx1_add_imx_i2c(pdata) \
17 imx_add_imx_i2c(&imx1_imx_i2c_data, pdata)
18
19extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[];
20#define imx1_add_imx_uart(id, pdata) \
21 imx_add_imx_uart_3irq(&imx1_imx_uart_data[id], pdata)
22#define imx1_add_imx_uart0(pdata) imx1_add_imx_uart(0, pdata)
23#define imx1_add_imx_uart1(pdata) imx1_add_imx_uart(1, pdata)
24
25extern const struct imx_spi_imx_data imx1_cspi_data[];
26#define imx1_add_cspi(id, pdata) \
27 imx_add_spi_imx(&imx1_cspi_data[id], pdata)
28
29#define imx1_add_spi_imx0(pdata) imx1_add_cspi(0, pdata)
30#define imx1_add_spi_imx1(pdata) imx1_add_cspi(1, pdata)
diff --git a/arch/arm/mach-imx/devices/Makefile b/arch/arm/mach-imx/devices/Makefile
index e5cf587bc1a0..aa6cee870795 100644
--- a/arch/arm/mach-imx/devices/Makefile
+++ b/arch/arm/mach-imx/devices/Makefile
@@ -20,7 +20,6 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o
20obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o 20obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o
21obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o 21obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o
22obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o 22obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
23obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o
24obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o 23obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o
25obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o 24obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
26obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o 25obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o
diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h
index 09cebd8cef2b..6920e356f4e5 100644
--- a/arch/arm/mach-imx/devices/devices-common.h
+++ b/arch/arm/mach-imx/devices/devices-common.h
@@ -154,18 +154,6 @@ struct platform_device *__init imx_add_imx_ssi(
154 const struct imx_ssi_platform_data *pdata); 154 const struct imx_ssi_platform_data *pdata);
155 155
156#include <linux/platform_data/serial-imx.h> 156#include <linux/platform_data/serial-imx.h>
157struct imx_imx_uart_3irq_data {
158 int id;
159 resource_size_t iobase;
160 resource_size_t iosize;
161 resource_size_t irqrx;
162 resource_size_t irqtx;
163 resource_size_t irqrts;
164};
165struct platform_device *__init imx_add_imx_uart_3irq(
166 const struct imx_imx_uart_3irq_data *data,
167 const struct imxuart_platform_data *pdata);
168
169struct imx_imx_uart_1irq_data { 157struct imx_imx_uart_1irq_data {
170 int id; 158 int id;
171 resource_size_t iobase; 159 resource_size_t iobase;
diff --git a/arch/arm/mach-imx/devices/platform-imx-fb.c b/arch/arm/mach-imx/devices/platform-imx-fb.c
index 7df6328306f9..aa00272252e0 100644
--- a/arch/arm/mach-imx/devices/platform-imx-fb.c
+++ b/arch/arm/mach-imx/devices/platform-imx-fb.c
@@ -19,11 +19,6 @@
19 .irq = soc ## _INT_LCDC, \ 19 .irq = soc ## _INT_LCDC, \
20 } 20 }
21 21
22#ifdef CONFIG_SOC_IMX1
23const struct imx_imx_fb_data imx1_imx_fb_data __initconst =
24 imx_imx_fb_data_entry_single(MX1, "imx1-fb", SZ_4K);
25#endif /* ifdef CONFIG_SOC_IMX1 */
26
27#ifdef CONFIG_SOC_IMX21 22#ifdef CONFIG_SOC_IMX21
28const struct imx_imx_fb_data imx21_imx_fb_data __initconst = 23const struct imx_imx_fb_data imx21_imx_fb_data __initconst =
29 imx_imx_fb_data_entry_single(MX21, "imx21-fb", SZ_4K); 24 imx_imx_fb_data_entry_single(MX21, "imx21-fb", SZ_4K);
diff --git a/arch/arm/mach-imx/devices/platform-imx-i2c.c b/arch/arm/mach-imx/devices/platform-imx-i2c.c
index ae9791522fc8..9822bedb5d09 100644
--- a/arch/arm/mach-imx/devices/platform-imx-i2c.c
+++ b/arch/arm/mach-imx/devices/platform-imx-i2c.c
@@ -21,11 +21,6 @@
21#define imx_imx_i2c_data_entry(soc, _devid, _id, _hwid, _size) \ 21#define imx_imx_i2c_data_entry(soc, _devid, _id, _hwid, _size) \
22 [_id] = imx_imx_i2c_data_entry_single(soc, _devid, _id, _hwid, _size) 22 [_id] = imx_imx_i2c_data_entry_single(soc, _devid, _id, _hwid, _size)
23 23
24#ifdef CONFIG_SOC_IMX1
25const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst =
26 imx_imx_i2c_data_entry_single(MX1, "imx1-i2c", 0, , SZ_4K);
27#endif /* ifdef CONFIG_SOC_IMX1 */
28
29#ifdef CONFIG_SOC_IMX21 24#ifdef CONFIG_SOC_IMX21
30const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst = 25const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst =
31 imx_imx_i2c_data_entry_single(MX21, "imx21-i2c", 0, , SZ_4K); 26 imx_imx_i2c_data_entry_single(MX21, "imx21-i2c", 0, , SZ_4K);
diff --git a/arch/arm/mach-imx/devices/platform-imx-uart.c b/arch/arm/mach-imx/devices/platform-imx-uart.c
index 6962cff4a950..e3c89e9caf93 100644
--- a/arch/arm/mach-imx/devices/platform-imx-uart.c
+++ b/arch/arm/mach-imx/devices/platform-imx-uart.c
@@ -27,15 +27,6 @@
27 .irq = soc ## _INT_UART ## _hwid, \ 27 .irq = soc ## _INT_UART ## _hwid, \
28 } 28 }
29 29
30#ifdef CONFIG_SOC_IMX1
31const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst = {
32#define imx1_imx_uart_data_entry(_id, _hwid) \
33 imx_imx_uart_3irq_data_entry(MX1, _id, _hwid, 0xd0)
34 imx1_imx_uart_data_entry(0, 1),
35 imx1_imx_uart_data_entry(1, 2),
36};
37#endif /* ifdef CONFIG_SOC_IMX1 */
38
39#ifdef CONFIG_SOC_IMX21 30#ifdef CONFIG_SOC_IMX21
40const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = { 31const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = {
41#define imx21_imx_uart_data_entry(_id, _hwid) \ 32#define imx21_imx_uart_data_entry(_id, _hwid) \
@@ -82,34 +73,6 @@ const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
82}; 73};
83#endif /* ifdef CONFIG_SOC_IMX35 */ 74#endif /* ifdef CONFIG_SOC_IMX35 */
84 75
85struct platform_device *__init imx_add_imx_uart_3irq(
86 const struct imx_imx_uart_3irq_data *data,
87 const struct imxuart_platform_data *pdata)
88{
89 struct resource res[] = {
90 {
91 .start = data->iobase,
92 .end = data->iobase + data->iosize - 1,
93 .flags = IORESOURCE_MEM,
94 }, {
95 .start = data->irqrx,
96 .end = data->irqrx,
97 .flags = IORESOURCE_IRQ,
98 }, {
99 .start = data->irqtx,
100 .end = data->irqtx,
101 .flags = IORESOURCE_IRQ,
102 }, {
103 .start = data->irqrts,
104 .end = data->irqrx,
105 .flags = IORESOURCE_IRQ,
106 },
107 };
108
109 return imx_add_platform_device("imx1-uart", data->id, res,
110 ARRAY_SIZE(res), pdata, sizeof(*pdata));
111}
112
113struct platform_device *__init imx_add_imx_uart_1irq( 76struct platform_device *__init imx_add_imx_uart_1irq(
114 const struct imx_imx_uart_1irq_data *data, 77 const struct imx_imx_uart_1irq_data *data,
115 const struct imxuart_platform_data *pdata) 78 const struct imxuart_platform_data *pdata)
diff --git a/arch/arm/mach-imx/devices/platform-spi_imx.c b/arch/arm/mach-imx/devices/platform-spi_imx.c
index 5e9707b47f92..d93c446c9c02 100644
--- a/arch/arm/mach-imx/devices/platform-spi_imx.c
+++ b/arch/arm/mach-imx/devices/platform-spi_imx.c
@@ -21,15 +21,6 @@
21#define imx_spi_imx_data_entry(soc, type, devid, id, hwid, size) \ 21#define imx_spi_imx_data_entry(soc, type, devid, id, hwid, size) \
22 [id] = imx_spi_imx_data_entry_single(soc, type, devid, id, hwid, size) 22 [id] = imx_spi_imx_data_entry_single(soc, type, devid, id, hwid, size)
23 23
24#ifdef CONFIG_SOC_IMX1
25const struct imx_spi_imx_data imx1_cspi_data[] __initconst = {
26#define imx1_cspi_data_entry(_id, _hwid) \
27 imx_spi_imx_data_entry(MX1, CSPI, "imx1-cspi", _id, _hwid, SZ_4K)
28 imx1_cspi_data_entry(0, 1),
29 imx1_cspi_data_entry(1, 2),
30};
31#endif
32
33#ifdef CONFIG_SOC_IMX21 24#ifdef CONFIG_SOC_IMX21
34const struct imx_spi_imx_data imx21_cspi_data[] __initconst = { 25const struct imx_spi_imx_data imx21_cspi_data[] __initconst = {
35#define imx21_cspi_data_entry(_id, _hwid) \ 26#define imx21_cspi_data_entry(_id, _hwid) \
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
index d737f95ebb07..90e10cbd8fd1 100644
--- a/arch/arm/mach-imx/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -112,7 +112,6 @@
112#include "mx2x.h" 112#include "mx2x.h"
113#include "mx21.h" 113#include "mx21.h"
114#include "mx27.h" 114#include "mx27.h"
115#include "mx1.h"
116 115
117#define imx_map_entry(soc, name, _type) { \ 116#define imx_map_entry(soc, name, _type) { \
118 .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ 117 .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
@@ -121,7 +120,7 @@
121 .type = _type, \ 120 .type = _type, \
122} 121}
123 122
124/* There's a off-by-one betweem the gpio bank number and the gpiochip */ 123/* There's an off-by-one between the gpio bank number and the gpiochip */
125/* range e.g. GPIO_1_5 is gpio 5 under linux */ 124/* range e.g. GPIO_1_5 is gpio 5 under linux */
126#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr)) 125#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
127 126
diff --git a/arch/arm/mach-imx/iomux-mx1.h b/arch/arm/mach-imx/iomux-mx1.h
deleted file mode 100644
index 95f4681d85d7..000000000000
--- a/arch/arm/mach-imx/iomux-mx1.h
+++ /dev/null
@@ -1,155 +0,0 @@
1/*
2 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18#ifndef __MACH_IOMUX_MX1_H__
19#define __MACH_IOMUX_MX1_H__
20
21#include "iomux-v1.h"
22
23#define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0)
24#define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0)
25#define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 1)
26#define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1)
27#define PA2_PF_PWM0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 2)
28#define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3)
29#define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4)
30#define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5)
31#define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6)
32#define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7)
33#define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8)
34#define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9)
35#define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10)
36#define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11)
37#define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12)
38#define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13)
39#define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14)
40#define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15)
41#define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16)
42#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17)
43#define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17)
44#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18)
45#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19)
46#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20)
47#define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21)
48#define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22)
49#define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23)
50#define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24)
51#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24)
52#define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25)
53#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25)
54#define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26)
55#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26)
56#define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27)
57#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27)
58#define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28)
59#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28)
60#define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29)
61#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29)
62#define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30)
63#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30)
64#define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31)
65#define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31)
66#define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8)
67#define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8)
68#define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9)
69#define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9)
70#define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10)
71#define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10)
72#define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11)
73#define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11)
74#define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12)
75#define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12)
76#define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13)
77#define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13)
78#define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14)
79#define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15)
80#define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_AF | GPIO_IN | 16)
81#define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_AF | GPIO_OUT | 17)
82#define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18)
83#define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19)
84#define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20)
85#define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21)
86#define PB22_PF_USBD_RCV (GPIO_PORTB | GPIO_PF | 22)
87#define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23)
88#define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24)
89#define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25)
90#define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26)
91#define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27)
92#define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_PF | GPIO_OUT | 28)
93#define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_PF | GPIO_IN | 29)
94#define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_PF | GPIO_OUT | 30)
95#define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_PF | GPIO_IN | 31)
96#define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3)
97#define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4)
98#define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_PF | GPIO_IN | 5)
99#define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_PF | GPIO_OUT | 6)
100#define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7)
101#define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8)
102#define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9)
103#define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_PF | GPIO_IN | 10)
104#define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11)
105#define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 12)
106#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13)
107#define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14)
108#define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15)
109#define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16)
110#define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17)
111#define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 24)
112#define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 25)
113#define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 26)
114#define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 27)
115#define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 28)
116#define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 29)
117#define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30)
118#define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 31)
119#define PD6_PF_LSCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 6)
120#define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7)
121#define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_AF | GPIO_IN | 7)
122#define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7)
123#define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8)
124#define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_AF | GPIO_OUT | 8)
125#define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8)
126#define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9)
127#define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_AF | GPIO_OUT | 9)
128#define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 9)
129#define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_PF | GPIO_OUT | 10)
130#define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_AF | GPIO_OUT | 10)
131#define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 10)
132#define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_PF | GPIO_OUT | 11)
133#define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_PF | GPIO_OUT | 12)
134#define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 13)
135#define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 14)
136#define PD15_PF_LD0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 15)
137#define PD16_PF_LD1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 16)
138#define PD17_PF_LD2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17)
139#define PD18_PF_LD3 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18)
140#define PD19_PF_LD4 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19)
141#define PD20_PF_LD5 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20)
142#define PD21_PF_LD6 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21)
143#define PD22_PF_LD7 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22)
144#define PD23_PF_LD8 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 23)
145#define PD24_PF_LD9 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24)
146#define PD25_PF_LD10 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25)
147#define PD26_PF_LD11 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26)
148#define PD27_PF_LD12 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27)
149#define PD28_PF_LD13 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28)
150#define PD29_PF_LD14 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29)
151#define PD30_PF_LD15 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 30)
152#define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31)
153#define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31)
154
155#endif /* ifndef __MACH_IOMUX_MX1_H__ */
diff --git a/arch/arm/mach-imx/iomux-mx3.h b/arch/arm/mach-imx/iomux-mx3.h
index 2e4a0ddca76c..368667b32760 100644
--- a/arch/arm/mach-imx/iomux-mx3.h
+++ b/arch/arm/mach-imx/iomux-mx3.h
@@ -598,10 +598,7 @@ enum iomux_pins {
598#define MX31_PIN_CONTRAST__CONTRAST IOMUX_MODE(MX31_PIN_CONTRAST, IOMUX_CONFIG_FUNC) 598#define MX31_PIN_CONTRAST__CONTRAST IOMUX_MODE(MX31_PIN_CONTRAST, IOMUX_CONFIG_FUNC)
599#define MX31_PIN_D3_SPL__D3_SPL IOMUX_MODE(MX31_PIN_D3_SPL, IOMUX_CONFIG_FUNC) 599#define MX31_PIN_D3_SPL__D3_SPL IOMUX_MODE(MX31_PIN_D3_SPL, IOMUX_CONFIG_FUNC)
600#define MX31_PIN_D3_CLS__D3_CLS IOMUX_MODE(MX31_PIN_D3_CLS, IOMUX_CONFIG_FUNC) 600#define MX31_PIN_D3_CLS__D3_CLS IOMUX_MODE(MX31_PIN_D3_CLS, IOMUX_CONFIG_FUNC)
601#define MX31_PIN_LCS0__GPI03_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO)
602#define MX31_PIN_GPIO1_1__GPIO IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO) 601#define MX31_PIN_GPIO1_1__GPIO IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO)
603#define MX31_PIN_I2C_CLK__SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC)
604#define MX31_PIN_I2C_DAT__SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
605#define MX31_PIN_DCD_DTE1__I2C2_SDA IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2) 602#define MX31_PIN_DCD_DTE1__I2C2_SDA IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2)
606#define MX31_PIN_RI_DTE1__I2C2_SCL IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2) 603#define MX31_PIN_RI_DTE1__I2C2_SCL IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2)
607#define MX31_PIN_CSPI2_SS2__I2C3_SDA IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_ALT1) 604#define MX31_PIN_CSPI2_SS2__I2C3_SDA IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_ALT1)
@@ -665,37 +662,6 @@ enum iomux_pins {
665#define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO) 662#define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO)
666#define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC) 663#define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
667#define MX31_PIN_I2C_CLK__I2C1_SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC) 664#define MX31_PIN_I2C_CLK__I2C1_SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC)
668#define MX31_PIN_DCD_DTE1__I2C2_SDA IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2)
669#define MX31_PIN_RI_DTE1__I2C2_SCL IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2)
670#define MX31_PIN_ATA_CS0__GPIO3_26 IOMUX_MODE(MX31_PIN_ATA_CS0, IOMUX_CONFIG_GPIO)
671#define MX31_PIN_ATA_CS1__GPIO3_27 IOMUX_MODE(MX31_PIN_ATA_CS1, IOMUX_CONFIG_GPIO)
672#define MX31_PIN_PC_PWRON__SD2_DATA3 IOMUX_MODE(MX31_PIN_PC_PWRON, IOMUX_CONFIG_ALT1)
673#define MX31_PIN_PC_VS1__SD2_DATA2 IOMUX_MODE(MX31_PIN_PC_VS1, IOMUX_CONFIG_ALT1)
674#define MX31_PIN_PC_READY__SD2_DATA1 IOMUX_MODE(MX31_PIN_PC_READY, IOMUX_CONFIG_ALT1)
675#define MX31_PIN_PC_WAIT_B__SD2_DATA0 IOMUX_MODE(MX31_PIN_PC_WAIT_B, IOMUX_CONFIG_ALT1)
676#define MX31_PIN_PC_CD2_B__SD2_CLK IOMUX_MODE(MX31_PIN_PC_CD2_B, IOMUX_CONFIG_ALT1)
677#define MX31_PIN_PC_CD1_B__SD2_CMD IOMUX_MODE(MX31_PIN_PC_CD1_B, IOMUX_CONFIG_ALT1)
678#define MX31_PIN_ATA_DIOR__GPIO3_28 IOMUX_MODE(MX31_PIN_ATA_DIOR, IOMUX_CONFIG_GPIO)
679#define MX31_PIN_ATA_DIOW__GPIO3_29 IOMUX_MODE(MX31_PIN_ATA_DIOW, IOMUX_CONFIG_GPIO)
680#define MX31_PIN_CSI_D4__CSI_D4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_FUNC)
681#define MX31_PIN_CSI_D5__CSI_D5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_FUNC)
682#define MX31_PIN_CSI_D6__CSI_D6 IOMUX_MODE(MX31_PIN_CSI_D6, IOMUX_CONFIG_FUNC)
683#define MX31_PIN_CSI_D7__CSI_D7 IOMUX_MODE(MX31_PIN_CSI_D7, IOMUX_CONFIG_FUNC)
684#define MX31_PIN_CSI_D8__CSI_D8 IOMUX_MODE(MX31_PIN_CSI_D8, IOMUX_CONFIG_FUNC)
685#define MX31_PIN_CSI_D9__CSI_D9 IOMUX_MODE(MX31_PIN_CSI_D9, IOMUX_CONFIG_FUNC)
686#define MX31_PIN_CSI_D10__CSI_D10 IOMUX_MODE(MX31_PIN_CSI_D10, IOMUX_CONFIG_FUNC)
687#define MX31_PIN_CSI_D11__CSI_D11 IOMUX_MODE(MX31_PIN_CSI_D11, IOMUX_CONFIG_FUNC)
688#define MX31_PIN_CSI_D12__CSI_D12 IOMUX_MODE(MX31_PIN_CSI_D12, IOMUX_CONFIG_FUNC)
689#define MX31_PIN_CSI_D13__CSI_D13 IOMUX_MODE(MX31_PIN_CSI_D13, IOMUX_CONFIG_FUNC)
690#define MX31_PIN_CSI_D14__CSI_D14 IOMUX_MODE(MX31_PIN_CSI_D14, IOMUX_CONFIG_FUNC)
691#define MX31_PIN_CSI_D15__CSI_D15 IOMUX_MODE(MX31_PIN_CSI_D15, IOMUX_CONFIG_FUNC)
692#define MX31_PIN_CSI_HSYNC__CSI_HSYNC IOMUX_MODE(MX31_PIN_CSI_HSYNC, IOMUX_CONFIG_FUNC)
693#define MX31_PIN_CSI_MCLK__CSI_MCLK IOMUX_MODE(MX31_PIN_CSI_MCLK, IOMUX_CONFIG_FUNC)
694#define MX31_PIN_CSI_PIXCLK__CSI_PIXCLK IOMUX_MODE(MX31_PIN_CSI_PIXCLK, IOMUX_CONFIG_FUNC)
695#define MX31_PIN_CSI_VSYNC__CSI_VSYNC IOMUX_MODE(MX31_PIN_CSI_VSYNC, IOMUX_CONFIG_FUNC)
696#define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO)
697#define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO)
698#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO)
699#define MX31_PIN_GPIO1_0__GPIO1_0 IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO) 665#define MX31_PIN_GPIO1_0__GPIO1_0 IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO)
700#define MX31_PIN_SVEN0__GPIO2_0 IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO) 666#define MX31_PIN_SVEN0__GPIO2_0 IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO)
701#define MX31_PIN_STX0__GPIO2_1 IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO) 667#define MX31_PIN_STX0__GPIO2_1 IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO)
diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c
deleted file mode 100644
index ebbb5ab63529..000000000000
--- a/arch/arm/mach-imx/mach-apf9328.c
+++ /dev/null
@@ -1,148 +0,0 @@
1/*
2 * linux/arch/arm/mach-imx/mach-apf9328.c
3 *
4 * Copyright (c) 2005-2011 ARMadeus systems <support@armadeus.com>
5 *
6 * This work is based on mach-scb9328.c which is:
7 * Copyright (c) 2004 Sascha Hauer <saschahauer@web.de>
8 * Copyright (c) 2006-2008 Juergen Beisert <jbeisert@netscape.net>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 */
15
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/platform_device.h>
19#include <linux/mtd/physmap.h>
20#include <linux/dm9000.h>
21#include <linux/gpio.h>
22#include <linux/i2c.h>
23
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h>
26#include <asm/mach/time.h>
27
28#include "common.h"
29#include "devices-imx1.h"
30#include "hardware.h"
31#include "iomux-mx1.h"
32
33static const int apf9328_pins[] __initconst = {
34 /* UART1 */
35 PC9_PF_UART1_CTS,
36 PC10_PF_UART1_RTS,
37 PC11_PF_UART1_TXD,
38 PC12_PF_UART1_RXD,
39 /* UART2 */
40 PB28_PF_UART2_CTS,
41 PB29_PF_UART2_RTS,
42 PB30_PF_UART2_TXD,
43 PB31_PF_UART2_RXD,
44 /* I2C */
45 PA15_PF_I2C_SDA,
46 PA16_PF_I2C_SCL,
47};
48
49/*
50 * The APF9328 can have up to 32MB NOR Flash
51 */
52static struct resource flash_resource = {
53 .start = MX1_CS0_PHYS,
54 .end = MX1_CS0_PHYS + SZ_32M - 1,
55 .flags = IORESOURCE_MEM,
56};
57
58static struct physmap_flash_data apf9328_flash_data = {
59 .width = 2,
60};
61
62static struct platform_device apf9328_flash_device = {
63 .name = "physmap-flash",
64 .id = 0,
65 .dev = {
66 .platform_data = &apf9328_flash_data,
67 },
68 .resource = &flash_resource,
69 .num_resources = 1,
70};
71
72/*
73 * APF9328 has a DM9000 Ethernet controller
74 */
75static struct dm9000_plat_data dm9000_setup = {
76 .flags = DM9000_PLATF_16BITONLY
77};
78
79static struct resource dm9000_resources[] = {
80 {
81 .start = MX1_CS4_PHYS + 0x00C00000,
82 .end = MX1_CS4_PHYS + 0x00C00001,
83 .flags = IORESOURCE_MEM,
84 }, {
85 .start = MX1_CS4_PHYS + 0x00C00002,
86 .end = MX1_CS4_PHYS + 0x00C00003,
87 .flags = IORESOURCE_MEM,
88 }, {
89 /* irq number is run-time assigned */
90 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
91 },
92};
93
94static struct platform_device dm9000x_device = {
95 .name = "dm9000",
96 .id = 0,
97 .num_resources = ARRAY_SIZE(dm9000_resources),
98 .resource = dm9000_resources,
99 .dev = {
100 .platform_data = &dm9000_setup,
101 }
102};
103
104static const struct imxuart_platform_data uart1_pdata __initconst = {
105 .flags = IMXUART_HAVE_RTSCTS,
106};
107
108static const struct imxi2c_platform_data apf9328_i2c_data __initconst = {
109 .bitrate = 100000,
110};
111
112static struct platform_device *devices[] __initdata = {
113 &apf9328_flash_device,
114 &dm9000x_device,
115};
116
117static void __init apf9328_init(void)
118{
119 imx1_soc_init();
120
121 mxc_gpio_setup_multiple_pins(apf9328_pins,
122 ARRAY_SIZE(apf9328_pins),
123 "APF9328");
124
125 imx1_add_imx_uart0(NULL);
126 imx1_add_imx_uart1(&uart1_pdata);
127
128 imx1_add_imx_i2c(&apf9328_i2c_data);
129
130 dm9000_resources[2].start = gpio_to_irq(IMX_GPIO_NR(2, 14));
131 dm9000_resources[2].end = gpio_to_irq(IMX_GPIO_NR(2, 14));
132 platform_add_devices(devices, ARRAY_SIZE(devices));
133}
134
135static void __init apf9328_timer_init(void)
136{
137 mx1_clocks_init(32768);
138}
139
140MACHINE_START(APF9328, "Armadeus APF9328")
141 /* Maintainer: Gwenhael Goavec-Merou, ARMadeus Systems */
142 .map_io = mx1_map_io,
143 .init_early = imx1_init_early,
144 .init_irq = mx1_init_irq,
145 .init_time = apf9328_timer_init,
146 .init_machine = apf9328_init,
147 .restart = mxc_restart,
148MACHINE_END
diff --git a/arch/arm/mach-imx/imx1-dt.c b/arch/arm/mach-imx/mach-imx1.c
index 6f915b0961c4..de5ab8d88549 100644
--- a/arch/arm/mach-imx/imx1-dt.c
+++ b/arch/arm/mach-imx/mach-imx1.c
@@ -9,8 +9,27 @@
9 9
10#include <linux/of_platform.h> 10#include <linux/of_platform.h>
11#include <asm/mach/arch.h> 11#include <asm/mach/arch.h>
12#include <asm/mach/map.h>
12 13
13#include "common.h" 14#include "common.h"
15#include "hardware.h"
16
17#define MX1_AVIC_ADDR 0x00223000
18
19static void __init imx1_init_early(void)
20{
21 mxc_set_cpu_type(MXC_CPU_MX1);
22}
23
24static void __init imx1_init_irq(void)
25{
26 void __iomem *avic_addr;
27
28 avic_addr = ioremap(MX1_AVIC_ADDR, SZ_4K);
29 WARN_ON(!avic_addr);
30
31 mxc_init_irq(avic_addr);
32}
14 33
15static const char * const imx1_dt_board_compat[] __initconst = { 34static const char * const imx1_dt_board_compat[] __initconst = {
16 "fsl,imx1", 35 "fsl,imx1",
@@ -18,9 +37,9 @@ static const char * const imx1_dt_board_compat[] __initconst = {
18}; 37};
19 38
20DT_MACHINE_START(IMX1_DT, "Freescale i.MX1 (Device Tree Support)") 39DT_MACHINE_START(IMX1_DT, "Freescale i.MX1 (Device Tree Support)")
21 .map_io = mx1_map_io, 40 .map_io = debug_ll_io_init,
22 .init_early = imx1_init_early, 41 .init_early = imx1_init_early,
23 .init_irq = mx1_init_irq, 42 .init_irq = imx1_init_irq,
24 .dt_compat = imx1_dt_board_compat, 43 .dt_compat = imx1_dt_board_compat,
25 .restart = mxc_restart, 44 .restart = mxc_restart,
26MACHINE_END 45MACHINE_END
diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c
index 31df4361996f..e277d9c230e5 100644
--- a/arch/arm/mach-imx/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c
@@ -63,7 +63,7 @@
63 */ 63 */
64#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050) 64#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050)
65 65
66#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) 66#if IS_ENABLED(CONFIG_SERIAL_8250)
67/* 67/*
68 * KZM-ARM11-01 has an external UART on FPGA 68 * KZM-ARM11-01 has an external UART on FPGA
69 */ 69 */
@@ -141,7 +141,7 @@ static inline int kzm_init_ext_uart(void)
141/* 141/*
142 * SMSC LAN9118 142 * SMSC LAN9118
143 */ 143 */
144#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) 144#if IS_ENABLED(CONFIG_SMSC911X)
145static struct smsc911x_platform_config kzm_smsc9118_config = { 145static struct smsc911x_platform_config kzm_smsc9118_config = {
146 .phy_interface = PHY_INTERFACE_MODE_MII, 146 .phy_interface = PHY_INTERFACE_MODE_MII,
147 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, 147 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
@@ -201,7 +201,7 @@ static inline int kzm_init_smsc9118(void)
201} 201}
202#endif 202#endif
203 203
204#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) 204#if IS_ENABLED(CONFIG_SERIAL_IMX)
205static const struct imxuart_platform_data uart_pdata __initconst = { 205static const struct imxuart_platform_data uart_pdata __initconst = {
206 .flags = IMXUART_HAVE_RTSCTS, 206 .flags = IMXUART_HAVE_RTSCTS,
207}; 207};
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index 6d879417db49..a159a7739993 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -149,7 +149,7 @@ static unsigned int pcm037_pins[] = {
149 MX31_PIN_CONTRAST__CONTRAST, 149 MX31_PIN_CONTRAST__CONTRAST,
150 MX31_PIN_D3_SPL__D3_SPL, 150 MX31_PIN_D3_SPL__D3_SPL,
151 MX31_PIN_D3_CLS__D3_CLS, 151 MX31_PIN_D3_CLS__D3_CLS,
152 MX31_PIN_LCS0__GPI03_23, 152 MX31_PIN_LCS0__GPIO3_23,
153 /* CSI */ 153 /* CSI */
154 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO), 154 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO),
155 MX31_PIN_CSI_D6__CSI_D6, 155 MX31_PIN_CSI_D6__CSI_D6,
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
deleted file mode 100644
index 1f6bc3f7ae14..000000000000
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ /dev/null
@@ -1,143 +0,0 @@
1/*
2 * linux/arch/arm/mach-mx1/mach-scb9328.c
3 *
4 * Copyright (c) 2004 Sascha Hauer <saschahauer@web.de>
5 * Copyright (c) 2006-2008 Juergen Beisert <jbeisert@netscape.net>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12
13#include <linux/platform_device.h>
14#include <linux/mtd/physmap.h>
15#include <linux/interrupt.h>
16#include <linux/dm9000.h>
17#include <linux/gpio.h>
18
19#include <asm/mach-types.h>
20#include <asm/mach/arch.h>
21#include <asm/mach/time.h>
22
23#include "common.h"
24#include "devices-imx1.h"
25#include "hardware.h"
26#include "iomux-mx1.h"
27
28/*
29 * This scb9328 has a 32MiB flash
30 */
31static struct resource flash_resource = {
32 .start = MX1_CS0_PHYS,
33 .end = MX1_CS0_PHYS + (32 * 1024 * 1024) - 1,
34 .flags = IORESOURCE_MEM,
35};
36
37static struct physmap_flash_data scb_flash_data = {
38 .width = 2,
39};
40
41static struct platform_device scb_flash_device = {
42 .name = "physmap-flash",
43 .id = 0,
44 .dev = {
45 .platform_data = &scb_flash_data,
46 },
47 .resource = &flash_resource,
48 .num_resources = 1,
49};
50
51/*
52 * scb9328 has a DM9000 network controller
53 * connected to CS5, with 16 bit data path
54 * and interrupt connected to GPIO 3
55 */
56
57/*
58 * internal datapath is fixed 16 bit
59 */
60static struct dm9000_plat_data dm9000_platdata = {
61 .flags = DM9000_PLATF_16BITONLY,
62};
63
64/*
65 * the DM9000 drivers wants two defined address spaces
66 * to gain access to address latch registers and the data path.
67 */
68static struct resource dm9000x_resources[] = {
69 {
70 .name = "address area",
71 .start = MX1_CS5_PHYS,
72 .end = MX1_CS5_PHYS + 1,
73 .flags = IORESOURCE_MEM, /* address access */
74 }, {
75 .name = "data area",
76 .start = MX1_CS5_PHYS + 4,
77 .end = MX1_CS5_PHYS + 5,
78 .flags = IORESOURCE_MEM, /* data access */
79 }, {
80 /* irq number is run-time assigned */
81 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
82 },
83};
84
85static struct platform_device dm9000x_device = {
86 .name = "dm9000",
87 .id = 0,
88 .num_resources = ARRAY_SIZE(dm9000x_resources),
89 .resource = dm9000x_resources,
90 .dev = {
91 .platform_data = &dm9000_platdata,
92 }
93};
94
95static const int mxc_uart1_pins[] = {
96 PC9_PF_UART1_CTS,
97 PC10_PF_UART1_RTS,
98 PC11_PF_UART1_TXD,
99 PC12_PF_UART1_RXD,
100};
101
102static const struct imxuart_platform_data uart_pdata __initconst = {
103 .flags = IMXUART_HAVE_RTSCTS,
104};
105
106static struct platform_device *devices[] __initdata = {
107 &scb_flash_device,
108 &dm9000x_device,
109};
110
111/*
112 * scb9328_init - Init the CPU card itself
113 */
114static void __init scb9328_init(void)
115{
116 imx1_soc_init();
117
118 mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
119 ARRAY_SIZE(mxc_uart1_pins), "UART1");
120
121 imx1_add_imx_uart0(&uart_pdata);
122
123 printk(KERN_INFO"Scb9328: Adding devices\n");
124 dm9000x_resources[2].start = gpio_to_irq(IMX_GPIO_NR(3, 3));
125 dm9000x_resources[2].end = gpio_to_irq(IMX_GPIO_NR(3, 3));
126 platform_add_devices(devices, ARRAY_SIZE(devices));
127}
128
129static void __init scb9328_timer_init(void)
130{
131 mx1_clocks_init(32000);
132}
133
134MACHINE_START(SCB9328, "Synertronixx scb9328")
135 /* Sascha Hauer */
136 .atag_offset = 100,
137 .map_io = mx1_map_io,
138 .init_early = imx1_init_early,
139 .init_irq = mx1_init_irq,
140 .init_time = scb9328_timer_init,
141 .init_machine = scb9328_init,
142 .restart = mxc_restart,
143MACHINE_END
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
deleted file mode 100644
index 9a42f19be81e..000000000000
--- a/arch/arm/mach-imx/mm-imx1.c
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * author: Sascha Hauer
3 * Created: april 20th, 2004
4 * Copyright: Synertronixx GmbH
5 *
6 * Common code for i.MX1 machines
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/io.h>
21#include <linux/pinctrl/machine.h>
22
23#include <asm/mach/map.h>
24
25#include "common.h"
26#include "devices/devices-common.h"
27#include "hardware.h"
28#include "iomux-v1.h"
29
30static struct map_desc imx_io_desc[] __initdata = {
31 imx_map_entry(MX1, IO, MT_DEVICE),
32};
33
34void __init mx1_map_io(void)
35{
36 iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
37}
38
39void __init imx1_init_early(void)
40{
41 mxc_set_cpu_type(MXC_CPU_MX1);
42 imx_iomuxv1_init(MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
43 MX1_NUM_GPIO_PORT);
44}
45
46void __init mx1_init_irq(void)
47{
48 mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR));
49}
50
51void __init imx1_soc_init(void)
52{
53 imx1_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
54 mxc_device_init();
55
56 mxc_register_gpio("imx1-gpio", 0, MX1_GPIO1_BASE_ADDR, SZ_256,
57 MX1_GPIO_INT_PORTA, 0);
58 mxc_register_gpio("imx1-gpio", 1, MX1_GPIO2_BASE_ADDR, SZ_256,
59 MX1_GPIO_INT_PORTB, 0);
60 mxc_register_gpio("imx1-gpio", 2, MX1_GPIO3_BASE_ADDR, SZ_256,
61 MX1_GPIO_INT_PORTC, 0);
62 mxc_register_gpio("imx1-gpio", 3, MX1_GPIO4_BASE_ADDR, SZ_256,
63 MX1_GPIO_INT_PORTD, 0);
64 imx_add_imx_dma("imx1-dma", MX1_DMA_BASE_ADDR,
65 MX1_DMA_INT, MX1_DMA_ERR);
66 pinctrl_provide_dummies();
67}
diff --git a/arch/arm/mach-imx/mx1.h b/arch/arm/mach-imx/mx1.h
deleted file mode 100644
index 45bd31cc34d6..000000000000
--- a/arch/arm/mach-imx/mx1.h
+++ /dev/null
@@ -1,172 +0,0 @@
1/*
2 * Copyright (C) 1997,1998 Russell King
3 * Copyright (C) 1999 ARM Limited
4 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __MACH_MX1_H__
13#define __MACH_MX1_H__
14
15/*
16 * Memory map
17 */
18#define MX1_IO_BASE_ADDR 0x00200000
19#define MX1_IO_SIZE SZ_1M
20
21#define MX1_CS0_PHYS 0x10000000
22#define MX1_CS0_SIZE 0x02000000
23
24#define MX1_CS1_PHYS 0x12000000
25#define MX1_CS1_SIZE 0x01000000
26
27#define MX1_CS2_PHYS 0x13000000
28#define MX1_CS2_SIZE 0x01000000
29
30#define MX1_CS3_PHYS 0x14000000
31#define MX1_CS3_SIZE 0x01000000
32
33#define MX1_CS4_PHYS 0x15000000
34#define MX1_CS4_SIZE 0x01000000
35
36#define MX1_CS5_PHYS 0x16000000
37#define MX1_CS5_SIZE 0x01000000
38
39/*
40 * Register BASEs, based on OFFSETs
41 */
42#define MX1_AIPI1_BASE_ADDR (0x00000 + MX1_IO_BASE_ADDR)
43#define MX1_WDT_BASE_ADDR (0x01000 + MX1_IO_BASE_ADDR)
44#define MX1_TIM1_BASE_ADDR (0x02000 + MX1_IO_BASE_ADDR)
45#define MX1_TIM2_BASE_ADDR (0x03000 + MX1_IO_BASE_ADDR)
46#define MX1_RTC_BASE_ADDR (0x04000 + MX1_IO_BASE_ADDR)
47#define MX1_LCDC_BASE_ADDR (0x05000 + MX1_IO_BASE_ADDR)
48#define MX1_UART1_BASE_ADDR (0x06000 + MX1_IO_BASE_ADDR)
49#define MX1_UART2_BASE_ADDR (0x07000 + MX1_IO_BASE_ADDR)
50#define MX1_PWM_BASE_ADDR (0x08000 + MX1_IO_BASE_ADDR)
51#define MX1_DMA_BASE_ADDR (0x09000 + MX1_IO_BASE_ADDR)
52#define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR)
53#define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR)
54#define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR)
55#define MX1_CSPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR)
56#define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR)
57#define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR)
58#define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR)
59#define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR)
60#define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR)
61#define MX1_CSPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR)
62#define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR)
63#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR)
64#define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR)
65#define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
66#define MX1_GPIO1_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
67#define MX1_GPIO2_BASE_ADDR (0x1C100 + MX1_IO_BASE_ADDR)
68#define MX1_GPIO3_BASE_ADDR (0x1C200 + MX1_IO_BASE_ADDR)
69#define MX1_GPIO4_BASE_ADDR (0x1C300 + MX1_IO_BASE_ADDR)
70#define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR)
71#define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR)
72#define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR)
73#define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR)
74#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR)
75
76/* macro to get at IO space when running virtually */
77#define MX1_IO_P2V(x) IMX_IO_P2V(x)
78#define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x))
79
80/* fixed interrput numbers */
81#include <asm/irq.h>
82#define MX1_INT_SOFTINT (NR_IRQS_LEGACY + 0)
83#define MX1_INT_CSI (NR_IRQS_LEGACY + 6)
84#define MX1_DSPA_MAC_INT (NR_IRQS_LEGACY + 7)
85#define MX1_DSPA_INT (NR_IRQS_LEGACY + 8)
86#define MX1_COMP_INT (NR_IRQS_LEGACY + 9)
87#define MX1_MSHC_XINT (NR_IRQS_LEGACY + 10)
88#define MX1_GPIO_INT_PORTA (NR_IRQS_LEGACY + 11)
89#define MX1_GPIO_INT_PORTB (NR_IRQS_LEGACY + 12)
90#define MX1_GPIO_INT_PORTC (NR_IRQS_LEGACY + 13)
91#define MX1_INT_LCDC (NR_IRQS_LEGACY + 14)
92#define MX1_SIM_INT (NR_IRQS_LEGACY + 15)
93#define MX1_SIM_DATA_INT (NR_IRQS_LEGACY + 16)
94#define MX1_RTC_INT (NR_IRQS_LEGACY + 17)
95#define MX1_RTC_SAMINT (NR_IRQS_LEGACY + 18)
96#define MX1_INT_UART2PFERR (NR_IRQS_LEGACY + 19)
97#define MX1_INT_UART2RTS (NR_IRQS_LEGACY + 20)
98#define MX1_INT_UART2DTR (NR_IRQS_LEGACY + 21)
99#define MX1_INT_UART2UARTC (NR_IRQS_LEGACY + 22)
100#define MX1_INT_UART2TX (NR_IRQS_LEGACY + 23)
101#define MX1_INT_UART2RX (NR_IRQS_LEGACY + 24)
102#define MX1_INT_UART1PFERR (NR_IRQS_LEGACY + 25)
103#define MX1_INT_UART1RTS (NR_IRQS_LEGACY + 26)
104#define MX1_INT_UART1DTR (NR_IRQS_LEGACY + 27)
105#define MX1_INT_UART1UARTC (NR_IRQS_LEGACY + 28)
106#define MX1_INT_UART1TX (NR_IRQS_LEGACY + 29)
107#define MX1_INT_UART1RX (NR_IRQS_LEGACY + 30)
108#define MX1_VOICE_DAC_INT (NR_IRQS_LEGACY + 31)
109#define MX1_VOICE_ADC_INT (NR_IRQS_LEGACY + 32)
110#define MX1_PEN_DATA_INT (NR_IRQS_LEGACY + 33)
111#define MX1_PWM_INT (NR_IRQS_LEGACY + 34)
112#define MX1_SDHC_INT (NR_IRQS_LEGACY + 35)
113#define MX1_INT_I2C (NR_IRQS_LEGACY + 39)
114#define MX1_INT_CSPI2 (NR_IRQS_LEGACY + 40)
115#define MX1_INT_CSPI1 (NR_IRQS_LEGACY + 41)
116#define MX1_SSI_TX_INT (NR_IRQS_LEGACY + 42)
117#define MX1_SSI_TX_ERR_INT (NR_IRQS_LEGACY + 43)
118#define MX1_SSI_RX_INT (NR_IRQS_LEGACY + 44)
119#define MX1_SSI_RX_ERR_INT (NR_IRQS_LEGACY + 45)
120#define MX1_TOUCH_INT (NR_IRQS_LEGACY + 46)
121#define MX1_INT_USBD0 (NR_IRQS_LEGACY + 47)
122#define MX1_INT_USBD1 (NR_IRQS_LEGACY + 48)
123#define MX1_INT_USBD2 (NR_IRQS_LEGACY + 49)
124#define MX1_INT_USBD3 (NR_IRQS_LEGACY + 50)
125#define MX1_INT_USBD4 (NR_IRQS_LEGACY + 51)
126#define MX1_INT_USBD5 (NR_IRQS_LEGACY + 52)
127#define MX1_INT_USBD6 (NR_IRQS_LEGACY + 53)
128#define MX1_BTSYS_INT (NR_IRQS_LEGACY + 55)
129#define MX1_BTTIM_INT (NR_IRQS_LEGACY + 56)
130#define MX1_BTWUI_INT (NR_IRQS_LEGACY + 57)
131#define MX1_TIM2_INT (NR_IRQS_LEGACY + 58)
132#define MX1_TIM1_INT (NR_IRQS_LEGACY + 59)
133#define MX1_DMA_ERR (NR_IRQS_LEGACY + 60)
134#define MX1_DMA_INT (NR_IRQS_LEGACY + 61)
135#define MX1_GPIO_INT_PORTD (NR_IRQS_LEGACY + 62)
136#define MX1_WDT_INT (NR_IRQS_LEGACY + 63)
137
138/* DMA */
139#define MX1_DMA_REQ_UART3_T 2
140#define MX1_DMA_REQ_UART3_R 3
141#define MX1_DMA_REQ_SSI2_T 4
142#define MX1_DMA_REQ_SSI2_R 5
143#define MX1_DMA_REQ_CSI_STAT 6
144#define MX1_DMA_REQ_CSI_R 7
145#define MX1_DMA_REQ_MSHC 8
146#define MX1_DMA_REQ_DSPA_DCT_DOUT 9
147#define MX1_DMA_REQ_DSPA_DCT_DIN 10
148#define MX1_DMA_REQ_DSPA_MAC 11
149#define MX1_DMA_REQ_EXT 12
150#define MX1_DMA_REQ_SDHC 13
151#define MX1_DMA_REQ_SPI1_R 14
152#define MX1_DMA_REQ_SPI1_T 15
153#define MX1_DMA_REQ_SSI_T 16
154#define MX1_DMA_REQ_SSI_R 17
155#define MX1_DMA_REQ_ASP_DAC 18
156#define MX1_DMA_REQ_ASP_ADC 19
157#define MX1_DMA_REQ_USP_EP(x) (20 + (x))
158#define MX1_DMA_REQ_SPI2_R 26
159#define MX1_DMA_REQ_SPI2_T 27
160#define MX1_DMA_REQ_UART2_T 28
161#define MX1_DMA_REQ_UART2_R 29
162#define MX1_DMA_REQ_UART1_T 30
163#define MX1_DMA_REQ_UART1_R 31
164
165/*
166 * This doesn't depend on IMX_NEEDS_DEPRECATED_SYMBOLS
167 * to not break drivers/usb/gadget/imx_udc. Should go
168 * away after this driver uses the new name.
169 */
170#define USBD_INT0 MX1_INT_USBD0
171
172#endif /* ifndef __MACH_MX1_H__ */
diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig
index 599f973e10d8..cefe44f6889b 100644
--- a/arch/arm/mach-integrator/Kconfig
+++ b/arch/arm/mach-integrator/Kconfig
@@ -21,7 +21,6 @@ if ARCH_INTEGRATOR
21config ARCH_INTEGRATOR_AP 21config ARCH_INTEGRATOR_AP
22 bool "Support Integrator/AP and Integrator/PP2 platforms" 22 bool "Support Integrator/AP and Integrator/PP2 platforms"
23 select INTEGRATOR_AP_TIMER 23 select INTEGRATOR_AP_TIMER
24 select MIGHT_HAVE_PCI
25 select SERIAL_AMBA_PL010 if TTY 24 select SERIAL_AMBA_PL010 if TTY
26 select SERIAL_AMBA_PL010_CONSOLE if TTY 25 select SERIAL_AMBA_PL010_CONSOLE if TTY
27 select SOC_BUS 26 select SOC_BUS
diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig
index 8ff61be1a29f..24bd64dabdfc 100644
--- a/arch/arm/mach-keystone/Kconfig
+++ b/arch/arm/mach-keystone/Kconfig
@@ -8,8 +8,6 @@ config ARCH_KEYSTONE
8 select COMMON_CLK_KEYSTONE 8 select COMMON_CLK_KEYSTONE
9 select ARCH_SUPPORTS_BIG_ENDIAN 9 select ARCH_SUPPORTS_BIG_ENDIAN
10 select ZONE_DMA if ARM_LPAE 10 select ZONE_DMA if ARM_LPAE
11 select MIGHT_HAVE_PCI
12 select PCI_DOMAINS if PCI
13 select PINCTRL 11 select PINCTRL
14 help 12 help
15 Support for boards based on the Texas Instruments Keystone family of 13 Support for boards based on the Texas Instruments Keystone family of
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 0b7fe74ff46d..e4f21086b42b 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -268,80 +268,6 @@ static void __init apx4devkit_init(void)
268 apx4devkit_phy_fixup); 268 apx4devkit_phy_fixup);
269} 269}
270 270
271#define ENET0_MDC__GPIO_4_0 MXS_GPIO_NR(4, 0)
272#define ENET0_MDIO__GPIO_4_1 MXS_GPIO_NR(4, 1)
273#define ENET0_RX_EN__GPIO_4_2 MXS_GPIO_NR(4, 2)
274#define ENET0_RXD0__GPIO_4_3 MXS_GPIO_NR(4, 3)
275#define ENET0_RXD1__GPIO_4_4 MXS_GPIO_NR(4, 4)
276#define ENET0_TX_EN__GPIO_4_6 MXS_GPIO_NR(4, 6)
277#define ENET0_TXD0__GPIO_4_7 MXS_GPIO_NR(4, 7)
278#define ENET0_TXD1__GPIO_4_8 MXS_GPIO_NR(4, 8)
279#define ENET_CLK__GPIO_4_16 MXS_GPIO_NR(4, 16)
280
281#define TX28_FEC_PHY_POWER MXS_GPIO_NR(3, 29)
282#define TX28_FEC_PHY_RESET MXS_GPIO_NR(4, 13)
283#define TX28_FEC_nINT MXS_GPIO_NR(4, 5)
284
285static const struct gpio const tx28_gpios[] __initconst = {
286 { ENET0_MDC__GPIO_4_0, GPIOF_OUT_INIT_LOW, "GPIO_4_0" },
287 { ENET0_MDIO__GPIO_4_1, GPIOF_OUT_INIT_LOW, "GPIO_4_1" },
288 { ENET0_RX_EN__GPIO_4_2, GPIOF_OUT_INIT_LOW, "GPIO_4_2" },
289 { ENET0_RXD0__GPIO_4_3, GPIOF_OUT_INIT_LOW, "GPIO_4_3" },
290 { ENET0_RXD1__GPIO_4_4, GPIOF_OUT_INIT_LOW, "GPIO_4_4" },
291 { ENET0_TX_EN__GPIO_4_6, GPIOF_OUT_INIT_LOW, "GPIO_4_6" },
292 { ENET0_TXD0__GPIO_4_7, GPIOF_OUT_INIT_LOW, "GPIO_4_7" },
293 { ENET0_TXD1__GPIO_4_8, GPIOF_OUT_INIT_LOW, "GPIO_4_8" },
294 { ENET_CLK__GPIO_4_16, GPIOF_OUT_INIT_LOW, "GPIO_4_16" },
295 { TX28_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" },
296 { TX28_FEC_PHY_RESET, GPIOF_OUT_INIT_LOW, "fec-phy-reset" },
297 { TX28_FEC_nINT, GPIOF_DIR_IN, "fec-int" },
298};
299
300static void __init tx28_post_init(void)
301{
302 struct device_node *np;
303 struct platform_device *pdev;
304 struct pinctrl *pctl;
305 int ret;
306
307 enable_clk_enet_out();
308
309 np = of_find_compatible_node(NULL, NULL, "fsl,imx28-fec");
310 pdev = of_find_device_by_node(np);
311 if (!pdev) {
312 pr_err("%s: failed to find fec device\n", __func__);
313 return;
314 }
315
316 pctl = pinctrl_get_select(&pdev->dev, "gpio_mode");
317 if (IS_ERR(pctl)) {
318 pr_err("%s: failed to get pinctrl state\n", __func__);
319 return;
320 }
321
322 ret = gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
323 if (ret) {
324 pr_err("%s: failed to request gpios: %d\n", __func__, ret);
325 return;
326 }
327
328 /* Power up fec phy */
329 gpio_set_value(TX28_FEC_PHY_POWER, 1);
330 msleep(26); /* 25ms according to data sheet */
331
332 /* Mode strap pins */
333 gpio_set_value(ENET0_RX_EN__GPIO_4_2, 1);
334 gpio_set_value(ENET0_RXD0__GPIO_4_3, 1);
335 gpio_set_value(ENET0_RXD1__GPIO_4_4, 1);
336
337 udelay(100); /* minimum assertion time for nRST */
338
339 /* Deasserting FEC PHY RESET */
340 gpio_set_value(TX28_FEC_PHY_RESET, 1);
341
342 pinctrl_put(pctl);
343}
344
345static void __init crystalfontz_init(void) 271static void __init crystalfontz_init(void)
346{ 272{
347 update_fec_mac_prop(OUI_CRYSTALFONTZ); 273 update_fec_mac_prop(OUI_CRYSTALFONTZ);
@@ -501,9 +427,6 @@ static void __init mxs_machine_init(void)
501 of_platform_default_populate(NULL, NULL, parent); 427 of_platform_default_populate(NULL, NULL, parent);
502 428
503 mxs_restart_init(); 429 mxs_restart_init();
504
505 if (of_machine_is_compatible("karo,tx28"))
506 tx28_post_init();
507} 430}
508 431
509#define MXS_CLKCTRL_RESET_CHIP (1 << 1) 432#define MXS_CLKCTRL_RESET_CHIP (1 << 1)
diff --git a/arch/arm/mach-omap1/board-h2-mmc.c b/arch/arm/mach-omap1/board-h2-mmc.c
index 7119ef28e0ad..357be2debc9d 100644
--- a/arch/arm/mach-omap1/board-h2-mmc.c
+++ b/arch/arm/mach-omap1/board-h2-mmc.c
@@ -19,7 +19,7 @@
19#include "board-h2.h" 19#include "board-h2.h"
20#include "mmc.h" 20#include "mmc.h"
21 21
22#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) 22#if IS_ENABLED(CONFIG_MMC_OMAP)
23 23
24static int mmc_set_power(struct device *dev, int slot, int power_on, 24static int mmc_set_power(struct device *dev, int slot, int power_on,
25 int vdd) 25 int vdd)
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index cd146ed0538d..675254ee4b1e 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -349,7 +349,7 @@ static struct omap_usb_config h2_usb_config __initdata = {
349#if IS_ENABLED(CONFIG_USB_OMAP) 349#if IS_ENABLED(CONFIG_USB_OMAP)
350 .hmc_mode = 19, /* 0:host(off) 1:dev|otg 2:disabled */ 350 .hmc_mode = 19, /* 0:host(off) 1:dev|otg 2:disabled */
351 /* .hmc_mode = 21,*/ /* 0:host(off) 1:dev(loopback) 2:host(loopback) */ 351 /* .hmc_mode = 21,*/ /* 0:host(off) 1:dev(loopback) 2:host(loopback) */
352#elif defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 352#elif IS_ENABLED(CONFIG_USB_OHCI_HCD)
353 /* needs OTG cable, or NONSTANDARD (B-to-MiniB) */ 353 /* needs OTG cable, or NONSTANDARD (B-to-MiniB) */
354 .hmc_mode = 20, /* 1:dev|otg(off) 1:host 2:disabled */ 354 .hmc_mode = 20, /* 1:dev|otg(off) 1:host 2:disabled */
355#endif 355#endif
diff --git a/arch/arm/mach-omap1/board-h3-mmc.c b/arch/arm/mach-omap1/board-h3-mmc.c
index 43aab63cbc39..4f58bfa5e754 100644
--- a/arch/arm/mach-omap1/board-h3-mmc.c
+++ b/arch/arm/mach-omap1/board-h3-mmc.c
@@ -20,7 +20,7 @@
20#include "board-h3.h" 20#include "board-h3.h"
21#include "mmc.h" 21#include "mmc.h"
22 22
23#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) 23#if IS_ENABLED(CONFIG_MMC_OMAP)
24 24
25static int mmc_set_power(struct device *dev, int slot, int power_on, 25static int mmc_set_power(struct device *dev, int slot, int power_on,
26 int vdd) 26 int vdd)
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index f7c8c63dd532..e62f9d454f10 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -368,7 +368,7 @@ static struct omap_usb_config h3_usb_config __initdata = {
368 368
369#if IS_ENABLED(CONFIG_USB_OMAP) 369#if IS_ENABLED(CONFIG_USB_OMAP)
370 .hmc_mode = 19, /* 0:host(off) 1:dev|otg 2:disabled */ 370 .hmc_mode = 19, /* 0:host(off) 1:dev|otg 2:disabled */
371#elif defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 371#elif IS_ENABLED(CONFIG_USB_OHCI_HCD)
372 /* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */ 372 /* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */
373 .hmc_mode = 20, /* 1:dev|otg(off) 1:host 2:disabled */ 373 .hmc_mode = 20, /* 1:dev|otg(off) 1:host 2:disabled */
374#endif 374#endif
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 9525ef9bc6c0..e424df901dbd 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -401,7 +401,7 @@ static struct platform_device lcd_device = {
401}; 401};
402 402
403/* MMC Card */ 403/* MMC Card */
404#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) 404#if IS_ENABLED(CONFIG_MMC_OMAP)
405static struct omap_mmc_platform_data htc_mmc1_data = { 405static struct omap_mmc_platform_data htc_mmc1_data = {
406 .nr_slots = 1, 406 .nr_slots = 1,
407 .switch_slot = NULL, 407 .switch_slot = NULL,
@@ -586,7 +586,7 @@ static void __init htcherald_init(void)
586 586
587 omap_register_i2c_bus(1, 100, NULL, 0); 587 omap_register_i2c_bus(1, 100, NULL, 0);
588 588
589#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) 589#if IS_ENABLED(CONFIG_MMC_OMAP)
590 htc_mmc_data[0] = &htc_mmc1_data; 590 htc_mmc_data[0] = &htc_mmc1_data;
591 omap1_init_mmc(htc_mmc_data, 1); 591 omap1_init_mmc(htc_mmc_data, 1);
592#endif 592#endif
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index ae90bd02b3bf..67e188271643 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -315,7 +315,7 @@ static struct omap_usb_config h2_usb_config __initdata = {
315#if IS_ENABLED(CONFIG_USB_OMAP) 315#if IS_ENABLED(CONFIG_USB_OMAP)
316 .hmc_mode = 19, /* 0:host(off) 1:dev|otg 2:disabled */ 316 .hmc_mode = 19, /* 0:host(off) 1:dev|otg 2:disabled */
317 /* .hmc_mode = 21,*/ /* 0:host(off) 1:dev(loopback) 2:host(loopback) */ 317 /* .hmc_mode = 21,*/ /* 0:host(off) 1:dev(loopback) 2:host(loopback) */
318#elif defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 318#elif IS_ENABLED(CONFIG_USB_OHCI_HCD)
319 /* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */ 319 /* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */
320 .hmc_mode = 20, /* 1:dev|otg(off) 1:host 2:disabled */ 320 .hmc_mode = 20, /* 1:dev|otg(off) 1:host 2:disabled */
321#endif 321#endif
@@ -328,7 +328,7 @@ static struct omap_lcd_config innovator1610_lcd_config __initdata = {
328}; 328};
329#endif 329#endif
330 330
331#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) 331#if IS_ENABLED(CONFIG_MMC_OMAP)
332 332
333static int mmc_set_power(struct device *dev, int slot, int power_on, 333static int mmc_set_power(struct device *dev, int slot, int power_on,
334 int vdd) 334 int vdd)
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index dd3a3ad797ea..ee8d9f553db4 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -159,7 +159,7 @@ static struct omap_usb_config nokia770_usb_config __initdata = {
159 .extcon = "tahvo-usb", 159 .extcon = "tahvo-usb",
160}; 160};
161 161
162#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) 162#if IS_ENABLED(CONFIG_MMC_OMAP)
163 163
164#define NOKIA770_GPIO_MMC_POWER 41 164#define NOKIA770_GPIO_MMC_POWER 41
165#define NOKIA770_GPIO_MMC_SWITCH 23 165#define NOKIA770_GPIO_MMC_SWITCH 23
@@ -216,7 +216,7 @@ static inline void nokia770_mmc_init(void)
216} 216}
217#endif 217#endif
218 218
219#if defined(CONFIG_I2C_CBUS_GPIO) || defined(CONFIG_I2C_CBUS_GPIO_MODULE) 219#if IS_ENABLED(CONFIG_I2C_CBUS_GPIO)
220static struct i2c_cbus_platform_data nokia770_cbus_data = { 220static struct i2c_cbus_platform_data nokia770_cbus_data = {
221 .clk_gpio = OMAP_MPUIO(9), 221 .clk_gpio = OMAP_MPUIO(9),
222 .dat_gpio = OMAP_MPUIO(10), 222 .dat_gpio = OMAP_MPUIO(10),
diff --git a/arch/arm/mach-omap1/board-sx1-mmc.c b/arch/arm/mach-omap1/board-sx1-mmc.c
index a9373570bbb1..79f0af8bfae0 100644
--- a/arch/arm/mach-omap1/board-sx1-mmc.c
+++ b/arch/arm/mach-omap1/board-sx1-mmc.c
@@ -20,7 +20,7 @@
20 20
21#include "mmc.h" 21#include "mmc.h"
22 22
23#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) 23#if IS_ENABLED(CONFIG_MMC_OMAP)
24 24
25static int mmc_set_power(struct device *dev, int slot, int power_on, 25static int mmc_set_power(struct device *dev, int slot, int power_on,
26 int vdd) 26 int vdd)
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 8c8be861fff2..baaf902b7016 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -33,7 +33,7 @@
33#include "mmc.h" 33#include "mmc.h"
34#include "sram.h" 34#include "sram.h"
35 35
36#if defined(CONFIG_RTC_DRV_OMAP) || defined(CONFIG_RTC_DRV_OMAP_MODULE) 36#if IS_ENABLED(CONFIG_RTC_DRV_OMAP)
37 37
38#define OMAP_RTC_BASE 0xfffb4800 38#define OMAP_RTC_BASE 0xfffb4800
39 39
@@ -72,7 +72,7 @@ static inline void omap_init_mbox(void) { }
72 72
73/*-------------------------------------------------------------------------*/ 73/*-------------------------------------------------------------------------*/
74 74
75#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) 75#if IS_ENABLED(CONFIG_MMC_OMAP)
76 76
77static inline void omap1_mmc_mux(struct omap_mmc_platform_data *mmc_controller, 77static inline void omap1_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
78 int controller_nr) 78 int controller_nr)
@@ -230,7 +230,7 @@ void __init omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
230/*-------------------------------------------------------------------------*/ 230/*-------------------------------------------------------------------------*/
231 231
232/* OMAP7xx SPI support */ 232/* OMAP7xx SPI support */
233#if defined(CONFIG_SPI_OMAP_100K) || defined(CONFIG_SPI_OMAP_100K_MODULE) 233#if IS_ENABLED(CONFIG_SPI_OMAP_100K)
234 234
235struct platform_device omap_spi1 = { 235struct platform_device omap_spi1 = {
236 .name = "omap1_spi100k", 236 .name = "omap1_spi100k",
@@ -312,7 +312,7 @@ static inline void omap_init_sti(void) {}
312 * mcbsp1..3 = 5..7 312 * mcbsp1..3 = 5..7
313 */ 313 */
314 314
315#if defined(CONFIG_SPI_OMAP_UWIRE) || defined(CONFIG_SPI_OMAP_UWIRE_MODULE) 315#if IS_ENABLED(CONFIG_SPI_OMAP_UWIRE)
316 316
317#define OMAP_UWIRE_BASE 0xfffb3000 317#define OMAP_UWIRE_BASE 0xfffb3000
318 318
@@ -418,7 +418,7 @@ static int __init omap1_init_devices(void)
418} 418}
419arch_initcall(omap1_init_devices); 419arch_initcall(omap1_init_devices);
420 420
421#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE) 421#if IS_ENABLED(CONFIG_OMAP_WATCHDOG)
422 422
423static struct resource wdt_resources[] = { 423static struct resource wdt_resources[] = {
424 { 424 {
diff --git a/arch/arm/mach-omap1/fb.c b/arch/arm/mach-omap1/fb.c
index c770d45c7226..ddab04087b7a 100644
--- a/arch/arm/mach-omap1/fb.c
+++ b/arch/arm/mach-omap1/fb.c
@@ -33,7 +33,7 @@
33 33
34#include <asm/mach/map.h> 34#include <asm/mach/map.h>
35 35
36#if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE) 36#if IS_ENABLED(CONFIG_FB_OMAP)
37 37
38static bool omapfb_lcd_configured; 38static bool omapfb_lcd_configured;
39static struct omapfb_platform_data omapfb_config; 39static struct omapfb_platform_data omapfb_config;
diff --git a/arch/arm/mach-omap1/include/mach/usb.h b/arch/arm/mach-omap1/include/mach/usb.h
index 2c263051dc51..a7c5559caef2 100644
--- a/arch/arm/mach-omap1/include/mach/usb.h
+++ b/arch/arm/mach-omap1/include/mach/usb.h
@@ -12,7 +12,7 @@
12 12
13void omap_otg_init(struct omap_usb_config *config); 13void omap_otg_init(struct omap_usb_config *config);
14 14
15#if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE) 15#if IS_ENABLED(CONFIG_USB)
16void omap1_usb_init(struct omap_usb_config *pdata); 16void omap1_usb_init(struct omap_usb_config *pdata);
17#else 17#else
18static inline void omap1_usb_init(struct omap_usb_config *pdata) 18static inline void omap1_usb_init(struct omap_usb_config *pdata)
diff --git a/arch/arm/mach-omap1/mmc.h b/arch/arm/mach-omap1/mmc.h
index 39c2b13de884..d7b46880e4ca 100644
--- a/arch/arm/mach-omap1/mmc.h
+++ b/arch/arm/mach-omap1/mmc.h
@@ -7,7 +7,7 @@
7#define OMAP1_MMC1_BASE 0xfffb7800 7#define OMAP1_MMC1_BASE 0xfffb7800
8#define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */ 8#define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */
9 9
10#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) 10#if IS_ENABLED(CONFIG_MMC_OMAP)
11void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, 11void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
12 int nr_controllers); 12 int nr_controllers);
13#else 13#else
diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c
index 4118db50d5e8..2506e598a067 100644
--- a/arch/arm/mach-omap1/usb.c
+++ b/arch/arm/mach-omap1/usb.c
@@ -136,7 +136,7 @@ omap_otg_init(struct omap_usb_config *config)
136 } 136 }
137#endif 137#endif
138 138
139#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 139#if IS_ENABLED(CONFIG_USB_OHCI_HCD)
140 if (config->otg || config->register_host) { 140 if (config->otg || config->register_host) {
141 struct platform_device *ohci_device = config->ohci_device; 141 struct platform_device *ohci_device = config->ohci_device;
142 int status; 142 int status;
@@ -221,7 +221,7 @@ static inline void udc_device_init(struct omap_usb_config *pdata)
221 221
222#endif 222#endif
223 223
224#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 224#if IS_ENABLED(CONFIG_USB_OHCI_HCD)
225 225
226/* The dmamask must be set for OHCI to work */ 226/* The dmamask must be set for OHCI to work */
227static u64 ohci_dmamask = ~(u32)0; 227static u64 ohci_dmamask = ~(u32)0;
@@ -612,7 +612,7 @@ static void __init omap_1510_usb_init(struct omap_usb_config *config)
612 } 612 }
613#endif 613#endif
614 614
615#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 615#if IS_ENABLED(CONFIG_USB_OHCI_HCD)
616 if (config->register_host) { 616 if (config->register_host) {
617 int status; 617 int status;
618 618
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 5a0b380a8166..a9afeebd59f2 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -192,12 +192,6 @@ config MACH_OMAP2_TUSB6010
192 depends on ARCH_OMAP2 && SOC_OMAP2420 192 depends on ARCH_OMAP2 && SOC_OMAP2420
193 default y if MACH_NOKIA_N8X0 193 default y if MACH_NOKIA_N8X0
194 194
195config MACH_OMAP_LDP
196 bool "OMAP3 LDP board"
197 depends on ARCH_OMAP3
198 default y
199 select OMAP_PACKAGE_CBB
200
201config MACH_OMAP3517EVM 195config MACH_OMAP3517EVM
202 bool "OMAP3517/ AM3517 EVM board" 196 bool "OMAP3517/ AM3517 EVM board"
203 depends on ARCH_OMAP3 197 depends on ARCH_OMAP3
@@ -222,12 +216,6 @@ config MACH_NOKIA_N8X0
222 select MACH_NOKIA_N810 216 select MACH_NOKIA_N810
223 select MACH_NOKIA_N810_WIMAX 217 select MACH_NOKIA_N810_WIMAX
224 218
225config MACH_NOKIA_RX51
226 bool "Nokia N900 (RX-51) phone"
227 depends on ARCH_OMAP3
228 default y
229 select OMAP_PACKAGE_CBB
230
231config OMAP3_SDRC_AC_TIMING 219config OMAP3_SDRC_AC_TIMING
232 bool "Enable SDRC AC timing register changes" 220 bool "Enable SDRC AC timing register changes"
233 depends on ARCH_OMAP3 221 depends on ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index a7f2d051f524..5b37ec29996e 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -231,11 +231,7 @@ obj-$(CONFIG_SOC_OMAP2420) += msdi.o
231 231
232# Specific board support 232# Specific board support
233obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o pdata-quirks.o 233obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o pdata-quirks.o
234obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o
235obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o 234obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o
236obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o sdram-nokia.o
237obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-peripherals.o
238obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-video.o
239 235
240# Platform specific device init code 236# Platform specific device init code
241 237
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index 70b21cc279ba..2188dc30e232 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -81,8 +81,7 @@ __init board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
81 pr_err("Unable to register NOR device\n"); 81 pr_err("Unable to register NOR device\n");
82} 82}
83 83
84#if defined(CONFIG_MTD_ONENAND_OMAP2) || \ 84#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
85 defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
86static struct omap_onenand_platform_data board_onenand_data = { 85static struct omap_onenand_platform_data board_onenand_data = {
87 .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */ 86 .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */
88}; 87};
@@ -97,10 +96,9 @@ __init board_onenand_init(struct mtd_partition *onenand_parts,
97 96
98 gpmc_onenand_init(&board_onenand_data); 97 gpmc_onenand_init(&board_onenand_data);
99} 98}
100#endif /* CONFIG_MTD_ONENAND_OMAP2 || CONFIG_MTD_ONENAND_OMAP2_MODULE */ 99#endif /* IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2) */
101 100
102#if defined(CONFIG_MTD_NAND_OMAP2) || \ 101#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2)
103 defined(CONFIG_MTD_NAND_OMAP2_MODULE)
104 102
105/* Note that all values in this struct are in nanoseconds */ 103/* Note that all values in this struct are in nanoseconds */
106struct gpmc_timings nand_default_timings[1] = { 104struct gpmc_timings nand_default_timings[1] = {
@@ -144,7 +142,7 @@ __init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
144 board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_SW; 142 board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_SW;
145 gpmc_nand_init(&board_nand_data, gpmc_t); 143 gpmc_nand_init(&board_nand_data, gpmc_t);
146} 144}
147#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */ 145#endif /* IS_ENABLED(CONFIG_MTD_NAND_OMAP2) */
148 146
149/** 147/**
150 * get_gpmc0_type - Reads the FPGA DIP_SWITCH_INPUT_REGISTER2 to get 148 * get_gpmc0_type - Reads the FPGA DIP_SWITCH_INPUT_REGISTER2 to get
diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h
index ea9aaebe11e7..8b39eec07318 100644
--- a/arch/arm/mach-omap2/board-flash.h
+++ b/arch/arm/mach-omap2/board-flash.h
@@ -23,10 +23,7 @@ struct flash_partitions {
23 int nr_parts; 23 int nr_parts;
24}; 24};
25 25
26#if defined(CONFIG_MTD_NAND_OMAP2) || \ 26#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2) || IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
27 defined(CONFIG_MTD_NAND_OMAP2_MODULE) || \
28 defined(CONFIG_MTD_ONENAND_OMAP2) || \
29 defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
30extern void board_flash_init(struct flash_partitions [], 27extern void board_flash_init(struct flash_partitions [],
31 char chip_sel[][GPMC_CS_NUM], int nand_type); 28 char chip_sel[][GPMC_CS_NUM], int nand_type);
32#else 29#else
@@ -36,8 +33,7 @@ static inline void board_flash_init(struct flash_partitions part[],
36} 33}
37#endif 34#endif
38 35
39#if defined(CONFIG_MTD_NAND_OMAP2) || \ 36#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2)
40 defined(CONFIG_MTD_NAND_OMAP2_MODULE)
41extern void board_nand_init(struct mtd_partition *nand_parts, 37extern void board_nand_init(struct mtd_partition *nand_parts,
42 u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t); 38 u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t);
43extern struct gpmc_timings nand_default_timings[]; 39extern struct gpmc_timings nand_default_timings[];
@@ -49,8 +45,7 @@ static inline void board_nand_init(struct mtd_partition *nand_parts,
49#define nand_default_timings NULL 45#define nand_default_timings NULL
50#endif 46#endif
51 47
52#if defined(CONFIG_MTD_ONENAND_OMAP2) || \ 48#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
53 defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
54extern void board_onenand_init(struct mtd_partition *nand_parts, 49extern void board_onenand_init(struct mtd_partition *nand_parts,
55 u8 nr_parts, u8 cs); 50 u8 nr_parts, u8 cs);
56#else 51#else
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
deleted file mode 100644
index 390795b334c3..000000000000
--- a/arch/arm/mach-omap2/board-ldp.c
+++ /dev/null
@@ -1,430 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/board-ldp.c
3 *
4 * Copyright (C) 2008 Texas Instruments Inc.
5 * Nishant Kamat <nskamat@ti.com>
6 *
7 * Modified from mach-omap2/board-3430sdp.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/gpio.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/delay.h>
18#include <linux/input.h>
19#include <linux/input/matrix_keypad.h>
20#include <linux/gpio_keys.h>
21#include <linux/workqueue.h>
22#include <linux/err.h>
23#include <linux/clk.h>
24#include <linux/spi/spi.h>
25#include <linux/regulator/fixed.h>
26#include <linux/regulator/machine.h>
27#include <linux/i2c/twl.h>
28#include <linux/io.h>
29#include <linux/smsc911x.h>
30#include <linux/mmc/host.h>
31#include <linux/usb/phy.h>
32#include <linux/platform_data/spi-omap2-mcspi.h>
33
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/map.h>
37
38#include "common.h"
39#include "gpmc.h"
40#include "gpmc-smsc911x.h"
41
42#include <linux/platform_data/omapdss.h>
43#include <video/omap-panel-data.h>
44
45#include "board-flash.h"
46#include "mux.h"
47#include "hsmmc.h"
48#include "control.h"
49#include "common-board-devices.h"
50#include "display.h"
51
52#define LDP_SMSC911X_CS 1
53#define LDP_SMSC911X_GPIO 152
54#define DEBUG_BASE 0x08000000
55#define LDP_ETHR_START DEBUG_BASE
56
57static uint32_t board_keymap[] = {
58 KEY(0, 0, KEY_1),
59 KEY(1, 0, KEY_2),
60 KEY(2, 0, KEY_3),
61 KEY(0, 1, KEY_4),
62 KEY(1, 1, KEY_5),
63 KEY(2, 1, KEY_6),
64 KEY(3, 1, KEY_F5),
65 KEY(0, 2, KEY_7),
66 KEY(1, 2, KEY_8),
67 KEY(2, 2, KEY_9),
68 KEY(3, 2, KEY_F6),
69 KEY(0, 3, KEY_F7),
70 KEY(1, 3, KEY_0),
71 KEY(2, 3, KEY_F8),
72 PERSISTENT_KEY(4, 5),
73 KEY(4, 4, KEY_VOLUMEUP),
74 KEY(5, 5, KEY_VOLUMEDOWN),
75 0
76};
77
78static struct matrix_keymap_data board_map_data = {
79 .keymap = board_keymap,
80 .keymap_size = ARRAY_SIZE(board_keymap),
81};
82
83static struct twl4030_keypad_data ldp_kp_twl4030_data = {
84 .keymap_data = &board_map_data,
85 .rows = 6,
86 .cols = 6,
87 .rep = 1,
88};
89
90static struct gpio_keys_button ldp_gpio_keys_buttons[] = {
91 [0] = {
92 .code = KEY_ENTER,
93 .gpio = 101,
94 .desc = "enter sw",
95 .active_low = 1,
96 .debounce_interval = 30,
97 },
98 [1] = {
99 .code = KEY_F1,
100 .gpio = 102,
101 .desc = "func 1",
102 .active_low = 1,
103 .debounce_interval = 30,
104 },
105 [2] = {
106 .code = KEY_F2,
107 .gpio = 103,
108 .desc = "func 2",
109 .active_low = 1,
110 .debounce_interval = 30,
111 },
112 [3] = {
113 .code = KEY_F3,
114 .gpio = 104,
115 .desc = "func 3",
116 .active_low = 1,
117 .debounce_interval = 30,
118 },
119 [4] = {
120 .code = KEY_F4,
121 .gpio = 105,
122 .desc = "func 4",
123 .active_low = 1,
124 .debounce_interval = 30,
125 },
126 [5] = {
127 .code = KEY_LEFT,
128 .gpio = 106,
129 .desc = "left sw",
130 .active_low = 1,
131 .debounce_interval = 30,
132 },
133 [6] = {
134 .code = KEY_RIGHT,
135 .gpio = 107,
136 .desc = "right sw",
137 .active_low = 1,
138 .debounce_interval = 30,
139 },
140 [7] = {
141 .code = KEY_UP,
142 .gpio = 108,
143 .desc = "up sw",
144 .active_low = 1,
145 .debounce_interval = 30,
146 },
147 [8] = {
148 .code = KEY_DOWN,
149 .gpio = 109,
150 .desc = "down sw",
151 .active_low = 1,
152 .debounce_interval = 30,
153 },
154};
155
156static struct gpio_keys_platform_data ldp_gpio_keys = {
157 .buttons = ldp_gpio_keys_buttons,
158 .nbuttons = ARRAY_SIZE(ldp_gpio_keys_buttons),
159 .rep = 1,
160};
161
162static struct platform_device ldp_gpio_keys_device = {
163 .name = "gpio-keys",
164 .id = -1,
165 .dev = {
166 .platform_data = &ldp_gpio_keys,
167 },
168};
169
170static struct omap_smsc911x_platform_data smsc911x_cfg = {
171 .cs = LDP_SMSC911X_CS,
172 .gpio_irq = LDP_SMSC911X_GPIO,
173 .gpio_reset = -EINVAL,
174 .flags = SMSC911X_USE_32BIT,
175};
176
177static inline void __init ldp_init_smsc911x(void)
178{
179 gpmc_smsc911x_init(&smsc911x_cfg);
180}
181
182/* LCD */
183
184#define LCD_PANEL_RESET_GPIO 55
185#define LCD_PANEL_QVGA_GPIO 56
186
187static const struct display_timing ldp_lcd_videomode = {
188 .pixelclock = { 0, 5400000, 0 },
189
190 .hactive = { 0, 240, 0 },
191 .hfront_porch = { 0, 3, 0 },
192 .hback_porch = { 0, 39, 0 },
193 .hsync_len = { 0, 3, 0 },
194
195 .vactive = { 0, 320, 0 },
196 .vfront_porch = { 0, 2, 0 },
197 .vback_porch = { 0, 7, 0 },
198 .vsync_len = { 0, 1, 0 },
199
200 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
201 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
202};
203
204static struct panel_dpi_platform_data ldp_lcd_pdata = {
205 .name = "lcd",
206 .source = "dpi.0",
207
208 .data_lines = 18,
209
210 .display_timing = &ldp_lcd_videomode,
211
212 .enable_gpio = -1, /* filled in code */
213 .backlight_gpio = -1, /* filled in code */
214};
215
216static struct platform_device ldp_lcd_device = {
217 .name = "panel-dpi",
218 .id = 0,
219 .dev.platform_data = &ldp_lcd_pdata,
220};
221
222static struct omap_dss_board_info ldp_dss_data = {
223 .default_display_name = "lcd",
224};
225
226static void __init ldp_display_init(void)
227{
228 int r;
229
230 static struct gpio gpios[] __initdata = {
231 {LCD_PANEL_RESET_GPIO, GPIOF_OUT_INIT_HIGH, "LCD RESET"},
232 {LCD_PANEL_QVGA_GPIO, GPIOF_OUT_INIT_HIGH, "LCD QVGA"},
233 };
234
235 r = gpio_request_array(gpios, ARRAY_SIZE(gpios));
236 if (r) {
237 pr_err("Cannot request LCD GPIOs, error %d\n", r);
238 return;
239 }
240
241 omap_display_init(&ldp_dss_data);
242}
243
244static int ldp_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio)
245{
246 int res;
247
248 /* LCD enable GPIO */
249 ldp_lcd_pdata.enable_gpio = gpio + 7;
250
251 /* Backlight enable GPIO */
252 ldp_lcd_pdata.backlight_gpio = gpio + 15;
253
254 res = platform_device_register(&ldp_lcd_device);
255 if (res)
256 pr_err("Unable to register LCD: %d\n", res);
257
258 return 0;
259}
260
261static struct twl4030_gpio_platform_data ldp_gpio_data = {
262 .setup = ldp_twl_gpio_setup,
263};
264
265static struct regulator_consumer_supply ldp_vmmc1_supply[] = {
266 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
267};
268
269/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
270static struct regulator_init_data ldp_vmmc1 = {
271 .constraints = {
272 .min_uV = 1850000,
273 .max_uV = 3150000,
274 .valid_modes_mask = REGULATOR_MODE_NORMAL
275 | REGULATOR_MODE_STANDBY,
276 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
277 | REGULATOR_CHANGE_MODE
278 | REGULATOR_CHANGE_STATUS,
279 },
280 .num_consumer_supplies = ARRAY_SIZE(ldp_vmmc1_supply),
281 .consumer_supplies = ldp_vmmc1_supply,
282};
283
284/* ads7846 on SPI */
285static struct regulator_consumer_supply ldp_vaux1_supplies[] = {
286 REGULATOR_SUPPLY("vcc", "spi1.0"),
287};
288
289/* VAUX1 */
290static struct regulator_init_data ldp_vaux1 = {
291 .constraints = {
292 .min_uV = 3000000,
293 .max_uV = 3000000,
294 .apply_uV = true,
295 .valid_modes_mask = REGULATOR_MODE_NORMAL
296 | REGULATOR_MODE_STANDBY,
297 .valid_ops_mask = REGULATOR_CHANGE_MODE
298 | REGULATOR_CHANGE_STATUS,
299 },
300 .num_consumer_supplies = ARRAY_SIZE(ldp_vaux1_supplies),
301 .consumer_supplies = ldp_vaux1_supplies,
302};
303
304static struct regulator_consumer_supply ldp_vpll2_supplies[] = {
305 REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
306 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
307 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
308};
309
310static struct regulator_init_data ldp_vpll2 = {
311 .constraints = {
312 .name = "VDVI",
313 .min_uV = 1800000,
314 .max_uV = 1800000,
315 .apply_uV = true,
316 .valid_modes_mask = REGULATOR_MODE_NORMAL
317 | REGULATOR_MODE_STANDBY,
318 .valid_ops_mask = REGULATOR_CHANGE_MODE
319 | REGULATOR_CHANGE_STATUS,
320 },
321 .num_consumer_supplies = ARRAY_SIZE(ldp_vpll2_supplies),
322 .consumer_supplies = ldp_vpll2_supplies,
323};
324
325static struct twl4030_platform_data ldp_twldata = {
326 /* platform_data for children goes here */
327 .vmmc1 = &ldp_vmmc1,
328 .vaux1 = &ldp_vaux1,
329 .vpll2 = &ldp_vpll2,
330 .gpio = &ldp_gpio_data,
331 .keypad = &ldp_kp_twl4030_data,
332};
333
334static int __init omap_i2c_init(void)
335{
336 omap3_pmic_get_config(&ldp_twldata,
337 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC, 0);
338 omap3_pmic_init("twl4030", &ldp_twldata);
339 omap_register_i2c_bus(2, 400, NULL, 0);
340 omap_register_i2c_bus(3, 400, NULL, 0);
341 return 0;
342}
343
344static struct omap2_hsmmc_info mmc[] __initdata = {
345 {
346 .mmc = 1,
347 .caps = MMC_CAP_4_BIT_DATA,
348 .gpio_cd = -EINVAL,
349 .gpio_wp = -EINVAL,
350 },
351 {} /* Terminator */
352};
353
354static struct platform_device *ldp_devices[] __initdata = {
355 &ldp_gpio_keys_device,
356};
357
358#ifdef CONFIG_OMAP_MUX
359static struct omap_board_mux board_mux[] __initdata = {
360 { .reg_offset = OMAP_MUX_TERMINATOR },
361};
362#endif
363
364static struct mtd_partition ldp_nand_partitions[] = {
365 /* All the partition sizes are listed in terms of NAND block size */
366 {
367 .name = "X-Loader-NAND",
368 .offset = 0,
369 .size = 4 * (64 * 2048), /* 512KB, 0x80000 */
370 .mask_flags = MTD_WRITEABLE, /* force read-only */
371 },
372 {
373 .name = "U-Boot-NAND",
374 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
375 .size = 10 * (64 * 2048), /* 1.25MB, 0x140000 */
376 .mask_flags = MTD_WRITEABLE, /* force read-only */
377 },
378 {
379 .name = "Boot Env-NAND",
380 .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */
381 .size = 2 * (64 * 2048), /* 256KB, 0x40000 */
382 },
383 {
384 .name = "Kernel-NAND",
385 .offset = MTDPART_OFS_APPEND, /* Offset = 0x0200000*/
386 .size = 240 * (64 * 2048), /* 30M, 0x1E00000 */
387 },
388 {
389 .name = "File System - NAND",
390 .offset = MTDPART_OFS_APPEND, /* Offset = 0x2000000 */
391 .size = MTDPART_SIZ_FULL, /* 96MB, 0x6000000 */
392 },
393
394};
395
396static struct regulator_consumer_supply dummy_supplies[] = {
397 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
398 REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
399};
400
401static void __init omap_ldp_init(void)
402{
403 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
404 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
405 ldp_init_smsc911x();
406 omap_i2c_init();
407 platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
408 omap_ads7846_init(1, 54, 310, NULL);
409 omap_serial_init();
410 omap_sdrc_init(NULL, NULL);
411 usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
412 usb_musb_init(NULL);
413 board_nand_init(ldp_nand_partitions, ARRAY_SIZE(ldp_nand_partitions),
414 0, 0, nand_default_timings);
415
416 omap_hsmmc_init(mmc);
417 ldp_display_init();
418}
419
420MACHINE_START(OMAP_LDP, "OMAP LDP board")
421 .atag_offset = 0x100,
422 .reserve = omap_reserve,
423 .map_io = omap3_map_io,
424 .init_early = omap3430_init_early,
425 .init_irq = omap3_init_irq,
426 .init_machine = omap_ldp_init,
427 .init_late = omap3430_init_late,
428 .init_time = omap_init_time,
429 .restart = omap3xxx_restart,
430MACHINE_END
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index b6443a4e0c78..6b6fda65fb3b 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -66,7 +66,7 @@ static void board_check_revision(void)
66 pr_err("Unknown board\n"); 66 pr_err("Unknown board\n");
67} 67}
68 68
69#if defined(CONFIG_USB_MUSB_TUSB6010) || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) 69#if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
70/* 70/*
71 * Enable or disable power to TUSB6010. When enabling, turn on 3.3 V and 71 * Enable or disable power to TUSB6010. When enabling, turn on 3.3 V and
72 * 1.5 V voltage regulators of PM companion chip. Companion chip will then 72 * 1.5 V voltage regulators of PM companion chip. Companion chip will then
@@ -163,8 +163,7 @@ static struct spi_board_info n800_spi_board_info[] __initdata = {
163 }, 163 },
164}; 164};
165 165
166#if defined(CONFIG_MENELAUS) && \ 166#if defined(CONFIG_MENELAUS) && IS_ENABLED(CONFIG_MMC_OMAP)
167 (defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE))
168 167
169/* 168/*
170 * On both N800 and N810, only the first of the two MMC controllers is in use. 169 * On both N800 and N810, only the first of the two MMC controllers is in use.
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
deleted file mode 100644
index 6d3af43ae3e4..000000000000
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ /dev/null
@@ -1,1313 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/board-rx51-peripherals.c
3 *
4 * Copyright (C) 2008-2009 Nokia
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/input.h>
15#include <linux/input/matrix_keypad.h>
16#include <linux/spi/spi.h>
17#include <linux/wl12xx.h>
18#include <linux/spi/tsc2005.h>
19#include <linux/i2c.h>
20#include <linux/i2c/twl.h>
21#include <linux/clk.h>
22#include <linux/delay.h>
23#include <linux/regulator/machine.h>
24#include <linux/gpio.h>
25#include <linux/gpio_keys.h>
26#include <linux/gpio/machine.h>
27#include <linux/omap-gpmc.h>
28#include <linux/mmc/host.h>
29#include <linux/power/isp1704_charger.h>
30#include <linux/platform_data/spi-omap2-mcspi.h>
31#include <linux/platform_data/mtd-onenand-omap2.h>
32#include <linux/module.h>
33
34#include <plat/dmtimer.h>
35
36#include <asm/system_info.h>
37
38#include "common.h"
39#include <linux/omap-dma.h>
40
41#include "board-rx51.h"
42
43#include <sound/tlv320aic3x.h>
44#include <sound/tpa6130a2-plat.h>
45#include <linux/platform_data/media/si4713.h>
46#include <linux/platform_data/leds-lp55xx.h>
47
48#include <linux/platform_data/tsl2563.h>
49#include <linux/lis3lv02d.h>
50
51#include <video/omap-panel-data.h>
52
53#include <linux/platform_data/pwm_omap_dmtimer.h>
54#include <linux/platform_data/media/ir-rx51.h>
55
56#include "mux.h"
57#include "omap-pm.h"
58#include "hsmmc.h"
59#include "common-board-devices.h"
60#include "soc.h"
61#include "omap-secure.h"
62
63#define SYSTEM_REV_B_USES_VAUX3 0x1699
64#define SYSTEM_REV_S_USES_VAUX3 0x8
65
66#define RX51_WL1251_POWER_GPIO 87
67#define RX51_WL1251_IRQ_GPIO 42
68#define RX51_FMTX_RESET_GPIO 163
69#define RX51_FMTX_IRQ 53
70#define RX51_LP5523_CHIP_EN_GPIO 41
71
72#define RX51_USB_TRANSCEIVER_RST_GPIO 67
73
74#define RX51_TSC2005_RESET_GPIO 104
75#define RX51_TSC2005_IRQ_GPIO 100
76
77#define LIS302_IRQ1_GPIO 181
78#define LIS302_IRQ2_GPIO 180 /* Not yet in use */
79
80/* List all SPI devices here. Note that the list/probe order seems to matter! */
81enum {
82 RX51_SPI_WL1251,
83 RX51_SPI_TSC2005, /* Touch Controller */
84 RX51_SPI_MIPID, /* LCD panel */
85};
86
87static struct wl1251_platform_data wl1251_pdata;
88static struct tsc2005_platform_data tsc2005_pdata;
89
90#if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE)
91static int lis302_setup(void)
92{
93 int err;
94 int irq1 = LIS302_IRQ1_GPIO;
95 int irq2 = LIS302_IRQ2_GPIO;
96
97 /* gpio for interrupt pin 1 */
98 err = gpio_request(irq1, "lis3lv02dl_irq1");
99 if (err) {
100 printk(KERN_ERR "lis3lv02dl: gpio request failed\n");
101 goto out;
102 }
103
104 /* gpio for interrupt pin 2 */
105 err = gpio_request(irq2, "lis3lv02dl_irq2");
106 if (err) {
107 gpio_free(irq1);
108 printk(KERN_ERR "lis3lv02dl: gpio request failed\n");
109 goto out;
110 }
111
112 gpio_direction_input(irq1);
113 gpio_direction_input(irq2);
114
115out:
116 return err;
117}
118
119static int lis302_release(void)
120{
121 gpio_free(LIS302_IRQ1_GPIO);
122 gpio_free(LIS302_IRQ2_GPIO);
123
124 return 0;
125}
126
127static struct lis3lv02d_platform_data rx51_lis3lv02d_data = {
128 .click_flags = LIS3_CLICK_SINGLE_X | LIS3_CLICK_SINGLE_Y |
129 LIS3_CLICK_SINGLE_Z,
130 /* Limits are 0.5g * value */
131 .click_thresh_x = 8,
132 .click_thresh_y = 8,
133 .click_thresh_z = 10,
134 /* Click must be longer than time limit */
135 .click_time_limit = 9,
136 /* Kind of debounce filter */
137 .click_latency = 50,
138
139 /* Limits for all axis. millig-value / 18 to get HW values */
140 .wakeup_flags = LIS3_WAKEUP_X_HI | LIS3_WAKEUP_Y_HI,
141 .wakeup_thresh = 800 / 18,
142 .wakeup_flags2 = LIS3_WAKEUP_Z_HI ,
143 .wakeup_thresh2 = 900 / 18,
144
145 .hipass_ctrl = LIS3_HIPASS1_DISABLE | LIS3_HIPASS2_DISABLE,
146
147 /* Interrupt line 2 for click detection, line 1 for thresholds */
148 .irq_cfg = LIS3_IRQ2_CLICK | LIS3_IRQ1_FF_WU_12,
149
150 .axis_x = LIS3_DEV_X,
151 .axis_y = LIS3_INV_DEV_Y,
152 .axis_z = LIS3_INV_DEV_Z,
153 .setup_resources = lis302_setup,
154 .release_resources = lis302_release,
155 .st_min_limits = {-32, 3, 3},
156 .st_max_limits = {-3, 32, 32},
157};
158#endif
159
160#if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE)
161static struct tsl2563_platform_data rx51_tsl2563_platform_data = {
162 .cover_comp_gain = 16,
163};
164#endif
165
166#if defined(CONFIG_LEDS_LP5523) || defined(CONFIG_LEDS_LP5523_MODULE)
167static struct lp55xx_led_config rx51_lp5523_led_config[] = {
168 {
169 .name = "lp5523:kb1",
170 .chan_nr = 0,
171 .led_current = 50,
172 .max_current = 100,
173 }, {
174 .name = "lp5523:kb2",
175 .chan_nr = 1,
176 .led_current = 50,
177 .max_current = 100,
178 }, {
179 .name = "lp5523:kb3",
180 .chan_nr = 2,
181 .led_current = 50,
182 .max_current = 100,
183 }, {
184 .name = "lp5523:kb4",
185 .chan_nr = 3,
186 .led_current = 50,
187 .max_current = 100,
188 }, {
189 .name = "lp5523:b",
190 .chan_nr = 4,
191 .led_current = 50,
192 .max_current = 100,
193 }, {
194 .name = "lp5523:g",
195 .chan_nr = 5,
196 .led_current = 50,
197 .max_current = 100,
198 }, {
199 .name = "lp5523:r",
200 .chan_nr = 6,
201 .led_current = 50,
202 .max_current = 100,
203 }, {
204 .name = "lp5523:kb5",
205 .chan_nr = 7,
206 .led_current = 50,
207 .max_current = 100,
208 }, {
209 .name = "lp5523:kb6",
210 .chan_nr = 8,
211 .led_current = 50,
212 .max_current = 100,
213 }
214};
215
216static struct lp55xx_platform_data rx51_lp5523_platform_data = {
217 .led_config = rx51_lp5523_led_config,
218 .num_channels = ARRAY_SIZE(rx51_lp5523_led_config),
219 .clock_mode = LP55XX_CLOCK_AUTO,
220 .enable_gpio = RX51_LP5523_CHIP_EN_GPIO,
221};
222#endif
223
224#define RX51_LCD_RESET_GPIO 90
225
226static struct panel_acx565akm_platform_data acx_pdata = {
227 .name = "lcd",
228 .source = "sdi.0",
229 .reset_gpio = RX51_LCD_RESET_GPIO,
230 .datapairs = 2,
231};
232
233static struct omap2_mcspi_device_config wl1251_mcspi_config = {
234 .turbo_mode = 0,
235};
236
237static struct omap2_mcspi_device_config mipid_mcspi_config = {
238 .turbo_mode = 0,
239};
240
241static struct omap2_mcspi_device_config tsc2005_mcspi_config = {
242 .turbo_mode = 0,
243};
244
245static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = {
246 [RX51_SPI_WL1251] = {
247 .modalias = "wl1251",
248 .bus_num = 4,
249 .chip_select = 0,
250 .max_speed_hz = 48000000,
251 .mode = SPI_MODE_3,
252 .controller_data = &wl1251_mcspi_config,
253 .platform_data = &wl1251_pdata,
254 },
255 [RX51_SPI_MIPID] = {
256 .modalias = "acx565akm",
257 .bus_num = 1,
258 .chip_select = 2,
259 .max_speed_hz = 6000000,
260 .controller_data = &mipid_mcspi_config,
261 .platform_data = &acx_pdata,
262 },
263 [RX51_SPI_TSC2005] = {
264 .modalias = "tsc2005",
265 .bus_num = 1,
266 .chip_select = 0,
267 .max_speed_hz = 6000000,
268 .controller_data = &tsc2005_mcspi_config,
269 .platform_data = &tsc2005_pdata,
270 },
271};
272
273static struct platform_device rx51_battery_device = {
274 .name = "rx51-battery",
275 .id = -1,
276};
277
278static void rx51_charger_set_power(bool on)
279{
280 gpio_set_value(RX51_USB_TRANSCEIVER_RST_GPIO, on);
281}
282
283static struct isp1704_charger_data rx51_charger_data = {
284 .set_power = rx51_charger_set_power,
285};
286
287static struct platform_device rx51_charger_device = {
288 .name = "isp1704_charger",
289 .dev = {
290 .platform_data = &rx51_charger_data,
291 },
292};
293
294static void __init rx51_charger_init(void)
295{
296 WARN_ON(gpio_request_one(RX51_USB_TRANSCEIVER_RST_GPIO,
297 GPIOF_OUT_INIT_HIGH, "isp1704_reset"));
298
299 platform_device_register(&rx51_battery_device);
300 platform_device_register(&rx51_charger_device);
301}
302
303#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
304
305#define RX51_GPIO_CAMERA_LENS_COVER 110
306#define RX51_GPIO_CAMERA_FOCUS 68
307#define RX51_GPIO_CAMERA_CAPTURE 69
308#define RX51_GPIO_KEYPAD_SLIDE 71
309#define RX51_GPIO_LOCK_BUTTON 113
310#define RX51_GPIO_PROXIMITY 89
311
312#define RX51_GPIO_DEBOUNCE_TIMEOUT 10
313
314static struct gpio_keys_button rx51_gpio_keys[] = {
315 {
316 .desc = "Camera Lens Cover",
317 .type = EV_SW,
318 .code = SW_CAMERA_LENS_COVER,
319 .gpio = RX51_GPIO_CAMERA_LENS_COVER,
320 .active_low = 1,
321 .debounce_interval = RX51_GPIO_DEBOUNCE_TIMEOUT,
322 }, {
323 .desc = "Camera Focus",
324 .type = EV_KEY,
325 .code = KEY_CAMERA_FOCUS,
326 .gpio = RX51_GPIO_CAMERA_FOCUS,
327 .active_low = 1,
328 .debounce_interval = RX51_GPIO_DEBOUNCE_TIMEOUT,
329 }, {
330 .desc = "Camera Capture",
331 .type = EV_KEY,
332 .code = KEY_CAMERA,
333 .gpio = RX51_GPIO_CAMERA_CAPTURE,
334 .active_low = 1,
335 .debounce_interval = RX51_GPIO_DEBOUNCE_TIMEOUT,
336 }, {
337 .desc = "Lock Button",
338 .type = EV_KEY,
339 .code = KEY_SCREENLOCK,
340 .gpio = RX51_GPIO_LOCK_BUTTON,
341 .active_low = 1,
342 .debounce_interval = RX51_GPIO_DEBOUNCE_TIMEOUT,
343 }, {
344 .desc = "Keypad Slide",
345 .type = EV_SW,
346 .code = SW_KEYPAD_SLIDE,
347 .gpio = RX51_GPIO_KEYPAD_SLIDE,
348 .active_low = 1,
349 .debounce_interval = RX51_GPIO_DEBOUNCE_TIMEOUT,
350 }, {
351 .desc = "Proximity Sensor",
352 .type = EV_SW,
353 .code = SW_FRONT_PROXIMITY,
354 .gpio = RX51_GPIO_PROXIMITY,
355 .active_low = 0,
356 .debounce_interval = RX51_GPIO_DEBOUNCE_TIMEOUT,
357 }
358};
359
360static struct gpio_keys_platform_data rx51_gpio_keys_data = {
361 .buttons = rx51_gpio_keys,
362 .nbuttons = ARRAY_SIZE(rx51_gpio_keys),
363};
364
365static struct platform_device rx51_gpio_keys_device = {
366 .name = "gpio-keys",
367 .id = -1,
368 .dev = {
369 .platform_data = &rx51_gpio_keys_data,
370 },
371};
372
373static void __init rx51_add_gpio_keys(void)
374{
375 platform_device_register(&rx51_gpio_keys_device);
376}
377#else
378static void __init rx51_add_gpio_keys(void)
379{
380}
381#endif /* CONFIG_KEYBOARD_GPIO || CONFIG_KEYBOARD_GPIO_MODULE */
382
383static uint32_t board_keymap[] = {
384 /*
385 * Note that KEY(x, 8, KEY_XXX) entries represent "entrire row
386 * connected to the ground" matrix state.
387 */
388 KEY(0, 0, KEY_Q),
389 KEY(0, 1, KEY_O),
390 KEY(0, 2, KEY_P),
391 KEY(0, 3, KEY_COMMA),
392 KEY(0, 4, KEY_BACKSPACE),
393 KEY(0, 6, KEY_A),
394 KEY(0, 7, KEY_S),
395
396 KEY(1, 0, KEY_W),
397 KEY(1, 1, KEY_D),
398 KEY(1, 2, KEY_F),
399 KEY(1, 3, KEY_G),
400 KEY(1, 4, KEY_H),
401 KEY(1, 5, KEY_J),
402 KEY(1, 6, KEY_K),
403 KEY(1, 7, KEY_L),
404
405 KEY(2, 0, KEY_E),
406 KEY(2, 1, KEY_DOT),
407 KEY(2, 2, KEY_UP),
408 KEY(2, 3, KEY_ENTER),
409 KEY(2, 5, KEY_Z),
410 KEY(2, 6, KEY_X),
411 KEY(2, 7, KEY_C),
412 KEY(2, 8, KEY_F9),
413
414 KEY(3, 0, KEY_R),
415 KEY(3, 1, KEY_V),
416 KEY(3, 2, KEY_B),
417 KEY(3, 3, KEY_N),
418 KEY(3, 4, KEY_M),
419 KEY(3, 5, KEY_SPACE),
420 KEY(3, 6, KEY_SPACE),
421 KEY(3, 7, KEY_LEFT),
422
423 KEY(4, 0, KEY_T),
424 KEY(4, 1, KEY_DOWN),
425 KEY(4, 2, KEY_RIGHT),
426 KEY(4, 4, KEY_LEFTCTRL),
427 KEY(4, 5, KEY_RIGHTALT),
428 KEY(4, 6, KEY_LEFTSHIFT),
429 KEY(4, 8, KEY_F10),
430
431 KEY(5, 0, KEY_Y),
432 KEY(5, 8, KEY_F11),
433
434 KEY(6, 0, KEY_U),
435
436 KEY(7, 0, KEY_I),
437 KEY(7, 1, KEY_F7),
438 KEY(7, 2, KEY_F8),
439};
440
441static struct matrix_keymap_data board_map_data = {
442 .keymap = board_keymap,
443 .keymap_size = ARRAY_SIZE(board_keymap),
444};
445
446static struct twl4030_keypad_data rx51_kp_data = {
447 .keymap_data = &board_map_data,
448 .rows = 8,
449 .cols = 8,
450 .rep = 1,
451};
452
453/* Enable input logic and pull all lines up when eMMC is on. */
454static struct omap_board_mux rx51_mmc2_on_mux[] = {
455 OMAP3_MUX(SDMMC2_CMD, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
456 OMAP3_MUX(SDMMC2_DAT0, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
457 OMAP3_MUX(SDMMC2_DAT1, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
458 OMAP3_MUX(SDMMC2_DAT2, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
459 OMAP3_MUX(SDMMC2_DAT3, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
460 OMAP3_MUX(SDMMC2_DAT4, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
461 OMAP3_MUX(SDMMC2_DAT5, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
462 OMAP3_MUX(SDMMC2_DAT6, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
463 OMAP3_MUX(SDMMC2_DAT7, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
464 { .reg_offset = OMAP_MUX_TERMINATOR },
465};
466
467/* Disable input logic and pull all lines down when eMMC is off. */
468static struct omap_board_mux rx51_mmc2_off_mux[] = {
469 OMAP3_MUX(SDMMC2_CMD, OMAP_PULL_ENA | OMAP_MUX_MODE0),
470 OMAP3_MUX(SDMMC2_DAT0, OMAP_PULL_ENA | OMAP_MUX_MODE0),
471 OMAP3_MUX(SDMMC2_DAT1, OMAP_PULL_ENA | OMAP_MUX_MODE0),
472 OMAP3_MUX(SDMMC2_DAT2, OMAP_PULL_ENA | OMAP_MUX_MODE0),
473 OMAP3_MUX(SDMMC2_DAT3, OMAP_PULL_ENA | OMAP_MUX_MODE0),
474 OMAP3_MUX(SDMMC2_DAT4, OMAP_PULL_ENA | OMAP_MUX_MODE0),
475 OMAP3_MUX(SDMMC2_DAT5, OMAP_PULL_ENA | OMAP_MUX_MODE0),
476 OMAP3_MUX(SDMMC2_DAT6, OMAP_PULL_ENA | OMAP_MUX_MODE0),
477 OMAP3_MUX(SDMMC2_DAT7, OMAP_PULL_ENA | OMAP_MUX_MODE0),
478 { .reg_offset = OMAP_MUX_TERMINATOR },
479};
480
481static struct omap_mux_partition *partition;
482
483/*
484 * Current flows to eMMC when eMMC is off and the data lines are pulled up,
485 * so pull them down. N.B. we pull 8 lines because we are using 8 lines.
486 */
487static void rx51_mmc2_remux(struct device *dev, int power_on)
488{
489 if (power_on)
490 omap_mux_write_array(partition, rx51_mmc2_on_mux);
491 else
492 omap_mux_write_array(partition, rx51_mmc2_off_mux);
493}
494
495static struct omap2_hsmmc_info mmc[] __initdata = {
496 {
497 .name = "external",
498 .mmc = 1,
499 .caps = MMC_CAP_4_BIT_DATA,
500 .cover_only = true,
501 .gpio_cd = 160,
502 .gpio_wp = -EINVAL,
503 },
504 {
505 .name = "internal",
506 .mmc = 2,
507 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
508 /* See also rx51_mmc2_remux */
509 .gpio_cd = -EINVAL,
510 .gpio_wp = -EINVAL,
511 .nonremovable = true,
512 .remux = rx51_mmc2_remux,
513 },
514 {} /* Terminator */
515};
516
517static struct regulator_consumer_supply rx51_vmmc1_supply[] = {
518 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
519};
520
521static struct regulator_consumer_supply rx51_vaux2_supply[] = {
522 REGULATOR_SUPPLY("vdds_csib", "omap3isp"),
523};
524
525static struct regulator_consumer_supply rx51_vaux3_supply[] = {
526 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
527};
528
529static struct regulator_consumer_supply rx51_vsim_supply[] = {
530 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"),
531};
532
533static struct regulator_consumer_supply rx51_vmmc2_supplies[] = {
534 /* tlv320aic3x analog supplies */
535 REGULATOR_SUPPLY("AVDD", "2-0018"),
536 REGULATOR_SUPPLY("DRVDD", "2-0018"),
537 REGULATOR_SUPPLY("AVDD", "2-0019"),
538 REGULATOR_SUPPLY("DRVDD", "2-0019"),
539 /* tpa6130a2 */
540 REGULATOR_SUPPLY("Vdd", "2-0060"),
541 /* Keep vmmc as last item. It is not iterated for newer boards */
542 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
543};
544
545static struct regulator_consumer_supply rx51_vio_supplies[] = {
546 /* tlv320aic3x digital supplies */
547 REGULATOR_SUPPLY("IOVDD", "2-0018"),
548 REGULATOR_SUPPLY("DVDD", "2-0018"),
549 REGULATOR_SUPPLY("IOVDD", "2-0019"),
550 REGULATOR_SUPPLY("DVDD", "2-0019"),
551 /* Si4713 IO supply */
552 REGULATOR_SUPPLY("vio", "2-0063"),
553 /* lis3lv02d */
554 REGULATOR_SUPPLY("Vdd_IO", "3-001d"),
555};
556
557static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
558 REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
559 REGULATOR_SUPPLY("vdds_sdi", "omapdss_sdi.0"),
560 /* Si4713 supply */
561 REGULATOR_SUPPLY("vdd", "2-0063"),
562 /* lis3lv02d */
563 REGULATOR_SUPPLY("Vdd", "3-001d"),
564};
565
566static struct regulator_init_data rx51_vaux1 = {
567 .constraints = {
568 .name = "V28",
569 .min_uV = 2800000,
570 .max_uV = 2800000,
571 .always_on = true, /* due battery cover sensor */
572 .valid_modes_mask = REGULATOR_MODE_NORMAL
573 | REGULATOR_MODE_STANDBY,
574 .valid_ops_mask = REGULATOR_CHANGE_MODE
575 | REGULATOR_CHANGE_STATUS,
576 },
577 .num_consumer_supplies = ARRAY_SIZE(rx51_vaux1_consumers),
578 .consumer_supplies = rx51_vaux1_consumers,
579};
580
581static struct regulator_init_data rx51_vaux2 = {
582 .constraints = {
583 .name = "VCSI",
584 .min_uV = 1800000,
585 .max_uV = 1800000,
586 .valid_modes_mask = REGULATOR_MODE_NORMAL
587 | REGULATOR_MODE_STANDBY,
588 .valid_ops_mask = REGULATOR_CHANGE_MODE
589 | REGULATOR_CHANGE_STATUS,
590 },
591 .num_consumer_supplies = ARRAY_SIZE(rx51_vaux2_supply),
592 .consumer_supplies = rx51_vaux2_supply,
593};
594
595/* VAUX3 - adds more power to VIO_18 rail */
596static struct regulator_init_data rx51_vaux3_cam = {
597 .constraints = {
598 .name = "VCAM_DIG_18",
599 .min_uV = 1800000,
600 .max_uV = 1800000,
601 .apply_uV = true,
602 .valid_modes_mask = REGULATOR_MODE_NORMAL
603 | REGULATOR_MODE_STANDBY,
604 .valid_ops_mask = REGULATOR_CHANGE_MODE
605 | REGULATOR_CHANGE_STATUS,
606 },
607};
608
609static struct regulator_init_data rx51_vaux3_mmc = {
610 .constraints = {
611 .name = "VMMC2_30",
612 .min_uV = 2800000,
613 .max_uV = 3000000,
614 .apply_uV = true,
615 .valid_modes_mask = REGULATOR_MODE_NORMAL
616 | REGULATOR_MODE_STANDBY,
617 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
618 | REGULATOR_CHANGE_MODE
619 | REGULATOR_CHANGE_STATUS,
620 },
621 .num_consumer_supplies = ARRAY_SIZE(rx51_vaux3_supply),
622 .consumer_supplies = rx51_vaux3_supply,
623};
624
625static struct regulator_init_data rx51_vaux4 = {
626 .constraints = {
627 .name = "VCAM_ANA_28",
628 .min_uV = 2800000,
629 .max_uV = 2800000,
630 .apply_uV = true,
631 .valid_modes_mask = REGULATOR_MODE_NORMAL
632 | REGULATOR_MODE_STANDBY,
633 .valid_ops_mask = REGULATOR_CHANGE_MODE
634 | REGULATOR_CHANGE_STATUS,
635 },
636};
637
638static struct regulator_init_data rx51_vmmc1 = {
639 .constraints = {
640 .min_uV = 1850000,
641 .max_uV = 3150000,
642 .valid_modes_mask = REGULATOR_MODE_NORMAL
643 | REGULATOR_MODE_STANDBY,
644 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
645 | REGULATOR_CHANGE_MODE
646 | REGULATOR_CHANGE_STATUS,
647 },
648 .num_consumer_supplies = ARRAY_SIZE(rx51_vmmc1_supply),
649 .consumer_supplies = rx51_vmmc1_supply,
650};
651
652static struct regulator_init_data rx51_vmmc2 = {
653 .constraints = {
654 .name = "V28_A",
655 .min_uV = 2800000,
656 .max_uV = 3000000,
657 .always_on = true, /* due VIO leak to AIC34 VDDs */
658 .apply_uV = true,
659 .valid_modes_mask = REGULATOR_MODE_NORMAL
660 | REGULATOR_MODE_STANDBY,
661 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
662 | REGULATOR_CHANGE_MODE
663 | REGULATOR_CHANGE_STATUS,
664 },
665 .num_consumer_supplies = ARRAY_SIZE(rx51_vmmc2_supplies),
666 .consumer_supplies = rx51_vmmc2_supplies,
667};
668
669static struct regulator_init_data rx51_vpll1 = {
670 .constraints = {
671 .name = "VPLL",
672 .min_uV = 1800000,
673 .max_uV = 1800000,
674 .apply_uV = true,
675 .always_on = true,
676 .valid_modes_mask = REGULATOR_MODE_NORMAL
677 | REGULATOR_MODE_STANDBY,
678 .valid_ops_mask = REGULATOR_CHANGE_MODE,
679 },
680};
681
682static struct regulator_init_data rx51_vpll2 = {
683 .constraints = {
684 .name = "VSDI_CSI",
685 .min_uV = 1800000,
686 .max_uV = 1800000,
687 .apply_uV = true,
688 .always_on = true,
689 .valid_modes_mask = REGULATOR_MODE_NORMAL
690 | REGULATOR_MODE_STANDBY,
691 .valid_ops_mask = REGULATOR_CHANGE_MODE,
692 },
693};
694
695static struct regulator_init_data rx51_vsim = {
696 .constraints = {
697 .name = "VMMC2_IO_18",
698 .min_uV = 1800000,
699 .max_uV = 1800000,
700 .apply_uV = true,
701 .valid_modes_mask = REGULATOR_MODE_NORMAL
702 | REGULATOR_MODE_STANDBY,
703 .valid_ops_mask = REGULATOR_CHANGE_MODE
704 | REGULATOR_CHANGE_STATUS,
705 },
706 .num_consumer_supplies = ARRAY_SIZE(rx51_vsim_supply),
707 .consumer_supplies = rx51_vsim_supply,
708};
709
710static struct regulator_init_data rx51_vio = {
711 .constraints = {
712 .min_uV = 1800000,
713 .max_uV = 1800000,
714 .valid_modes_mask = REGULATOR_MODE_NORMAL
715 | REGULATOR_MODE_STANDBY,
716 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
717 | REGULATOR_CHANGE_MODE
718 | REGULATOR_CHANGE_STATUS,
719 },
720 .num_consumer_supplies = ARRAY_SIZE(rx51_vio_supplies),
721 .consumer_supplies = rx51_vio_supplies,
722};
723
724static struct regulator_init_data rx51_vintana1 = {
725 .constraints = {
726 .name = "VINTANA1",
727 .min_uV = 1500000,
728 .max_uV = 1500000,
729 .always_on = true,
730 .valid_modes_mask = REGULATOR_MODE_NORMAL
731 | REGULATOR_MODE_STANDBY,
732 .valid_ops_mask = REGULATOR_CHANGE_MODE,
733 },
734};
735
736static struct regulator_init_data rx51_vintana2 = {
737 .constraints = {
738 .name = "VINTANA2",
739 .min_uV = 2750000,
740 .max_uV = 2750000,
741 .apply_uV = true,
742 .always_on = true,
743 .valid_modes_mask = REGULATOR_MODE_NORMAL
744 | REGULATOR_MODE_STANDBY,
745 .valid_ops_mask = REGULATOR_CHANGE_MODE,
746 },
747};
748
749static struct regulator_init_data rx51_vintdig = {
750 .constraints = {
751 .name = "VINTDIG",
752 .min_uV = 1500000,
753 .max_uV = 1500000,
754 .always_on = true,
755 .valid_modes_mask = REGULATOR_MODE_NORMAL
756 | REGULATOR_MODE_STANDBY,
757 .valid_ops_mask = REGULATOR_CHANGE_MODE,
758 },
759};
760
761static struct gpiod_lookup_table rx51_fmtx_gpios_table = {
762 .dev_id = "2-0063",
763 .table = {
764 GPIO_LOOKUP("gpio.6", 3, "reset", GPIO_ACTIVE_HIGH), /* 163 */
765 { },
766 },
767};
768
769static __init void rx51_gpio_init(void)
770{
771 gpiod_add_lookup_table(&rx51_fmtx_gpios_table);
772}
773
774static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n)
775{
776 /* FIXME this gpio setup is just a placeholder for now */
777 gpio_request_one(gpio + 6, GPIOF_OUT_INIT_LOW, "backlight_pwm");
778 gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "speaker_en");
779
780 return 0;
781}
782
783static struct twl4030_gpio_platform_data rx51_gpio_data = {
784 .pulldowns = BIT(0) | BIT(1) | BIT(2) | BIT(3)
785 | BIT(4) | BIT(5)
786 | BIT(8) | BIT(9) | BIT(10) | BIT(11)
787 | BIT(12) | BIT(13) | BIT(14) | BIT(15)
788 | BIT(16) | BIT(17) ,
789 .setup = rx51_twlgpio_setup,
790};
791
792static struct twl4030_ins sleep_on_seq[] __initdata = {
793/*
794 * Turn off everything
795 */
796 {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 1, 0, RES_STATE_SLEEP), 2},
797};
798
799static struct twl4030_script sleep_on_script __initdata = {
800 .script = sleep_on_seq,
801 .size = ARRAY_SIZE(sleep_on_seq),
802 .flags = TWL4030_SLEEP_SCRIPT,
803};
804
805static struct twl4030_ins wakeup_seq[] __initdata = {
806/*
807 * Reenable everything
808 */
809 {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 1, 0, RES_STATE_ACTIVE), 2},
810};
811
812static struct twl4030_script wakeup_script __initdata = {
813 .script = wakeup_seq,
814 .size = ARRAY_SIZE(wakeup_seq),
815 .flags = TWL4030_WAKEUP12_SCRIPT,
816};
817
818static struct twl4030_ins wakeup_p3_seq[] __initdata = {
819/*
820 * Reenable everything
821 */
822 {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 1, 0, RES_STATE_ACTIVE), 2},
823};
824
825static struct twl4030_script wakeup_p3_script __initdata = {
826 .script = wakeup_p3_seq,
827 .size = ARRAY_SIZE(wakeup_p3_seq),
828 .flags = TWL4030_WAKEUP3_SCRIPT,
829};
830
831static struct twl4030_ins wrst_seq[] __initdata = {
832/*
833 * Reset twl4030.
834 * Reset VDD1 regulator.
835 * Reset VDD2 regulator.
836 * Reset VPLL1 regulator.
837 * Enable sysclk output.
838 * Reenable twl4030.
839 */
840 {MSG_SINGULAR(DEV_GRP_NULL, RES_RESET, RES_STATE_OFF), 2},
841 {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 0, 1, RES_STATE_ACTIVE),
842 0x13},
843 {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP, 0, 3, RES_STATE_OFF), 0x13},
844 {MSG_SINGULAR(DEV_GRP_NULL, RES_VDD1, RES_STATE_WRST), 0x13},
845 {MSG_SINGULAR(DEV_GRP_NULL, RES_VDD2, RES_STATE_WRST), 0x13},
846 {MSG_SINGULAR(DEV_GRP_NULL, RES_VPLL1, RES_STATE_WRST), 0x35},
847 {MSG_SINGULAR(DEV_GRP_P3, RES_HFCLKOUT, RES_STATE_ACTIVE), 2},
848 {MSG_SINGULAR(DEV_GRP_NULL, RES_RESET, RES_STATE_ACTIVE), 2},
849};
850
851static struct twl4030_script wrst_script __initdata = {
852 .script = wrst_seq,
853 .size = ARRAY_SIZE(wrst_seq),
854 .flags = TWL4030_WRST_SCRIPT,
855};
856
857static struct twl4030_script *twl4030_scripts[] __initdata = {
858 /* wakeup12 script should be loaded before sleep script, otherwise a
859 board might hit retention before loading of wakeup script is
860 completed. This can cause boot failures depending on timing issues.
861 */
862 &wakeup_script,
863 &sleep_on_script,
864 &wakeup_p3_script,
865 &wrst_script,
866};
867
868static struct twl4030_resconfig twl4030_rconfig[] __initdata = {
869 { .resource = RES_VDD1, .devgroup = -1,
870 .type = 1, .type2 = -1, .remap_off = RES_STATE_OFF,
871 .remap_sleep = RES_STATE_OFF
872 },
873 { .resource = RES_VDD2, .devgroup = -1,
874 .type = 1, .type2 = -1, .remap_off = RES_STATE_OFF,
875 .remap_sleep = RES_STATE_OFF
876 },
877 { .resource = RES_VPLL1, .devgroup = -1,
878 .type = 1, .type2 = -1, .remap_off = RES_STATE_OFF,
879 .remap_sleep = RES_STATE_OFF
880 },
881 { .resource = RES_VPLL2, .devgroup = -1,
882 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
883 },
884 { .resource = RES_VAUX1, .devgroup = -1,
885 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
886 },
887 { .resource = RES_VAUX2, .devgroup = -1,
888 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
889 },
890 { .resource = RES_VAUX3, .devgroup = -1,
891 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
892 },
893 { .resource = RES_VAUX4, .devgroup = -1,
894 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
895 },
896 { .resource = RES_VMMC1, .devgroup = -1,
897 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
898 },
899 { .resource = RES_VMMC2, .devgroup = -1,
900 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
901 },
902 { .resource = RES_VDAC, .devgroup = -1,
903 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
904 },
905 { .resource = RES_VSIM, .devgroup = -1,
906 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
907 },
908 { .resource = RES_VINTANA1, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
909 .type = -1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
910 },
911 { .resource = RES_VINTANA2, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
912 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
913 },
914 { .resource = RES_VINTDIG, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
915 .type = -1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
916 },
917 { .resource = RES_VIO, .devgroup = DEV_GRP_P3,
918 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
919 },
920 { .resource = RES_CLKEN, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
921 .type = 1, .type2 = -1 , .remap_off = -1, .remap_sleep = -1
922 },
923 { .resource = RES_REGEN, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
924 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
925 },
926 { .resource = RES_NRES_PWRON, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
927 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
928 },
929 { .resource = RES_SYSEN, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
930 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
931 },
932 { .resource = RES_HFCLKOUT, .devgroup = DEV_GRP_P3,
933 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
934 },
935 { .resource = RES_32KCLKOUT, .devgroup = -1,
936 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
937 },
938 { .resource = RES_RESET, .devgroup = -1,
939 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
940 },
941 { .resource = RES_MAIN_REF, .devgroup = -1,
942 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
943 },
944 { 0, 0},
945};
946
947static struct twl4030_power_data rx51_t2scripts_data __initdata = {
948 .scripts = twl4030_scripts,
949 .num = ARRAY_SIZE(twl4030_scripts),
950 .resource_config = twl4030_rconfig,
951};
952
953static struct twl4030_vibra_data rx51_vibra_data __initdata = {
954 .coexist = 0,
955};
956
957static struct twl4030_audio_data rx51_audio_data __initdata = {
958 .audio_mclk = 26000000,
959 .vibra = &rx51_vibra_data,
960};
961
962static struct twl4030_platform_data rx51_twldata __initdata = {
963 /* platform_data for children goes here */
964 .gpio = &rx51_gpio_data,
965 .keypad = &rx51_kp_data,
966 .power = &rx51_t2scripts_data,
967 .audio = &rx51_audio_data,
968
969 .vaux1 = &rx51_vaux1,
970 .vaux2 = &rx51_vaux2,
971 .vaux4 = &rx51_vaux4,
972 .vmmc1 = &rx51_vmmc1,
973 .vpll1 = &rx51_vpll1,
974 .vpll2 = &rx51_vpll2,
975 .vsim = &rx51_vsim,
976 .vintana1 = &rx51_vintana1,
977 .vintana2 = &rx51_vintana2,
978 .vintdig = &rx51_vintdig,
979 .vio = &rx51_vio,
980};
981
982static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata_or_module = {
983 .power_gpio = 98,
984};
985
986/* Audio setup data */
987static struct aic3x_setup_data rx51_aic34_setup = {
988 .gpio_func[0] = AIC3X_GPIO1_FUNC_DISABLED,
989 .gpio_func[1] = AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT,
990};
991
992static struct aic3x_pdata rx51_aic3x_data = {
993 .setup = &rx51_aic34_setup,
994 .gpio_reset = 60,
995};
996
997static struct aic3x_pdata rx51_aic3x_data2 = {
998 .gpio_reset = 60,
999};
1000
1001#if IS_ENABLED(CONFIG_I2C_SI4713) && IS_ENABLED(CONFIG_PLATFORM_SI4713)
1002static struct si4713_platform_data rx51_si4713_platform_data = {
1003 .is_platform_device = true
1004};
1005#endif
1006
1007static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = {
1008#if IS_ENABLED(CONFIG_I2C_SI4713) && IS_ENABLED(CONFIG_PLATFORM_SI4713)
1009 {
1010 I2C_BOARD_INFO("si4713", 0x63),
1011 .platform_data = &rx51_si4713_platform_data,
1012 },
1013#endif
1014 {
1015 I2C_BOARD_INFO("tlv320aic3x", 0x18),
1016 .platform_data = &rx51_aic3x_data,
1017 },
1018 {
1019 I2C_BOARD_INFO("tlv320aic3x", 0x19),
1020 .platform_data = &rx51_aic3x_data2,
1021 },
1022#if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE)
1023 {
1024 I2C_BOARD_INFO("tsl2563", 0x29),
1025 .platform_data = &rx51_tsl2563_platform_data,
1026 },
1027#endif
1028#if defined(CONFIG_LEDS_LP5523) || defined(CONFIG_LEDS_LP5523_MODULE)
1029 {
1030 I2C_BOARD_INFO("lp5523", 0x32),
1031 .platform_data = &rx51_lp5523_platform_data,
1032 },
1033#endif
1034 {
1035 I2C_BOARD_INFO("bq27200", 0x55),
1036 },
1037 {
1038 I2C_BOARD_INFO("tpa6130a2", 0x60),
1039 .platform_data = &rx51_tpa6130a2_data,
1040 }
1041};
1042
1043static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_3[] = {
1044#if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE)
1045 {
1046 I2C_BOARD_INFO("lis3lv02d", 0x1d),
1047 .platform_data = &rx51_lis3lv02d_data,
1048 },
1049#endif
1050};
1051
1052static int __init rx51_i2c_init(void)
1053{
1054#if IS_ENABLED(CONFIG_I2C_SI4713) && IS_ENABLED(CONFIG_PLATFORM_SI4713)
1055 int err;
1056#endif
1057
1058 if ((system_rev >= SYSTEM_REV_S_USES_VAUX3 && system_rev < 0x100) ||
1059 system_rev >= SYSTEM_REV_B_USES_VAUX3) {
1060 rx51_twldata.vaux3 = &rx51_vaux3_mmc;
1061 /* Only older boards use VMMC2 for internal MMC */
1062 rx51_vmmc2.num_consumer_supplies--;
1063 } else {
1064 rx51_twldata.vaux3 = &rx51_vaux3_cam;
1065 }
1066 rx51_twldata.vmmc2 = &rx51_vmmc2;
1067 omap3_pmic_get_config(&rx51_twldata,
1068 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC,
1069 TWL_COMMON_REGULATOR_VDAC);
1070
1071 rx51_twldata.vdac->constraints.apply_uV = true;
1072 rx51_twldata.vdac->constraints.name = "VDAC";
1073
1074 omap_pmic_init(1, 2200, "twl5030", 7 + OMAP_INTC_START, &rx51_twldata);
1075#if IS_ENABLED(CONFIG_I2C_SI4713) && IS_ENABLED(CONFIG_PLATFORM_SI4713)
1076 err = gpio_request_one(RX51_FMTX_IRQ, GPIOF_DIR_IN, "si4713 irq");
1077 if (err) {
1078 printk(KERN_ERR "Cannot request si4713 irq gpio. %d\n", err);
1079 return err;
1080 }
1081 rx51_peripherals_i2c_board_info_2[0].irq = gpio_to_irq(RX51_FMTX_IRQ);
1082#endif
1083 omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2,
1084 ARRAY_SIZE(rx51_peripherals_i2c_board_info_2));
1085#if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE)
1086 rx51_lis3lv02d_data.irq2 = gpio_to_irq(LIS302_IRQ2_GPIO);
1087 rx51_peripherals_i2c_board_info_3[0].irq = gpio_to_irq(LIS302_IRQ1_GPIO);
1088#endif
1089 omap_register_i2c_bus(3, 400, rx51_peripherals_i2c_board_info_3,
1090 ARRAY_SIZE(rx51_peripherals_i2c_board_info_3));
1091 return 0;
1092}
1093
1094#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
1095 defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
1096
1097static struct mtd_partition onenand_partitions[] = {
1098 {
1099 .name = "bootloader",
1100 .offset = 0,
1101 .size = 0x20000,
1102 .mask_flags = MTD_WRITEABLE, /* Force read-only */
1103 },
1104 {
1105 .name = "config",
1106 .offset = MTDPART_OFS_APPEND,
1107 .size = 0x60000,
1108 },
1109 {
1110 .name = "log",
1111 .offset = MTDPART_OFS_APPEND,
1112 .size = 0x40000,
1113 },
1114 {
1115 .name = "kernel",
1116 .offset = MTDPART_OFS_APPEND,
1117 .size = 0x200000,
1118 },
1119 {
1120 .name = "initfs",
1121 .offset = MTDPART_OFS_APPEND,
1122 .size = 0x200000,
1123 },
1124 {
1125 .name = "rootfs",
1126 .offset = MTDPART_OFS_APPEND,
1127 .size = MTDPART_SIZ_FULL,
1128 },
1129};
1130
1131static struct omap_onenand_platform_data board_onenand_data[] = {
1132 {
1133 .cs = 0,
1134 .gpio_irq = 65,
1135 .parts = onenand_partitions,
1136 .nr_parts = ARRAY_SIZE(onenand_partitions),
1137 .flags = ONENAND_SYNC_READWRITE,
1138 }
1139};
1140#endif
1141
1142static struct gpio rx51_wl1251_gpios[] __initdata = {
1143 { RX51_WL1251_IRQ_GPIO, GPIOF_IN, "wl1251 irq" },
1144};
1145
1146static void __init rx51_init_wl1251(void)
1147{
1148 int irq, ret;
1149
1150 ret = gpio_request_array(rx51_wl1251_gpios,
1151 ARRAY_SIZE(rx51_wl1251_gpios));
1152 if (ret < 0)
1153 goto error;
1154
1155 irq = gpio_to_irq(RX51_WL1251_IRQ_GPIO);
1156 if (irq < 0)
1157 goto err_irq;
1158
1159 wl1251_pdata.power_gpio = RX51_WL1251_POWER_GPIO;
1160 rx51_peripherals_spi_board_info[RX51_SPI_WL1251].irq = irq;
1161
1162 return;
1163
1164err_irq:
1165 gpio_free(RX51_WL1251_IRQ_GPIO);
1166error:
1167 printk(KERN_ERR "wl1251 board initialisation failed\n");
1168 wl1251_pdata.power_gpio = -1;
1169
1170 /*
1171 * Now rx51_peripherals_spi_board_info[1].irq is zero and
1172 * set_power is null, and wl1251_probe() will fail.
1173 */
1174}
1175
1176static struct tsc2005_platform_data tsc2005_pdata = {
1177 .ts_pressure_max = 2048,
1178 .ts_pressure_fudge = 2,
1179 .ts_x_max = 4096,
1180 .ts_x_fudge = 4,
1181 .ts_y_max = 4096,
1182 .ts_y_fudge = 7,
1183 .ts_x_plate_ohm = 280,
1184 .esd_timeout_ms = 8000,
1185};
1186
1187static struct gpio rx51_tsc2005_gpios[] __initdata = {
1188 { RX51_TSC2005_IRQ_GPIO, GPIOF_IN, "tsc2005 IRQ" },
1189 { RX51_TSC2005_RESET_GPIO, GPIOF_OUT_INIT_HIGH, "tsc2005 reset" },
1190};
1191
1192static void rx51_tsc2005_set_reset(bool enable)
1193{
1194 gpio_set_value(RX51_TSC2005_RESET_GPIO, enable);
1195}
1196
1197static void __init rx51_init_tsc2005(void)
1198{
1199 int r;
1200
1201 omap_mux_init_gpio(RX51_TSC2005_RESET_GPIO, OMAP_PIN_OUTPUT);
1202 omap_mux_init_gpio(RX51_TSC2005_IRQ_GPIO, OMAP_PIN_INPUT_PULLUP);
1203
1204 r = gpio_request_array(rx51_tsc2005_gpios,
1205 ARRAY_SIZE(rx51_tsc2005_gpios));
1206 if (r < 0) {
1207 printk(KERN_ERR "tsc2005 board initialization failed\n");
1208 tsc2005_pdata.esd_timeout_ms = 0;
1209 return;
1210 }
1211
1212 tsc2005_pdata.set_reset = rx51_tsc2005_set_reset;
1213 rx51_peripherals_spi_board_info[RX51_SPI_TSC2005].irq =
1214 gpio_to_irq(RX51_TSC2005_IRQ_GPIO);
1215}
1216
1217#if IS_ENABLED(CONFIG_OMAP_DM_TIMER)
1218static struct pwm_omap_dmtimer_pdata __maybe_unused pwm_dmtimer_pdata = {
1219 .request_by_node = omap_dm_timer_request_by_node,
1220 .request_specific = omap_dm_timer_request_specific,
1221 .request = omap_dm_timer_request,
1222 .set_source = omap_dm_timer_set_source,
1223 .get_irq = omap_dm_timer_get_irq,
1224 .set_int_enable = omap_dm_timer_set_int_enable,
1225 .set_int_disable = omap_dm_timer_set_int_disable,
1226 .free = omap_dm_timer_free,
1227 .enable = omap_dm_timer_enable,
1228 .disable = omap_dm_timer_disable,
1229 .get_fclk = omap_dm_timer_get_fclk,
1230 .start = omap_dm_timer_start,
1231 .stop = omap_dm_timer_stop,
1232 .set_load = omap_dm_timer_set_load,
1233 .set_match = omap_dm_timer_set_match,
1234 .set_pwm = omap_dm_timer_set_pwm,
1235 .set_prescaler = omap_dm_timer_set_prescaler,
1236 .read_counter = omap_dm_timer_read_counter,
1237 .write_counter = omap_dm_timer_write_counter,
1238 .read_status = omap_dm_timer_read_status,
1239 .write_status = omap_dm_timer_write_status,
1240};
1241#endif
1242
1243#if defined(CONFIG_IR_RX51) || defined(CONFIG_IR_RX51_MODULE)
1244static struct lirc_rx51_platform_data rx51_lirc_data = {
1245 .set_max_mpu_wakeup_lat = omap_pm_set_max_mpu_wakeup_lat,
1246};
1247
1248static struct platform_device rx51_lirc_device = {
1249 .name = "lirc_rx51",
1250 .id = -1,
1251 .dev = {
1252 .platform_data = &rx51_lirc_data,
1253 },
1254};
1255
1256static void __init rx51_init_lirc(void)
1257{
1258 platform_device_register(&rx51_lirc_device);
1259}
1260#else
1261static void __init rx51_init_lirc(void)
1262{
1263}
1264#endif
1265
1266static struct platform_device madc_hwmon = {
1267 .name = "twl4030_madc_hwmon",
1268 .id = -1,
1269};
1270
1271static void __init rx51_init_twl4030_hwmon(void)
1272{
1273 platform_device_register(&madc_hwmon);
1274}
1275
1276static struct platform_device omap3_rom_rng_device = {
1277 .name = "omap3-rom-rng",
1278 .id = -1,
1279 .dev = {
1280 .platform_data = rx51_secure_rng_call,
1281 },
1282};
1283
1284static void __init rx51_init_omap3_rom_rng(void)
1285{
1286 if (omap_type() == OMAP2_DEVICE_TYPE_SEC) {
1287 pr_info("RX-51: Registering OMAP3 HWRNG device\n");
1288 platform_device_register(&omap3_rom_rng_device);
1289 }
1290}
1291
1292void __init rx51_peripherals_init(void)
1293{
1294 rx51_gpio_init();
1295 rx51_i2c_init();
1296 regulator_has_full_constraints();
1297 gpmc_onenand_init(board_onenand_data);
1298 rx51_add_gpio_keys();
1299 rx51_init_wl1251();
1300 rx51_init_tsc2005();
1301 rx51_init_lirc();
1302 spi_register_board_info(rx51_peripherals_spi_board_info,
1303 ARRAY_SIZE(rx51_peripherals_spi_board_info));
1304
1305 partition = omap_mux_get("core");
1306 if (partition)
1307 omap_hsmmc_init(mmc);
1308
1309 rx51_charger_init();
1310 rx51_init_twl4030_hwmon();
1311 rx51_init_omap3_rom_rng();
1312}
1313
diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c
deleted file mode 100644
index 180c6aa633bd..000000000000
--- a/arch/arm/mach-omap2/board-rx51-video.c
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/board-rx51-video.c
3 *
4 * Copyright (C) 2010 Nokia
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/gpio.h>
15#include <linux/spi/spi.h>
16#include <linux/mm.h>
17#include <asm/mach-types.h>
18#include <linux/platform_data/omapdss.h>
19#include <video/omap-panel-data.h>
20
21#include <linux/platform_data/spi-omap2-mcspi.h>
22
23#include "soc.h"
24#include "board-rx51.h"
25#include "display.h"
26
27#include "mux.h"
28
29#define RX51_LCD_RESET_GPIO 90
30
31#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
32
33static struct connector_atv_platform_data rx51_tv_pdata = {
34 .name = "tv",
35 .source = "venc.0",
36 .invert_polarity = false,
37};
38
39static struct platform_device rx51_tv_connector_device = {
40 .name = "connector-analog-tv",
41 .id = 0,
42 .dev.platform_data = &rx51_tv_pdata,
43};
44
45static struct omap_dss_board_info rx51_dss_board_info = {
46 .default_display_name = "lcd",
47};
48
49static int __init rx51_video_init(void)
50{
51 if (!machine_is_nokia_rx51())
52 return 0;
53
54 if (omap_mux_init_gpio(RX51_LCD_RESET_GPIO, OMAP_PIN_OUTPUT)) {
55 pr_err("%s cannot configure MUX for LCD RESET\n", __func__);
56 return 0;
57 }
58
59 omap_display_init(&rx51_dss_board_info);
60
61 platform_device_register(&rx51_tv_connector_device);
62
63 return 0;
64}
65
66omap_subsys_initcall(rx51_video_init);
67#endif /* defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) */
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
deleted file mode 100644
index 41161ca97d74..000000000000
--- a/arch/arm/mach-omap2/board-rx51.c
+++ /dev/null
@@ -1,141 +0,0 @@
1/*
2 * Board support file for Nokia N900 (aka RX-51).
3 *
4 * Copyright (C) 2007, 2008 Nokia
5 * Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg>
6 * Copyright (C) 2013 Pali Rohár <pali.rohar@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17#include <linux/err.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20#include <linux/gpio.h>
21#include <linux/leds.h>
22#include <linux/usb/phy.h>
23#include <linux/usb/musb.h>
24#include <linux/platform_data/spi-omap2-mcspi.h>
25
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29
30#include <linux/omap-dma.h>
31
32#include "common.h"
33#include "mux.h"
34#include "gpmc.h"
35#include "pm.h"
36#include "soc.h"
37#include "sdram-nokia.h"
38#include "omap-secure.h"
39
40#define RX51_GPIO_SLEEP_IND 162
41
42static struct gpio_led gpio_leds[] = {
43 {
44 .name = "sleep_ind",
45 .gpio = RX51_GPIO_SLEEP_IND,
46 },
47};
48
49static struct gpio_led_platform_data gpio_led_info = {
50 .leds = gpio_leds,
51 .num_leds = ARRAY_SIZE(gpio_leds),
52};
53
54static struct platform_device leds_gpio = {
55 .name = "leds-gpio",
56 .id = -1,
57 .dev = {
58 .platform_data = &gpio_led_info,
59 },
60};
61
62/*
63 * cpuidle C-states definition for rx51.
64 *
65 * The 'exit_latency' field is the sum of sleep
66 * and wake-up latencies.
67
68 ---------------------------------------------
69 | state | exit_latency | target_residency |
70 ---------------------------------------------
71 | C1 | 110 + 162 | 5 |
72 | C2 | 106 + 180 | 309 |
73 | C3 | 107 + 410 | 46057 |
74 | C4 | 121 + 3374 | 46057 |
75 | C5 | 855 + 1146 | 46057 |
76 | C6 | 7580 + 4134 | 484329 |
77 | C7 | 7505 + 15274 | 484329 |
78 ---------------------------------------------
79
80*/
81
82extern void __init rx51_peripherals_init(void);
83
84#ifdef CONFIG_OMAP_MUX
85static struct omap_board_mux board_mux[] __initdata = {
86 { .reg_offset = OMAP_MUX_TERMINATOR },
87};
88#endif
89
90static struct omap_musb_board_data musb_board_data = {
91 .interface_type = MUSB_INTERFACE_ULPI,
92 .mode = MUSB_OTG,
93 .power = 0,
94};
95
96static void __init rx51_init(void)
97{
98 struct omap_sdrc_params *sdrc_params;
99
100 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
101 omap_serial_init();
102
103 sdrc_params = nokia_get_sdram_timings();
104 omap_sdrc_init(sdrc_params, sdrc_params);
105
106 usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
107 usb_musb_init(&musb_board_data);
108 rx51_peripherals_init();
109
110 if (omap_type() == OMAP2_DEVICE_TYPE_SEC) {
111#ifdef CONFIG_ARM_ERRATA_430973
112 pr_info("RX-51: Enabling ARM errata 430973 workaround\n");
113 /* set IBE to 1 */
114 rx51_secure_update_aux_cr(BIT(6), 0);
115#endif
116 }
117
118 /* Ensure SDRC pins are mux'd for self-refresh */
119 omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
120 omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
121
122 platform_device_register(&leds_gpio);
123}
124
125static void __init rx51_reserve(void)
126{
127 omap_reserve();
128}
129
130MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
131 /* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */
132 .atag_offset = 0x100,
133 .reserve = rx51_reserve,
134 .map_io = omap3_map_io,
135 .init_early = omap3430_init_early,
136 .init_irq = omap3_init_irq,
137 .init_machine = rx51_init,
138 .init_late = omap3430_init_late,
139 .init_time = omap_init_time,
140 .restart = omap3xxx_restart,
141MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rx51.h b/arch/arm/mach-omap2/board-rx51.h
deleted file mode 100644
index b76f49e7eed5..000000000000
--- a/arch/arm/mach-omap2/board-rx51.h
+++ /dev/null
@@ -1,11 +0,0 @@
1/*
2 * Defines for rx51 boards
3 */
4
5#ifndef _OMAP_BOARD_RX51_H
6#define _OMAP_BOARD_RX51_H
7
8extern void __init rx51_peripherals_init(void);
9extern void __init rx51_video_mem_init(void);
10
11#endif
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index d246efd9f734..5388fcd3de72 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -29,8 +29,7 @@
29#include "common.h" 29#include "common.h"
30#include "common-board-devices.h" 30#include "common-board-devices.h"
31 31
32#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ 32#if IS_ENABLED(CONFIG_TOUCHSCREEN_ADS7846)
33 defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
34static struct omap2_mcspi_device_config ads7846_mcspi_config = { 33static struct omap2_mcspi_device_config ads7846_mcspi_config = {
35 .turbo_mode = 0, 34 .turbo_mode = 0,
36}; 35};
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index d7f1d69daf6d..60a20f3b44de 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -67,7 +67,7 @@ omap_postcore_initcall(omap3_l3_init);
67 67
68static inline void omap_init_sti(void) {} 68static inline void omap_init_sti(void) {}
69 69
70#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) 70#if IS_ENABLED(CONFIG_SPI_OMAP24XX)
71 71
72#include <linux/platform_data/spi-omap2-mcspi.h> 72#include <linux/platform_data/spi-omap2-mcspi.h>
73 73
@@ -163,9 +163,8 @@ static void __init omap_init_aes(void)
163 163
164/*-------------------------------------------------------------------------*/ 164/*-------------------------------------------------------------------------*/
165 165
166#if defined(CONFIG_VIDEO_OMAP2_VOUT) || \ 166#if IS_ENABLED(CONFIG_VIDEO_OMAP2_VOUT)
167 defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE) 167#if IS_ENABLED(CONFIG_FB_OMAP2)
168#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
169static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = { 168static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
170}; 169};
171#else 170#else
diff --git a/arch/arm/mach-omap2/drm.c b/arch/arm/mach-omap2/drm.c
index facd7406a03d..44fef961bb70 100644
--- a/arch/arm/mach-omap2/drm.c
+++ b/arch/arm/mach-omap2/drm.c
@@ -28,7 +28,7 @@
28#include "soc.h" 28#include "soc.h"
29#include "display.h" 29#include "display.h"
30 30
31#if defined(CONFIG_DRM_OMAP) || defined(CONFIG_DRM_OMAP_MODULE) 31#if IS_ENABLED(CONFIG_DRM_OMAP)
32 32
33static struct omap_drm_platform_data platform_data; 33static struct omap_drm_platform_data platform_data;
34 34
diff --git a/arch/arm/mach-omap2/fb.c b/arch/arm/mach-omap2/fb.c
index 1f1ecf8807eb..ecd00b63181e 100644
--- a/arch/arm/mach-omap2/fb.c
+++ b/arch/arm/mach-omap2/fb.c
@@ -90,7 +90,7 @@ int __init omap_init_vrfb(void)
90int __init omap_init_vrfb(void) { return 0; } 90int __init omap_init_vrfb(void) { return 0; }
91#endif 91#endif
92 92
93#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) 93#if IS_ENABLED(CONFIG_FB_OMAP2)
94 94
95static u64 omap_fb_dma_mask = ~(u32)0; 95static u64 omap_fb_dma_mask = ~(u32)0;
96static struct omapfb_platform_data omapfb_config; 96static struct omapfb_platform_data omapfb_config;
diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.h b/arch/arm/mach-omap2/gpmc-smsc911x.h
index ea6c9c88c725..99a05b8412fa 100644
--- a/arch/arm/mach-omap2/gpmc-smsc911x.h
+++ b/arch/arm/mach-omap2/gpmc-smsc911x.h
@@ -21,7 +21,7 @@ struct omap_smsc911x_platform_data {
21 u32 flags; 21 u32 flags;
22}; 22};
23 23
24#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) 24#if IS_ENABLED(CONFIG_SMSC911X)
25 25
26extern void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d); 26extern void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d);
27 27
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index cff079e563f4..478097741bce 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -26,7 +26,7 @@
26#include "hsmmc.h" 26#include "hsmmc.h"
27#include "control.h" 27#include "control.h"
28 28
29#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) 29#if IS_ENABLED(CONFIG_MMC_OMAP_HS)
30 30
31static u16 control_pbias_offset; 31static u16 control_pbias_offset;
32static u16 control_devconf1_offset; 32static u16 control_devconf1_offset;
diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h
index 148cd9b15499..69b619ddc765 100644
--- a/arch/arm/mach-omap2/hsmmc.h
+++ b/arch/arm/mach-omap2/hsmmc.h
@@ -28,7 +28,7 @@ struct omap2_hsmmc_info {
28 void (*init_card)(struct mmc_card *card); 28 void (*init_card)(struct mmc_card *card);
29}; 29};
30 30
31#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) 31#if IS_ENABLED(CONFIG_MMC_OMAP_HS)
32 32
33void omap_hsmmc_init(struct omap2_hsmmc_info *); 33void omap_hsmmc_init(struct omap2_hsmmc_info *);
34void omap_hsmmc_late_init(struct omap2_hsmmc_info *); 34void omap_hsmmc_late_init(struct omap2_hsmmc_info *);
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 292eca0e78ed..a72738eab009 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -532,8 +532,7 @@ void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
532} 532}
533#endif /* CONFIG_ARCH_OMAP4 */ 533#endif /* CONFIG_ARCH_OMAP4 */
534 534
535#if defined(CONFIG_SND_OMAP_SOC_OMAP_TWL4030) || \ 535#if IS_ENABLED(CONFIG_SND_OMAP_SOC_OMAP_TWL4030)
536 defined(CONFIG_SND_OMAP_SOC_OMAP_TWL4030_MODULE)
537#include <linux/platform_data/omap-twl4030.h> 536#include <linux/platform_data/omap-twl4030.h>
538 537
539/* Commonly used configuration */ 538/* Commonly used configuration */
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index 70ab4a25a5f8..1d7c83e73ffb 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -2,34 +2,29 @@ menuconfig ARCH_REALVIEW
2 bool "ARM Ltd. RealView family" 2 bool "ARM Ltd. RealView family"
3 depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 || ARCH_MULTI_V7 3 depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 || ARCH_MULTI_V7
4 select ARM_AMBA 4 select ARM_AMBA
5 select ARM_GIC
5 select ARM_TIMER_SP804 6 select ARM_TIMER_SP804
7 select CLK_SP810
6 select COMMON_CLK_VERSATILE 8 select COMMON_CLK_VERSATILE
7 select GPIO_PL061 if GPIOLIB 9 select GPIO_PL061 if GPIOLIB
8 select ICST 10 select HAVE_ARM_SCU if SMP
9 select PLAT_VERSATILE 11 select HAVE_ARM_TWD if SMP
10 select PLAT_VERSATILE_SCHED_CLOCK 12 select HAVE_PATA_PLATFORM
11 help 13 select HAVE_TCM
12 This enables support for ARM Ltd RealView boards.
13
14if ARCH_REALVIEW
15
16config REALVIEW_DT
17 bool "Support RealView(R) Device Tree based boot"
18 select ARM_GIC
19 select CLK_SP810
20 select HAVE_SMP
21 select ICST 14 select ICST
22 select MACH_REALVIEW_EB if ARCH_MULTI_V5 15 select MACH_REALVIEW_EB if ARCH_MULTI_V5
23 select MFD_SYSCON 16 select MFD_SYSCON
17 select PLAT_VERSATILE
18 select PLAT_VERSATILE_SCHED_CLOCK
24 select POWER_RESET 19 select POWER_RESET
25 select POWER_RESET_VERSATILE 20 select POWER_RESET_VERSATILE
26 select POWER_SUPPLY 21 select POWER_SUPPLY
27 select SMP_ON_UP if SMP
28 select SOC_REALVIEW 22 select SOC_REALVIEW
29 select USE_OF 23 select USE_OF
30 help 24 help
31 Include support for booting the ARM(R) RealView(R) evaluation 25 This enables support for ARM Ltd RealView boards.
32 boards using a device tree machine description. 26
27if ARCH_REALVIEW
33 28
34config MACH_REALVIEW_EB 29config MACH_REALVIEW_EB
35 bool "Support RealView(R) Emulation Baseboard" 30 bool "Support RealView(R) Emulation Baseboard"
@@ -60,8 +55,6 @@ config REALVIEW_EB_ARM1176
60config REALVIEW_EB_A9MP 55config REALVIEW_EB_A9MP
61 bool "Support Multicore Cortex-A9 Tile" 56 bool "Support Multicore Cortex-A9 Tile"
62 depends on MACH_REALVIEW_EB && ARCH_MULTI_V7 57 depends on MACH_REALVIEW_EB && ARCH_MULTI_V7
63 select HAVE_ARM_SCU if SMP
64 select HAVE_ARM_TWD if SMP
65 select HAVE_SMP 58 select HAVE_SMP
66 select MIGHT_HAVE_CACHE_L2X0 59 select MIGHT_HAVE_CACHE_L2X0
67 help 60 help
@@ -71,30 +64,15 @@ config REALVIEW_EB_A9MP
71config REALVIEW_EB_ARM11MP 64config REALVIEW_EB_ARM11MP
72 bool "Support ARM11MPCore Tile" 65 bool "Support ARM11MPCore Tile"
73 depends on MACH_REALVIEW_EB && ARCH_MULTI_V6 66 depends on MACH_REALVIEW_EB && ARCH_MULTI_V6
74 select HAVE_ARM_SCU if SMP
75 select HAVE_ARM_TWD if SMP
76 select HAVE_SMP 67 select HAVE_SMP
77 select MIGHT_HAVE_CACHE_L2X0 68 select MIGHT_HAVE_CACHE_L2X0
78 help 69 help
79 Enable support for the ARM11MPCore tile fitted to the Realview(R) 70 Enable support for the ARM11MPCore tile fitted to the Realview(R)
80 Emulation Baseboard platform. 71 Emulation Baseboard platform.
81 72
82config REALVIEW_EB_ARM11MP_REVB
83 bool "Support ARM11MPCore RevB Tile"
84 depends on REALVIEW_EB_ARM11MP && ARCH_MULTI_V6
85 help
86 Enable support for the ARM11MPCore Revision B tile on the
87 Realview(R) Emulation Baseboard platform. Since there are device
88 address differences, a kernel built with this option enabled is
89 not compatible with other revisions of the ARM11MPCore tile.
90
91config MACH_REALVIEW_PB11MP 73config MACH_REALVIEW_PB11MP
92 bool "Support RealView(R) Platform Baseboard for ARM11MPCore" 74 bool "Support RealView(R) Platform Baseboard for ARM11MPCore"
93 depends on ARCH_MULTI_V6 75 depends on ARCH_MULTI_V6
94 select ARM_GIC
95 select HAVE_ARM_SCU if SMP
96 select HAVE_ARM_TWD if SMP
97 select HAVE_PATA_PLATFORM
98 select HAVE_SMP 76 select HAVE_SMP
99 select MIGHT_HAVE_CACHE_L2X0 77 select MIGHT_HAVE_CACHE_L2X0
100 help 78 help
@@ -106,7 +84,6 @@ config MACH_REALVIEW_PB11MP
106config MACH_REALVIEW_PB1176 84config MACH_REALVIEW_PB1176
107 bool "Support RealView(R) Platform Baseboard for ARM1176JZF-S" 85 bool "Support RealView(R) Platform Baseboard for ARM1176JZF-S"
108 depends on ARCH_MULTI_V6 86 depends on ARCH_MULTI_V6
109 select ARM_GIC
110 select CPU_V6 87 select CPU_V6
111 select HAVE_TCM 88 select HAVE_TCM
112 select MIGHT_HAVE_CACHE_L2X0 89 select MIGHT_HAVE_CACHE_L2X0
@@ -114,20 +91,9 @@ config MACH_REALVIEW_PB1176
114 Include support for the ARM(R) RealView(R) Platform Baseboard for 91 Include support for the ARM(R) RealView(R) Platform Baseboard for
115 ARM1176JZF-S. 92 ARM1176JZF-S.
116 93
117config REALVIEW_PB1176_SECURE_FLASH
118 bool "Allow access to the secure flash memory block"
119 depends on MACH_REALVIEW_PB1176
120 default n
121 help
122 Select this option if Linux will only run in secure mode on the
123 RealView PB1176 platform and access to the secure flash memory
124 block (64MB @ 0x3c000000) is required.
125
126config MACH_REALVIEW_PBA8 94config MACH_REALVIEW_PBA8
127 bool "Support RealView(R) Platform Baseboard for Cortex(tm)-A8 platform" 95 bool "Support RealView(R) Platform Baseboard for Cortex(tm)-A8 platform"
128 depends on ARCH_MULTI_V7 96 depends on ARCH_MULTI_V7
129 select ARM_GIC
130 select HAVE_PATA_PLATFORM
131 help 97 help
132 Include support for the ARM(R) RealView Platform Baseboard for 98 Include support for the ARM(R) RealView Platform Baseboard for
133 Cortex(tm)-A8. This platform has an on-board Cortex-A8 and has 99 Cortex(tm)-A8. This platform has an on-board Cortex-A8 and has
@@ -136,10 +102,6 @@ config MACH_REALVIEW_PBA8
136config MACH_REALVIEW_PBX 102config MACH_REALVIEW_PBX
137 bool "Support RealView(R) Platform Baseboard Explore for Cortex-A9" 103 bool "Support RealView(R) Platform Baseboard Explore for Cortex-A9"
138 depends on ARCH_MULTI_V7 104 depends on ARCH_MULTI_V7
139 select ARM_GIC
140 select HAVE_ARM_SCU if SMP
141 select HAVE_ARM_TWD if SMP
142 select HAVE_PATA_PLATFORM
143 select HAVE_SMP 105 select HAVE_SMP
144 select MIGHT_HAVE_CACHE_L2X0 106 select MIGHT_HAVE_CACHE_L2X0
145 select ZONE_DMA 107 select ZONE_DMA
@@ -147,16 +109,4 @@ config MACH_REALVIEW_PBX
147 Include support for the ARM(R) RealView(R) Platform Baseboard 109 Include support for the ARM(R) RealView(R) Platform Baseboard
148 Explore. 110 Explore.
149 111
150config REALVIEW_HIGH_PHYS_OFFSET
151 bool "High physical base address for the RealView platform"
152 depends on MMU && !MACH_REALVIEW_PB1176
153 default y
154 help
155 RealView boards other than PB1176 have the RAM available at
156 0x70000000, 256MB of which being mirrored at 0x00000000. If
157 the board supports 512MB of RAM, this option allows the
158 memory to be accessed contiguously at the high physical
159 offset. On the PBX board, disabling this option allows 1GB of
160 RAM to be used with HIGHMEM.
161
162endif 112endif
diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile
index 404882130956..adf39ad71cc3 100644
--- a/arch/arm/mach-realview/Makefile
+++ b/arch/arm/mach-realview/Makefile
@@ -3,16 +3,6 @@
3# 3#
4ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-versatile/include 4ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-versatile/include
5 5
6obj-y := core.o 6obj-y += realview-dt.o
7obj-$(CONFIG_REALVIEW_DT) += realview-dt.o
8obj-$(CONFIG_SMP) += platsmp-dt.o 7obj-$(CONFIG_SMP) += platsmp-dt.o
9
10ifdef CONFIG_ATAGS
11obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o
12obj-$(CONFIG_MACH_REALVIEW_PB11MP) += realview_pb11mp.o
13obj-$(CONFIG_MACH_REALVIEW_PB1176) += realview_pb1176.o
14obj-$(CONFIG_MACH_REALVIEW_PBA8) += realview_pba8.o
15obj-$(CONFIG_MACH_REALVIEW_PBX) += realview_pbx.o
16obj-$(CONFIG_SMP) += platsmp.o
17endif
18obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 8obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-realview/board-eb.h b/arch/arm/mach-realview/board-eb.h
deleted file mode 100644
index a850ae6945b0..000000000000
--- a/arch/arm/mach-realview/board-eb.h
+++ /dev/null
@@ -1,94 +0,0 @@
1/*
2 * Copyright (C) 2007 ARM Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef __ASM_ARCH_BOARD_EB_H
20#define __ASM_ARCH_BOARD_EB_H
21
22#include "platform.h"
23
24/*
25 * RealView EB + ARM11MPCore peripheral addresses
26 */
27#define REALVIEW_EB_UART0_BASE 0x10009000 /* UART 0 */
28#define REALVIEW_EB_UART1_BASE 0x1000A000 /* UART 1 */
29#define REALVIEW_EB_UART2_BASE 0x1000B000 /* UART 2 */
30#define REALVIEW_EB_UART3_BASE 0x1000C000 /* UART 3 */
31#define REALVIEW_EB_SSP_BASE 0x1000D000 /* Synchronous Serial Port */
32#define REALVIEW_EB_WATCHDOG_BASE 0x10010000 /* watchdog interface */
33#define REALVIEW_EB_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */
34#define REALVIEW_EB_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */
35#define REALVIEW_EB_GPIO0_BASE 0x10013000 /* GPIO port 0 */
36#define REALVIEW_EB_RTC_BASE 0x10017000 /* Real Time Clock */
37#define REALVIEW_EB_CLCD_BASE 0x10020000 /* CLCD */
38#define REALVIEW_EB_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
39#define REALVIEW_EB_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
40#define REALVIEW_EB_SMC_BASE 0x10080000 /* Static memory controller */
41
42#define REALVIEW_EB_FLASH_BASE 0x40000000
43#define REALVIEW_EB_FLASH_SIZE SZ_64M
44#define REALVIEW_EB_ETH_BASE 0x4E000000 /* Ethernet */
45#define REALVIEW_EB_USB_BASE 0x4F000000 /* USB */
46
47#ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB
48#define REALVIEW_EB11MP_PRIV_MEM_BASE 0x10100000
49#define REALVIEW_EB11MP_L220_BASE 0x10102000 /* L220 registers */
50#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
51#else
52#define REALVIEW_EB11MP_PRIV_MEM_BASE 0x1F000000
53#define REALVIEW_EB11MP_L220_BASE 0x1F002000 /* L220 registers */
54#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
55#endif
56
57#define REALVIEW_EB11MP_PRIV_MEM_SIZE SZ_8K
58#define REALVIEW_EB11MP_PRIV_MEM_OFF(x) (REALVIEW_EB11MP_PRIV_MEM_BASE + (x))
59
60#define REALVIEW_EB11MP_SCU_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0) /* SCU registers */
61#define REALVIEW_EB11MP_GIC_CPU_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x0100) /* Generic interrupt controller CPU interface */
62#define REALVIEW_EB11MP_TWD_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x0600)
63#define REALVIEW_EB11MP_GIC_DIST_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x1000) /* Generic interrupt controller distributor */
64
65/*
66 * Core tile identification (REALVIEW_SYS_PROCID)
67 */
68#define REALVIEW_EB_PROC_MASK 0xFF000000
69#define REALVIEW_EB_PROC_ARM7TDMI 0x00000000
70#define REALVIEW_EB_PROC_ARM9 0x02000000
71#define REALVIEW_EB_PROC_ARM11 0x04000000
72#define REALVIEW_EB_PROC_ARM11MP 0x06000000
73#define REALVIEW_EB_PROC_A9MP 0x0C000000
74
75#define check_eb_proc(proc_type) \
76 ((readl(__io_address(REALVIEW_SYS_PROCID)) & REALVIEW_EB_PROC_MASK) \
77 == proc_type)
78
79#ifdef CONFIG_REALVIEW_EB_ARM11MP
80#define core_tile_eb11mp() check_eb_proc(REALVIEW_EB_PROC_ARM11MP)
81#else
82#define core_tile_eb11mp() 0
83#endif
84
85#ifdef CONFIG_REALVIEW_EB_A9MP
86#define core_tile_a9mp() check_eb_proc(REALVIEW_EB_PROC_A9MP)
87#else
88#define core_tile_a9mp() 0
89#endif
90
91#define machine_is_realview_eb_mp() \
92 (machine_is_realview_eb() && (core_tile_eb11mp() || core_tile_a9mp()))
93
94#endif /* __ASM_ARCH_BOARD_EB_H */
diff --git a/arch/arm/mach-realview/board-pb1176.h b/arch/arm/mach-realview/board-pb1176.h
deleted file mode 100644
index 29c04a9e1344..000000000000
--- a/arch/arm/mach-realview/board-pb1176.h
+++ /dev/null
@@ -1,81 +0,0 @@
1/*
2 * Copyright (C) 2008 ARM Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef __ASM_ARCH_BOARD_PB1176_H
20#define __ASM_ARCH_BOARD_PB1176_H
21
22#include "platform.h"
23
24/*
25 * Peripheral addresses
26 */
27#define REALVIEW_PB1176_UART4_BASE 0x10009000 /* UART 4 */
28#define REALVIEW_PB1176_SCTL_BASE 0x10100000 /* System controller */
29#define REALVIEW_PB1176_SMC_BASE 0x10111000 /* SMC */
30#define REALVIEW_PB1176_DMC_BASE 0x10109000 /* DMC configuration */
31#define REALVIEW_PB1176_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */
32#define REALVIEW_PB1176_FLASH_BASE 0x30000000
33#define REALVIEW_PB1176_FLASH_SIZE SZ_64M
34#define REALVIEW_PB1176_SEC_FLASH_BASE 0x3C000000 /* Secure flash */
35#define REALVIEW_PB1176_SEC_FLASH_SIZE SZ_64M
36
37#define REALVIEW_PB1176_TIMER0_1_BASE 0x10104000 /* Timer 0 and 1 */
38#define REALVIEW_PB1176_TIMER2_3_BASE 0x10105000 /* Timer 2 and 3 */
39#define REALVIEW_PB1176_TIMER4_5_BASE 0x10106000 /* Timer 4 and 5 */
40#define REALVIEW_PB1176_WATCHDOG_BASE 0x10107000 /* watchdog interface */
41#define REALVIEW_PB1176_RTC_BASE 0x10108000 /* Real Time Clock */
42#define REALVIEW_PB1176_GPIO0_BASE 0x1010A000 /* GPIO port 0 */
43#define REALVIEW_PB1176_SSP_BASE 0x1010B000 /* Synchronous Serial Port */
44#define REALVIEW_PB1176_UART0_BASE 0x1010C000 /* UART 0 */
45#define REALVIEW_PB1176_UART1_BASE 0x1010D000 /* UART 1 */
46#define REALVIEW_PB1176_UART2_BASE 0x1010E000 /* UART 2 */
47#define REALVIEW_PB1176_UART3_BASE 0x1010F000 /* UART 3 */
48#define REALVIEW_PB1176_CLCD_BASE 0x10112000 /* CLCD */
49#define REALVIEW_PB1176_ETH_BASE 0x3A000000 /* Ethernet */
50#define REALVIEW_PB1176_USB_BASE 0x3B000000 /* USB */
51
52/*
53 * PCI regions
54 */
55#define REALVIEW_PB1176_PCI_BASE 0x60000000 /* PCI self config */
56#define REALVIEW_PB1176_PCI_CFG_BASE 0x61000000 /* PCI config */
57#define REALVIEW_PB1176_PCI_IO_BASE0 0x62000000 /* PCI IO region */
58#define REALVIEW_PB1176_PCI_MEM_BASE0 0x63000000 /* Memory region 1 */
59#define REALVIEW_PB1176_PCI_MEM_BASE1 0x64000000 /* Memory region 2 */
60#define REALVIEW_PB1176_PCI_MEM_BASE2 0x68000000 /* Memory region 3 */
61
62#define REALVIEW_PB1176_PCI_BASE_SIZE 0x01000000 /* 16MB */
63#define REALVIEW_PB1176_PCI_CFG_BASE_SIZE 0x01000000 /* 16MB */
64#define REALVIEW_PB1176_PCI_IO_BASE0_SIZE 0x01000000 /* 16MB */
65#define REALVIEW_PB1176_PCI_MEM_BASE0_SIZE 0x01000000 /* 16MB */
66#define REALVIEW_PB1176_PCI_MEM_BASE1_SIZE 0x04000000 /* 64MB */
67#define REALVIEW_PB1176_PCI_MEM_BASE2_SIZE 0x08000000 /* 128MB */
68
69#define REALVIEW_DC1176_GIC_CPU_BASE 0x10120000 /* GIC CPU interface, on devchip */
70#define REALVIEW_DC1176_GIC_DIST_BASE 0x10121000 /* GIC distributor, on devchip */
71#define REALVIEW_DC1176_ROM_BASE 0x10200000 /* 16KiB NRAM preudo-ROM, on devchip */
72#define REALVIEW_PB1176_GIC_CPU_BASE 0x10040000 /* GIC CPU interface, on FPGA */
73#define REALVIEW_PB1176_GIC_DIST_BASE 0x10041000 /* GIC distributor, on FPGA */
74#define REALVIEW_PB1176_L220_BASE 0x10110000 /* L220 registers */
75
76/*
77 * Control register SYS_RESETCTL Bit 8 is set to 1 to force a soft reset
78 */
79#define REALVIEW_PB1176_SYS_SOFT_RESET 0x0100
80
81#endif /* __ASM_ARCH_BOARD_PB1176_H */
diff --git a/arch/arm/mach-realview/board-pb11mp.h b/arch/arm/mach-realview/board-pb11mp.h
deleted file mode 100644
index b16e6e85e92d..000000000000
--- a/arch/arm/mach-realview/board-pb11mp.h
+++ /dev/null
@@ -1,96 +0,0 @@
1/*
2 * Copyright (C) 2008 ARM Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef __ASM_ARCH_BOARD_PB11MP_H
20#define __ASM_ARCH_BOARD_PB11MP_H
21
22#include "platform.h"
23
24/*
25 * Peripheral addresses
26 */
27#define REALVIEW_PB11MP_UART0_BASE 0x10009000 /* UART 0 */
28#define REALVIEW_PB11MP_UART1_BASE 0x1000A000 /* UART 1 */
29#define REALVIEW_PB11MP_UART2_BASE 0x1000B000 /* UART 2 */
30#define REALVIEW_PB11MP_UART3_BASE 0x1000C000 /* UART 3 */
31#define REALVIEW_PB11MP_SSP_BASE 0x1000D000 /* Synchronous Serial Port */
32#define REALVIEW_PB11MP_WATCHDOG0_BASE 0x1000F000 /* Watchdog 0 */
33#define REALVIEW_PB11MP_WATCHDOG_BASE 0x10010000 /* watchdog interface */
34#define REALVIEW_PB11MP_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */
35#define REALVIEW_PB11MP_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */
36#define REALVIEW_PB11MP_GPIO0_BASE 0x10013000 /* GPIO port 0 */
37#define REALVIEW_PB11MP_RTC_BASE 0x10017000 /* Real Time Clock */
38#define REALVIEW_PB11MP_TIMER4_5_BASE 0x10018000 /* Timer 4/5 */
39#define REALVIEW_PB11MP_TIMER6_7_BASE 0x10019000 /* Timer 6/7 */
40#define REALVIEW_PB11MP_SCTL_BASE 0x1001A000 /* System Controller */
41#define REALVIEW_PB11MP_CLCD_BASE 0x10020000 /* CLCD */
42#define REALVIEW_PB11MP_ONB_SRAM_BASE 0x10060000 /* On-board SRAM */
43#define REALVIEW_PB11MP_DMC_BASE 0x100E0000 /* DMC configuration */
44#define REALVIEW_PB11MP_SMC_BASE 0x100E1000 /* SMC configuration */
45#define REALVIEW_PB11MP_CAN_BASE 0x100E2000 /* CAN bus */
46#define REALVIEW_PB11MP_CF_BASE 0x18000000 /* Compact flash */
47#define REALVIEW_PB11MP_CF_MEM_BASE 0x18003000 /* SMC for Compact flash */
48#define REALVIEW_PB11MP_GIC_CPU_BASE 0x1E000000 /* Generic interrupt controller CPU interface */
49#define REALVIEW_PB11MP_FLASH0_BASE 0x40000000
50#define REALVIEW_PB11MP_FLASH0_SIZE SZ_64M
51#define REALVIEW_PB11MP_FLASH1_BASE 0x44000000
52#define REALVIEW_PB11MP_FLASH1_SIZE SZ_64M
53#define REALVIEW_PB11MP_ETH_BASE 0x4E000000 /* Ethernet */
54#define REALVIEW_PB11MP_USB_BASE 0x4F000000 /* USB */
55#define REALVIEW_PB11MP_GIC_DIST_BASE 0x1E001000 /* Generic interrupt controller distributor */
56#define REALVIEW_PB11MP_LT_BASE 0xC0000000 /* Logic Tile expansion */
57#define REALVIEW_PB11MP_SDRAM6_BASE 0x70000000 /* SDRAM bank 6 256MB */
58#define REALVIEW_PB11MP_SDRAM7_BASE 0x80000000 /* SDRAM bank 7 256MB */
59
60#define REALVIEW_PB11MP_SYS_PLD_CTRL1 0x74
61
62/*
63 * PB11MPCore PCI regions
64 */
65#define REALVIEW_PB11MP_PCI_BASE 0x90040000 /* PCI-X Unit base */
66#define REALVIEW_PB11MP_PCI_IO_BASE 0x90050000 /* IO Region on AHB */
67#define REALVIEW_PB11MP_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */
68
69#define REALVIEW_PB11MP_PCI_BASE_SIZE 0x10000 /* 16 Kb */
70#define REALVIEW_PB11MP_PCI_IO_SIZE 0x1000 /* 4 Kb */
71#define REALVIEW_PB11MP_PCI_MEM_SIZE 0x20000000 /* 512 MB */
72
73/*
74 * Testchip peripheral and fpga gic regions
75 */
76#define REALVIEW_TC11MP_PRIV_MEM_BASE 0x1F000000
77#define REALVIEW_TC11MP_PRIV_MEM_SIZE SZ_8K
78#define REALVIEW_TC11MP_SCU_BASE 0x1F000000 /* IRQ, Test chip */
79#define REALVIEW_TC11MP_GIC_CPU_BASE 0x1F000100 /* Test chip interrupt controller CPU interface */
80#define REALVIEW_TC11MP_TWD_BASE 0x1F000600
81#define REALVIEW_TC11MP_GIC_DIST_BASE 0x1F001000 /* Test chip interrupt controller distributor */
82#define REALVIEW_TC11MP_L220_BASE 0x1F002000 /* L220 registers */
83
84 /*
85 * Values for REALVIEW_SYS_RESET_CTRL
86 */
87#define REALVIEW_PB11MP_SYS_CTRL_RESET_CONFIGCLR 0x01
88#define REALVIEW_PB11MP_SYS_CTRL_RESET_CONFIGINIT 0x02
89#define REALVIEW_PB11MP_SYS_CTRL_RESET_DLLRESET 0x03
90#define REALVIEW_PB11MP_SYS_CTRL_RESET_PLLRESET 0x04
91#define REALVIEW_PB11MP_SYS_CTRL_RESET_POR 0x05
92#define REALVIEW_PB11MP_SYS_CTRL_RESET_DoC 0x06
93
94#define REALVIEW_PB11MP_SYS_CTRL_LED (1 << 0)
95
96#endif /* __ASM_ARCH_BOARD_PB11MP_H */
diff --git a/arch/arm/mach-realview/board-pba8.h b/arch/arm/mach-realview/board-pba8.h
deleted file mode 100644
index 6a1391f50373..000000000000
--- a/arch/arm/mach-realview/board-pba8.h
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * Copyright (C) 2008 ARM Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef __ASM_ARCH_BOARD_PBA8_H
20#define __ASM_ARCH_BOARD_PBA8_H
21
22#include "platform.h"
23
24/*
25 * Peripheral addresses
26 */
27#define REALVIEW_PBA8_UART0_BASE 0x10009000 /* UART 0 */
28#define REALVIEW_PBA8_UART1_BASE 0x1000A000 /* UART 1 */
29#define REALVIEW_PBA8_UART2_BASE 0x1000B000 /* UART 2 */
30#define REALVIEW_PBA8_UART3_BASE 0x1000C000 /* UART 3 */
31#define REALVIEW_PBA8_SSP_BASE 0x1000D000 /* Synchronous Serial Port */
32#define REALVIEW_PBA8_WATCHDOG0_BASE 0x1000F000 /* Watchdog 0 */
33#define REALVIEW_PBA8_WATCHDOG_BASE 0x10010000 /* watchdog interface */
34#define REALVIEW_PBA8_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */
35#define REALVIEW_PBA8_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */
36#define REALVIEW_PBA8_GPIO0_BASE 0x10013000 /* GPIO port 0 */
37#define REALVIEW_PBA8_RTC_BASE 0x10017000 /* Real Time Clock */
38#define REALVIEW_PBA8_TIMER4_5_BASE 0x10018000 /* Timer 4/5 */
39#define REALVIEW_PBA8_TIMER6_7_BASE 0x10019000 /* Timer 6/7 */
40#define REALVIEW_PBA8_SCTL_BASE 0x1001A000 /* System Controller */
41#define REALVIEW_PBA8_CLCD_BASE 0x10020000 /* CLCD */
42#define REALVIEW_PBA8_ONB_SRAM_BASE 0x10060000 /* On-board SRAM */
43#define REALVIEW_PBA8_DMC_BASE 0x100E0000 /* DMC configuration */
44#define REALVIEW_PBA8_SMC_BASE 0x100E1000 /* SMC configuration */
45#define REALVIEW_PBA8_CAN_BASE 0x100E2000 /* CAN bus */
46#define REALVIEW_PBA8_GIC_CPU_BASE 0x1E000000 /* Generic interrupt controller CPU interface */
47#define REALVIEW_PBA8_FLASH0_BASE 0x40000000
48#define REALVIEW_PBA8_FLASH0_SIZE SZ_64M
49#define REALVIEW_PBA8_FLASH1_BASE 0x44000000
50#define REALVIEW_PBA8_FLASH1_SIZE SZ_64M
51#define REALVIEW_PBA8_ETH_BASE 0x4E000000 /* Ethernet */
52#define REALVIEW_PBA8_USB_BASE 0x4F000000 /* USB */
53#define REALVIEW_PBA8_GIC_DIST_BASE 0x1E001000 /* Generic interrupt controller distributor */
54#define REALVIEW_PBA8_LT_BASE 0xC0000000 /* Logic Tile expansion */
55#define REALVIEW_PBA8_SDRAM6_BASE 0x70000000 /* SDRAM bank 6 256MB */
56#define REALVIEW_PBA8_SDRAM7_BASE 0x80000000 /* SDRAM bank 7 256MB */
57
58#define REALVIEW_PBA8_SYS_PLD_CTRL1 0x74
59
60/*
61 * PBA8 PCI regions
62 */
63#define REALVIEW_PBA8_PCI_BASE 0x90040000 /* PCI-X Unit base */
64#define REALVIEW_PBA8_PCI_IO_BASE 0x90050000 /* IO Region on AHB */
65#define REALVIEW_PBA8_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */
66
67#define REALVIEW_PBA8_PCI_BASE_SIZE 0x10000 /* 16 Kb */
68#define REALVIEW_PBA8_PCI_IO_SIZE 0x1000 /* 4 Kb */
69#define REALVIEW_PBA8_PCI_MEM_SIZE 0x20000000 /* 512 MB */
70
71#endif /* __ASM_ARCH_BOARD_PBA8_H */
diff --git a/arch/arm/mach-realview/board-pbx.h b/arch/arm/mach-realview/board-pbx.h
deleted file mode 100644
index 5cda480b12bb..000000000000
--- a/arch/arm/mach-realview/board-pbx.h
+++ /dev/null
@@ -1,106 +0,0 @@
1/*
2 * Copyright (C) 2009 ARM Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18#ifndef __ASM_ARCH_BOARD_PBX_H
19#define __ASM_ARCH_BOARD_PBX_H
20
21#include "platform.h"
22
23/*
24 * Peripheral addresses
25 */
26#define REALVIEW_PBX_UART0_BASE 0x10009000 /* UART 0 */
27#define REALVIEW_PBX_UART1_BASE 0x1000A000 /* UART 1 */
28#define REALVIEW_PBX_UART2_BASE 0x1000B000 /* UART 2 */
29#define REALVIEW_PBX_UART3_BASE 0x1000C000 /* UART 3 */
30#define REALVIEW_PBX_SSP_BASE 0x1000D000 /* Synchronous Serial Port */
31#define REALVIEW_PBX_WATCHDOG0_BASE 0x1000F000 /* Watchdog 0 */
32#define REALVIEW_PBX_WATCHDOG_BASE 0x10010000 /* watchdog interface */
33#define REALVIEW_PBX_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */
34#define REALVIEW_PBX_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */
35#define REALVIEW_PBX_GPIO0_BASE 0x10013000 /* GPIO port 0 */
36#define REALVIEW_PBX_RTC_BASE 0x10017000 /* Real Time Clock */
37#define REALVIEW_PBX_TIMER4_5_BASE 0x10018000 /* Timer 4/5 */
38#define REALVIEW_PBX_TIMER6_7_BASE 0x10019000 /* Timer 6/7 */
39#define REALVIEW_PBX_SCTL_BASE 0x1001A000 /* System Controller */
40#define REALVIEW_PBX_CLCD_BASE 0x10020000 /* CLCD */
41#define REALVIEW_PBX_ONB_SRAM_BASE 0x10060000 /* On-board SRAM */
42#define REALVIEW_PBX_DMC_BASE 0x100E0000 /* DMC configuration */
43#define REALVIEW_PBX_SMC_BASE 0x100E1000 /* SMC configuration */
44#define REALVIEW_PBX_CAN_BASE 0x100E2000 /* CAN bus */
45#define REALVIEW_PBX_GIC_CPU_BASE 0x1E000000 /* Generic interrupt controller CPU interface */
46#define REALVIEW_PBX_FLASH0_BASE 0x40000000
47#define REALVIEW_PBX_FLASH0_SIZE SZ_64M
48#define REALVIEW_PBX_FLASH1_BASE 0x44000000
49#define REALVIEW_PBX_FLASH1_SIZE SZ_64M
50#define REALVIEW_PBX_ETH_BASE 0x4E000000 /* Ethernet */
51#define REALVIEW_PBX_USB_BASE 0x4F000000 /* USB */
52#define REALVIEW_PBX_GIC_DIST_BASE 0x1E001000 /* Generic interrupt controller distributor */
53#define REALVIEW_PBX_LT_BASE 0xC0000000 /* Logic Tile expansion */
54#define REALVIEW_PBX_SDRAM6_BASE 0x70000000 /* SDRAM bank 6 256MB */
55#define REALVIEW_PBX_SDRAM7_BASE 0x80000000 /* SDRAM bank 7 256MB */
56
57/*
58 * Tile-specific addresses
59 */
60#define REALVIEW_PBX_TILE_SCU_BASE 0x1F000000 /* SCU registers */
61#define REALVIEW_PBX_TILE_GIC_CPU_BASE 0x1F000100 /* Private Generic interrupt controller CPU interface */
62#define REALVIEW_PBX_TILE_TWD_BASE 0x1F000600
63#define REALVIEW_PBX_TILE_TWD_PERCPU_BASE 0x1F000700
64#define REALVIEW_PBX_TILE_TWD_SIZE 0x00000100
65#define REALVIEW_PBX_TILE_GIC_DIST_BASE 0x1F001000 /* Private Generic interrupt controller distributor */
66#define REALVIEW_PBX_TILE_L220_BASE 0x1F002000 /* L220 registers */
67
68#define REALVIEW_PBX_SYS_PLD_CTRL1 0x74
69
70/*
71 * PBX PCI regions
72 */
73#define REALVIEW_PBX_PCI_BASE 0x90040000 /* PCI-X Unit base */
74#define REALVIEW_PBX_PCI_IO_BASE 0x90050000 /* IO Region on AHB */
75#define REALVIEW_PBX_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */
76
77#define REALVIEW_PBX_PCI_BASE_SIZE 0x10000 /* 16 Kb */
78#define REALVIEW_PBX_PCI_IO_SIZE 0x1000 /* 4 Kb */
79#define REALVIEW_PBX_PCI_MEM_SIZE 0x20000000 /* 512 MB */
80
81/*
82 * Core tile identification (REALVIEW_SYS_PROCID)
83 */
84#define REALVIEW_PBX_PROC_MASK 0xFF000000
85#define REALVIEW_PBX_PROC_ARM7TDMI 0x00000000
86#define REALVIEW_PBX_PROC_ARM9 0x02000000
87#define REALVIEW_PBX_PROC_ARM11 0x04000000
88#define REALVIEW_PBX_PROC_ARM11MP 0x06000000
89#define REALVIEW_PBX_PROC_A9MP 0x0C000000
90#define REALVIEW_PBX_PROC_A8 0x0E000000
91
92#define check_pbx_proc(proc_type) \
93 ((readl(__io_address(REALVIEW_SYS_PROCID)) & REALVIEW_PBX_PROC_MASK) \
94 == proc_type)
95
96#ifdef CONFIG_MACH_REALVIEW_PBX
97#define core_tile_pbx11mp() check_pbx_proc(REALVIEW_PBX_PROC_ARM11MP)
98#define core_tile_pbxa9mp() check_pbx_proc(REALVIEW_PBX_PROC_A9MP)
99#define core_tile_pbxa8() check_pbx_proc(REALVIEW_PBX_PROC_A8)
100#else
101#define core_tile_pbx11mp() 0
102#define core_tile_pbxa9mp() 0
103#define core_tile_pbxa8() 0
104#endif
105
106#endif /* __ASM_ARCH_BOARD_PBX_H */
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
deleted file mode 100644
index a0ead0ae23d6..000000000000
--- a/arch/arm/mach-realview/core.c
+++ /dev/null
@@ -1,405 +0,0 @@
1/*
2 * linux/arch/arm/mach-realview/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/dma-mapping.h>
24#include <linux/device.h>
25#include <linux/interrupt.h>
26#include <linux/amba/bus.h>
27#include <linux/amba/clcd.h>
28#include <linux/platform_data/video-clcd-versatile.h>
29#include <linux/io.h>
30#include <linux/smsc911x.h>
31#include <linux/smc91x.h>
32#include <linux/ata_platform.h>
33#include <linux/amba/mmci.h>
34#include <linux/gfp.h>
35#include <linux/mtd/physmap.h>
36#include <linux/memblock.h>
37
38#include <clocksource/timer-sp804.h>
39#include "hardware.h"
40#include <asm/irq.h>
41#include <asm/mach-types.h>
42#include <asm/hardware/icst.h>
43
44#include <asm/mach/arch.h>
45#include <asm/mach/irq.h>
46#include <asm/mach/map.h>
47
48#include "platform.h"
49
50#include <plat/sched_clock.h>
51
52#include "core.h"
53
54#define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
55
56static void realview_flash_set_vpp(struct platform_device *pdev, int on)
57{
58 u32 val;
59
60 val = __raw_readl(REALVIEW_FLASHCTRL);
61 if (on)
62 val |= REALVIEW_FLASHPROG_FLVPPEN;
63 else
64 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
65 __raw_writel(val, REALVIEW_FLASHCTRL);
66}
67
68static struct physmap_flash_data realview_flash_data = {
69 .width = 4,
70 .set_vpp = realview_flash_set_vpp,
71};
72
73struct platform_device realview_flash_device = {
74 .name = "physmap-flash",
75 .id = 0,
76 .dev = {
77 .platform_data = &realview_flash_data,
78 },
79};
80
81int realview_flash_register(struct resource *res, u32 num)
82{
83 realview_flash_device.resource = res;
84 realview_flash_device.num_resources = num;
85 return platform_device_register(&realview_flash_device);
86}
87
88static struct smsc911x_platform_config smsc911x_config = {
89 .flags = SMSC911X_USE_32BIT,
90 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
91 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
92 .phy_interface = PHY_INTERFACE_MODE_MII,
93};
94
95static struct smc91x_platdata smc91x_platdata = {
96 .flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT | SMC91X_USE_32BIT |
97 SMC91X_NOWAIT,
98};
99
100static struct platform_device realview_eth_device = {
101 .name = "smsc911x",
102 .id = 0,
103 .num_resources = 2,
104};
105
106int realview_eth_register(const char *name, struct resource *res)
107{
108 if (name)
109 realview_eth_device.name = name;
110 realview_eth_device.resource = res;
111 if (strcmp(realview_eth_device.name, "smsc911x") == 0)
112 realview_eth_device.dev.platform_data = &smsc911x_config;
113 else
114 realview_eth_device.dev.platform_data = &smc91x_platdata;
115
116 return platform_device_register(&realview_eth_device);
117}
118
119struct platform_device realview_usb_device = {
120 .name = "isp1760",
121 .num_resources = 2,
122};
123
124int realview_usb_register(struct resource *res)
125{
126 realview_usb_device.resource = res;
127 return platform_device_register(&realview_usb_device);
128}
129
130static struct pata_platform_info pata_platform_data = {
131 .ioport_shift = 1,
132};
133
134static struct resource pata_resources[] = {
135 [0] = {
136 .start = REALVIEW_CF_BASE,
137 .end = REALVIEW_CF_BASE + 0xff,
138 .flags = IORESOURCE_MEM,
139 },
140 [1] = {
141 .start = REALVIEW_CF_BASE + 0x100,
142 .end = REALVIEW_CF_BASE + SZ_4K - 1,
143 .flags = IORESOURCE_MEM,
144 },
145};
146
147struct platform_device realview_cf_device = {
148 .name = "pata_platform",
149 .id = -1,
150 .num_resources = ARRAY_SIZE(pata_resources),
151 .resource = pata_resources,
152 .dev = {
153 .platform_data = &pata_platform_data,
154 },
155};
156
157static struct resource realview_leds_resources[] = {
158 {
159 .start = REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET,
160 .end = REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET + 4,
161 .flags = IORESOURCE_MEM,
162 },
163};
164
165struct platform_device realview_leds_device = {
166 .name = "versatile-leds",
167 .id = -1,
168 .num_resources = ARRAY_SIZE(realview_leds_resources),
169 .resource = realview_leds_resources,
170};
171
172static struct resource realview_i2c_resource = {
173 .start = REALVIEW_I2C_BASE,
174 .end = REALVIEW_I2C_BASE + SZ_4K - 1,
175 .flags = IORESOURCE_MEM,
176};
177
178struct platform_device realview_i2c_device = {
179 .name = "versatile-i2c",
180 .id = 0,
181 .num_resources = 1,
182 .resource = &realview_i2c_resource,
183};
184
185static struct i2c_board_info realview_i2c_board_info[] = {
186 {
187 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
188 },
189};
190
191static int __init realview_i2c_init(void)
192{
193 return i2c_register_board_info(0, realview_i2c_board_info,
194 ARRAY_SIZE(realview_i2c_board_info));
195}
196arch_initcall(realview_i2c_init);
197
198#define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
199
200/*
201 * This is only used if GPIOLIB support is disabled
202 */
203static unsigned int realview_mmc_status(struct device *dev)
204{
205 struct amba_device *adev = container_of(dev, struct amba_device, dev);
206 u32 mask;
207
208 if (machine_is_realview_pb1176()) {
209 static bool inserted = false;
210
211 /*
212 * The PB1176 does not have the status register,
213 * assume it is inserted at startup, then invert
214 * for each call so card insertion/removal will
215 * be detected anyway. This will not be called if
216 * GPIO on PL061 is active, which is the proper
217 * way to do this on the PB1176.
218 */
219 inserted = !inserted;
220 return inserted ? 0 : 1;
221 }
222
223 if (adev->res.start == REALVIEW_MMCI0_BASE)
224 mask = 1;
225 else
226 mask = 2;
227
228 return readl(REALVIEW_SYSMCI) & mask;
229}
230
231struct mmci_platform_data realview_mmc0_plat_data = {
232 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
233 .status = realview_mmc_status,
234 .gpio_wp = 17,
235 .gpio_cd = 16,
236 .cd_invert = true,
237};
238
239struct mmci_platform_data realview_mmc1_plat_data = {
240 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
241 .status = realview_mmc_status,
242 .gpio_wp = 19,
243 .gpio_cd = 18,
244 .cd_invert = true,
245};
246
247void __init realview_init_early(void)
248{
249 void __iomem *sys = __io_address(REALVIEW_SYS_BASE);
250
251 versatile_sched_clock_init(sys + REALVIEW_SYS_24MHz_OFFSET, 24000000);
252}
253
254/*
255 * CLCD support.
256 */
257#define SYS_CLCD_NLCDIOON (1 << 2)
258#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
259#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
260#define SYS_CLCD_ID_MASK (0x1f << 8)
261#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
262#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
263#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
264#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
265#define SYS_CLCD_ID_VGA (0x1f << 8)
266
267/*
268 * Disable all display connectors on the interface module.
269 */
270static void realview_clcd_disable(struct clcd_fb *fb)
271{
272 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
273 u32 val;
274
275 val = readl(sys_clcd);
276 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
277 writel(val, sys_clcd);
278}
279
280/*
281 * Enable the relevant connector on the interface module.
282 */
283static void realview_clcd_enable(struct clcd_fb *fb)
284{
285 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
286 u32 val;
287
288 /*
289 * Enable the PSUs
290 */
291 val = readl(sys_clcd);
292 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
293 writel(val, sys_clcd);
294}
295
296/*
297 * Detect which LCD panel is connected, and return the appropriate
298 * clcd_panel structure. Note: we do not have any information on
299 * the required timings for the 8.4in panel, so we presently assume
300 * VGA timings.
301 */
302static int realview_clcd_setup(struct clcd_fb *fb)
303{
304 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
305 const char *panel_name, *vga_panel_name;
306 unsigned long framesize;
307 u32 val;
308
309 if (machine_is_realview_eb()) {
310 /* VGA, 16bpp */
311 framesize = 640 * 480 * 2;
312 vga_panel_name = "VGA";
313 } else {
314 /* XVGA, 16bpp */
315 framesize = 1024 * 768 * 2;
316 vga_panel_name = "XVGA";
317 }
318
319 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
320 if (val == SYS_CLCD_ID_SANYO_3_8)
321 panel_name = "Sanyo TM38QV67A02A";
322 else if (val == SYS_CLCD_ID_SANYO_2_5)
323 panel_name = "Sanyo QVGA Portrait";
324 else if (val == SYS_CLCD_ID_EPSON_2_2)
325 panel_name = "Epson L2F50113T00";
326 else if (val == SYS_CLCD_ID_VGA)
327 panel_name = vga_panel_name;
328 else {
329 pr_err("CLCD: unknown LCD panel ID 0x%08x, using VGA\n", val);
330 panel_name = vga_panel_name;
331 }
332
333 fb->panel = versatile_clcd_get_panel(panel_name);
334 if (!fb->panel)
335 return -EINVAL;
336
337 return versatile_clcd_setup_dma(fb, framesize);
338}
339
340struct clcd_board clcd_plat_data = {
341 .name = "RealView",
342 .caps = CLCD_CAP_ALL,
343 .check = clcdfb_check,
344 .decode = clcdfb_decode,
345 .disable = realview_clcd_disable,
346 .enable = realview_clcd_enable,
347 .setup = realview_clcd_setup,
348 .mmap = versatile_clcd_mmap_dma,
349 .remove = versatile_clcd_remove_dma,
350};
351
352/*
353 * Where is the timer (VA)?
354 */
355void __iomem *timer0_va_base;
356void __iomem *timer1_va_base;
357void __iomem *timer2_va_base;
358void __iomem *timer3_va_base;
359
360/*
361 * Set up the clock source and clock events devices
362 */
363void __init realview_timer_init(unsigned int timer_irq)
364{
365 u32 val;
366
367 /*
368 * set clock frequency:
369 * REALVIEW_REFCLK is 32KHz
370 * REALVIEW_TIMCLK is 1MHz
371 */
372 val = readl(__io_address(REALVIEW_SCTL_BASE));
373 writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
374 (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
375 (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
376 (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
377 __io_address(REALVIEW_SCTL_BASE));
378
379 /*
380 * Initialise to a known state (all timers off)
381 */
382 sp804_timer_disable(timer0_va_base);
383 sp804_timer_disable(timer1_va_base);
384 sp804_timer_disable(timer2_va_base);
385 sp804_timer_disable(timer3_va_base);
386
387 sp804_clocksource_init(timer3_va_base, "timer3");
388 sp804_clockevents_init(timer0_va_base, timer_irq, "timer0");
389}
390
391/*
392 * Setup the memory banks.
393 */
394void realview_fixup(struct tag *tags, char **from)
395{
396 /*
397 * Most RealView platforms have 512MB contiguous RAM at 0x70000000.
398 * Half of this is mirrored at 0.
399 */
400#ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
401 memblock_add(0x70000000, SZ_512M);
402#else
403 memblock_add(0, SZ_256M);
404#endif
405}
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
deleted file mode 100644
index 05a995ea16d3..000000000000
--- a/arch/arm/mach-realview/core.h
+++ /dev/null
@@ -1,58 +0,0 @@
1/*
2 * Copyright (C) 2004 ARM Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef __ASM_ARCH_REALVIEW_H
21#define __ASM_ARCH_REALVIEW_H
22
23#include <linux/amba/bus.h>
24#include <linux/io.h>
25
26#include <asm/setup.h>
27
28#define APB_DEVICE(name, busid, base, plat) \
29static AMBA_APB_DEVICE(name, busid, 0, REALVIEW_##base##_BASE, base##_IRQ, plat)
30
31#define AHB_DEVICE(name, busid, base, plat) \
32static AMBA_AHB_DEVICE(name, busid, 0, REALVIEW_##base##_BASE, base##_IRQ, plat)
33
34struct machine_desc;
35
36extern struct platform_device realview_flash_device;
37extern struct platform_device realview_cf_device;
38extern struct platform_device realview_leds_device;
39extern struct platform_device realview_i2c_device;
40extern struct mmci_platform_data realview_mmc0_plat_data;
41extern struct mmci_platform_data realview_mmc1_plat_data;
42extern struct clcd_board clcd_plat_data;
43extern void __iomem *timer0_va_base;
44extern void __iomem *timer1_va_base;
45extern void __iomem *timer2_va_base;
46extern void __iomem *timer3_va_base;
47
48extern void realview_timer_init(unsigned int timer_irq);
49extern int realview_flash_register(struct resource *res, u32 num);
50extern int realview_eth_register(const char *name, struct resource *res);
51extern int realview_usb_register(struct resource *res);
52extern void realview_init_early(void);
53extern void realview_fixup(struct tag *tags, char **from);
54
55extern const struct smp_operations realview_smp_ops;
56extern void realview_cpu_die(unsigned int cpu);
57
58#endif
diff --git a/arch/arm/mach-realview/hardware.h b/arch/arm/mach-realview/hardware.h
deleted file mode 100644
index 957a230aadf4..000000000000
--- a/arch/arm/mach-realview/hardware.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * This file contains the hardware definitions of the RealView boards.
3 *
4 * Copyright (C) 2003 ARM Limited.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARCH_HARDWARE_H
21#define __ASM_ARCH_HARDWARE_H
22
23#include <asm/sizes.h>
24
25/* macro to get at IO space when running virtually */
26#ifdef CONFIG_MMU
27/*
28 * Statically mapped addresses:
29 *
30 * 10xx xxxx -> fbxx xxxx
31 * 1exx xxxx -> fdxx xxxx
32 * 1fxx xxxx -> fexx xxxx
33 */
34#define IO_ADDRESS(x) (((x) & 0x03ffffff) + 0xfb000000)
35#else
36#define IO_ADDRESS(x) (x)
37#endif
38#define __io_address(n) IOMEM(IO_ADDRESS(n))
39
40#endif
diff --git a/arch/arm/mach-realview/hotplug.h b/arch/arm/mach-realview/hotplug.h
new file mode 100644
index 000000000000..eacd7a4dad2f
--- /dev/null
+++ b/arch/arm/mach-realview/hotplug.h
@@ -0,0 +1 @@
void realview_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-realview/irqs-eb.h b/arch/arm/mach-realview/irqs-eb.h
deleted file mode 100644
index 61e31680a749..000000000000
--- a/arch/arm/mach-realview/irqs-eb.h
+++ /dev/null
@@ -1,114 +0,0 @@
1/*
2 * Copyright (C) 2007 ARM Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef __MACH_IRQS_EB_H
20#define __MACH_IRQS_EB_H
21
22#define IRQ_LOCALTIMER 29
23#define IRQ_EB_GIC_START 32
24
25/*
26 * RealView EB interrupt sources
27 */
28#define IRQ_EB_WDOG (IRQ_EB_GIC_START + 0) /* Watchdog timer */
29#define IRQ_EB_SOFT (IRQ_EB_GIC_START + 1) /* Software interrupt */
30#define IRQ_EB_COMMRx (IRQ_EB_GIC_START + 2) /* Debug Comm Rx interrupt */
31#define IRQ_EB_COMMTx (IRQ_EB_GIC_START + 3) /* Debug Comm Tx interrupt */
32#define IRQ_EB_TIMER0_1 (IRQ_EB_GIC_START + 4) /* Timer 0 and 1 */
33#define IRQ_EB_TIMER2_3 (IRQ_EB_GIC_START + 5) /* Timer 2 and 3 */
34#define IRQ_EB_GPIO0 (IRQ_EB_GIC_START + 6) /* GPIO 0 */
35#define IRQ_EB_GPIO1 (IRQ_EB_GIC_START + 7) /* GPIO 1 */
36#define IRQ_EB_GPIO2 (IRQ_EB_GIC_START + 8) /* GPIO 2 */
37 /* 9 reserved */
38#define IRQ_EB_RTC (IRQ_EB_GIC_START + 10) /* Real Time Clock */
39#define IRQ_EB_SSP (IRQ_EB_GIC_START + 11) /* Synchronous Serial Port */
40#define IRQ_EB_UART0 (IRQ_EB_GIC_START + 12) /* UART 0 on development chip */
41#define IRQ_EB_UART1 (IRQ_EB_GIC_START + 13) /* UART 1 on development chip */
42#define IRQ_EB_UART2 (IRQ_EB_GIC_START + 14) /* UART 2 on development chip */
43#define IRQ_EB_UART3 (IRQ_EB_GIC_START + 15) /* UART 3 on development chip */
44#define IRQ_EB_SCI (IRQ_EB_GIC_START + 16) /* Smart Card Interface */
45#define IRQ_EB_MMCI0A (IRQ_EB_GIC_START + 17) /* Multimedia Card 0A */
46#define IRQ_EB_MMCI0B (IRQ_EB_GIC_START + 18) /* Multimedia Card 0B */
47#define IRQ_EB_AACI (IRQ_EB_GIC_START + 19) /* Audio Codec */
48#define IRQ_EB_KMI0 (IRQ_EB_GIC_START + 20) /* Keyboard/Mouse port 0 */
49#define IRQ_EB_KMI1 (IRQ_EB_GIC_START + 21) /* Keyboard/Mouse port 1 */
50#define IRQ_EB_CHARLCD (IRQ_EB_GIC_START + 22) /* Character LCD */
51#define IRQ_EB_CLCD (IRQ_EB_GIC_START + 23) /* CLCD controller */
52#define IRQ_EB_DMA (IRQ_EB_GIC_START + 24) /* DMA controller */
53#define IRQ_EB_PWRFAIL (IRQ_EB_GIC_START + 25) /* Power failure */
54#define IRQ_EB_PISMO (IRQ_EB_GIC_START + 26) /* PISMO interface */
55#define IRQ_EB_DoC (IRQ_EB_GIC_START + 27) /* Disk on Chip memory controller */
56#define IRQ_EB_ETH (IRQ_EB_GIC_START + 28) /* Ethernet controller */
57#define IRQ_EB_USB (IRQ_EB_GIC_START + 29) /* USB controller */
58#define IRQ_EB_TSPEN (IRQ_EB_GIC_START + 30) /* Touchscreen pen */
59#define IRQ_EB_TSKPAD (IRQ_EB_GIC_START + 31) /* Touchscreen keypad */
60
61/*
62 * RealView EB + ARM11MPCore interrupt sources (primary GIC on the core tile)
63 */
64#define IRQ_EB11MP_AACI (IRQ_EB_GIC_START + 0)
65#define IRQ_EB11MP_TIMER0_1 (IRQ_EB_GIC_START + 1)
66#define IRQ_EB11MP_TIMER2_3 (IRQ_EB_GIC_START + 2)
67#define IRQ_EB11MP_USB (IRQ_EB_GIC_START + 3)
68#define IRQ_EB11MP_UART0 (IRQ_EB_GIC_START + 4)
69#define IRQ_EB11MP_UART1 (IRQ_EB_GIC_START + 5)
70#define IRQ_EB11MP_RTC (IRQ_EB_GIC_START + 6)
71#define IRQ_EB11MP_KMI0 (IRQ_EB_GIC_START + 7)
72#define IRQ_EB11MP_KMI1 (IRQ_EB_GIC_START + 8)
73#define IRQ_EB11MP_ETH (IRQ_EB_GIC_START + 9)
74#define IRQ_EB11MP_EB_IRQ1 (IRQ_EB_GIC_START + 10) /* main GIC */
75#define IRQ_EB11MP_EB_IRQ2 (IRQ_EB_GIC_START + 11) /* tile GIC */
76#define IRQ_EB11MP_EB_FIQ1 (IRQ_EB_GIC_START + 12) /* main GIC */
77#define IRQ_EB11MP_EB_FIQ2 (IRQ_EB_GIC_START + 13) /* tile GIC */
78#define IRQ_EB11MP_MMCI0A (IRQ_EB_GIC_START + 14)
79#define IRQ_EB11MP_MMCI0B (IRQ_EB_GIC_START + 15)
80
81#define IRQ_EB11MP_PMU_CPU0 (IRQ_EB_GIC_START + 17)
82#define IRQ_EB11MP_PMU_CPU1 (IRQ_EB_GIC_START + 18)
83#define IRQ_EB11MP_PMU_CPU2 (IRQ_EB_GIC_START + 19)
84#define IRQ_EB11MP_PMU_CPU3 (IRQ_EB_GIC_START + 20)
85#define IRQ_EB11MP_PMU_SCU0 (IRQ_EB_GIC_START + 21)
86#define IRQ_EB11MP_PMU_SCU1 (IRQ_EB_GIC_START + 22)
87#define IRQ_EB11MP_PMU_SCU2 (IRQ_EB_GIC_START + 23)
88#define IRQ_EB11MP_PMU_SCU3 (IRQ_EB_GIC_START + 24)
89#define IRQ_EB11MP_PMU_SCU4 (IRQ_EB_GIC_START + 25)
90#define IRQ_EB11MP_PMU_SCU5 (IRQ_EB_GIC_START + 26)
91#define IRQ_EB11MP_PMU_SCU6 (IRQ_EB_GIC_START + 27)
92#define IRQ_EB11MP_PMU_SCU7 (IRQ_EB_GIC_START + 28)
93
94#define IRQ_EB11MP_L220_EVENT (IRQ_EB_GIC_START + 29)
95#define IRQ_EB11MP_L220_SLAVE (IRQ_EB_GIC_START + 30)
96#define IRQ_EB11MP_L220_DECODE (IRQ_EB_GIC_START + 31)
97
98/*
99 * The 11MPcore tile leaves the following unconnected.
100 */
101#define IRQ_EB11MP_UART2 0
102#define IRQ_EB11MP_UART3 0
103#define IRQ_EB11MP_CLCD 0
104#define IRQ_EB11MP_DMA 0
105#define IRQ_EB11MP_WDOG 0
106#define IRQ_EB11MP_GPIO0 0
107#define IRQ_EB11MP_GPIO1 0
108#define IRQ_EB11MP_GPIO2 0
109#define IRQ_EB11MP_SCI 0
110#define IRQ_EB11MP_SSP 0
111
112#define NR_GIC_EB11MP 2
113
114#endif /* __MACH_IRQS_EB_H */
diff --git a/arch/arm/mach-realview/irqs-pb1176.h b/arch/arm/mach-realview/irqs-pb1176.h
deleted file mode 100644
index 778edfd430e7..000000000000
--- a/arch/arm/mach-realview/irqs-pb1176.h
+++ /dev/null
@@ -1,77 +0,0 @@
1/*
2 * Copyright (C) 2008 ARM Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef __MACH_IRQS_PB1176_H
20#define __MACH_IRQS_PB1176_H
21
22#define IRQ_DC1176_GIC_START 32
23#define IRQ_PB1176_GIC_START 64
24
25/*
26 * ARM1176 DevChip interrupt sources (primary GIC)
27 */
28#define IRQ_DC1176_WATCHDOG (IRQ_DC1176_GIC_START + 0) /* Watchdog timer */
29#define IRQ_DC1176_SOFTINT (IRQ_DC1176_GIC_START + 1) /* Software interrupt */
30#define IRQ_DC1176_COMMRx (IRQ_DC1176_GIC_START + 2) /* Debug Comm Rx interrupt */
31#define IRQ_DC1176_COMMTx (IRQ_DC1176_GIC_START + 3) /* Debug Comm Tx interrupt */
32#define IRQ_DC1176_CORE_PMU (IRQ_DC1176_GIC_START + 7) /* Core PMU interrupt */
33#define IRQ_DC1176_TIMER0 (IRQ_DC1176_GIC_START + 8) /* Timer 0 */
34#define IRQ_DC1176_TIMER1 (IRQ_DC1176_GIC_START + 9) /* Timer 1 */
35#define IRQ_DC1176_TIMER2 (IRQ_DC1176_GIC_START + 10) /* Timer 2 */
36#define IRQ_DC1176_APC (IRQ_DC1176_GIC_START + 11)
37#define IRQ_DC1176_IEC (IRQ_DC1176_GIC_START + 12)
38#define IRQ_DC1176_L2CC (IRQ_DC1176_GIC_START + 13)
39#define IRQ_DC1176_RTC (IRQ_DC1176_GIC_START + 14)
40#define IRQ_DC1176_CLCD (IRQ_DC1176_GIC_START + 15) /* CLCD controller */
41#define IRQ_DC1176_GPIO0 (IRQ_DC1176_GIC_START + 16)
42#define IRQ_DC1176_SSP (IRQ_DC1176_GIC_START + 17) /* SSP port */
43#define IRQ_DC1176_UART0 (IRQ_DC1176_GIC_START + 18) /* UART 0 on development chip */
44#define IRQ_DC1176_UART1 (IRQ_DC1176_GIC_START + 19) /* UART 1 on development chip */
45#define IRQ_DC1176_UART2 (IRQ_DC1176_GIC_START + 20) /* UART 2 on development chip */
46#define IRQ_DC1176_UART3 (IRQ_DC1176_GIC_START + 21) /* UART 3 on development chip */
47
48#define IRQ_DC1176_PB_IRQ2 (IRQ_DC1176_GIC_START + 30) /* tile GIC */
49#define IRQ_DC1176_PB_IRQ1 (IRQ_DC1176_GIC_START + 31) /* main GIC */
50
51/*
52 * RealView PB1176 interrupt sources (secondary GIC)
53 */
54#define IRQ_PB1176_MMCI0A (IRQ_PB1176_GIC_START + 1) /* Multimedia Card 0A */
55#define IRQ_PB1176_MMCI0B (IRQ_PB1176_GIC_START + 2) /* Multimedia Card 0A */
56#define IRQ_PB1176_KMI0 (IRQ_PB1176_GIC_START + 3) /* Keyboard/Mouse port 0 */
57#define IRQ_PB1176_KMI1 (IRQ_PB1176_GIC_START + 4) /* Keyboard/Mouse port 1 */
58#define IRQ_PB1176_SCI (IRQ_PB1176_GIC_START + 5)
59#define IRQ_PB1176_UART4 (IRQ_PB1176_GIC_START + 6) /* UART 4 on baseboard */
60#define IRQ_PB1176_CHARLCD (IRQ_PB1176_GIC_START + 7) /* Character LCD */
61#define IRQ_PB1176_GPIO1 (IRQ_PB1176_GIC_START + 8)
62#define IRQ_PB1176_GPIO2 (IRQ_PB1176_GIC_START + 9)
63#define IRQ_PB1176_ETH (IRQ_PB1176_GIC_START + 10) /* Ethernet controller */
64#define IRQ_PB1176_USB (IRQ_PB1176_GIC_START + 11) /* USB controller */
65
66#define IRQ_PB1176_PISMO (IRQ_PB1176_GIC_START + 16)
67
68#define IRQ_PB1176_AACI (IRQ_PB1176_GIC_START + 19) /* Audio Codec */
69
70#define IRQ_PB1176_TIMER0_1 (IRQ_PB1176_GIC_START + 22)
71#define IRQ_PB1176_TIMER2_3 (IRQ_PB1176_GIC_START + 23)
72#define IRQ_PB1176_DMAC (IRQ_PB1176_GIC_START + 24) /* DMA controller */
73#define IRQ_PB1176_RTC (IRQ_PB1176_GIC_START + 25) /* Real Time Clock */
74
75#define IRQ_PB1176_SCTL -1
76
77#endif /* __MACH_IRQS_PB1176_H */
diff --git a/arch/arm/mach-realview/irqs-pb11mp.h b/arch/arm/mach-realview/irqs-pb11mp.h
deleted file mode 100644
index 938898a3df9f..000000000000
--- a/arch/arm/mach-realview/irqs-pb11mp.h
+++ /dev/null
@@ -1,97 +0,0 @@
1/*
2 * Copyright (C) 2008 ARM Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef __MACH_IRQS_PB11MP_H
20#define __MACH_IRQS_PB11MP_H
21
22#define IRQ_LOCALTIMER 29
23#define IRQ_TC11MP_GIC_START 32
24#define IRQ_PB11MP_GIC_START 64
25
26/*
27 * ARM11MPCore test chip interrupt sources (primary GIC on the test chip)
28 */
29#define IRQ_TC11MP_AACI (IRQ_TC11MP_GIC_START + 0)
30#define IRQ_TC11MP_TIMER0_1 (IRQ_TC11MP_GIC_START + 1)
31#define IRQ_TC11MP_TIMER2_3 (IRQ_TC11MP_GIC_START + 2)
32#define IRQ_TC11MP_USB (IRQ_TC11MP_GIC_START + 3)
33#define IRQ_TC11MP_UART0 (IRQ_TC11MP_GIC_START + 4)
34#define IRQ_TC11MP_UART1 (IRQ_TC11MP_GIC_START + 5)
35#define IRQ_TC11MP_RTC (IRQ_TC11MP_GIC_START + 6)
36#define IRQ_TC11MP_KMI0 (IRQ_TC11MP_GIC_START + 7)
37#define IRQ_TC11MP_KMI1 (IRQ_TC11MP_GIC_START + 8)
38#define IRQ_TC11MP_ETH (IRQ_TC11MP_GIC_START + 9)
39#define IRQ_TC11MP_PB_IRQ1 (IRQ_TC11MP_GIC_START + 10) /* main GIC */
40#define IRQ_TC11MP_PB_IRQ2 (IRQ_TC11MP_GIC_START + 11) /* tile GIC */
41#define IRQ_TC11MP_PB_FIQ1 (IRQ_TC11MP_GIC_START + 12) /* main GIC */
42#define IRQ_TC11MP_PB_FIQ2 (IRQ_TC11MP_GIC_START + 13) /* tile GIC */
43#define IRQ_TC11MP_MMCI0A (IRQ_TC11MP_GIC_START + 14)
44#define IRQ_TC11MP_MMCI0B (IRQ_TC11MP_GIC_START + 15)
45
46#define IRQ_TC11MP_PMU_CPU0 (IRQ_TC11MP_GIC_START + 17)
47#define IRQ_TC11MP_PMU_CPU1 (IRQ_TC11MP_GIC_START + 18)
48#define IRQ_TC11MP_PMU_CPU2 (IRQ_TC11MP_GIC_START + 19)
49#define IRQ_TC11MP_PMU_CPU3 (IRQ_TC11MP_GIC_START + 20)
50#define IRQ_TC11MP_PMU_SCU0 (IRQ_TC11MP_GIC_START + 21)
51#define IRQ_TC11MP_PMU_SCU1 (IRQ_TC11MP_GIC_START + 22)
52#define IRQ_TC11MP_PMU_SCU2 (IRQ_TC11MP_GIC_START + 23)
53#define IRQ_TC11MP_PMU_SCU3 (IRQ_TC11MP_GIC_START + 24)
54#define IRQ_TC11MP_PMU_SCU4 (IRQ_TC11MP_GIC_START + 25)
55#define IRQ_TC11MP_PMU_SCU5 (IRQ_TC11MP_GIC_START + 26)
56#define IRQ_TC11MP_PMU_SCU6 (IRQ_TC11MP_GIC_START + 27)
57#define IRQ_TC11MP_PMU_SCU7 (IRQ_TC11MP_GIC_START + 28)
58
59#define IRQ_TC11MP_L220_EVENT (IRQ_TC11MP_GIC_START + 29)
60#define IRQ_TC11MP_L220_SLAVE (IRQ_TC11MP_GIC_START + 30)
61#define IRQ_TC11MP_L220_DECODE (IRQ_TC11MP_GIC_START + 31)
62
63/*
64 * RealView PB11MPCore GIC interrupt sources (secondary GIC on the board)
65 */
66#define IRQ_PB11MP_WATCHDOG (IRQ_PB11MP_GIC_START + 0) /* Watchdog timer */
67#define IRQ_PB11MP_SOFT (IRQ_PB11MP_GIC_START + 1) /* Software interrupt */
68#define IRQ_PB11MP_COMMRx (IRQ_PB11MP_GIC_START + 2) /* Debug Comm Rx interrupt */
69#define IRQ_PB11MP_COMMTx (IRQ_PB11MP_GIC_START + 3) /* Debug Comm Tx interrupt */
70#define IRQ_PB11MP_GPIO0 (IRQ_PB11MP_GIC_START + 6) /* GPIO 0 */
71#define IRQ_PB11MP_GPIO1 (IRQ_PB11MP_GIC_START + 7) /* GPIO 1 */
72#define IRQ_PB11MP_GPIO2 (IRQ_PB11MP_GIC_START + 8) /* GPIO 2 */
73 /* 9 reserved */
74#define IRQ_PB11MP_RTC_GIC1 (IRQ_PB11MP_GIC_START + 10) /* Real Time Clock */
75#define IRQ_PB11MP_SSP (IRQ_PB11MP_GIC_START + 11) /* Synchronous Serial Port */
76#define IRQ_PB11MP_UART0_GIC1 (IRQ_PB11MP_GIC_START + 12) /* UART 0 on development chip */
77#define IRQ_PB11MP_UART1_GIC1 (IRQ_PB11MP_GIC_START + 13) /* UART 1 on development chip */
78#define IRQ_PB11MP_UART2 (IRQ_PB11MP_GIC_START + 14) /* UART 2 on development chip */
79#define IRQ_PB11MP_UART3 (IRQ_PB11MP_GIC_START + 15) /* UART 3 on development chip */
80#define IRQ_PB11MP_SCI (IRQ_PB11MP_GIC_START + 16) /* Smart Card Interface */
81#define IRQ_PB11MP_MMCI0A_GIC1 (IRQ_PB11MP_GIC_START + 17) /* Multimedia Card 0A */
82#define IRQ_PB11MP_MMCI0B_GIC1 (IRQ_PB11MP_GIC_START + 18) /* Multimedia Card 0B */
83#define IRQ_PB11MP_AACI_GIC1 (IRQ_PB11MP_GIC_START + 19) /* Audio Codec */
84#define IRQ_PB11MP_KMI0_GIC1 (IRQ_PB11MP_GIC_START + 20) /* Keyboard/Mouse port 0 */
85#define IRQ_PB11MP_KMI1_GIC1 (IRQ_PB11MP_GIC_START + 21) /* Keyboard/Mouse port 1 */
86#define IRQ_PB11MP_CHARLCD (IRQ_PB11MP_GIC_START + 22) /* Character LCD */
87#define IRQ_PB11MP_CLCD (IRQ_PB11MP_GIC_START + 23) /* CLCD controller */
88#define IRQ_PB11MP_DMAC (IRQ_PB11MP_GIC_START + 24) /* DMA controller */
89#define IRQ_PB11MP_PWRFAIL (IRQ_PB11MP_GIC_START + 25) /* Power failure */
90#define IRQ_PB11MP_PISMO (IRQ_PB11MP_GIC_START + 26) /* PISMO interface */
91#define IRQ_PB11MP_DoC (IRQ_PB11MP_GIC_START + 27) /* Disk on Chip memory controller */
92#define IRQ_PB11MP_ETH_GIC1 (IRQ_PB11MP_GIC_START + 28) /* Ethernet controller */
93#define IRQ_PB11MP_USB_GIC1 (IRQ_PB11MP_GIC_START + 29) /* USB controller */
94#define IRQ_PB11MP_TSPEN (IRQ_PB11MP_GIC_START + 30) /* Touchscreen pen */
95#define IRQ_PB11MP_TSKPAD (IRQ_PB11MP_GIC_START + 31) /* Touchscreen keypad */
96
97#endif /* __MACH_IRQS_PB11MP_H */
diff --git a/arch/arm/mach-realview/irqs-pba8.h b/arch/arm/mach-realview/irqs-pba8.h
deleted file mode 100644
index 262e321938b8..000000000000
--- a/arch/arm/mach-realview/irqs-pba8.h
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * Copyright (C) 2008 ARM Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef __MACH_IRQS_PBA8_H
20#define __MACH_IRQS_PBA8_H
21
22#define IRQ_PBA8_GIC_START 32
23
24/*
25 * PB-A8 on-board gic irq sources
26 */
27#define IRQ_PBA8_WATCHDOG (IRQ_PBA8_GIC_START + 0) /* Watchdog timer */
28#define IRQ_PBA8_SOFT (IRQ_PBA8_GIC_START + 1) /* Software interrupt */
29#define IRQ_PBA8_COMMRx (IRQ_PBA8_GIC_START + 2) /* Debug Comm Rx interrupt */
30#define IRQ_PBA8_COMMTx (IRQ_PBA8_GIC_START + 3) /* Debug Comm Tx interrupt */
31#define IRQ_PBA8_TIMER0_1 (IRQ_PBA8_GIC_START + 4) /* Timer 0/1 (default timer) */
32#define IRQ_PBA8_TIMER2_3 (IRQ_PBA8_GIC_START + 5) /* Timer 2/3 */
33#define IRQ_PBA8_GPIO0 (IRQ_PBA8_GIC_START + 6) /* GPIO 0 */
34#define IRQ_PBA8_GPIO1 (IRQ_PBA8_GIC_START + 7) /* GPIO 1 */
35#define IRQ_PBA8_GPIO2 (IRQ_PBA8_GIC_START + 8) /* GPIO 2 */
36 /* 9 reserved */
37#define IRQ_PBA8_RTC (IRQ_PBA8_GIC_START + 10) /* Real Time Clock */
38#define IRQ_PBA8_SSP (IRQ_PBA8_GIC_START + 11) /* Synchronous Serial Port */
39#define IRQ_PBA8_UART0 (IRQ_PBA8_GIC_START + 12) /* UART 0 on development chip */
40#define IRQ_PBA8_UART1 (IRQ_PBA8_GIC_START + 13) /* UART 1 on development chip */
41#define IRQ_PBA8_UART2 (IRQ_PBA8_GIC_START + 14) /* UART 2 on development chip */
42#define IRQ_PBA8_UART3 (IRQ_PBA8_GIC_START + 15) /* UART 3 on development chip */
43#define IRQ_PBA8_SCI (IRQ_PBA8_GIC_START + 16) /* Smart Card Interface */
44#define IRQ_PBA8_MMCI0A (IRQ_PBA8_GIC_START + 17) /* Multimedia Card 0A */
45#define IRQ_PBA8_MMCI0B (IRQ_PBA8_GIC_START + 18) /* Multimedia Card 0B */
46#define IRQ_PBA8_AACI (IRQ_PBA8_GIC_START + 19) /* Audio Codec */
47#define IRQ_PBA8_KMI0 (IRQ_PBA8_GIC_START + 20) /* Keyboard/Mouse port 0 */
48#define IRQ_PBA8_KMI1 (IRQ_PBA8_GIC_START + 21) /* Keyboard/Mouse port 1 */
49#define IRQ_PBA8_CHARLCD (IRQ_PBA8_GIC_START + 22) /* Character LCD */
50#define IRQ_PBA8_CLCD (IRQ_PBA8_GIC_START + 23) /* CLCD controller */
51#define IRQ_PBA8_DMAC (IRQ_PBA8_GIC_START + 24) /* DMA controller */
52#define IRQ_PBA8_PWRFAIL (IRQ_PBA8_GIC_START + 25) /* Power failure */
53#define IRQ_PBA8_PISMO (IRQ_PBA8_GIC_START + 26) /* PISMO interface */
54#define IRQ_PBA8_DoC (IRQ_PBA8_GIC_START + 27) /* Disk on Chip memory controller */
55#define IRQ_PBA8_ETH (IRQ_PBA8_GIC_START + 28) /* Ethernet controller */
56#define IRQ_PBA8_USB (IRQ_PBA8_GIC_START + 29) /* USB controller */
57#define IRQ_PBA8_TSPEN (IRQ_PBA8_GIC_START + 30) /* Touchscreen pen */
58#define IRQ_PBA8_TSKPAD (IRQ_PBA8_GIC_START + 31) /* Touchscreen keypad */
59
60#define IRQ_PBA8_PMU (IRQ_PBA8_GIC_START + 47) /* Cortex-A8 PMU */
61
62/* ... */
63#define IRQ_PBA8_PCI0 (IRQ_PBA8_GIC_START + 50)
64#define IRQ_PBA8_PCI1 (IRQ_PBA8_GIC_START + 51)
65#define IRQ_PBA8_PCI2 (IRQ_PBA8_GIC_START + 52)
66#define IRQ_PBA8_PCI3 (IRQ_PBA8_GIC_START + 53)
67
68#define IRQ_PBA8_SMC -1
69#define IRQ_PBA8_SCTL -1
70
71#endif /* __MACH_IRQS_PBA8_H */
diff --git a/arch/arm/mach-realview/irqs-pbx.h b/arch/arm/mach-realview/irqs-pbx.h
deleted file mode 100644
index 4ef0567dec32..000000000000
--- a/arch/arm/mach-realview/irqs-pbx.h
+++ /dev/null
@@ -1,87 +0,0 @@
1/*
2 * Copyright (C) 2009 ARM Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18#ifndef __MACH_IRQS_PBX_H
19#define __MACH_IRQS_PBX_H
20
21#define IRQ_LOCALTIMER 29
22#define IRQ_PBX_GIC_START 32
23
24/*
25 * PBX on-board gic irq sources
26 */
27#define IRQ_PBX_WATCHDOG (IRQ_PBX_GIC_START + 0) /* Watchdog timer */
28#define IRQ_PBX_SOFT (IRQ_PBX_GIC_START + 1) /* Software interrupt */
29#define IRQ_PBX_COMMRx (IRQ_PBX_GIC_START + 2) /* Debug Comm Rx interrupt */
30#define IRQ_PBX_COMMTx (IRQ_PBX_GIC_START + 3) /* Debug Comm Tx interrupt */
31#define IRQ_PBX_TIMER0_1 (IRQ_PBX_GIC_START + 4) /* Timer 0/1 (default timer) */
32#define IRQ_PBX_TIMER2_3 (IRQ_PBX_GIC_START + 5) /* Timer 2/3 */
33#define IRQ_PBX_GPIO0 (IRQ_PBX_GIC_START + 6) /* GPIO 0 */
34#define IRQ_PBX_GPIO1 (IRQ_PBX_GIC_START + 7) /* GPIO 1 */
35#define IRQ_PBX_GPIO2 (IRQ_PBX_GIC_START + 8) /* GPIO 2 */
36 /* 9 reserved */
37#define IRQ_PBX_RTC (IRQ_PBX_GIC_START + 10) /* Real Time Clock */
38#define IRQ_PBX_SSP (IRQ_PBX_GIC_START + 11) /* Synchronous Serial Port */
39#define IRQ_PBX_UART0 (IRQ_PBX_GIC_START + 12) /* UART 0 on development chip */
40#define IRQ_PBX_UART1 (IRQ_PBX_GIC_START + 13) /* UART 1 on development chip */
41#define IRQ_PBX_UART2 (IRQ_PBX_GIC_START + 14) /* UART 2 on development chip */
42#define IRQ_PBX_UART3 (IRQ_PBX_GIC_START + 15) /* UART 3 on development chip */
43#define IRQ_PBX_SCI (IRQ_PBX_GIC_START + 16) /* Smart Card Interface */
44#define IRQ_PBX_MMCI0A (IRQ_PBX_GIC_START + 17) /* Multimedia Card 0A */
45#define IRQ_PBX_MMCI0B (IRQ_PBX_GIC_START + 18) /* Multimedia Card 0B */
46#define IRQ_PBX_AACI (IRQ_PBX_GIC_START + 19) /* Audio Codec */
47#define IRQ_PBX_KMI0 (IRQ_PBX_GIC_START + 20) /* Keyboard/Mouse port 0 */
48#define IRQ_PBX_KMI1 (IRQ_PBX_GIC_START + 21) /* Keyboard/Mouse port 1 */
49#define IRQ_PBX_CHARLCD (IRQ_PBX_GIC_START + 22) /* Character LCD */
50#define IRQ_PBX_CLCD (IRQ_PBX_GIC_START + 23) /* CLCD controller */
51#define IRQ_PBX_DMAC (IRQ_PBX_GIC_START + 24) /* DMA controller */
52#define IRQ_PBX_PWRFAIL (IRQ_PBX_GIC_START + 25) /* Power failure */
53#define IRQ_PBX_PISMO (IRQ_PBX_GIC_START + 26) /* PISMO interface */
54#define IRQ_PBX_DoC (IRQ_PBX_GIC_START + 27) /* Disk on Chip memory controller */
55#define IRQ_PBX_ETH (IRQ_PBX_GIC_START + 28) /* Ethernet controller */
56#define IRQ_PBX_USB (IRQ_PBX_GIC_START + 29) /* USB controller */
57#define IRQ_PBX_TSPEN (IRQ_PBX_GIC_START + 30) /* Touchscreen pen */
58#define IRQ_PBX_TSKPAD (IRQ_PBX_GIC_START + 31) /* Touchscreen keypad */
59
60#define IRQ_PBX_PMU_SCU0 (IRQ_PBX_GIC_START + 32) /* SCU PMU Interrupts (11mp) */
61#define IRQ_PBX_PMU_SCU1 (IRQ_PBX_GIC_START + 33)
62#define IRQ_PBX_PMU_SCU2 (IRQ_PBX_GIC_START + 34)
63#define IRQ_PBX_PMU_SCU3 (IRQ_PBX_GIC_START + 35)
64#define IRQ_PBX_PMU_SCU4 (IRQ_PBX_GIC_START + 36)
65#define IRQ_PBX_PMU_SCU5 (IRQ_PBX_GIC_START + 37)
66#define IRQ_PBX_PMU_SCU6 (IRQ_PBX_GIC_START + 38)
67#define IRQ_PBX_PMU_SCU7 (IRQ_PBX_GIC_START + 39)
68
69#define IRQ_PBX_WATCHDOG1 (IRQ_PBX_GIC_START + 40) /* Watchdog1 timer */
70#define IRQ_PBX_TIMER4_5 (IRQ_PBX_GIC_START + 41) /* Timer 0/1 (default timer) */
71#define IRQ_PBX_TIMER6_7 (IRQ_PBX_GIC_START + 42) /* Timer 2/3 */
72/* ... */
73#define IRQ_PBX_PMU_CPU0 (IRQ_PBX_GIC_START + 44) /* CPU PMU Interrupts */
74#define IRQ_PBX_PMU_CPU1 (IRQ_PBX_GIC_START + 45)
75#define IRQ_PBX_PMU_CPU2 (IRQ_PBX_GIC_START + 46)
76#define IRQ_PBX_PMU_CPU3 (IRQ_PBX_GIC_START + 47)
77
78/* ... */
79#define IRQ_PBX_PCI0 (IRQ_PBX_GIC_START + 50)
80#define IRQ_PBX_PCI1 (IRQ_PBX_GIC_START + 51)
81#define IRQ_PBX_PCI2 (IRQ_PBX_GIC_START + 52)
82#define IRQ_PBX_PCI3 (IRQ_PBX_GIC_START + 53)
83
84#define IRQ_PBX_SMC -1
85#define IRQ_PBX_SCTL -1
86
87#endif /* __MACH_IRQS_PBX_H */
diff --git a/arch/arm/mach-realview/platform.h b/arch/arm/mach-realview/platform.h
deleted file mode 100644
index 11121739d371..000000000000
--- a/arch/arm/mach-realview/platform.h
+++ /dev/null
@@ -1,247 +0,0 @@
1/*
2 * Copyright (c) ARM Limited 2003. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#ifndef __ASM_ARCH_PLATFORM_H
20#define __ASM_ARCH_PLATFORM_H
21
22/*
23 * Memory definitions
24 */
25#define REALVIEW_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)...*/
26#define REALVIEW_BOOT_ROM_HI 0x30000000
27#define REALVIEW_BOOT_ROM_BASE REALVIEW_BOOT_ROM_HI /* Normal position */
28#define REALVIEW_BOOT_ROM_SIZE SZ_64M
29
30#define REALVIEW_SSRAM_BASE /* REALVIEW_SSMC_BASE ? */
31#define REALVIEW_SSRAM_SIZE SZ_2M
32
33/*
34 * SDRAM
35 */
36#define REALVIEW_SDRAM_BASE 0x00000000
37
38/*
39 * Logic expansion modules
40 *
41 */
42
43
44/* ------------------------------------------------------------------------
45 * RealView Registers
46 * ------------------------------------------------------------------------
47 *
48 */
49#define REALVIEW_SYS_ID_OFFSET 0x00
50#define REALVIEW_SYS_SW_OFFSET 0x04
51#define REALVIEW_SYS_LED_OFFSET 0x08
52#define REALVIEW_SYS_OSC0_OFFSET 0x0C
53
54#define REALVIEW_SYS_OSC1_OFFSET 0x10
55#define REALVIEW_SYS_OSC2_OFFSET 0x14
56#define REALVIEW_SYS_OSC3_OFFSET 0x18
57#define REALVIEW_SYS_OSC4_OFFSET 0x1C /* OSC1 for RealView/AB */
58
59#define REALVIEW_SYS_LOCK_OFFSET 0x20
60#define REALVIEW_SYS_100HZ_OFFSET 0x24
61#define REALVIEW_SYS_CFGDATA1_OFFSET 0x28
62#define REALVIEW_SYS_CFGDATA2_OFFSET 0x2C
63#define REALVIEW_SYS_FLAGS_OFFSET 0x30
64#define REALVIEW_SYS_FLAGSSET_OFFSET 0x30
65#define REALVIEW_SYS_FLAGSCLR_OFFSET 0x34
66#define REALVIEW_SYS_NVFLAGS_OFFSET 0x38
67#define REALVIEW_SYS_NVFLAGSSET_OFFSET 0x38
68#define REALVIEW_SYS_NVFLAGSCLR_OFFSET 0x3C
69#define REALVIEW_SYS_RESETCTL_OFFSET 0x40
70#define REALVIEW_SYS_PCICTL_OFFSET 0x44
71#define REALVIEW_SYS_MCI_OFFSET 0x48
72#define REALVIEW_SYS_FLASH_OFFSET 0x4C
73#define REALVIEW_SYS_CLCD_OFFSET 0x50
74#define REALVIEW_SYS_CLCDSER_OFFSET 0x54
75#define REALVIEW_SYS_BOOTCS_OFFSET 0x58
76#define REALVIEW_SYS_24MHz_OFFSET 0x5C
77#define REALVIEW_SYS_MISC_OFFSET 0x60
78#define REALVIEW_SYS_IOSEL_OFFSET 0x70
79#define REALVIEW_SYS_PROCID_OFFSET 0x84
80#define REALVIEW_SYS_TEST_OSC0_OFFSET 0xC0
81#define REALVIEW_SYS_TEST_OSC1_OFFSET 0xC4
82#define REALVIEW_SYS_TEST_OSC2_OFFSET 0xC8
83#define REALVIEW_SYS_TEST_OSC3_OFFSET 0xCC
84#define REALVIEW_SYS_TEST_OSC4_OFFSET 0xD0
85
86#define REALVIEW_SYS_BASE 0x10000000
87#define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET)
88#define REALVIEW_SYS_SW (REALVIEW_SYS_BASE + REALVIEW_SYS_SW_OFFSET)
89#define REALVIEW_SYS_LED (REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET)
90#define REALVIEW_SYS_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC0_OFFSET)
91#define REALVIEW_SYS_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC1_OFFSET)
92
93#define REALVIEW_SYS_LOCK (REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET)
94#define REALVIEW_SYS_100HZ (REALVIEW_SYS_BASE + REALVIEW_SYS_100HZ_OFFSET)
95#define REALVIEW_SYS_CFGDATA1 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA1_OFFSET)
96#define REALVIEW_SYS_CFGDATA2 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA2_OFFSET)
97#define REALVIEW_SYS_FLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGS_OFFSET)
98#define REALVIEW_SYS_FLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSSET_OFFSET)
99#define REALVIEW_SYS_FLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSCLR_OFFSET)
100#define REALVIEW_SYS_NVFLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGS_OFFSET)
101#define REALVIEW_SYS_NVFLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSSET_OFFSET)
102#define REALVIEW_SYS_NVFLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSCLR_OFFSET)
103#define REALVIEW_SYS_RESETCTL (REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET)
104#define REALVIEW_SYS_PCICTL (REALVIEW_SYS_BASE + REALVIEW_SYS_PCICTL_OFFSET)
105#define REALVIEW_SYS_MCI (REALVIEW_SYS_BASE + REALVIEW_SYS_MCI_OFFSET)
106#define REALVIEW_SYS_FLASH (REALVIEW_SYS_BASE + REALVIEW_SYS_FLASH_OFFSET)
107#define REALVIEW_SYS_CLCD (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCD_OFFSET)
108#define REALVIEW_SYS_CLCDSER (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCDSER_OFFSET)
109#define REALVIEW_SYS_BOOTCS (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET)
110#define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET)
111#define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET)
112#define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET)
113#define REALVIEW_SYS_PROCID (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET)
114#define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET)
115#define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET)
116#define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET)
117#define REALVIEW_SYS_TEST_OSC3 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET)
118#define REALVIEW_SYS_TEST_OSC4 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET)
119
120/* ------------------------------------------------------------------------
121 * RealView control registers
122 * ------------------------------------------------------------------------
123 */
124
125/*
126 * REALVIEW_IDFIELD
127 *
128 * 31:24 = manufacturer (0x41 = ARM)
129 * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
130 * 15:12 = FPGA (0x3 = XVC600 or XVC600E)
131 * 11:4 = build value
132 * 3:0 = revision number (0x1 = rev B (AHB))
133 */
134
135/*
136 * REALVIEW_SYS_LOCK
137 * control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL,
138 * SYS_CLD, SYS_BOOTCS
139 */
140#define REALVIEW_SYS_LOCK_LOCKED (1 << 16)
141#define REALVIEW_SYS_LOCK_VAL 0xA05F /* Enable write access */
142
143/*
144 * REALVIEW_SYS_FLASH
145 */
146#define REALVIEW_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */
147
148/*
149 * REALVIEW_INTREG
150 * - used to acknowledge and control MMCI and UART interrupts
151 */
152#define REALVIEW_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */
153#define REALVIEW_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */
154#define REALVIEW_INTREG_CARDIN 0x08 /* MMCI card in detect */
155 /* write 1 to acknowledge and clear */
156#define REALVIEW_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */
157#define REALVIEW_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */
158
159/*
160 * RealView common peripheral addresses
161 */
162#define REALVIEW_SCTL_BASE 0x10001000 /* System controller */
163#define REALVIEW_I2C_BASE 0x10002000 /* I2C control */
164#define REALVIEW_AACI_BASE 0x10004000 /* Audio */
165#define REALVIEW_MMCI0_BASE 0x10005000 /* MMC interface */
166#define REALVIEW_KMI0_BASE 0x10006000 /* KMI interface */
167#define REALVIEW_KMI1_BASE 0x10007000 /* KMI 2nd interface */
168#define REALVIEW_CHAR_LCD_BASE 0x10008000 /* Character LCD */
169#define REALVIEW_SCI_BASE 0x1000E000 /* Smart card controller */
170#define REALVIEW_GPIO1_BASE 0x10014000 /* GPIO port 1 */
171#define REALVIEW_GPIO2_BASE 0x10015000 /* GPIO port 2 */
172#define REALVIEW_DMC_BASE 0x10018000 /* DMC configuration */
173#define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */
174
175/* PCI space */
176#define REALVIEW_PCI_BASE 0x41000000 /* PCI Interface */
177#define REALVIEW_PCI_CFG_BASE 0x42000000
178#define REALVIEW_PCI_MEM_BASE0 0x44000000
179#define REALVIEW_PCI_MEM_BASE1 0x50000000
180#define REALVIEW_PCI_MEM_BASE2 0x60000000
181/* Sizes of above maps */
182#define REALVIEW_PCI_BASE_SIZE 0x01000000
183#define REALVIEW_PCI_CFG_BASE_SIZE 0x02000000
184#define REALVIEW_PCI_MEM_BASE0_SIZE 0x0c000000 /* 32Mb */
185#define REALVIEW_PCI_MEM_BASE1_SIZE 0x10000000 /* 256Mb */
186#define REALVIEW_PCI_MEM_BASE2_SIZE 0x10000000 /* 256Mb */
187
188#define REALVIEW_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */
189#define REALVIEW_LT_BASE 0x80000000 /* Logic Tile expansion */
190
191/*
192 * CompactFlash
193 */
194#define REALVIEW_CF_BASE 0x18000000 /* CompactFlash */
195#define REALVIEW_CF_MEM_BASE 0x18003000 /* SMC for CompactFlash */
196
197/*
198 * Disk on Chip
199 */
200#define REALVIEW_DOC_BASE 0x2C000000
201#define REALVIEW_DOC_SIZE (16 << 20)
202#define REALVIEW_DOC_PAGE_SIZE 512
203#define REALVIEW_DOC_TOTAL_PAGES (DOC_SIZE / PAGE_SIZE)
204
205#define ERASE_UNIT_PAGES 32
206#define START_PAGE 0x80
207
208/*
209 * LED settings, bits [7:0]
210 */
211#define REALVIEW_SYS_LED0 (1 << 0)
212#define REALVIEW_SYS_LED1 (1 << 1)
213#define REALVIEW_SYS_LED2 (1 << 2)
214#define REALVIEW_SYS_LED3 (1 << 3)
215#define REALVIEW_SYS_LED4 (1 << 4)
216#define REALVIEW_SYS_LED5 (1 << 5)
217#define REALVIEW_SYS_LED6 (1 << 6)
218#define REALVIEW_SYS_LED7 (1 << 7)
219
220#define ALL_LEDS 0xFF
221
222#define LED_BANK REALVIEW_SYS_LED
223
224/*
225 * Control registers
226 */
227#define REALVIEW_IDFIELD_OFFSET 0x0 /* RealView build information */
228#define REALVIEW_FLASHPROG_OFFSET 0x4 /* Flash devices */
229#define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */
230#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */
231
232/*
233 * System controller bit assignment
234 */
235#define REALVIEW_REFCLK 0
236#define REALVIEW_TIMCLK 1
237
238#define REALVIEW_TIMER1_EnSel 15
239#define REALVIEW_TIMER2_EnSel 17
240#define REALVIEW_TIMER3_EnSel 19
241#define REALVIEW_TIMER4_EnSel 21
242
243
244#define REALVIEW_CSR_BASE 0x10000000
245#define REALVIEW_CSR_SIZE 0x10000000
246
247#endif /* __ASM_ARCH_PLATFORM_H */
diff --git a/arch/arm/mach-realview/platsmp-dt.c b/arch/arm/mach-realview/platsmp-dt.c
index 6964e8876061..70ca99eb52c6 100644
--- a/arch/arm/mach-realview/platsmp-dt.c
+++ b/arch/arm/mach-realview/platsmp-dt.c
@@ -17,8 +17,7 @@
17#include <asm/smp_scu.h> 17#include <asm/smp_scu.h>
18 18
19#include <plat/platsmp.h> 19#include <plat/platsmp.h>
20 20#include "hotplug.h"
21#include "core.h"
22 21
23#define REALVIEW_SYS_FLAGSSET_OFFSET 0x30 22#define REALVIEW_SYS_FLAGSSET_OFFSET 0x30
24 23
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
deleted file mode 100644
index e8ab69c7abfb..000000000000
--- a/arch/arm/mach-realview/platsmp.c
+++ /dev/null
@@ -1,86 +0,0 @@
1/*
2 * linux/arch/arm/mach-realview/platsmp.c
3 *
4 * Copyright (C) 2002 ARM Ltd.
5 * All Rights Reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/init.h>
12#include <linux/errno.h>
13#include <linux/smp.h>
14#include <linux/io.h>
15
16#include "hardware.h"
17#include <asm/mach-types.h>
18#include <asm/smp_scu.h>
19
20#include "board-eb.h"
21#include "board-pb11mp.h"
22#include "board-pbx.h"
23
24#include <plat/platsmp.h>
25
26#include "core.h"
27
28static void __iomem *scu_base_addr(void)
29{
30 if (machine_is_realview_eb_mp())
31 return __io_address(REALVIEW_EB11MP_SCU_BASE);
32 else if (machine_is_realview_pb11mp())
33 return __io_address(REALVIEW_TC11MP_SCU_BASE);
34 else if (machine_is_realview_pbx() &&
35 (core_tile_pbx11mp() || core_tile_pbxa9mp()))
36 return __io_address(REALVIEW_PBX_TILE_SCU_BASE);
37 else
38 return (void __iomem *)0;
39}
40
41/*
42 * Initialise the CPU possible map early - this describes the CPUs
43 * which may be present or become present in the system.
44 */
45static void __init realview_smp_init_cpus(void)
46{
47 void __iomem *scu_base = scu_base_addr();
48 unsigned int i, ncores;
49
50 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
51
52 /* sanity check */
53 if (ncores > nr_cpu_ids) {
54 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
55 ncores, nr_cpu_ids);
56 ncores = nr_cpu_ids;
57 }
58
59 for (i = 0; i < ncores; i++)
60 set_cpu_possible(i, true);
61}
62
63static void __init realview_smp_prepare_cpus(unsigned int max_cpus)
64{
65
66 scu_enable(scu_base_addr());
67
68 /*
69 * Write the address of secondary startup into the
70 * system-wide flags register. The BootMonitor waits
71 * until it receives a soft interrupt, and then the
72 * secondary CPU branches to this address.
73 */
74 __raw_writel(virt_to_phys(versatile_secondary_startup),
75 __io_address(REALVIEW_SYS_FLAGSSET));
76}
77
78const struct smp_operations realview_smp_ops __initconst = {
79 .smp_init_cpus = realview_smp_init_cpus,
80 .smp_prepare_cpus = realview_smp_prepare_cpus,
81 .smp_secondary_init = versatile_secondary_init,
82 .smp_boot_secondary = versatile_boot_secondary,
83#ifdef CONFIG_HOTPLUG_CPU
84 .cpu_die = realview_cpu_die,
85#endif
86};
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
deleted file mode 100644
index b442fa61e943..000000000000
--- a/arch/arm/mach-realview/realview_eb.c
+++ /dev/null
@@ -1,492 +0,0 @@
1/*
2 * linux/arch/arm/mach-realview/realview_eb.c
3 *
4 * Copyright (C) 2004 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/init.h>
23#include <linux/platform_device.h>
24#include <linux/device.h>
25#include <linux/amba/bus.h>
26#include <linux/amba/pl061.h>
27#include <linux/amba/mmci.h>
28#include <linux/amba/pl022.h>
29#include <linux/io.h>
30#include <linux/irqchip/arm-gic.h>
31#include <linux/platform_data/clk-realview.h>
32#include <linux/reboot.h>
33
34#include "hardware.h"
35#include <asm/irq.h>
36#include <asm/mach-types.h>
37#include <asm/pgtable.h>
38#include <asm/hardware/cache-l2x0.h>
39#include <asm/smp_twd.h>
40#include <asm/system_info.h>
41#include <asm/outercache.h>
42
43#include <asm/mach/arch.h>
44#include <asm/mach/map.h>
45#include <asm/mach/time.h>
46
47#include "board-eb.h"
48#include "irqs-eb.h"
49
50#include "core.h"
51
52static struct map_desc realview_eb_io_desc[] __initdata = {
53 {
54 .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
55 .pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
56 .length = SZ_4K,
57 .type = MT_DEVICE,
58 }, {
59 .virtual = IO_ADDRESS(REALVIEW_EB_GIC_CPU_BASE),
60 .pfn = __phys_to_pfn(REALVIEW_EB_GIC_CPU_BASE),
61 .length = SZ_4K,
62 .type = MT_DEVICE,
63 }, {
64 .virtual = IO_ADDRESS(REALVIEW_EB_GIC_DIST_BASE),
65 .pfn = __phys_to_pfn(REALVIEW_EB_GIC_DIST_BASE),
66 .length = SZ_4K,
67 .type = MT_DEVICE,
68 }, {
69 .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
70 .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
71 .length = SZ_4K,
72 .type = MT_DEVICE,
73 }, {
74 .virtual = IO_ADDRESS(REALVIEW_EB_TIMER0_1_BASE),
75 .pfn = __phys_to_pfn(REALVIEW_EB_TIMER0_1_BASE),
76 .length = SZ_4K,
77 .type = MT_DEVICE,
78 }, {
79 .virtual = IO_ADDRESS(REALVIEW_EB_TIMER2_3_BASE),
80 .pfn = __phys_to_pfn(REALVIEW_EB_TIMER2_3_BASE),
81 .length = SZ_4K,
82 .type = MT_DEVICE,
83 },
84#ifdef CONFIG_DEBUG_LL
85 {
86 .virtual = IO_ADDRESS(REALVIEW_EB_UART0_BASE),
87 .pfn = __phys_to_pfn(REALVIEW_EB_UART0_BASE),
88 .length = SZ_4K,
89 .type = MT_DEVICE,
90 }
91#endif
92};
93
94static struct map_desc realview_eb11mp_io_desc[] __initdata = {
95 {
96 .virtual = IO_ADDRESS(REALVIEW_EB11MP_PRIV_MEM_BASE),
97 .pfn = __phys_to_pfn(REALVIEW_EB11MP_PRIV_MEM_BASE),
98 .length = REALVIEW_EB11MP_PRIV_MEM_SIZE,
99 .type = MT_DEVICE,
100 }, {
101 .virtual = IO_ADDRESS(REALVIEW_EB11MP_L220_BASE),
102 .pfn = __phys_to_pfn(REALVIEW_EB11MP_L220_BASE),
103 .length = SZ_8K,
104 .type = MT_DEVICE,
105 }
106};
107
108static void __init realview_eb_map_io(void)
109{
110 iotable_init(realview_eb_io_desc, ARRAY_SIZE(realview_eb_io_desc));
111 if (core_tile_eb11mp() || core_tile_a9mp())
112 iotable_init(realview_eb11mp_io_desc, ARRAY_SIZE(realview_eb11mp_io_desc));
113}
114
115static struct pl061_platform_data gpio0_plat_data = {
116 .gpio_base = 0,
117};
118
119static struct pl061_platform_data gpio1_plat_data = {
120 .gpio_base = 8,
121};
122
123static struct pl061_platform_data gpio2_plat_data = {
124 .gpio_base = 16,
125};
126
127static struct pl022_ssp_controller ssp0_plat_data = {
128 .bus_id = 0,
129 .enable_dma = 0,
130 .num_chipselect = 1,
131};
132
133/*
134 * RealView EB AMBA devices
135 */
136
137/*
138 * These devices are connected via the core APB bridge
139 */
140#define GPIO2_IRQ { IRQ_EB_GPIO2 }
141#define GPIO3_IRQ { IRQ_EB_GPIO3 }
142
143#define AACI_IRQ { IRQ_EB_AACI }
144#define MMCI0_IRQ { IRQ_EB_MMCI0A, IRQ_EB_MMCI0B }
145#define KMI0_IRQ { IRQ_EB_KMI0 }
146#define KMI1_IRQ { IRQ_EB_KMI1 }
147
148/*
149 * These devices are connected directly to the multi-layer AHB switch
150 */
151#define EB_SMC_IRQ { }
152#define MPMC_IRQ { }
153#define EB_CLCD_IRQ { IRQ_EB_CLCD }
154#define DMAC_IRQ { IRQ_EB_DMA }
155
156/*
157 * These devices are connected via the core APB bridge
158 */
159#define SCTL_IRQ { }
160#define EB_WATCHDOG_IRQ { IRQ_EB_WDOG }
161#define EB_GPIO0_IRQ { IRQ_EB_GPIO0 }
162#define GPIO1_IRQ { IRQ_EB_GPIO1 }
163#define EB_RTC_IRQ { IRQ_EB_RTC }
164
165/*
166 * These devices are connected via the DMA APB bridge
167 */
168#define SCI_IRQ { IRQ_EB_SCI }
169#define EB_UART0_IRQ { IRQ_EB_UART0 }
170#define EB_UART1_IRQ { IRQ_EB_UART1 }
171#define EB_UART2_IRQ { IRQ_EB_UART2 }
172#define EB_UART3_IRQ { IRQ_EB_UART3 }
173#define EB_SSP_IRQ { IRQ_EB_SSP }
174
175/* FPGA Primecells */
176APB_DEVICE(aaci, "fpga:aaci", AACI, NULL);
177APB_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data);
178APB_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL);
179APB_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL);
180APB_DEVICE(uart3, "fpga:uart3", EB_UART3, NULL);
181
182/* DevChip Primecells */
183AHB_DEVICE(smc, "dev:smc", EB_SMC, NULL);
184AHB_DEVICE(clcd, "dev:clcd", EB_CLCD, &clcd_plat_data);
185AHB_DEVICE(dmac, "dev:dmac", DMAC, NULL);
186AHB_DEVICE(sctl, "dev:sctl", SCTL, NULL);
187APB_DEVICE(wdog, "dev:wdog", EB_WATCHDOG, NULL);
188APB_DEVICE(gpio0, "dev:gpio0", EB_GPIO0, &gpio0_plat_data);
189APB_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data);
190APB_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data);
191APB_DEVICE(rtc, "dev:rtc", EB_RTC, NULL);
192APB_DEVICE(sci0, "dev:sci0", SCI, NULL);
193APB_DEVICE(uart0, "dev:uart0", EB_UART0, NULL);
194APB_DEVICE(uart1, "dev:uart1", EB_UART1, NULL);
195APB_DEVICE(uart2, "dev:uart2", EB_UART2, NULL);
196APB_DEVICE(ssp0, "dev:ssp0", EB_SSP, &ssp0_plat_data);
197
198static struct amba_device *amba_devs[] __initdata = {
199 &dmac_device,
200 &uart0_device,
201 &uart1_device,
202 &uart2_device,
203 &uart3_device,
204 &smc_device,
205 &clcd_device,
206 &sctl_device,
207 &wdog_device,
208 &gpio0_device,
209 &gpio1_device,
210 &gpio2_device,
211 &rtc_device,
212 &sci0_device,
213 &ssp0_device,
214 &aaci_device,
215 &mmc0_device,
216 &kmi0_device,
217 &kmi1_device,
218};
219
220/*
221 * RealView EB platform devices
222 */
223static struct resource realview_eb_flash_resource = {
224 .start = REALVIEW_EB_FLASH_BASE,
225 .end = REALVIEW_EB_FLASH_BASE + REALVIEW_EB_FLASH_SIZE - 1,
226 .flags = IORESOURCE_MEM,
227};
228
229static struct resource realview_eb_eth_resources[] = {
230 [0] = {
231 .start = REALVIEW_EB_ETH_BASE,
232 .end = REALVIEW_EB_ETH_BASE + SZ_64K - 1,
233 .flags = IORESOURCE_MEM,
234 },
235 [1] = {
236 .start = IRQ_EB_ETH,
237 .end = IRQ_EB_ETH,
238 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
239 },
240};
241
242/*
243 * Detect and register the correct Ethernet device. RealView/EB rev D
244 * platforms use the newer SMSC LAN9118 Ethernet chip
245 */
246static int eth_device_register(void)
247{
248 void __iomem *eth_addr = ioremap(REALVIEW_EB_ETH_BASE, SZ_4K);
249 const char *name = NULL;
250 u32 idrev;
251
252 if (!eth_addr)
253 return -ENOMEM;
254
255 idrev = readl(eth_addr + 0x50);
256 if ((idrev & 0xFFFF0000) != 0x01180000)
257 /* SMSC LAN9118 not present, use LAN91C111 instead */
258 name = "smc91x";
259
260 iounmap(eth_addr);
261 return realview_eth_register(name, realview_eb_eth_resources);
262}
263
264static struct resource realview_eb_isp1761_resources[] = {
265 [0] = {
266 .start = REALVIEW_EB_USB_BASE,
267 .end = REALVIEW_EB_USB_BASE + SZ_128K - 1,
268 .flags = IORESOURCE_MEM,
269 },
270 [1] = {
271 .start = IRQ_EB_USB,
272 .end = IRQ_EB_USB,
273 .flags = IORESOURCE_IRQ,
274 },
275};
276
277static struct resource pmu_resources[] = {
278 [0] = {
279 .start = IRQ_EB11MP_PMU_CPU0,
280 .end = IRQ_EB11MP_PMU_CPU0,
281 .flags = IORESOURCE_IRQ,
282 },
283 [1] = {
284 .start = IRQ_EB11MP_PMU_CPU1,
285 .end = IRQ_EB11MP_PMU_CPU1,
286 .flags = IORESOURCE_IRQ,
287 },
288 [2] = {
289 .start = IRQ_EB11MP_PMU_CPU2,
290 .end = IRQ_EB11MP_PMU_CPU2,
291 .flags = IORESOURCE_IRQ,
292 },
293 [3] = {
294 .start = IRQ_EB11MP_PMU_CPU3,
295 .end = IRQ_EB11MP_PMU_CPU3,
296 .flags = IORESOURCE_IRQ,
297 },
298};
299
300static struct platform_device pmu_device = {
301 .id = -1,
302 .num_resources = ARRAY_SIZE(pmu_resources),
303 .resource = pmu_resources,
304};
305
306static struct resource char_lcd_resources[] = {
307 {
308 .start = REALVIEW_CHAR_LCD_BASE,
309 .end = (REALVIEW_CHAR_LCD_BASE + SZ_4K - 1),
310 .flags = IORESOURCE_MEM,
311 },
312 {
313 .start = IRQ_EB_CHARLCD,
314 .end = IRQ_EB_CHARLCD,
315 .flags = IORESOURCE_IRQ,
316 },
317};
318
319static struct platform_device char_lcd_device = {
320 .name = "arm-charlcd",
321 .id = -1,
322 .num_resources = ARRAY_SIZE(char_lcd_resources),
323 .resource = char_lcd_resources,
324};
325
326static void __init gic_init_irq(void)
327{
328 if (core_tile_eb11mp() || core_tile_a9mp()) {
329 unsigned int pldctrl;
330
331 /* new irq mode */
332 writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
333 pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1);
334 pldctrl |= 0x00800000;
335 writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1);
336 writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
337
338 /* core tile GIC, primary */
339 gic_init(0, 29, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE),
340 __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
341
342#ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB
343 /* board GIC, secondary */
344 gic_init(1, 96, __io_address(REALVIEW_EB_GIC_DIST_BASE),
345 __io_address(REALVIEW_EB_GIC_CPU_BASE));
346 gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1);
347#endif
348 } else {
349 /* board GIC, primary */
350 gic_init(0, 29, __io_address(REALVIEW_EB_GIC_DIST_BASE),
351 __io_address(REALVIEW_EB_GIC_CPU_BASE));
352 }
353}
354
355/*
356 * Fix up the IRQ numbers for the RealView EB/ARM11MPCore tile
357 */
358static void realview_eb11mp_fixup(void)
359{
360 /* AMBA devices */
361 dmac_device.irq[0] = IRQ_EB11MP_DMA;
362 uart0_device.irq[0] = IRQ_EB11MP_UART0;
363 uart1_device.irq[0] = IRQ_EB11MP_UART1;
364 uart2_device.irq[0] = IRQ_EB11MP_UART2;
365 uart3_device.irq[0] = IRQ_EB11MP_UART3;
366 clcd_device.irq[0] = IRQ_EB11MP_CLCD;
367 wdog_device.irq[0] = IRQ_EB11MP_WDOG;
368 gpio0_device.irq[0] = IRQ_EB11MP_GPIO0;
369 gpio1_device.irq[0] = IRQ_EB11MP_GPIO1;
370 gpio2_device.irq[0] = IRQ_EB11MP_GPIO2;
371 rtc_device.irq[0] = IRQ_EB11MP_RTC;
372 sci0_device.irq[0] = IRQ_EB11MP_SCI;
373 ssp0_device.irq[0] = IRQ_EB11MP_SSP;
374 aaci_device.irq[0] = IRQ_EB11MP_AACI;
375 mmc0_device.irq[0] = IRQ_EB11MP_MMCI0A;
376 mmc0_device.irq[1] = IRQ_EB11MP_MMCI0B;
377 kmi0_device.irq[0] = IRQ_EB11MP_KMI0;
378 kmi1_device.irq[0] = IRQ_EB11MP_KMI1;
379
380 /* platform devices */
381 realview_eb_eth_resources[1].start = IRQ_EB11MP_ETH;
382 realview_eb_eth_resources[1].end = IRQ_EB11MP_ETH;
383 realview_eb_isp1761_resources[1].start = IRQ_EB11MP_USB;
384 realview_eb_isp1761_resources[1].end = IRQ_EB11MP_USB;
385}
386
387#ifdef CONFIG_HAVE_ARM_TWD
388static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
389 REALVIEW_EB11MP_TWD_BASE,
390 IRQ_LOCALTIMER);
391
392static void __init realview_eb_twd_init(void)
393{
394 if (core_tile_eb11mp() || core_tile_a9mp()) {
395 int err = twd_local_timer_register(&twd_local_timer);
396 if (err)
397 pr_err("twd_local_timer_register failed %d\n", err);
398 }
399}
400#else
401#define realview_eb_twd_init() do { } while(0)
402#endif
403
404static void __init realview_eb_timer_init(void)
405{
406 unsigned int timer_irq;
407
408 timer0_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE);
409 timer1_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE) + 0x20;
410 timer2_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE);
411 timer3_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE) + 0x20;
412
413 if (core_tile_eb11mp() || core_tile_a9mp())
414 timer_irq = IRQ_EB11MP_TIMER0_1;
415 else
416 timer_irq = IRQ_EB_TIMER0_1;
417
418 realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
419 realview_timer_init(timer_irq);
420 realview_eb_twd_init();
421}
422
423static void realview_eb_restart(enum reboot_mode mode, const char *cmd)
424{
425 void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
426 void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
427
428 /*
429 * To reset, we hit the on-board reset register
430 * in the system FPGA
431 */
432 __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
433 if (core_tile_eb11mp())
434 __raw_writel(0x0008, reset_ctrl);
435 dsb();
436}
437
438static void __init realview_eb_init(void)
439{
440 int i;
441
442 if (core_tile_eb11mp() || core_tile_a9mp()) {
443 realview_eb11mp_fixup();
444
445#ifdef CONFIG_CACHE_L2X0
446 /*
447 * The PL220 needs to be manually configured as the hardware
448 * doesn't report the correct sizes.
449 * 1MB (128KB/way), 8-way associativity, event monitor and
450 * parity enabled, ignore share bit, no force write allocate
451 * Bits: .... ...0 0111 1001 0000 .... .... ....
452 */
453 l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff);
454
455 /*
456 * due to a bug in the l220 cache controller, we must not call
457 * the sync function. stub it out here instead!
458 */
459 outer_cache.sync = NULL;
460#endif
461 pmu_device.name = core_tile_a9mp() ? "armv7-pmu" : "armv6-pmu";
462 platform_device_register(&pmu_device);
463 }
464
465 realview_flash_register(&realview_eb_flash_resource, 1);
466 platform_device_register(&realview_i2c_device);
467 platform_device_register(&char_lcd_device);
468 platform_device_register(&realview_leds_device);
469 eth_device_register();
470 realview_usb_register(realview_eb_isp1761_resources);
471
472 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
473 struct amba_device *d = amba_devs[i];
474 amba_device_register(d, &iomem_resource);
475 }
476}
477
478MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
479 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
480 .atag_offset = 0x100,
481 .smp = smp_ops(realview_smp_ops),
482 .fixup = realview_fixup,
483 .map_io = realview_eb_map_io,
484 .init_early = realview_init_early,
485 .init_irq = gic_init_irq,
486 .init_time = realview_eb_timer_init,
487 .init_machine = realview_eb_init,
488#ifdef CONFIG_ZONE_DMA
489 .dma_zone_size = SZ_256M,
490#endif
491 .restart = realview_eb_restart,
492MACHINE_END
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
deleted file mode 100644
index 537f3878d501..000000000000
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ /dev/null
@@ -1,395 +0,0 @@
1/*
2 * linux/arch/arm/mach-realview/realview_pb1176.c
3 *
4 * Copyright (C) 2008 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/init.h>
23#include <linux/platform_device.h>
24#include <linux/device.h>
25#include <linux/amba/bus.h>
26#include <linux/amba/pl061.h>
27#include <linux/amba/mmci.h>
28#include <linux/amba/pl022.h>
29#include <linux/mtd/physmap.h>
30#include <linux/mtd/partitions.h>
31#include <linux/io.h>
32#include <linux/irqchip/arm-gic.h>
33#include <linux/platform_data/clk-realview.h>
34#include <linux/reboot.h>
35#include <linux/memblock.h>
36
37#include "hardware.h"
38#include <asm/irq.h>
39#include <asm/mach-types.h>
40#include <asm/pgtable.h>
41#include <asm/hardware/cache-l2x0.h>
42
43#include <asm/mach/arch.h>
44#include <asm/mach/flash.h>
45#include <asm/mach/map.h>
46#include <asm/mach/time.h>
47
48#include "board-pb1176.h"
49#include "irqs-pb1176.h"
50
51#include "core.h"
52
53static struct map_desc realview_pb1176_io_desc[] __initdata = {
54 {
55 .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
56 .pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
57 .length = SZ_4K,
58 .type = MT_DEVICE,
59 }, {
60 .virtual = IO_ADDRESS(REALVIEW_PB1176_GIC_CPU_BASE),
61 .pfn = __phys_to_pfn(REALVIEW_PB1176_GIC_CPU_BASE),
62 .length = SZ_4K,
63 .type = MT_DEVICE,
64 }, {
65 .virtual = IO_ADDRESS(REALVIEW_PB1176_GIC_DIST_BASE),
66 .pfn = __phys_to_pfn(REALVIEW_PB1176_GIC_DIST_BASE),
67 .length = SZ_4K,
68 .type = MT_DEVICE,
69 }, {
70 .virtual = IO_ADDRESS(REALVIEW_DC1176_GIC_CPU_BASE),
71 .pfn = __phys_to_pfn(REALVIEW_DC1176_GIC_CPU_BASE),
72 .length = SZ_4K,
73 .type = MT_DEVICE,
74 }, {
75 .virtual = IO_ADDRESS(REALVIEW_DC1176_GIC_DIST_BASE),
76 .pfn = __phys_to_pfn(REALVIEW_DC1176_GIC_DIST_BASE),
77 .length = SZ_4K,
78 .type = MT_DEVICE,
79 }, {
80 .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
81 .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
82 .length = SZ_4K,
83 .type = MT_DEVICE,
84 }, {
85 .virtual = IO_ADDRESS(REALVIEW_PB1176_TIMER0_1_BASE),
86 .pfn = __phys_to_pfn(REALVIEW_PB1176_TIMER0_1_BASE),
87 .length = SZ_4K,
88 .type = MT_DEVICE,
89 }, {
90 .virtual = IO_ADDRESS(REALVIEW_PB1176_TIMER2_3_BASE),
91 .pfn = __phys_to_pfn(REALVIEW_PB1176_TIMER2_3_BASE),
92 .length = SZ_4K,
93 .type = MT_DEVICE,
94 }, {
95 .virtual = IO_ADDRESS(REALVIEW_PB1176_L220_BASE),
96 .pfn = __phys_to_pfn(REALVIEW_PB1176_L220_BASE),
97 .length = SZ_8K,
98 .type = MT_DEVICE,
99 },
100#ifdef CONFIG_DEBUG_LL
101 {
102 .virtual = IO_ADDRESS(REALVIEW_PB1176_UART0_BASE),
103 .pfn = __phys_to_pfn(REALVIEW_PB1176_UART0_BASE),
104 .length = SZ_4K,
105 .type = MT_DEVICE,
106 },
107#endif
108};
109
110static void __init realview_pb1176_map_io(void)
111{
112 iotable_init(realview_pb1176_io_desc, ARRAY_SIZE(realview_pb1176_io_desc));
113}
114
115static struct pl061_platform_data gpio0_plat_data = {
116 .gpio_base = 0,
117};
118
119static struct pl061_platform_data gpio1_plat_data = {
120 .gpio_base = 8,
121};
122
123static struct pl061_platform_data gpio2_plat_data = {
124 .gpio_base = 16,
125};
126
127static struct pl022_ssp_controller ssp0_plat_data = {
128 .bus_id = 0,
129 .enable_dma = 0,
130 .num_chipselect = 1,
131};
132
133/*
134 * RealView PB1176 AMBA devices
135 */
136#define GPIO2_IRQ { IRQ_PB1176_GPIO2 }
137#define GPIO3_IRQ { IRQ_PB1176_GPIO3 }
138#define AACI_IRQ { IRQ_PB1176_AACI }
139#define MMCI0_IRQ { IRQ_PB1176_MMCI0A, IRQ_PB1176_MMCI0B }
140#define KMI0_IRQ { IRQ_PB1176_KMI0 }
141#define KMI1_IRQ { IRQ_PB1176_KMI1 }
142#define PB1176_SMC_IRQ { }
143#define MPMC_IRQ { }
144#define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD }
145#define SCTL_IRQ { }
146#define PB1176_WATCHDOG_IRQ { IRQ_DC1176_WATCHDOG }
147#define PB1176_GPIO0_IRQ { IRQ_DC1176_GPIO0 }
148#define GPIO1_IRQ { IRQ_PB1176_GPIO1 }
149#define PB1176_RTC_IRQ { IRQ_DC1176_RTC }
150#define SCI_IRQ { IRQ_PB1176_SCI }
151#define PB1176_UART0_IRQ { IRQ_DC1176_UART0 }
152#define PB1176_UART1_IRQ { IRQ_DC1176_UART1 }
153#define PB1176_UART2_IRQ { IRQ_DC1176_UART2 }
154#define PB1176_UART3_IRQ { IRQ_DC1176_UART3 }
155#define PB1176_UART4_IRQ { IRQ_PB1176_UART4 }
156#define PB1176_SSP_IRQ { IRQ_DC1176_SSP }
157
158/* FPGA Primecells */
159APB_DEVICE(aaci, "fpga:aaci", AACI, NULL);
160APB_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data);
161APB_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL);
162APB_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL);
163APB_DEVICE(uart4, "fpga:uart4", PB1176_UART4, NULL);
164
165/* DevChip Primecells */
166AHB_DEVICE(smc, "dev:smc", PB1176_SMC, NULL);
167AHB_DEVICE(sctl, "dev:sctl", SCTL, NULL);
168APB_DEVICE(wdog, "dev:wdog", PB1176_WATCHDOG, NULL);
169APB_DEVICE(gpio0, "dev:gpio0", PB1176_GPIO0, &gpio0_plat_data);
170APB_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data);
171APB_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data);
172APB_DEVICE(rtc, "dev:rtc", PB1176_RTC, NULL);
173APB_DEVICE(sci0, "dev:sci0", SCI, NULL);
174APB_DEVICE(uart0, "dev:uart0", PB1176_UART0, NULL);
175APB_DEVICE(uart1, "dev:uart1", PB1176_UART1, NULL);
176APB_DEVICE(uart2, "dev:uart2", PB1176_UART2, NULL);
177APB_DEVICE(uart3, "dev:uart3", PB1176_UART3, NULL);
178APB_DEVICE(ssp0, "dev:ssp0", PB1176_SSP, &ssp0_plat_data);
179AHB_DEVICE(clcd, "dev:clcd", PB1176_CLCD, &clcd_plat_data);
180
181static struct amba_device *amba_devs[] __initdata = {
182 &uart0_device,
183 &uart1_device,
184 &uart2_device,
185 &uart3_device,
186 &uart4_device,
187 &smc_device,
188 &clcd_device,
189 &sctl_device,
190 &wdog_device,
191 &gpio0_device,
192 &gpio1_device,
193 &gpio2_device,
194 &rtc_device,
195 &sci0_device,
196 &ssp0_device,
197 &aaci_device,
198 &mmc0_device,
199 &kmi0_device,
200 &kmi1_device,
201};
202
203/*
204 * RealView PB1176 platform devices
205 */
206static struct resource realview_pb1176_flash_resources[] = {
207 {
208 .start = REALVIEW_PB1176_FLASH_BASE,
209 .end = REALVIEW_PB1176_FLASH_BASE + REALVIEW_PB1176_FLASH_SIZE - 1,
210 .flags = IORESOURCE_MEM,
211 },
212#ifdef CONFIG_REALVIEW_PB1176_SECURE_FLASH
213 {
214 .start = REALVIEW_PB1176_SEC_FLASH_BASE,
215 .end = REALVIEW_PB1176_SEC_FLASH_BASE + REALVIEW_PB1176_SEC_FLASH_SIZE - 1,
216 .flags = IORESOURCE_MEM,
217 },
218#endif
219};
220
221static struct physmap_flash_data pb1176_rom_pdata = {
222 .probe_type = "map_rom",
223 .width = 4,
224 .nr_parts = 0,
225};
226
227static struct resource pb1176_rom_resources[] = {
228 /*
229 * This exposes the PB1176 DevChip ROM as an MTD ROM mapping.
230 * The reference manual states that this is actually a pseudo-ROM
231 * programmed in NVRAM.
232 */
233 {
234 .start = REALVIEW_DC1176_ROM_BASE,
235 .end = REALVIEW_DC1176_ROM_BASE + SZ_16K - 1,
236 .flags = IORESOURCE_MEM,
237 }
238};
239
240static struct platform_device pb1176_rom_device = {
241 .name = "physmap-flash",
242 .id = -1,
243 .num_resources = ARRAY_SIZE(pb1176_rom_resources),
244 .resource = pb1176_rom_resources,
245 .dev = {
246 .platform_data = &pb1176_rom_pdata,
247 },
248};
249
250static struct resource realview_pb1176_smsc911x_resources[] = {
251 [0] = {
252 .start = REALVIEW_PB1176_ETH_BASE,
253 .end = REALVIEW_PB1176_ETH_BASE + SZ_64K - 1,
254 .flags = IORESOURCE_MEM,
255 },
256 [1] = {
257 .start = IRQ_PB1176_ETH,
258 .end = IRQ_PB1176_ETH,
259 .flags = IORESOURCE_IRQ,
260 },
261};
262
263static struct resource realview_pb1176_isp1761_resources[] = {
264 [0] = {
265 .start = REALVIEW_PB1176_USB_BASE,
266 .end = REALVIEW_PB1176_USB_BASE + SZ_128K - 1,
267 .flags = IORESOURCE_MEM,
268 },
269 [1] = {
270 .start = IRQ_PB1176_USB,
271 .end = IRQ_PB1176_USB,
272 .flags = IORESOURCE_IRQ,
273 },
274};
275
276static struct resource pmu_resource = {
277 .start = IRQ_DC1176_CORE_PMU,
278 .end = IRQ_DC1176_CORE_PMU,
279 .flags = IORESOURCE_IRQ,
280};
281
282static struct platform_device pmu_device = {
283 .name = "armv6-pmu",
284 .id = -1,
285 .num_resources = 1,
286 .resource = &pmu_resource,
287};
288
289static struct resource char_lcd_resources[] = {
290 {
291 .start = REALVIEW_CHAR_LCD_BASE,
292 .end = (REALVIEW_CHAR_LCD_BASE + SZ_4K - 1),
293 .flags = IORESOURCE_MEM,
294 },
295 {
296 .start = IRQ_PB1176_CHARLCD,
297 .end = IRQ_PB1176_CHARLCD,
298 .flags = IORESOURCE_IRQ,
299 },
300};
301
302static struct platform_device char_lcd_device = {
303 .name = "arm-charlcd",
304 .id = -1,
305 .num_resources = ARRAY_SIZE(char_lcd_resources),
306 .resource = char_lcd_resources,
307};
308
309static void __init gic_init_irq(void)
310{
311 /* ARM1176 DevChip GIC, primary */
312 gic_init(0, IRQ_DC1176_GIC_START,
313 __io_address(REALVIEW_DC1176_GIC_DIST_BASE),
314 __io_address(REALVIEW_DC1176_GIC_CPU_BASE));
315
316 /* board GIC, secondary */
317 gic_init(1, IRQ_PB1176_GIC_START,
318 __io_address(REALVIEW_PB1176_GIC_DIST_BASE),
319 __io_address(REALVIEW_PB1176_GIC_CPU_BASE));
320 gic_cascade_irq(1, IRQ_DC1176_PB_IRQ1);
321}
322
323static void __init realview_pb1176_timer_init(void)
324{
325 timer0_va_base = __io_address(REALVIEW_PB1176_TIMER0_1_BASE);
326 timer1_va_base = __io_address(REALVIEW_PB1176_TIMER0_1_BASE) + 0x20;
327 timer2_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE);
328 timer3_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE) + 0x20;
329
330 realview_clk_init(__io_address(REALVIEW_SYS_BASE), true);
331 realview_timer_init(IRQ_DC1176_TIMER0);
332}
333
334static void realview_pb1176_restart(enum reboot_mode mode, const char *cmd)
335{
336 void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
337 void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
338 __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
339 __raw_writel(REALVIEW_PB1176_SYS_SOFT_RESET, reset_ctrl);
340 dsb();
341}
342
343static void realview_pb1176_fixup(struct tag *tags, char **from)
344{
345 /*
346 * RealView PB1176 only has 128MB of RAM mapped at 0.
347 */
348 memblock_add(0, SZ_128M);
349}
350
351static void __init realview_pb1176_init(void)
352{
353 int i;
354
355#ifdef CONFIG_CACHE_L2X0
356 /*
357 * The PL220 needs to be manually configured as the hardware
358 * doesn't report the correct sizes.
359 * 128kB (16kB/way), 8-way associativity, event monitor and
360 * parity enabled, ignore share bit, no force write allocate
361 * Bits: .... ...0 0111 0011 0000 .... .... ....
362 */
363 l2x0_init(__io_address(REALVIEW_PB1176_L220_BASE), 0x00730000, 0xfe000fff);
364#endif
365
366 realview_flash_register(realview_pb1176_flash_resources,
367 ARRAY_SIZE(realview_pb1176_flash_resources));
368 platform_device_register(&pb1176_rom_device);
369 realview_eth_register(NULL, realview_pb1176_smsc911x_resources);
370 platform_device_register(&realview_i2c_device);
371 realview_usb_register(realview_pb1176_isp1761_resources);
372 platform_device_register(&pmu_device);
373 platform_device_register(&char_lcd_device);
374 platform_device_register(&realview_leds_device);
375
376 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
377 struct amba_device *d = amba_devs[i];
378 amba_device_register(d, &iomem_resource);
379 }
380}
381
382MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
383 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
384 .atag_offset = 0x100,
385 .fixup = realview_pb1176_fixup,
386 .map_io = realview_pb1176_map_io,
387 .init_early = realview_init_early,
388 .init_irq = gic_init_irq,
389 .init_time = realview_pb1176_timer_init,
390 .init_machine = realview_pb1176_init,
391#ifdef CONFIG_ZONE_DMA
392 .dma_zone_size = SZ_256M,
393#endif
394 .restart = realview_pb1176_restart,
395MACHINE_END
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
deleted file mode 100644
index a90a0752f157..000000000000
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ /dev/null
@@ -1,385 +0,0 @@
1/*
2 * linux/arch/arm/mach-realview/realview_pb11mp.c
3 *
4 * Copyright (C) 2008 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/init.h>
23#include <linux/platform_device.h>
24#include <linux/device.h>
25#include <linux/amba/bus.h>
26#include <linux/amba/pl061.h>
27#include <linux/amba/mmci.h>
28#include <linux/amba/pl022.h>
29#include <linux/io.h>
30#include <linux/irqchip/arm-gic.h>
31#include <linux/platform_data/clk-realview.h>
32#include <linux/reboot.h>
33
34#include "hardware.h"
35#include <asm/irq.h>
36#include <asm/mach-types.h>
37#include <asm/pgtable.h>
38#include <asm/hardware/cache-l2x0.h>
39#include <asm/smp_twd.h>
40
41#include <asm/mach/arch.h>
42#include <asm/mach/flash.h>
43#include <asm/mach/map.h>
44#include <asm/mach/time.h>
45#include <asm/outercache.h>
46
47#include "board-pb11mp.h"
48#include "irqs-pb11mp.h"
49
50#include "core.h"
51
52static struct map_desc realview_pb11mp_io_desc[] __initdata = {
53 {
54 .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
55 .pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
56 .length = SZ_4K,
57 .type = MT_DEVICE,
58 }, {
59 .virtual = IO_ADDRESS(REALVIEW_PB11MP_GIC_CPU_BASE),
60 .pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_CPU_BASE),
61 .length = SZ_4K,
62 .type = MT_DEVICE,
63 }, {
64 .virtual = IO_ADDRESS(REALVIEW_PB11MP_GIC_DIST_BASE),
65 .pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_DIST_BASE),
66 .length = SZ_4K,
67 .type = MT_DEVICE,
68 }, { /* Maps the SCU, GIC CPU interface, TWD, GIC DIST */
69 .virtual = IO_ADDRESS(REALVIEW_TC11MP_PRIV_MEM_BASE),
70 .pfn = __phys_to_pfn(REALVIEW_TC11MP_PRIV_MEM_BASE),
71 .length = REALVIEW_TC11MP_PRIV_MEM_SIZE,
72 .type = MT_DEVICE,
73 }, {
74 .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
75 .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
76 .length = SZ_4K,
77 .type = MT_DEVICE,
78 }, {
79 .virtual = IO_ADDRESS(REALVIEW_PB11MP_TIMER0_1_BASE),
80 .pfn = __phys_to_pfn(REALVIEW_PB11MP_TIMER0_1_BASE),
81 .length = SZ_4K,
82 .type = MT_DEVICE,
83 }, {
84 .virtual = IO_ADDRESS(REALVIEW_PB11MP_TIMER2_3_BASE),
85 .pfn = __phys_to_pfn(REALVIEW_PB11MP_TIMER2_3_BASE),
86 .length = SZ_4K,
87 .type = MT_DEVICE,
88 }, {
89 .virtual = IO_ADDRESS(REALVIEW_TC11MP_L220_BASE),
90 .pfn = __phys_to_pfn(REALVIEW_TC11MP_L220_BASE),
91 .length = SZ_8K,
92 .type = MT_DEVICE,
93 },
94#ifdef CONFIG_DEBUG_LL
95 {
96 .virtual = IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE),
97 .pfn = __phys_to_pfn(REALVIEW_PB11MP_UART0_BASE),
98 .length = SZ_4K,
99 .type = MT_DEVICE,
100 },
101#endif
102};
103
104static void __init realview_pb11mp_map_io(void)
105{
106 iotable_init(realview_pb11mp_io_desc, ARRAY_SIZE(realview_pb11mp_io_desc));
107}
108
109static struct pl061_platform_data gpio0_plat_data = {
110 .gpio_base = 0,
111};
112
113static struct pl061_platform_data gpio1_plat_data = {
114 .gpio_base = 8,
115};
116
117static struct pl061_platform_data gpio2_plat_data = {
118 .gpio_base = 16,
119};
120
121static struct pl022_ssp_controller ssp0_plat_data = {
122 .bus_id = 0,
123 .enable_dma = 0,
124 .num_chipselect = 1,
125};
126
127/*
128 * RealView PB11MPCore AMBA devices
129 */
130
131#define GPIO2_IRQ { IRQ_PB11MP_GPIO2 }
132#define GPIO3_IRQ { IRQ_PB11MP_GPIO3 }
133#define AACI_IRQ { IRQ_TC11MP_AACI }
134#define MMCI0_IRQ { IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B }
135#define KMI0_IRQ { IRQ_TC11MP_KMI0 }
136#define KMI1_IRQ { IRQ_TC11MP_KMI1 }
137#define PB11MP_SMC_IRQ { }
138#define MPMC_IRQ { }
139#define PB11MP_CLCD_IRQ { IRQ_PB11MP_CLCD }
140#define DMAC_IRQ { IRQ_PB11MP_DMAC }
141#define SCTL_IRQ { }
142#define PB11MP_WATCHDOG_IRQ { IRQ_PB11MP_WATCHDOG }
143#define PB11MP_GPIO0_IRQ { IRQ_PB11MP_GPIO0 }
144#define GPIO1_IRQ { IRQ_PB11MP_GPIO1 }
145#define PB11MP_RTC_IRQ { IRQ_TC11MP_RTC }
146#define SCI_IRQ { IRQ_PB11MP_SCI }
147#define PB11MP_UART0_IRQ { IRQ_TC11MP_UART0 }
148#define PB11MP_UART1_IRQ { IRQ_TC11MP_UART1 }
149#define PB11MP_UART2_IRQ { IRQ_PB11MP_UART2 }
150#define PB11MP_UART3_IRQ { IRQ_PB11MP_UART3 }
151#define PB11MP_SSP_IRQ { IRQ_PB11MP_SSP }
152
153/* FPGA Primecells */
154APB_DEVICE(aaci, "fpga:aaci", AACI, NULL);
155APB_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data);
156APB_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL);
157APB_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL);
158APB_DEVICE(uart3, "fpga:uart3", PB11MP_UART3, NULL);
159
160/* DevChip Primecells */
161AHB_DEVICE(smc, "dev:smc", PB11MP_SMC, NULL);
162AHB_DEVICE(sctl, "dev:sctl", SCTL, NULL);
163APB_DEVICE(wdog, "dev:wdog", PB11MP_WATCHDOG, NULL);
164APB_DEVICE(gpio0, "dev:gpio0", PB11MP_GPIO0, &gpio0_plat_data);
165APB_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data);
166APB_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data);
167APB_DEVICE(rtc, "dev:rtc", PB11MP_RTC, NULL);
168APB_DEVICE(sci0, "dev:sci0", SCI, NULL);
169APB_DEVICE(uart0, "dev:uart0", PB11MP_UART0, NULL);
170APB_DEVICE(uart1, "dev:uart1", PB11MP_UART1, NULL);
171APB_DEVICE(uart2, "dev:uart2", PB11MP_UART2, NULL);
172APB_DEVICE(ssp0, "dev:ssp0", PB11MP_SSP, &ssp0_plat_data);
173
174/* Primecells on the NEC ISSP chip */
175AHB_DEVICE(clcd, "issp:clcd", PB11MP_CLCD, &clcd_plat_data);
176AHB_DEVICE(dmac, "issp:dmac", DMAC, NULL);
177
178static struct amba_device *amba_devs[] __initdata = {
179 &dmac_device,
180 &uart0_device,
181 &uart1_device,
182 &uart2_device,
183 &uart3_device,
184 &smc_device,
185 &clcd_device,
186 &sctl_device,
187 &wdog_device,
188 &gpio0_device,
189 &gpio1_device,
190 &gpio2_device,
191 &rtc_device,
192 &sci0_device,
193 &ssp0_device,
194 &aaci_device,
195 &mmc0_device,
196 &kmi0_device,
197 &kmi1_device,
198};
199
200/*
201 * RealView PB11MPCore platform devices
202 */
203static struct resource realview_pb11mp_flash_resource[] = {
204 [0] = {
205 .start = REALVIEW_PB11MP_FLASH0_BASE,
206 .end = REALVIEW_PB11MP_FLASH0_BASE + REALVIEW_PB11MP_FLASH0_SIZE - 1,
207 .flags = IORESOURCE_MEM,
208 },
209 [1] = {
210 .start = REALVIEW_PB11MP_FLASH1_BASE,
211 .end = REALVIEW_PB11MP_FLASH1_BASE + REALVIEW_PB11MP_FLASH1_SIZE - 1,
212 .flags = IORESOURCE_MEM,
213 },
214};
215
216static struct resource realview_pb11mp_smsc911x_resources[] = {
217 [0] = {
218 .start = REALVIEW_PB11MP_ETH_BASE,
219 .end = REALVIEW_PB11MP_ETH_BASE + SZ_64K - 1,
220 .flags = IORESOURCE_MEM,
221 },
222 [1] = {
223 .start = IRQ_TC11MP_ETH,
224 .end = IRQ_TC11MP_ETH,
225 .flags = IORESOURCE_IRQ,
226 },
227};
228
229static struct resource realview_pb11mp_isp1761_resources[] = {
230 [0] = {
231 .start = REALVIEW_PB11MP_USB_BASE,
232 .end = REALVIEW_PB11MP_USB_BASE + SZ_128K - 1,
233 .flags = IORESOURCE_MEM,
234 },
235 [1] = {
236 .start = IRQ_TC11MP_USB,
237 .end = IRQ_TC11MP_USB,
238 .flags = IORESOURCE_IRQ,
239 },
240};
241
242static struct resource pmu_resources[] = {
243 [0] = {
244 .start = IRQ_TC11MP_PMU_CPU0,
245 .end = IRQ_TC11MP_PMU_CPU0,
246 .flags = IORESOURCE_IRQ,
247 },
248 [1] = {
249 .start = IRQ_TC11MP_PMU_CPU1,
250 .end = IRQ_TC11MP_PMU_CPU1,
251 .flags = IORESOURCE_IRQ,
252 },
253 [2] = {
254 .start = IRQ_TC11MP_PMU_CPU2,
255 .end = IRQ_TC11MP_PMU_CPU2,
256 .flags = IORESOURCE_IRQ,
257 },
258 [3] = {
259 .start = IRQ_TC11MP_PMU_CPU3,
260 .end = IRQ_TC11MP_PMU_CPU3,
261 .flags = IORESOURCE_IRQ,
262 },
263};
264
265static struct platform_device pmu_device = {
266 .name = "armv6-pmu",
267 .id = -1,
268 .num_resources = ARRAY_SIZE(pmu_resources),
269 .resource = pmu_resources,
270};
271
272static void __init gic_init_irq(void)
273{
274 unsigned int pldctrl;
275
276 /* new irq mode with no DCC */
277 writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
278 pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1);
279 pldctrl |= 2 << 22;
280 writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1);
281 writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
282
283 /* ARM11MPCore test chip GIC, primary */
284 gic_init(0, 29, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE),
285 __io_address(REALVIEW_TC11MP_GIC_CPU_BASE));
286
287 /* board GIC, secondary */
288 gic_init(1, IRQ_PB11MP_GIC_START,
289 __io_address(REALVIEW_PB11MP_GIC_DIST_BASE),
290 __io_address(REALVIEW_PB11MP_GIC_CPU_BASE));
291 gic_cascade_irq(1, IRQ_TC11MP_PB_IRQ1);
292}
293
294#ifdef CONFIG_HAVE_ARM_TWD
295static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
296 REALVIEW_TC11MP_TWD_BASE,
297 IRQ_LOCALTIMER);
298
299static void __init realview_pb11mp_twd_init(void)
300{
301 int err = twd_local_timer_register(&twd_local_timer);
302 if (err)
303 pr_err("twd_local_timer_register failed %d\n", err);
304}
305#else
306#define realview_pb11mp_twd_init() do {} while(0)
307#endif
308
309static void __init realview_pb11mp_timer_init(void)
310{
311 timer0_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE);
312 timer1_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE) + 0x20;
313 timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE);
314 timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20;
315
316 realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
317 realview_timer_init(IRQ_TC11MP_TIMER0_1);
318 realview_pb11mp_twd_init();
319}
320
321static void realview_pb11mp_restart(enum reboot_mode mode, const char *cmd)
322{
323 void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
324 void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
325
326 /*
327 * To reset, we hit the on-board reset register
328 * in the system FPGA
329 */
330 __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
331 __raw_writel(0x0000, reset_ctrl);
332 __raw_writel(0x0004, reset_ctrl);
333 dsb();
334}
335
336static void __init realview_pb11mp_init(void)
337{
338 int i;
339
340#ifdef CONFIG_CACHE_L2X0
341 /*
342 * The PL220 needs to be manually configured as the hardware
343 * doesn't report the correct sizes.
344 * 1MB (128KB/way), 8-way associativity, event monitor and
345 * parity enabled, ignore share bit, no force write allocate
346 * Bits: .... ...0 0111 1001 0000 .... .... ....
347 */
348 l2x0_init(__io_address(REALVIEW_TC11MP_L220_BASE), 0x00790000, 0xfe000fff);
349 /*
350 * due to a bug in the l220 cache controller, we must not call
351 * the sync function. stub it out here instead!
352 */
353 outer_cache.sync = NULL;
354#endif
355
356 realview_flash_register(realview_pb11mp_flash_resource,
357 ARRAY_SIZE(realview_pb11mp_flash_resource));
358 realview_eth_register(NULL, realview_pb11mp_smsc911x_resources);
359 platform_device_register(&realview_i2c_device);
360 platform_device_register(&realview_cf_device);
361 platform_device_register(&realview_leds_device);
362 realview_usb_register(realview_pb11mp_isp1761_resources);
363 platform_device_register(&pmu_device);
364
365 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
366 struct amba_device *d = amba_devs[i];
367 amba_device_register(d, &iomem_resource);
368 }
369}
370
371MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
372 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
373 .atag_offset = 0x100,
374 .smp = smp_ops(realview_smp_ops),
375 .fixup = realview_fixup,
376 .map_io = realview_pb11mp_map_io,
377 .init_early = realview_init_early,
378 .init_irq = gic_init_irq,
379 .init_time = realview_pb11mp_timer_init,
380 .init_machine = realview_pb11mp_init,
381#ifdef CONFIG_ZONE_DMA
382 .dma_zone_size = SZ_256M,
383#endif
384 .restart = realview_pb11mp_restart,
385MACHINE_END
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
deleted file mode 100644
index ddafb67c2b6f..000000000000
--- a/arch/arm/mach-realview/realview_pba8.c
+++ /dev/null
@@ -1,307 +0,0 @@
1/*
2 * linux/arch/arm/mach-realview/realview_pba8.c
3 *
4 * Copyright (C) 2008 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/init.h>
23#include <linux/platform_device.h>
24#include <linux/device.h>
25#include <linux/amba/bus.h>
26#include <linux/amba/pl061.h>
27#include <linux/amba/mmci.h>
28#include <linux/amba/pl022.h>
29#include <linux/io.h>
30#include <linux/irqchip/arm-gic.h>
31#include <linux/platform_data/clk-realview.h>
32#include <linux/reboot.h>
33
34#include <asm/irq.h>
35#include <asm/mach-types.h>
36#include <asm/pgtable.h>
37
38#include <asm/mach/arch.h>
39#include <asm/mach/map.h>
40#include <asm/mach/time.h>
41
42#include "hardware.h"
43#include "board-pba8.h"
44#include "irqs-pba8.h"
45
46#include "core.h"
47
48static struct map_desc realview_pba8_io_desc[] __initdata = {
49 {
50 .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
51 .pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
52 .length = SZ_4K,
53 .type = MT_DEVICE,
54 }, {
55 .virtual = IO_ADDRESS(REALVIEW_PBA8_GIC_CPU_BASE),
56 .pfn = __phys_to_pfn(REALVIEW_PBA8_GIC_CPU_BASE),
57 .length = SZ_4K,
58 .type = MT_DEVICE,
59 }, {
60 .virtual = IO_ADDRESS(REALVIEW_PBA8_GIC_DIST_BASE),
61 .pfn = __phys_to_pfn(REALVIEW_PBA8_GIC_DIST_BASE),
62 .length = SZ_4K,
63 .type = MT_DEVICE,
64 }, {
65 .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
66 .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
67 .length = SZ_4K,
68 .type = MT_DEVICE,
69 }, {
70 .virtual = IO_ADDRESS(REALVIEW_PBA8_TIMER0_1_BASE),
71 .pfn = __phys_to_pfn(REALVIEW_PBA8_TIMER0_1_BASE),
72 .length = SZ_4K,
73 .type = MT_DEVICE,
74 }, {
75 .virtual = IO_ADDRESS(REALVIEW_PBA8_TIMER2_3_BASE),
76 .pfn = __phys_to_pfn(REALVIEW_PBA8_TIMER2_3_BASE),
77 .length = SZ_4K,
78 .type = MT_DEVICE,
79 },
80#ifdef CONFIG_DEBUG_LL
81 {
82 .virtual = IO_ADDRESS(REALVIEW_PBA8_UART0_BASE),
83 .pfn = __phys_to_pfn(REALVIEW_PBA8_UART0_BASE),
84 .length = SZ_4K,
85 .type = MT_DEVICE,
86 },
87#endif
88};
89
90static void __init realview_pba8_map_io(void)
91{
92 iotable_init(realview_pba8_io_desc, ARRAY_SIZE(realview_pba8_io_desc));
93}
94
95static struct pl061_platform_data gpio0_plat_data = {
96 .gpio_base = 0,
97};
98
99static struct pl061_platform_data gpio1_plat_data = {
100 .gpio_base = 8,
101};
102
103static struct pl061_platform_data gpio2_plat_data = {
104 .gpio_base = 16,
105};
106
107static struct pl022_ssp_controller ssp0_plat_data = {
108 .bus_id = 0,
109 .enable_dma = 0,
110 .num_chipselect = 1,
111};
112
113/*
114 * RealView PBA8Core AMBA devices
115 */
116
117#define GPIO2_IRQ { IRQ_PBA8_GPIO2 }
118#define GPIO3_IRQ { IRQ_PBA8_GPIO3 }
119#define AACI_IRQ { IRQ_PBA8_AACI }
120#define MMCI0_IRQ { IRQ_PBA8_MMCI0A, IRQ_PBA8_MMCI0B }
121#define KMI0_IRQ { IRQ_PBA8_KMI0 }
122#define KMI1_IRQ { IRQ_PBA8_KMI1 }
123#define PBA8_SMC_IRQ { }
124#define MPMC_IRQ { }
125#define PBA8_CLCD_IRQ { IRQ_PBA8_CLCD }
126#define DMAC_IRQ { IRQ_PBA8_DMAC }
127#define SCTL_IRQ { }
128#define PBA8_WATCHDOG_IRQ { IRQ_PBA8_WATCHDOG }
129#define PBA8_GPIO0_IRQ { IRQ_PBA8_GPIO0 }
130#define GPIO1_IRQ { IRQ_PBA8_GPIO1 }
131#define PBA8_RTC_IRQ { IRQ_PBA8_RTC }
132#define SCI_IRQ { IRQ_PBA8_SCI }
133#define PBA8_UART0_IRQ { IRQ_PBA8_UART0 }
134#define PBA8_UART1_IRQ { IRQ_PBA8_UART1 }
135#define PBA8_UART2_IRQ { IRQ_PBA8_UART2 }
136#define PBA8_UART3_IRQ { IRQ_PBA8_UART3 }
137#define PBA8_SSP_IRQ { IRQ_PBA8_SSP }
138
139/* FPGA Primecells */
140APB_DEVICE(aaci, "fpga:aaci", AACI, NULL);
141APB_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data);
142APB_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL);
143APB_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL);
144APB_DEVICE(uart3, "fpga:uart3", PBA8_UART3, NULL);
145
146/* DevChip Primecells */
147AHB_DEVICE(smc, "dev:smc", PBA8_SMC, NULL);
148AHB_DEVICE(sctl, "dev:sctl", SCTL, NULL);
149APB_DEVICE(wdog, "dev:wdog", PBA8_WATCHDOG, NULL);
150APB_DEVICE(gpio0, "dev:gpio0", PBA8_GPIO0, &gpio0_plat_data);
151APB_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data);
152APB_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data);
153APB_DEVICE(rtc, "dev:rtc", PBA8_RTC, NULL);
154APB_DEVICE(sci0, "dev:sci0", SCI, NULL);
155APB_DEVICE(uart0, "dev:uart0", PBA8_UART0, NULL);
156APB_DEVICE(uart1, "dev:uart1", PBA8_UART1, NULL);
157APB_DEVICE(uart2, "dev:uart2", PBA8_UART2, NULL);
158APB_DEVICE(ssp0, "dev:ssp0", PBA8_SSP, &ssp0_plat_data);
159
160/* Primecells on the NEC ISSP chip */
161AHB_DEVICE(clcd, "issp:clcd", PBA8_CLCD, &clcd_plat_data);
162AHB_DEVICE(dmac, "issp:dmac", DMAC, NULL);
163
164static struct amba_device *amba_devs[] __initdata = {
165 &dmac_device,
166 &uart0_device,
167 &uart1_device,
168 &uart2_device,
169 &uart3_device,
170 &smc_device,
171 &clcd_device,
172 &sctl_device,
173 &wdog_device,
174 &gpio0_device,
175 &gpio1_device,
176 &gpio2_device,
177 &rtc_device,
178 &sci0_device,
179 &ssp0_device,
180 &aaci_device,
181 &mmc0_device,
182 &kmi0_device,
183 &kmi1_device,
184};
185
186/*
187 * RealView PB-A8 platform devices
188 */
189static struct resource realview_pba8_flash_resource[] = {
190 [0] = {
191 .start = REALVIEW_PBA8_FLASH0_BASE,
192 .end = REALVIEW_PBA8_FLASH0_BASE + REALVIEW_PBA8_FLASH0_SIZE - 1,
193 .flags = IORESOURCE_MEM,
194 },
195 [1] = {
196 .start = REALVIEW_PBA8_FLASH1_BASE,
197 .end = REALVIEW_PBA8_FLASH1_BASE + REALVIEW_PBA8_FLASH1_SIZE - 1,
198 .flags = IORESOURCE_MEM,
199 },
200};
201
202static struct resource realview_pba8_smsc911x_resources[] = {
203 [0] = {
204 .start = REALVIEW_PBA8_ETH_BASE,
205 .end = REALVIEW_PBA8_ETH_BASE + SZ_64K - 1,
206 .flags = IORESOURCE_MEM,
207 },
208 [1] = {
209 .start = IRQ_PBA8_ETH,
210 .end = IRQ_PBA8_ETH,
211 .flags = IORESOURCE_IRQ,
212 },
213};
214
215static struct resource realview_pba8_isp1761_resources[] = {
216 [0] = {
217 .start = REALVIEW_PBA8_USB_BASE,
218 .end = REALVIEW_PBA8_USB_BASE + SZ_128K - 1,
219 .flags = IORESOURCE_MEM,
220 },
221 [1] = {
222 .start = IRQ_PBA8_USB,
223 .end = IRQ_PBA8_USB,
224 .flags = IORESOURCE_IRQ,
225 },
226};
227
228static struct resource pmu_resource = {
229 .start = IRQ_PBA8_PMU,
230 .end = IRQ_PBA8_PMU,
231 .flags = IORESOURCE_IRQ,
232};
233
234static struct platform_device pmu_device = {
235 .name = "armv7-pmu",
236 .id = -1,
237 .num_resources = 1,
238 .resource = &pmu_resource,
239};
240
241static void __init gic_init_irq(void)
242{
243 /* ARM PB-A8 on-board GIC */
244 gic_init(0, IRQ_PBA8_GIC_START,
245 __io_address(REALVIEW_PBA8_GIC_DIST_BASE),
246 __io_address(REALVIEW_PBA8_GIC_CPU_BASE));
247}
248
249static void __init realview_pba8_timer_init(void)
250{
251 timer0_va_base = __io_address(REALVIEW_PBA8_TIMER0_1_BASE);
252 timer1_va_base = __io_address(REALVIEW_PBA8_TIMER0_1_BASE) + 0x20;
253 timer2_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE);
254 timer3_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE) + 0x20;
255
256 realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
257 realview_timer_init(IRQ_PBA8_TIMER0_1);
258}
259
260static void realview_pba8_restart(enum reboot_mode mode, const char *cmd)
261{
262 void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
263 void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
264
265 /*
266 * To reset, we hit the on-board reset register
267 * in the system FPGA
268 */
269 __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
270 __raw_writel(0x0000, reset_ctrl);
271 __raw_writel(0x0004, reset_ctrl);
272 dsb();
273}
274
275static void __init realview_pba8_init(void)
276{
277 int i;
278
279 realview_flash_register(realview_pba8_flash_resource,
280 ARRAY_SIZE(realview_pba8_flash_resource));
281 realview_eth_register(NULL, realview_pba8_smsc911x_resources);
282 platform_device_register(&realview_i2c_device);
283 platform_device_register(&realview_cf_device);
284 platform_device_register(&realview_leds_device);
285 realview_usb_register(realview_pba8_isp1761_resources);
286 platform_device_register(&pmu_device);
287
288 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
289 struct amba_device *d = amba_devs[i];
290 amba_device_register(d, &iomem_resource);
291 }
292}
293
294MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
295 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
296 .atag_offset = 0x100,
297 .fixup = realview_fixup,
298 .map_io = realview_pba8_map_io,
299 .init_early = realview_init_early,
300 .init_irq = gic_init_irq,
301 .init_time = realview_pba8_timer_init,
302 .init_machine = realview_pba8_init,
303#ifdef CONFIG_ZONE_DMA
304 .dma_zone_size = SZ_256M,
305#endif
306 .restart = realview_pba8_restart,
307MACHINE_END
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
deleted file mode 100644
index be1cec5fe3ad..000000000000
--- a/arch/arm/mach-realview/realview_pbx.c
+++ /dev/null
@@ -1,402 +0,0 @@
1/*
2 * arch/arm/mach-realview/realview_pbx.c
3 *
4 * Copyright (C) 2009 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/device.h>
24#include <linux/amba/bus.h>
25#include <linux/amba/pl061.h>
26#include <linux/amba/mmci.h>
27#include <linux/amba/pl022.h>
28#include <linux/io.h>
29#include <linux/irqchip/arm-gic.h>
30#include <linux/platform_data/clk-realview.h>
31#include <linux/reboot.h>
32#include <linux/memblock.h>
33
34#include <asm/irq.h>
35#include <asm/mach-types.h>
36#include <asm/smp_twd.h>
37#include <asm/pgtable.h>
38#include <asm/hardware/cache-l2x0.h>
39
40#include <asm/mach/arch.h>
41#include <asm/mach/map.h>
42#include <asm/mach/time.h>
43
44#include "hardware.h"
45#include "board-pbx.h"
46#include "irqs-pbx.h"
47
48#include "core.h"
49
50static struct map_desc realview_pbx_io_desc[] __initdata = {
51 {
52 .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
53 .pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
54 .length = SZ_4K,
55 .type = MT_DEVICE,
56 }, {
57 .virtual = IO_ADDRESS(REALVIEW_PBX_GIC_CPU_BASE),
58 .pfn = __phys_to_pfn(REALVIEW_PBX_GIC_CPU_BASE),
59 .length = SZ_4K,
60 .type = MT_DEVICE,
61 }, {
62 .virtual = IO_ADDRESS(REALVIEW_PBX_GIC_DIST_BASE),
63 .pfn = __phys_to_pfn(REALVIEW_PBX_GIC_DIST_BASE),
64 .length = SZ_4K,
65 .type = MT_DEVICE,
66 }, {
67 .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
68 .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
69 .length = SZ_4K,
70 .type = MT_DEVICE,
71 }, {
72 .virtual = IO_ADDRESS(REALVIEW_PBX_TIMER0_1_BASE),
73 .pfn = __phys_to_pfn(REALVIEW_PBX_TIMER0_1_BASE),
74 .length = SZ_4K,
75 .type = MT_DEVICE,
76 }, {
77 .virtual = IO_ADDRESS(REALVIEW_PBX_TIMER2_3_BASE),
78 .pfn = __phys_to_pfn(REALVIEW_PBX_TIMER2_3_BASE),
79 .length = SZ_4K,
80 .type = MT_DEVICE,
81 },
82#ifdef CONFIG_DEBUG_LL
83 {
84 .virtual = IO_ADDRESS(REALVIEW_PBX_UART0_BASE),
85 .pfn = __phys_to_pfn(REALVIEW_PBX_UART0_BASE),
86 .length = SZ_4K,
87 .type = MT_DEVICE,
88 },
89#endif
90};
91
92static struct map_desc realview_local_io_desc[] __initdata = {
93 {
94 .virtual = IO_ADDRESS(REALVIEW_PBX_TILE_SCU_BASE),
95 .pfn = __phys_to_pfn(REALVIEW_PBX_TILE_SCU_BASE),
96 .length = SZ_4K,
97 .type = MT_DEVICE,
98 }, {
99 .virtual = IO_ADDRESS(REALVIEW_PBX_TILE_GIC_DIST_BASE),
100 .pfn = __phys_to_pfn(REALVIEW_PBX_TILE_GIC_DIST_BASE),
101 .length = SZ_4K,
102 .type = MT_DEVICE,
103 }, {
104 .virtual = IO_ADDRESS(REALVIEW_PBX_TILE_L220_BASE),
105 .pfn = __phys_to_pfn(REALVIEW_PBX_TILE_L220_BASE),
106 .length = SZ_8K,
107 .type = MT_DEVICE,
108 }
109};
110
111static void __init realview_pbx_map_io(void)
112{
113 iotable_init(realview_pbx_io_desc, ARRAY_SIZE(realview_pbx_io_desc));
114 if (core_tile_pbx11mp() || core_tile_pbxa9mp())
115 iotable_init(realview_local_io_desc, ARRAY_SIZE(realview_local_io_desc));
116}
117
118static struct pl061_platform_data gpio0_plat_data = {
119 .gpio_base = 0,
120};
121
122static struct pl061_platform_data gpio1_plat_data = {
123 .gpio_base = 8,
124};
125
126static struct pl061_platform_data gpio2_plat_data = {
127 .gpio_base = 16,
128};
129
130static struct pl022_ssp_controller ssp0_plat_data = {
131 .bus_id = 0,
132 .enable_dma = 0,
133 .num_chipselect = 1,
134};
135
136/*
137 * RealView PBXCore AMBA devices
138 */
139
140#define GPIO2_IRQ { IRQ_PBX_GPIO2 }
141#define GPIO3_IRQ { IRQ_PBX_GPIO3 }
142#define AACI_IRQ { IRQ_PBX_AACI }
143#define MMCI0_IRQ { IRQ_PBX_MMCI0A, IRQ_PBX_MMCI0B }
144#define KMI0_IRQ { IRQ_PBX_KMI0 }
145#define KMI1_IRQ { IRQ_PBX_KMI1 }
146#define PBX_SMC_IRQ { }
147#define MPMC_IRQ { }
148#define PBX_CLCD_IRQ { IRQ_PBX_CLCD }
149#define DMAC_IRQ { IRQ_PBX_DMAC }
150#define SCTL_IRQ { }
151#define PBX_WATCHDOG_IRQ { IRQ_PBX_WATCHDOG }
152#define PBX_GPIO0_IRQ { IRQ_PBX_GPIO0 }
153#define GPIO1_IRQ { IRQ_PBX_GPIO1 }
154#define PBX_RTC_IRQ { IRQ_PBX_RTC }
155#define SCI_IRQ { IRQ_PBX_SCI }
156#define PBX_UART0_IRQ { IRQ_PBX_UART0 }
157#define PBX_UART1_IRQ { IRQ_PBX_UART1 }
158#define PBX_UART2_IRQ { IRQ_PBX_UART2 }
159#define PBX_UART3_IRQ { IRQ_PBX_UART3 }
160#define PBX_SSP_IRQ { IRQ_PBX_SSP }
161
162/* FPGA Primecells */
163APB_DEVICE(aaci, "fpga:aaci", AACI, NULL);
164APB_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data);
165APB_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL);
166APB_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL);
167APB_DEVICE(uart3, "fpga:uart3", PBX_UART3, NULL);
168
169/* DevChip Primecells */
170AHB_DEVICE(smc, "dev:smc", PBX_SMC, NULL);
171AHB_DEVICE(sctl, "dev:sctl", SCTL, NULL);
172APB_DEVICE(wdog, "dev:wdog", PBX_WATCHDOG, NULL);
173APB_DEVICE(gpio0, "dev:gpio0", PBX_GPIO0, &gpio0_plat_data);
174APB_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data);
175APB_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data);
176APB_DEVICE(rtc, "dev:rtc", PBX_RTC, NULL);
177APB_DEVICE(sci0, "dev:sci0", SCI, NULL);
178APB_DEVICE(uart0, "dev:uart0", PBX_UART0, NULL);
179APB_DEVICE(uart1, "dev:uart1", PBX_UART1, NULL);
180APB_DEVICE(uart2, "dev:uart2", PBX_UART2, NULL);
181APB_DEVICE(ssp0, "dev:ssp0", PBX_SSP, &ssp0_plat_data);
182
183/* Primecells on the NEC ISSP chip */
184AHB_DEVICE(clcd, "issp:clcd", PBX_CLCD, &clcd_plat_data);
185AHB_DEVICE(dmac, "issp:dmac", DMAC, NULL);
186
187static struct amba_device *amba_devs[] __initdata = {
188 &dmac_device,
189 &uart0_device,
190 &uart1_device,
191 &uart2_device,
192 &uart3_device,
193 &smc_device,
194 &clcd_device,
195 &sctl_device,
196 &wdog_device,
197 &gpio0_device,
198 &gpio1_device,
199 &gpio2_device,
200 &rtc_device,
201 &sci0_device,
202 &ssp0_device,
203 &aaci_device,
204 &mmc0_device,
205 &kmi0_device,
206 &kmi1_device,
207};
208
209/*
210 * RealView PB-X platform devices
211 */
212static struct resource realview_pbx_flash_resources[] = {
213 [0] = {
214 .start = REALVIEW_PBX_FLASH0_BASE,
215 .end = REALVIEW_PBX_FLASH0_BASE + REALVIEW_PBX_FLASH0_SIZE - 1,
216 .flags = IORESOURCE_MEM,
217 },
218 [1] = {
219 .start = REALVIEW_PBX_FLASH1_BASE,
220 .end = REALVIEW_PBX_FLASH1_BASE + REALVIEW_PBX_FLASH1_SIZE - 1,
221 .flags = IORESOURCE_MEM,
222 },
223};
224
225static struct resource realview_pbx_smsc911x_resources[] = {
226 [0] = {
227 .start = REALVIEW_PBX_ETH_BASE,
228 .end = REALVIEW_PBX_ETH_BASE + SZ_64K - 1,
229 .flags = IORESOURCE_MEM,
230 },
231 [1] = {
232 .start = IRQ_PBX_ETH,
233 .end = IRQ_PBX_ETH,
234 .flags = IORESOURCE_IRQ,
235 },
236};
237
238static struct resource realview_pbx_isp1761_resources[] = {
239 [0] = {
240 .start = REALVIEW_PBX_USB_BASE,
241 .end = REALVIEW_PBX_USB_BASE + SZ_128K - 1,
242 .flags = IORESOURCE_MEM,
243 },
244 [1] = {
245 .start = IRQ_PBX_USB,
246 .end = IRQ_PBX_USB,
247 .flags = IORESOURCE_IRQ,
248 },
249};
250
251#ifdef CONFIG_CACHE_L2X0
252static struct resource pmu_resources[] = {
253 [0] = {
254 .start = IRQ_PBX_PMU_CPU0,
255 .end = IRQ_PBX_PMU_CPU0,
256 .flags = IORESOURCE_IRQ,
257 },
258 [1] = {
259 .start = IRQ_PBX_PMU_CPU1,
260 .end = IRQ_PBX_PMU_CPU1,
261 .flags = IORESOURCE_IRQ,
262 },
263 [2] = {
264 .start = IRQ_PBX_PMU_CPU2,
265 .end = IRQ_PBX_PMU_CPU2,
266 .flags = IORESOURCE_IRQ,
267 },
268 [3] = {
269 .start = IRQ_PBX_PMU_CPU3,
270 .end = IRQ_PBX_PMU_CPU3,
271 .flags = IORESOURCE_IRQ,
272 },
273};
274
275static struct platform_device pmu_device = {
276 .name = "armv7-pmu",
277 .id = -1,
278 .num_resources = ARRAY_SIZE(pmu_resources),
279 .resource = pmu_resources,
280};
281#endif
282
283static void __init gic_init_irq(void)
284{
285 /* ARM PBX on-board GIC */
286 if (core_tile_pbx11mp() || core_tile_pbxa9mp()) {
287 gic_init(0, 29, __io_address(REALVIEW_PBX_TILE_GIC_DIST_BASE),
288 __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE));
289 } else {
290 gic_init(0, IRQ_PBX_GIC_START,
291 __io_address(REALVIEW_PBX_GIC_DIST_BASE),
292 __io_address(REALVIEW_PBX_GIC_CPU_BASE));
293 }
294}
295
296#ifdef CONFIG_HAVE_ARM_TWD
297static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
298 REALVIEW_PBX_TILE_TWD_BASE,
299 IRQ_LOCALTIMER);
300
301static void __init realview_pbx_twd_init(void)
302{
303 int err = twd_local_timer_register(&twd_local_timer);
304 if (err)
305 pr_err("twd_local_timer_register failed %d\n", err);
306}
307#else
308#define realview_pbx_twd_init() do { } while(0)
309#endif
310
311static void __init realview_pbx_timer_init(void)
312{
313 timer0_va_base = __io_address(REALVIEW_PBX_TIMER0_1_BASE);
314 timer1_va_base = __io_address(REALVIEW_PBX_TIMER0_1_BASE) + 0x20;
315 timer2_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE);
316 timer3_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE) + 0x20;
317
318 realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
319 realview_timer_init(IRQ_PBX_TIMER0_1);
320 realview_pbx_twd_init();
321}
322
323static void realview_pbx_fixup(struct tag *tags, char **from)
324{
325#ifdef CONFIG_SPARSEMEM
326 /*
327 * Memory configuration with SPARSEMEM enabled on RealView PBX (see
328 * asm/mach/memory.h for more information).
329 */
330
331 memblock_add(0, SZ_256M);
332 memblock_add(0x20000000, SZ_512M);
333 memblock_add(0x80000000, SZ_256M);
334#else
335 realview_fixup(tags, from);
336#endif
337}
338
339static void realview_pbx_restart(enum reboot_mode mode, const char *cmd)
340{
341 void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
342 void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
343
344 /*
345 * To reset, we hit the on-board reset register
346 * in the system FPGA
347 */
348 __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
349 __raw_writel(0x00F0, reset_ctrl);
350 __raw_writel(0x00F4, reset_ctrl);
351 dsb();
352}
353
354static void __init realview_pbx_init(void)
355{
356 int i;
357
358#ifdef CONFIG_CACHE_L2X0
359 if (core_tile_pbxa9mp()) {
360 void __iomem *l2x0_base =
361 __io_address(REALVIEW_PBX_TILE_L220_BASE);
362
363 /* set RAM latencies to 1 cycle for eASIC */
364 writel(0, l2x0_base + L310_TAG_LATENCY_CTRL);
365 writel(0, l2x0_base + L310_DATA_LATENCY_CTRL);
366
367 /* 16KB way size, 8-way associativity, parity disabled
368 * Bits: .. 0 0 0 0 1 00 1 0 1 001 0 000 0 .... .... .... */
369 l2x0_init(l2x0_base, 0x02520000, 0xc0000fff);
370 platform_device_register(&pmu_device);
371 }
372#endif
373
374 realview_flash_register(realview_pbx_flash_resources,
375 ARRAY_SIZE(realview_pbx_flash_resources));
376 realview_eth_register(NULL, realview_pbx_smsc911x_resources);
377 platform_device_register(&realview_i2c_device);
378 platform_device_register(&realview_cf_device);
379 platform_device_register(&realview_leds_device);
380 realview_usb_register(realview_pbx_isp1761_resources);
381
382 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
383 struct amba_device *d = amba_devs[i];
384 amba_device_register(d, &iomem_resource);
385 }
386}
387
388MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
389 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
390 .atag_offset = 0x100,
391 .smp = smp_ops(realview_smp_ops),
392 .fixup = realview_pbx_fixup,
393 .map_io = realview_pbx_map_io,
394 .init_early = realview_init_early,
395 .init_irq = gic_init_irq,
396 .init_time = realview_pbx_timer_init,
397 .init_machine = realview_pbx_init,
398#ifdef CONFIG_ZONE_DMA
399 .dma_zone_size = SZ_256M,
400#endif
401 .restart = realview_pbx_restart,
402MACHINE_END
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 4a48c9f5f725..09817bae4558 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -22,7 +22,6 @@ config ARCH_RCAR_GEN2
22 select PM_GENERIC_DOMAINS 22 select PM_GENERIC_DOMAINS
23 select RENESAS_IRQC 23 select RENESAS_IRQC
24 select SYS_SUPPORTS_SH_CMT 24 select SYS_SUPPORTS_SH_CMT
25 select PCI_DOMAINS if PCI
26 25
27config ARCH_RMOBILE 26config ARCH_RMOBILE
28 bool 27 bool
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index b7260c2b510c..1b6cae5e78f4 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -20,7 +20,6 @@ config ARCH_SPEAR13XX
20 select HAVE_ARM_TWD if SMP 20 select HAVE_ARM_TWD if SMP
21 select PINCTRL 21 select PINCTRL
22 select MFD_SYSCON 22 select MFD_SYSCON
23 select MIGHT_HAVE_PCI
24 help 23 help
25 Supports for ARM's SPEAR13XX family 24 Supports for ARM's SPEAR13XX family
26 25
diff --git a/arch/arm/mach-versatile/Kconfig b/arch/arm/mach-versatile/Kconfig
index b0cc26284fc9..c257d40ca51d 100644
--- a/arch/arm/mach-versatile/Kconfig
+++ b/arch/arm/mach-versatile/Kconfig
@@ -9,7 +9,6 @@ config ARCH_VERSATILE
9 select CPU_ARM926T 9 select CPU_ARM926T
10 select ICST 10 select ICST
11 select MFD_SYSCON 11 select MFD_SYSCON
12 select MIGHT_HAVE_PCI
13 select PLAT_VERSATILE 12 select PLAT_VERSATILE
14 select POWER_RESET 13 select POWER_RESET
15 select POWER_RESET_VERSATILE 14 select POWER_RESET_VERSATILE
diff --git a/drivers/clk/imx/clk-imx1.c b/drivers/clk/imx/clk-imx1.c
index 99cf802fa51f..eaa462ad09e8 100644
--- a/drivers/clk/imx/clk-imx1.c
+++ b/drivers/clk/imx/clk-imx1.c
@@ -45,10 +45,13 @@ static void __iomem *ccm __initdata;
45#define CCM_PCDR (ccm + 0x0020) 45#define CCM_PCDR (ccm + 0x0020)
46#define SCM_GCCR (ccm + 0x0810) 46#define SCM_GCCR (ccm + 0x0810)
47 47
48static void __init _mx1_clocks_init(unsigned long fref) 48static void __init mx1_clocks_init_dt(struct device_node *np)
49{ 49{
50 ccm = of_iomap(np, 0);
51 BUG_ON(!ccm);
52
50 clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0); 53 clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
51 clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", fref); 54 clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", 32768);
52 clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000); 55 clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000);
53 clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17); 56 clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);
54 clk[IMX1_CLK_CLK32_PREMULT] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1); 57 clk[IMX1_CLK_CLK32_PREMULT] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
@@ -74,45 +77,6 @@ static void __init _mx1_clocks_init(unsigned long fref)
74 clk[IMX1_CLK_USBD_GATE] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0); 77 clk[IMX1_CLK_USBD_GATE] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
75 78
76 imx_check_clocks(clk, ARRAY_SIZE(clk)); 79 imx_check_clocks(clk, ARRAY_SIZE(clk));
77}
78
79int __init mx1_clocks_init(unsigned long fref)
80{
81 ccm = ioremap(MX1_CCM_BASE_ADDR, SZ_4K);
82 BUG_ON(!ccm);
83
84 _mx1_clocks_init(fref);
85
86 clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx-gpt.0");
87 clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx-gpt.0");
88 clk_register_clkdev(clk[IMX1_CLK_DMA_GATE], "ahb", "imx1-dma");
89 clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-dma");
90 clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.0");
91 clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.0");
92 clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.1");
93 clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.1");
94 clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.2");
95 clk_register_clkdev(clk[IMX1_CLK_UART3_GATE], "ipg", "imx1-uart.2");
96 clk_register_clkdev(clk[IMX1_CLK_HCLK], NULL, "imx1-i2c.0");
97 clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.0");
98 clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.0");
99 clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.1");
100 clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.1");
101 clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-fb.0");
102 clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-fb.0");
103 clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ahb", "imx1-fb.0");
104
105 mxc_timer_init(MX1_TIM1_BASE_ADDR, MX1_TIM1_INT, GPT_TYPE_IMX1);
106
107 return 0;
108}
109
110static void __init mx1_clocks_init_dt(struct device_node *np)
111{
112 ccm = of_iomap(np, 0);
113 BUG_ON(!ccm);
114
115 _mx1_clocks_init(32768);
116 80
117 clk_data.clks = clk; 81 clk_data.clks = clk;
118 clk_data.clk_num = ARRAY_SIZE(clk); 82 clk_data.clk_num = ARRAY_SIZE(clk);
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index b372e792adc2..e4dbfc85abdb 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -25,7 +25,7 @@ obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o
25obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o 25obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
26obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o 26obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o
27obj-$(CONFIG_ARM_GIC_PM) += irq-gic-pm.o 27obj-$(CONFIG_ARM_GIC_PM) += irq-gic-pm.o
28obj-$(CONFIG_REALVIEW_DT) += irq-gic-realview.o 28obj-$(CONFIG_ARCH_REALVIEW) += irq-gic-realview.o
29obj-$(CONFIG_ARM_GIC_V2M) += irq-gic-v2m.o 29obj-$(CONFIG_ARM_GIC_V2M) += irq-gic-v2m.o
30obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-common.o 30obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-common.o
31obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v3-its-pci-msi.o irq-gic-v3-its-platform-msi.o 31obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v3-its-pci-msi.o irq-gic-v3-its-platform-msi.o
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
index 392f9eff5fb7..5bcc896a48c3 100644
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -78,7 +78,7 @@ config MTD_PHYSMAP_OF_VERSATILE
78 bool "Support ARM Versatile physmap OF" 78 bool "Support ARM Versatile physmap OF"
79 depends on MTD_PHYSMAP_OF 79 depends on MTD_PHYSMAP_OF
80 depends on MFD_SYSCON 80 depends on MFD_SYSCON
81 default y if (ARCH_INTEGRATOR || ARCH_VERSATILE || REALVIEW_DT) 81 default y if (ARCH_INTEGRATOR || ARCH_VERSATILE || ARCH_REALVIEW)
82 help 82 help
83 This provides some extra DT physmap parsing for the ARM Versatile 83 This provides some extra DT physmap parsing for the ARM Versatile
84 platforms, basically to add a VPP (write protection) callback so 84 platforms, basically to add a VPP (write protection) callback so
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-11 09:43:28 -0400