diff options
| author | Alexandre Belloni <alexandre.belloni@free-electrons.com> | 2015-03-16 10:25:01 -0400 |
|---|---|---|
| committer | Alexandre Belloni <alexandre.belloni@free-electrons.com> | 2015-05-20 10:37:55 -0400 |
| commit | a11683b72da7552b724ee21760df5d19cf53f031 (patch) | |
| tree | f3ed17b1aea7c8f4d78fd1dfea1b65be74338991 | |
| parent | 09099f1942e993b1c63408b5a385883876e3e35e (diff) | |
ARM: at91: remove at91rm9200_sdramc.h
include/soc/at91/at91rm9200_sdramc.h is replaced by
include/linux/mfd/syscon/atmel-smc.h as this is actually a syscon device.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| -rw-r--r-- | include/soc/at91/at91rm9200_sdramc.h | 63 |
1 files changed, 0 insertions, 63 deletions
diff --git a/include/soc/at91/at91rm9200_sdramc.h b/include/soc/at91/at91rm9200_sdramc.h deleted file mode 100644 index aa047f458f1b..000000000000 --- a/include/soc/at91/at91rm9200_sdramc.h +++ /dev/null | |||
| @@ -1,63 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Memory Controllers (SDRAMC only) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91RM9200_SDRAMC_H | ||
| 17 | #define AT91RM9200_SDRAMC_H | ||
| 18 | |||
| 19 | /* SDRAM Controller registers */ | ||
| 20 | #define AT91RM9200_SDRAMC_MR 0x90 /* Mode Register */ | ||
| 21 | #define AT91RM9200_SDRAMC_MODE (0xf << 0) /* Command Mode */ | ||
| 22 | #define AT91RM9200_SDRAMC_MODE_NORMAL (0 << 0) | ||
| 23 | #define AT91RM9200_SDRAMC_MODE_NOP (1 << 0) | ||
| 24 | #define AT91RM9200_SDRAMC_MODE_PRECHARGE (2 << 0) | ||
| 25 | #define AT91RM9200_SDRAMC_MODE_LMR (3 << 0) | ||
| 26 | #define AT91RM9200_SDRAMC_MODE_REFRESH (4 << 0) | ||
| 27 | #define AT91RM9200_SDRAMC_DBW (1 << 4) /* Data Bus Width */ | ||
| 28 | #define AT91RM9200_SDRAMC_DBW_32 (0 << 4) | ||
| 29 | #define AT91RM9200_SDRAMC_DBW_16 (1 << 4) | ||
| 30 | |||
| 31 | #define AT91RM9200_SDRAMC_TR 0x94 /* Refresh Timer Register */ | ||
| 32 | #define AT91RM9200_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */ | ||
| 33 | |||
| 34 | #define AT91RM9200_SDRAMC_CR 0x98 /* Configuration Register */ | ||
| 35 | #define AT91RM9200_SDRAMC_NC (3 << 0) /* Number of Column Bits */ | ||
| 36 | #define AT91RM9200_SDRAMC_NC_8 (0 << 0) | ||
| 37 | #define AT91RM9200_SDRAMC_NC_9 (1 << 0) | ||
| 38 | #define AT91RM9200_SDRAMC_NC_10 (2 << 0) | ||
| 39 | #define AT91RM9200_SDRAMC_NC_11 (3 << 0) | ||
| 40 | #define AT91RM9200_SDRAMC_NR (3 << 2) /* Number of Row Bits */ | ||
| 41 | #define AT91RM9200_SDRAMC_NR_11 (0 << 2) | ||
| 42 | #define AT91RM9200_SDRAMC_NR_12 (1 << 2) | ||
| 43 | #define AT91RM9200_SDRAMC_NR_13 (2 << 2) | ||
| 44 | #define AT91RM9200_SDRAMC_NB (1 << 4) /* Number of Banks */ | ||
| 45 | #define AT91RM9200_SDRAMC_NB_2 (0 << 4) | ||
| 46 | #define AT91RM9200_SDRAMC_NB_4 (1 << 4) | ||
| 47 | #define AT91RM9200_SDRAMC_CAS (3 << 5) /* CAS Latency */ | ||
| 48 | #define AT91RM9200_SDRAMC_CAS_2 (2 << 5) | ||
| 49 | #define AT91RM9200_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */ | ||
| 50 | #define AT91RM9200_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */ | ||
| 51 | #define AT91RM9200_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */ | ||
| 52 | #define AT91RM9200_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */ | ||
| 53 | #define AT91RM9200_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */ | ||
| 54 | #define AT91RM9200_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */ | ||
| 55 | |||
| 56 | #define AT91RM9200_SDRAMC_SRR 0x9c /* Self Refresh Register */ | ||
| 57 | #define AT91RM9200_SDRAMC_LPR 0xa0 /* Low Power Register */ | ||
| 58 | #define AT91RM9200_SDRAMC_IER 0xa4 /* Interrupt Enable Register */ | ||
| 59 | #define AT91RM9200_SDRAMC_IDR 0xa8 /* Interrupt Disable Register */ | ||
| 60 | #define AT91RM9200_SDRAMC_IMR 0xac /* Interrupt Mask Register */ | ||
| 61 | #define AT91RM9200_SDRAMC_ISR 0xb0 /* Interrupt Status Register */ | ||
| 62 | |||
| 63 | #endif | ||