diff options
author | Gabor Juhos <juhosg@openwrt.org> | 2013-02-02 06:44:24 -0500 |
---|---|---|
committer | John Crispin <blogic@openwrt.org> | 2013-02-16 19:25:36 -0500 |
commit | 9fc1ca5b73a82daedffa2d1d5daa48dd2093c39a (patch) | |
tree | 67c462783bdb6ce761886229b8a642e7a27f58d2 | |
parent | ad4ce92e919f7ad5561a2060deb58899de58b40c (diff) |
MIPS: ath79: register platform devices for the PCI controllers
The pci-ar71xx and pci-ar724x drivers were converted
into platform drivers. Register the corresponding
platform devices for the PCI controllers instead
of using the ar7{1x,24}x_pcibios_init functions.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4908/
Signed-off-by: John Crispin <blogic@openwrt.org>
-rw-r--r-- | arch/mips/ath79/pci.c | 87 |
1 files changed, 78 insertions, 9 deletions
diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c index ca83abd9d31e..81ef5797944a 100644 --- a/arch/mips/ath79/pci.c +++ b/arch/mips/ath79/pci.c | |||
@@ -14,6 +14,8 @@ | |||
14 | 14 | ||
15 | #include <linux/init.h> | 15 | #include <linux/init.h> |
16 | #include <linux/pci.h> | 16 | #include <linux/pci.h> |
17 | #include <linux/resource.h> | ||
18 | #include <linux/platform_device.h> | ||
17 | #include <asm/mach-ath79/ar71xx_regs.h> | 19 | #include <asm/mach-ath79/ar71xx_regs.h> |
18 | #include <asm/mach-ath79/ath79.h> | 20 | #include <asm/mach-ath79/ath79.h> |
19 | #include <asm/mach-ath79/irq.h> | 21 | #include <asm/mach-ath79/irq.h> |
@@ -110,21 +112,88 @@ void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)) | |||
110 | ath79_pci_plat_dev_init = func; | 112 | ath79_pci_plat_dev_init = func; |
111 | } | 113 | } |
112 | 114 | ||
113 | int __init ath79_register_pci(void) | 115 | static struct platform_device * |
116 | ath79_register_pci_ar71xx(void) | ||
117 | { | ||
118 | struct platform_device *pdev; | ||
119 | struct resource res[2]; | ||
120 | |||
121 | memset(res, 0, sizeof(res)); | ||
122 | |||
123 | res[0].name = "cfg_base"; | ||
124 | res[0].flags = IORESOURCE_MEM; | ||
125 | res[0].start = AR71XX_PCI_CFG_BASE; | ||
126 | res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1; | ||
127 | |||
128 | res[1].flags = IORESOURCE_IRQ; | ||
129 | res[1].start = ATH79_CPU_IRQ_IP2; | ||
130 | res[1].end = ATH79_CPU_IRQ_IP2; | ||
131 | |||
132 | pdev = platform_device_register_simple("ar71xx-pci", -1, | ||
133 | res, ARRAY_SIZE(res)); | ||
134 | return pdev; | ||
135 | } | ||
136 | |||
137 | static struct platform_device * | ||
138 | ath79_register_pci_ar724x(int id, | ||
139 | unsigned long cfg_base, | ||
140 | unsigned long ctrl_base, | ||
141 | int irq) | ||
114 | { | 142 | { |
115 | if (soc_is_ar71xx()) | 143 | struct platform_device *pdev; |
116 | return ar71xx_pcibios_init(); | 144 | struct resource res[3]; |
117 | 145 | ||
118 | if (soc_is_ar724x()) | 146 | memset(res, 0, sizeof(res)); |
119 | return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2); | ||
120 | 147 | ||
121 | if (soc_is_ar9342() || soc_is_ar9344()) { | 148 | res[0].name = "cfg_base"; |
149 | res[0].flags = IORESOURCE_MEM; | ||
150 | res[0].start = cfg_base; | ||
151 | res[0].end = cfg_base + AR724X_PCI_CFG_SIZE - 1; | ||
152 | |||
153 | res[1].name = "ctrl_base"; | ||
154 | res[1].flags = IORESOURCE_MEM; | ||
155 | res[1].start = ctrl_base; | ||
156 | res[1].end = ctrl_base + AR724X_PCI_CTRL_SIZE - 1; | ||
157 | |||
158 | res[2].flags = IORESOURCE_IRQ; | ||
159 | res[2].start = irq; | ||
160 | res[2].end = irq; | ||
161 | |||
162 | pdev = platform_device_register_simple("ar724x-pci", id, | ||
163 | res, ARRAY_SIZE(res)); | ||
164 | return pdev; | ||
165 | } | ||
166 | |||
167 | int __init ath79_register_pci(void) | ||
168 | { | ||
169 | struct platform_device *pdev = NULL; | ||
170 | |||
171 | if (soc_is_ar71xx()) { | ||
172 | pdev = ath79_register_pci_ar71xx(); | ||
173 | } else if (soc_is_ar724x()) { | ||
174 | pdev = ath79_register_pci_ar724x(-1, | ||
175 | AR724X_PCI_CFG_BASE, | ||
176 | AR724X_PCI_CTRL_BASE, | ||
177 | ATH79_CPU_IRQ_IP2); | ||
178 | } else if (soc_is_ar9342() || | ||
179 | soc_is_ar9344()) { | ||
122 | u32 bootstrap; | 180 | u32 bootstrap; |
123 | 181 | ||
124 | bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); | 182 | bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); |
125 | if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC) | 183 | if ((bootstrap & AR934X_BOOTSTRAP_PCIE_RC) == 0) |
126 | return ar724x_pcibios_init(ATH79_IP2_IRQ(0)); | 184 | return -ENODEV; |
185 | |||
186 | pdev = ath79_register_pci_ar724x(-1, | ||
187 | AR724X_PCI_CFG_BASE, | ||
188 | AR724X_PCI_CTRL_BASE, | ||
189 | ATH79_IP2_IRQ(0)); | ||
190 | } else { | ||
191 | /* No PCI support */ | ||
192 | return -ENODEV; | ||
127 | } | 193 | } |
128 | 194 | ||
129 | return -ENODEV; | 195 | if (!pdev) |
196 | pr_err("unable to register PCI controller device\n"); | ||
197 | |||
198 | return pdev ? 0 : -ENODEV; | ||
130 | } | 199 | } |