diff options
author | Vladimir Murzin <vladimir.murzin@arm.com> | 2017-04-24 05:40:48 -0400 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2017-05-25 09:44:44 -0400 |
commit | 9f6cea2e3bbd6f90b6328423c384083b4572069f (patch) | |
tree | 9545d4000627c97305b9559236d89c98953c2908 | |
parent | 3304f5a1cb874c63fcc48f9021320510a73c03f9 (diff) |
ARM: 8670/1: V7M: Do not corrupt vector table around v7m_invalidate_l1 call
commit 6d80594936914e798b1b54b3bfe4bd68d8418966 upstream.
We save/restore registers around v7m_invalidate_l1 to address pointed
by r12, which is vector table, so the first eight entries are
overwritten with a garbage. We already have stack setup at that stage,
so use it to save/restore register.
Fixes: 6a8146f420be ("ARM: 8609/1: V7M: Add support for the Cortex-M7 processor")
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r-- | arch/arm/mm/proc-v7m.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S index 8dea61640cc1..50497778c2e5 100644 --- a/arch/arm/mm/proc-v7m.S +++ b/arch/arm/mm/proc-v7m.S | |||
@@ -147,10 +147,10 @@ __v7m_setup_cont: | |||
147 | 147 | ||
148 | @ Configure caches (if implemented) | 148 | @ Configure caches (if implemented) |
149 | teq r8, #0 | 149 | teq r8, #0 |
150 | stmneia r12, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6 | 150 | stmneia sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6 |
151 | blne v7m_invalidate_l1 | 151 | blne v7m_invalidate_l1 |
152 | teq r8, #0 @ re-evalutae condition | 152 | teq r8, #0 @ re-evalutae condition |
153 | ldmneia r12, {r0-r6, lr} | 153 | ldmneia sp, {r0-r6, lr} |
154 | 154 | ||
155 | @ Configure the System Control Register to ensure 8-byte stack alignment | 155 | @ Configure the System Control Register to ensure 8-byte stack alignment |
156 | @ Note the STKALIGN bit is either RW or RAO. | 156 | @ Note the STKALIGN bit is either RW or RAO. |