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authorKelvin Cheung <keguang.zhang@gmail.com>2016-04-06 08:34:54 -0400
committerRalf Baechle <ralf@linux-mips.org>2016-05-13 08:02:05 -0400
commit9ec88b60cb481a6862dc98a78400a6945d9675ba (patch)
tree1ab93bc4c34b01530eebae043780ea2469c9f917
parent0d61ed17dd30fc31533ce07750d03bdb34fb6d7a (diff)
MIPS: Loongson1B: Some updates/fixes for LS1B
- Add DMA device - Add NAND device - Add GPIO device - Add LED device - Update the defconfig and rename it to loongson1b_defconfig - Fix ioremap size - Other minor fixes Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Vinod Koul <vinod.koul@intel.com> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Richard Weinberger <richard@nod.at> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Brian Norris <computersforpeace@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-clk@vger.kernel.org Cc: linux-pm@vger.kernel.org Cc: dmaengine@vger.kernel.org Cc: linux-gpio@vger.kernel.org Cc: linux-mtd@lists.infradead.org Patchwork: https://patchwork.linux-mips.org/patch/13033/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat
-rw-r--r--arch/mips/Kconfig2
-rw-r--r--arch/mips/configs/loongson1b_defconfig (renamed from arch/mips/configs/ls1b_defconfig)35
-rw-r--r--arch/mips/include/asm/mach-loongson32/cpufreq.h1
-rw-r--r--arch/mips/include/asm/mach-loongson32/dma.h25
-rw-r--r--arch/mips/include/asm/mach-loongson32/irq.h1
-rw-r--r--arch/mips/include/asm/mach-loongson32/loongson1.h4
-rw-r--r--arch/mips/include/asm/mach-loongson32/nand.h30
-rw-r--r--arch/mips/include/asm/mach-loongson32/platform.h14
-rw-r--r--arch/mips/include/asm/mach-loongson32/regs-clk.h24
-rw-r--r--arch/mips/include/asm/mach-loongson32/regs-mux.h84
-rw-r--r--arch/mips/include/asm/mach-loongson32/regs-pwm.h12
-rw-r--r--arch/mips/loongson32/common/platform.c105
-rw-r--r--arch/mips/loongson32/common/reset.c13
-rw-r--r--arch/mips/loongson32/common/time.c27
-rw-r--r--arch/mips/loongson32/ls1b/board.c67
15 files changed, 340 insertions, 104 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 79a1c6991c08..fbd63ff8eba4 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1387,6 +1387,8 @@ config CPU_LOONGSON1B
1387 bool "Loongson 1B" 1387 bool "Loongson 1B"
1388 depends on SYS_HAS_CPU_LOONGSON1B 1388 depends on SYS_HAS_CPU_LOONGSON1B
1389 select CPU_LOONGSON1 1389 select CPU_LOONGSON1
1390 select ARCH_WANT_OPTIONAL_GPIOLIB
1391 select LEDS_GPIO_REGISTER
1390 help 1392 help
1391 The Loongson 1B is a 32-bit SoC, which implements the MIPS32 1393 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
1392 release 2 instruction set. 1394 release 2 instruction set.
diff --git a/arch/mips/configs/ls1b_defconfig b/arch/mips/configs/loongson1b_defconfig
index 1b2cc1fb26a1..c442f27685f4 100644
--- a/arch/mips/configs/ls1b_defconfig
+++ b/arch/mips/configs/loongson1b_defconfig
@@ -1,19 +1,17 @@
1CONFIG_MACH_LOONGSON32=y 1CONFIG_MACH_LOONGSON32=y
2CONFIG_PREEMPT=y 2CONFIG_PREEMPT=y
3# CONFIG_SECCOMP is not set 3# CONFIG_SECCOMP is not set
4CONFIG_EXPERIMENTAL=y
5# CONFIG_LOCALVERSION_AUTO is not set 4# CONFIG_LOCALVERSION_AUTO is not set
5CONFIG_KERNEL_XZ=y
6CONFIG_SYSVIPC=y 6CONFIG_SYSVIPC=y
7CONFIG_HIGH_RES_TIMERS=y
7CONFIG_BSD_PROCESS_ACCT=y 8CONFIG_BSD_PROCESS_ACCT=y
8CONFIG_BSD_PROCESS_ACCT_V3=y 9CONFIG_BSD_PROCESS_ACCT_V3=y
9CONFIG_HIGH_RES_TIMERS=y
10CONFIG_IKCONFIG=y 10CONFIG_IKCONFIG=y
11CONFIG_IKCONFIG_PROC=y 11CONFIG_IKCONFIG_PROC=y
12CONFIG_LOG_BUF_SHIFT=16 12CONFIG_LOG_BUF_SHIFT=16
13CONFIG_NAMESPACES=y 13CONFIG_NAMESPACES=y
14CONFIG_BLK_DEV_INITRD=y 14CONFIG_CC_OPTIMIZE_FOR_SIZE=y
15CONFIG_RD_BZIP2=y
16CONFIG_RD_LZMA=y
17CONFIG_EXPERT=y 15CONFIG_EXPERT=y
18CONFIG_PERF_EVENTS=y 16CONFIG_PERF_EVENTS=y
19# CONFIG_COMPAT_BRK is not set 17# CONFIG_COMPAT_BRK is not set
@@ -41,6 +39,12 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
41CONFIG_DEVTMPFS=y 39CONFIG_DEVTMPFS=y
42CONFIG_DEVTMPFS_MOUNT=y 40CONFIG_DEVTMPFS_MOUNT=y
43# CONFIG_STANDALONE is not set 41# CONFIG_STANDALONE is not set
42CONFIG_MTD=y
43CONFIG_MTD_CMDLINE_PARTS=y
44CONFIG_MTD_BLOCK=y
45CONFIG_MTD_NAND=y
46CONFIG_MTD_NAND_LOONGSON1=y
47CONFIG_MTD_UBI=y
44CONFIG_BLK_DEV_LOOP=y 48CONFIG_BLK_DEV_LOOP=y
45CONFIG_SCSI=m 49CONFIG_SCSI=m
46# CONFIG_SCSI_PROC_FS is not set 50# CONFIG_SCSI_PROC_FS is not set
@@ -48,7 +52,6 @@ CONFIG_BLK_DEV_SD=m
48# CONFIG_SCSI_LOWLEVEL is not set 52# CONFIG_SCSI_LOWLEVEL is not set
49CONFIG_NETDEVICES=y 53CONFIG_NETDEVICES=y
50# CONFIG_NET_VENDOR_BROADCOM is not set 54# CONFIG_NET_VENDOR_BROADCOM is not set
51# CONFIG_NET_VENDOR_CHELSIO is not set
52# CONFIG_NET_VENDOR_INTEL is not set 55# CONFIG_NET_VENDOR_INTEL is not set
53# CONFIG_NET_VENDOR_MARVELL is not set 56# CONFIG_NET_VENDOR_MARVELL is not set
54# CONFIG_NET_VENDOR_MICREL is not set 57# CONFIG_NET_VENDOR_MICREL is not set
@@ -56,7 +59,6 @@ CONFIG_NETDEVICES=y
56# CONFIG_NET_VENDOR_SEEQ is not set 59# CONFIG_NET_VENDOR_SEEQ is not set
57# CONFIG_NET_VENDOR_SMSC is not set 60# CONFIG_NET_VENDOR_SMSC is not set
58CONFIG_STMMAC_ETH=y 61CONFIG_STMMAC_ETH=y
59CONFIG_STMMAC_DA=y
60# CONFIG_NET_VENDOR_WIZNET is not set 62# CONFIG_NET_VENDOR_WIZNET is not set
61# CONFIG_WLAN is not set 63# CONFIG_WLAN is not set
62CONFIG_INPUT_EVDEV=y 64CONFIG_INPUT_EVDEV=y
@@ -69,18 +71,25 @@ CONFIG_LEGACY_PTY_COUNT=8
69CONFIG_SERIAL_8250=y 71CONFIG_SERIAL_8250=y
70CONFIG_SERIAL_8250_CONSOLE=y 72CONFIG_SERIAL_8250_CONSOLE=y
71# CONFIG_HW_RANDOM is not set 73# CONFIG_HW_RANDOM is not set
74CONFIG_GPIOLIB=y
75CONFIG_GPIO_LOONGSON1=y
72# CONFIG_HWMON is not set 76# CONFIG_HWMON is not set
73# CONFIG_VGA_CONSOLE is not set 77# CONFIG_VGA_CONSOLE is not set
74CONFIG_USB_HID=m
75CONFIG_HID_GENERIC=m 78CONFIG_HID_GENERIC=m
79CONFIG_USB_HID=m
76CONFIG_USB=y 80CONFIG_USB=y
77CONFIG_USB_ANNOUNCE_NEW_DEVICES=y 81CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
78CONFIG_USB_EHCI_HCD=y 82CONFIG_USB_EHCI_HCD=y
79CONFIG_USB_EHCI_HCD_PLATFORM=y
80# CONFIG_USB_EHCI_TT_NEWSCHED is not set 83# CONFIG_USB_EHCI_TT_NEWSCHED is not set
84CONFIG_USB_EHCI_HCD_PLATFORM=y
81CONFIG_USB_STORAGE=m 85CONFIG_USB_STORAGE=m
82CONFIG_USB_SERIAL=m 86CONFIG_USB_SERIAL=m
83CONFIG_USB_SERIAL_PL2303=m 87CONFIG_USB_SERIAL_PL2303=m
88CONFIG_NEW_LEDS=y
89CONFIG_LEDS_CLASS=y
90CONFIG_LEDS_GPIO=y
91CONFIG_LEDS_TRIGGERS=y
92CONFIG_LEDS_TRIGGER_HEARTBEAT=y
84CONFIG_RTC_CLASS=y 93CONFIG_RTC_CLASS=y
85CONFIG_RTC_DRV_LOONGSON1=y 94CONFIG_RTC_DRV_LOONGSON1=y
86# CONFIG_IOMMU_SUPPORT is not set 95# CONFIG_IOMMU_SUPPORT is not set
@@ -96,15 +105,21 @@ CONFIG_VFAT_FS=y
96CONFIG_PROC_KCORE=y 105CONFIG_PROC_KCORE=y
97CONFIG_TMPFS=y 106CONFIG_TMPFS=y
98CONFIG_TMPFS_POSIX_ACL=y 107CONFIG_TMPFS_POSIX_ACL=y
99# CONFIG_MISC_FILESYSTEMS is not set 108CONFIG_UBIFS_FS=y
109CONFIG_UBIFS_FS_ADVANCED_COMPR=y
110CONFIG_UBIFS_ATIME_SUPPORT=y
100CONFIG_NFS_FS=y 111CONFIG_NFS_FS=y
101CONFIG_ROOT_NFS=y 112CONFIG_ROOT_NFS=y
102CONFIG_NLS_CODEPAGE_437=m 113CONFIG_NLS_CODEPAGE_437=m
103CONFIG_NLS_ISO8859_1=m 114CONFIG_NLS_ISO8859_1=m
115CONFIG_DYNAMIC_DEBUG=y
104# CONFIG_ENABLE_WARN_DEPRECATED is not set 116# CONFIG_ENABLE_WARN_DEPRECATED is not set
105# CONFIG_ENABLE_MUST_CHECK is not set 117# CONFIG_ENABLE_MUST_CHECK is not set
118CONFIG_DEBUG_FS=y
106CONFIG_MAGIC_SYSRQ=y 119CONFIG_MAGIC_SYSRQ=y
107# CONFIG_SCHED_DEBUG is not set 120# CONFIG_SCHED_DEBUG is not set
108# CONFIG_DEBUG_PREEMPT is not set 121# CONFIG_DEBUG_PREEMPT is not set
109# CONFIG_FTRACE is not set 122# CONFIG_FTRACE is not set
110# CONFIG_EARLY_PRINTK is not set 123# CONFIG_EARLY_PRINTK is not set
124# CONFIG_CRYPTO_ECHAINIV is not set
125# CONFIG_CRYPTO_HW is not set
diff --git a/arch/mips/include/asm/mach-loongson32/cpufreq.h b/arch/mips/include/asm/mach-loongson32/cpufreq.h
index 6843fa1a608d..2f1ecb081223 100644
--- a/arch/mips/include/asm/mach-loongson32/cpufreq.h
+++ b/arch/mips/include/asm/mach-loongson32/cpufreq.h
@@ -9,7 +9,6 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12
13#ifndef __ASM_MACH_LOONGSON32_CPUFREQ_H 12#ifndef __ASM_MACH_LOONGSON32_CPUFREQ_H
14#define __ASM_MACH_LOONGSON32_CPUFREQ_H 13#define __ASM_MACH_LOONGSON32_CPUFREQ_H
15 14
diff --git a/arch/mips/include/asm/mach-loongson32/dma.h b/arch/mips/include/asm/mach-loongson32/dma.h
new file mode 100644
index 000000000000..ad1dec743ccc
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson32/dma.h
@@ -0,0 +1,25 @@
1/*
2 * Copyright (c) 2015 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * Loongson 1 NAND platform support.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#ifndef __ASM_MACH_LOONGSON32_DMA_H
13#define __ASM_MACH_LOONGSON32_DMA_H
14
15#define LS1X_DMA_CHANNEL0 0
16#define LS1X_DMA_CHANNEL1 1
17#define LS1X_DMA_CHANNEL2 2
18
19struct plat_ls1x_dma {
20 int nr_channels;
21};
22
23extern struct plat_ls1x_dma ls1b_dma_pdata;
24
25#endif /* __ASM_MACH_LOONGSON32_DMA_H */
diff --git a/arch/mips/include/asm/mach-loongson32/irq.h b/arch/mips/include/asm/mach-loongson32/irq.h
index 0d35b994e8d2..c1c744197de4 100644
--- a/arch/mips/include/asm/mach-loongson32/irq.h
+++ b/arch/mips/include/asm/mach-loongson32/irq.h
@@ -9,7 +9,6 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12
13#ifndef __ASM_MACH_LOONGSON32_IRQ_H 12#ifndef __ASM_MACH_LOONGSON32_IRQ_H
14#define __ASM_MACH_LOONGSON32_IRQ_H 13#define __ASM_MACH_LOONGSON32_IRQ_H
15 14
diff --git a/arch/mips/include/asm/mach-loongson32/loongson1.h b/arch/mips/include/asm/mach-loongson32/loongson1.h
index 12aa129aad80..978f6df8970a 100644
--- a/arch/mips/include/asm/mach-loongson32/loongson1.h
+++ b/arch/mips/include/asm/mach-loongson32/loongson1.h
@@ -9,7 +9,6 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12
13#ifndef __ASM_MACH_LOONGSON32_LOONGSON1_H 12#ifndef __ASM_MACH_LOONGSON32_LOONGSON1_H
14#define __ASM_MACH_LOONGSON32_LOONGSON1_H 13#define __ASM_MACH_LOONGSON32_LOONGSON1_H
15 14
@@ -18,6 +17,9 @@
18/* Loongson 1 Register Bases */ 17/* Loongson 1 Register Bases */
19#define LS1X_MUX_BASE 0x1fd00420 18#define LS1X_MUX_BASE 0x1fd00420
20#define LS1X_INTC_BASE 0x1fd01040 19#define LS1X_INTC_BASE 0x1fd01040
20#define LS1X_GPIO0_BASE 0x1fd010c0
21#define LS1X_GPIO1_BASE 0x1fd010c4
22#define LS1X_DMAC_BASE 0x1fd01160
21#define LS1X_EHCI_BASE 0x1fe00000 23#define LS1X_EHCI_BASE 0x1fe00000
22#define LS1X_OHCI_BASE 0x1fe08000 24#define LS1X_OHCI_BASE 0x1fe08000
23#define LS1X_GMAC0_BASE 0x1fe10000 25#define LS1X_GMAC0_BASE 0x1fe10000
diff --git a/arch/mips/include/asm/mach-loongson32/nand.h b/arch/mips/include/asm/mach-loongson32/nand.h
new file mode 100644
index 000000000000..e274912e9de1
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson32/nand.h
@@ -0,0 +1,30 @@
1/*
2 * Copyright (c) 2015 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * Loongson 1 NAND platform support.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#ifndef __ASM_MACH_LOONGSON32_NAND_H
13#define __ASM_MACH_LOONGSON32_NAND_H
14
15#include <linux/dmaengine.h>
16#include <linux/mtd/partitions.h>
17
18struct plat_ls1x_nand {
19 struct mtd_partition *parts;
20 unsigned int nr_parts;
21
22 int hold_cycle;
23 int wait_cycle;
24};
25
26extern struct plat_ls1x_nand ls1b_nand_pdata;
27
28bool ls1x_dma_filter_fn(struct dma_chan *chan, void *param);
29
30#endif /* __ASM_MACH_LOONGSON32_NAND_H */
diff --git a/arch/mips/include/asm/mach-loongson32/platform.h b/arch/mips/include/asm/mach-loongson32/platform.h
index c32f03f3f72c..672531aa9bef 100644
--- a/arch/mips/include/asm/mach-loongson32/platform.h
+++ b/arch/mips/include/asm/mach-loongson32/platform.h
@@ -7,20 +7,28 @@
7 * option) any later version. 7 * option) any later version.
8 */ 8 */
9 9
10
11#ifndef __ASM_MACH_LOONGSON32_PLATFORM_H 10#ifndef __ASM_MACH_LOONGSON32_PLATFORM_H
12#define __ASM_MACH_LOONGSON32_PLATFORM_H 11#define __ASM_MACH_LOONGSON32_PLATFORM_H
13 12
14#include <linux/platform_device.h> 13#include <linux/platform_device.h>
15 14
15#include <dma.h>
16#include <nand.h>
17
16extern struct platform_device ls1x_uart_pdev; 18extern struct platform_device ls1x_uart_pdev;
17extern struct platform_device ls1x_cpufreq_pdev; 19extern struct platform_device ls1x_cpufreq_pdev;
20extern struct platform_device ls1x_dma_pdev;
18extern struct platform_device ls1x_eth0_pdev; 21extern struct platform_device ls1x_eth0_pdev;
19extern struct platform_device ls1x_eth1_pdev; 22extern struct platform_device ls1x_eth1_pdev;
20extern struct platform_device ls1x_ehci_pdev; 23extern struct platform_device ls1x_ehci_pdev;
24extern struct platform_device ls1x_gpio0_pdev;
25extern struct platform_device ls1x_gpio1_pdev;
26extern struct platform_device ls1x_nand_pdev;
21extern struct platform_device ls1x_rtc_pdev; 27extern struct platform_device ls1x_rtc_pdev;
22 28
23extern void __init ls1x_clk_init(void); 29void __init ls1x_clk_init(void);
24extern void __init ls1x_serial_setup(struct platform_device *pdev); 30void __init ls1x_dma_set_platdata(struct plat_ls1x_dma *pdata);
31void __init ls1x_nand_set_platdata(struct plat_ls1x_nand *pdata);
32void __init ls1x_serial_set_uartclk(struct platform_device *pdev);
25 33
26#endif /* __ASM_MACH_LOONGSON32_PLATFORM_H */ 34#endif /* __ASM_MACH_LOONGSON32_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-loongson32/regs-clk.h b/arch/mips/include/asm/mach-loongson32/regs-clk.h
index 1f5a715ac841..4d56fc38f0c4 100644
--- a/arch/mips/include/asm/mach-loongson32/regs-clk.h
+++ b/arch/mips/include/asm/mach-loongson32/regs-clk.h
@@ -19,18 +19,18 @@
19#define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4) 19#define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4)
20 20
21/* Clock PLL Divisor Register Bits */ 21/* Clock PLL Divisor Register Bits */
22#define DIV_DC_EN (0x1 << 31) 22#define DIV_DC_EN BIT(31)
23#define DIV_DC_RST (0x1 << 30) 23#define DIV_DC_RST BIT(30)
24#define DIV_CPU_EN (0x1 << 25) 24#define DIV_CPU_EN BIT(25)
25#define DIV_CPU_RST (0x1 << 24) 25#define DIV_CPU_RST BIT(24)
26#define DIV_DDR_EN (0x1 << 19) 26#define DIV_DDR_EN BIT(19)
27#define DIV_DDR_RST (0x1 << 18) 27#define DIV_DDR_RST BIT(18)
28#define RST_DC_EN (0x1 << 5) 28#define RST_DC_EN BIT(5)
29#define RST_DC (0x1 << 4) 29#define RST_DC BIT(4)
30#define RST_DDR_EN (0x1 << 3) 30#define RST_DDR_EN BIT(3)
31#define RST_DDR (0x1 << 2) 31#define RST_DDR BIT(2)
32#define RST_CPU_EN (0x1 << 1) 32#define RST_CPU_EN BIT(1)
33#define RST_CPU 0x1 33#define RST_CPU BIT(0)
34 34
35#define DIV_DC_SHIFT 26 35#define DIV_DC_SHIFT 26
36#define DIV_CPU_SHIFT 20 36#define DIV_CPU_SHIFT 20
diff --git a/arch/mips/include/asm/mach-loongson32/regs-mux.h b/arch/mips/include/asm/mach-loongson32/regs-mux.h
index 8302d92f2da2..7c394f93cb9e 100644
--- a/arch/mips/include/asm/mach-loongson32/regs-mux.h
+++ b/arch/mips/include/asm/mach-loongson32/regs-mux.h
@@ -19,49 +19,49 @@
19#define LS1X_MUX_CTRL1 LS1X_MUX_REG(0x4) 19#define LS1X_MUX_CTRL1 LS1X_MUX_REG(0x4)
20 20
21/* MUX CTRL0 Register Bits */ 21/* MUX CTRL0 Register Bits */
22#define UART0_USE_PWM23 (0x1 << 28) 22#define UART0_USE_PWM23 BIT(28)
23#define UART0_USE_PWM01 (0x1 << 27) 23#define UART0_USE_PWM01 BIT(27)
24#define UART1_USE_LCD0_5_6_11 (0x1 << 26) 24#define UART1_USE_LCD0_5_6_11 BIT(26)
25#define I2C2_USE_CAN1 (0x1 << 25) 25#define I2C2_USE_CAN1 BIT(25)
26#define I2C1_USE_CAN0 (0x1 << 24) 26#define I2C1_USE_CAN0 BIT(24)
27#define NAND3_USE_UART5 (0x1 << 23) 27#define NAND3_USE_UART5 BIT(23)
28#define NAND3_USE_UART4 (0x1 << 22) 28#define NAND3_USE_UART4 BIT(22)
29#define NAND3_USE_UART1_DAT (0x1 << 21) 29#define NAND3_USE_UART1_DAT BIT(21)
30#define NAND3_USE_UART1_CTS (0x1 << 20) 30#define NAND3_USE_UART1_CTS BIT(20)
31#define NAND3_USE_PWM23 (0x1 << 19) 31#define NAND3_USE_PWM23 BIT(19)
32#define NAND3_USE_PWM01 (0x1 << 18) 32#define NAND3_USE_PWM01 BIT(18)
33#define NAND2_USE_UART5 (0x1 << 17) 33#define NAND2_USE_UART5 BIT(17)
34#define NAND2_USE_UART4 (0x1 << 16) 34#define NAND2_USE_UART4 BIT(16)
35#define NAND2_USE_UART1_DAT (0x1 << 15) 35#define NAND2_USE_UART1_DAT BIT(15)
36#define NAND2_USE_UART1_CTS (0x1 << 14) 36#define NAND2_USE_UART1_CTS BIT(14)
37#define NAND2_USE_PWM23 (0x1 << 13) 37#define NAND2_USE_PWM23 BIT(13)
38#define NAND2_USE_PWM01 (0x1 << 12) 38#define NAND2_USE_PWM01 BIT(12)
39#define NAND1_USE_UART5 (0x1 << 11) 39#define NAND1_USE_UART5 BIT(11)
40#define NAND1_USE_UART4 (0x1 << 10) 40#define NAND1_USE_UART4 BIT(10)
41#define NAND1_USE_UART1_DAT (0x1 << 9) 41#define NAND1_USE_UART1_DAT BIT(9)
42#define NAND1_USE_UART1_CTS (0x1 << 8) 42#define NAND1_USE_UART1_CTS BIT(8)
43#define NAND1_USE_PWM23 (0x1 << 7) 43#define NAND1_USE_PWM23 BIT(7)
44#define NAND1_USE_PWM01 (0x1 << 6) 44#define NAND1_USE_PWM01 BIT(6)
45#define GMAC1_USE_UART1 (0x1 << 4) 45#define GMAC1_USE_UART1 BIT(4)
46#define GMAC1_USE_UART0 (0x1 << 3) 46#define GMAC1_USE_UART0 BIT(3)
47#define LCD_USE_UART0_DAT (0x1 << 2) 47#define LCD_USE_UART0_DAT BIT(2)
48#define LCD_USE_UART15 (0x1 << 1) 48#define LCD_USE_UART15 BIT(1)
49#define LCD_USE_UART0 0x1 49#define LCD_USE_UART0 BIT(0)
50 50
51/* MUX CTRL1 Register Bits */ 51/* MUX CTRL1 Register Bits */
52#define USB_RESET (0x1 << 31) 52#define USB_RESET BIT(31)
53#define SPI1_CS_USE_PWM01 (0x1 << 24) 53#define SPI1_CS_USE_PWM01 BIT(24)
54#define SPI1_USE_CAN (0x1 << 23) 54#define SPI1_USE_CAN BIT(23)
55#define DISABLE_DDR_CONFSPACE (0x1 << 20) 55#define DISABLE_DDR_CONFSPACE BIT(20)
56#define DDR32TO16EN (0x1 << 16) 56#define DDR32TO16EN BIT(16)
57#define GMAC1_SHUT (0x1 << 13) 57#define GMAC1_SHUT BIT(13)
58#define GMAC0_SHUT (0x1 << 12) 58#define GMAC0_SHUT BIT(12)
59#define USB_SHUT (0x1 << 11) 59#define USB_SHUT BIT(11)
60#define UART1_3_USE_CAN1 (0x1 << 5) 60#define UART1_3_USE_CAN1 BIT(5)
61#define UART1_2_USE_CAN0 (0x1 << 4) 61#define UART1_2_USE_CAN0 BIT(4)
62#define GMAC1_USE_TXCLK (0x1 << 3) 62#define GMAC1_USE_TXCLK BIT(3)
63#define GMAC0_USE_TXCLK (0x1 << 2) 63#define GMAC0_USE_TXCLK BIT(2)
64#define GMAC1_USE_PWM23 (0x1 << 1) 64#define GMAC1_USE_PWM23 BIT(1)
65#define GMAC0_USE_PWM01 0x1 65#define GMAC0_USE_PWM01 BIT(0)
66 66
67#endif /* __ASM_MACH_LOONGSON32_REGS_MUX_H */ 67#endif /* __ASM_MACH_LOONGSON32_REGS_MUX_H */
diff --git a/arch/mips/include/asm/mach-loongson32/regs-pwm.h b/arch/mips/include/asm/mach-loongson32/regs-pwm.h
index 69f174ed13a4..4119600ce79a 100644
--- a/arch/mips/include/asm/mach-loongson32/regs-pwm.h
+++ b/arch/mips/include/asm/mach-loongson32/regs-pwm.h
@@ -19,11 +19,11 @@
19#define PWM_CTRL 0xc 19#define PWM_CTRL 0xc
20 20
21/* PWM Control Register Bits */ 21/* PWM Control Register Bits */
22#define CNT_RST (0x1 << 7) 22#define CNT_RST BIT(7)
23#define INT_SR (0x1 << 6) 23#define INT_SR BIT(6)
24#define INT_EN (0x1 << 5) 24#define INT_EN BIT(5)
25#define PWM_SINGLE (0x1 << 4) 25#define PWM_SINGLE BIT(4)
26#define PWM_OE (0x1 << 3) 26#define PWM_OE BIT(3)
27#define CNT_EN 0x1 27#define CNT_EN BIT(0)
28 28
29#endif /* __ASM_MACH_LOONGSON32_REGS_PWM_H */ 29#endif /* __ASM_MACH_LOONGSON32_REGS_PWM_H */
diff --git a/arch/mips/loongson32/common/platform.c b/arch/mips/loongson32/common/platform.c
index ddf1d4cbf31e..f2c714d8fb60 100644
--- a/arch/mips/loongson32/common/platform.c
+++ b/arch/mips/loongson32/common/platform.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com> 2 * Copyright (c) 2011-2016 Zhang, Keguang <keguang.zhang@gmail.com>
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the 5 * under the terms of the GNU General Public License as published by the
@@ -10,14 +10,17 @@
10#include <linux/clk.h> 10#include <linux/clk.h>
11#include <linux/dma-mapping.h> 11#include <linux/dma-mapping.h>
12#include <linux/err.h> 12#include <linux/err.h>
13#include <linux/mtd/partitions.h>
14#include <linux/sizes.h>
13#include <linux/phy.h> 15#include <linux/phy.h>
14#include <linux/serial_8250.h> 16#include <linux/serial_8250.h>
15#include <linux/stmmac.h> 17#include <linux/stmmac.h>
16#include <linux/usb/ehci_pdriver.h> 18#include <linux/usb/ehci_pdriver.h>
17#include <asm-generic/sizes.h>
18 19
19#include <cpufreq.h>
20#include <loongson1.h> 20#include <loongson1.h>
21#include <cpufreq.h>
22#include <dma.h>
23#include <nand.h>
21 24
22/* 8250/16550 compatible UART */ 25/* 8250/16550 compatible UART */
23#define LS1X_UART(_id) \ 26#define LS1X_UART(_id) \
@@ -45,7 +48,7 @@ struct platform_device ls1x_uart_pdev = {
45 }, 48 },
46}; 49};
47 50
48void __init ls1x_serial_setup(struct platform_device *pdev) 51void __init ls1x_serial_set_uartclk(struct platform_device *pdev)
49{ 52{
50 struct clk *clk; 53 struct clk *clk;
51 struct plat_serial8250_port *p; 54 struct plat_serial8250_port *p;
@@ -77,6 +80,42 @@ struct platform_device ls1x_cpufreq_pdev = {
77 }, 80 },
78}; 81};
79 82
83/* DMA */
84static struct resource ls1x_dma_resources[] = {
85 [0] = {
86 .start = LS1X_DMAC_BASE,
87 .end = LS1X_DMAC_BASE + SZ_4 - 1,
88 .flags = IORESOURCE_MEM,
89 },
90 [1] = {
91 .start = LS1X_DMA0_IRQ,
92 .end = LS1X_DMA0_IRQ,
93 .flags = IORESOURCE_IRQ,
94 },
95 [2] = {
96 .start = LS1X_DMA1_IRQ,
97 .end = LS1X_DMA1_IRQ,
98 .flags = IORESOURCE_IRQ,
99 },
100 [3] = {
101 .start = LS1X_DMA2_IRQ,
102 .end = LS1X_DMA2_IRQ,
103 .flags = IORESOURCE_IRQ,
104 },
105};
106
107struct platform_device ls1x_dma_pdev = {
108 .name = "ls1x-dma",
109 .id = -1,
110 .num_resources = ARRAY_SIZE(ls1x_dma_resources),
111 .resource = ls1x_dma_resources,
112};
113
114void __init ls1x_dma_set_platdata(struct plat_ls1x_dma *pdata)
115{
116 ls1x_dma_pdev.dev.platform_data = pdata;
117}
118
80/* Synopsys Ethernet GMAC */ 119/* Synopsys Ethernet GMAC */
81static struct stmmac_mdio_bus_data ls1x_mdio_bus_data = { 120static struct stmmac_mdio_bus_data ls1x_mdio_bus_data = {
82 .phy_mask = 0, 121 .phy_mask = 0,
@@ -198,6 +237,64 @@ struct platform_device ls1x_eth1_pdev = {
198 }, 237 },
199}; 238};
200 239
240/* GPIO */
241static struct resource ls1x_gpio0_resources[] = {
242 [0] = {
243 .start = LS1X_GPIO0_BASE,
244 .end = LS1X_GPIO0_BASE + SZ_4 - 1,
245 .flags = IORESOURCE_MEM,
246 },
247};
248
249struct platform_device ls1x_gpio0_pdev = {
250 .name = "ls1x-gpio",
251 .id = 0,
252 .num_resources = ARRAY_SIZE(ls1x_gpio0_resources),
253 .resource = ls1x_gpio0_resources,
254};
255
256static struct resource ls1x_gpio1_resources[] = {
257 [0] = {
258 .start = LS1X_GPIO1_BASE,
259 .end = LS1X_GPIO1_BASE + SZ_4 - 1,
260 .flags = IORESOURCE_MEM,
261 },
262};
263
264struct platform_device ls1x_gpio1_pdev = {
265 .name = "ls1x-gpio",
266 .id = 1,
267 .num_resources = ARRAY_SIZE(ls1x_gpio1_resources),
268 .resource = ls1x_gpio1_resources,
269};
270
271/* NAND Flash */
272static struct resource ls1x_nand_resources[] = {
273 [0] = {
274 .start = LS1X_NAND_BASE,
275 .end = LS1X_NAND_BASE + SZ_32 - 1,
276 .flags = IORESOURCE_MEM,
277 },
278 [1] = {
279 /* DMA channel 0 is dedicated to NAND */
280 .start = LS1X_DMA_CHANNEL0,
281 .end = LS1X_DMA_CHANNEL0,
282 .flags = IORESOURCE_DMA,
283 },
284};
285
286struct platform_device ls1x_nand_pdev = {
287 .name = "ls1x-nand",
288 .id = -1,
289 .num_resources = ARRAY_SIZE(ls1x_nand_resources),
290 .resource = ls1x_nand_resources,
291};
292
293void __init ls1x_nand_set_platdata(struct plat_ls1x_nand *pdata)
294{
295 ls1x_nand_pdev.dev.platform_data = pdata;
296}
297
201/* USB EHCI */ 298/* USB EHCI */
202static u64 ls1x_ehci_dmamask = DMA_BIT_MASK(32); 299static u64 ls1x_ehci_dmamask = DMA_BIT_MASK(32);
203 300
diff --git a/arch/mips/loongson32/common/reset.c b/arch/mips/loongson32/common/reset.c
index c41e4ca56ab4..8a1d9cc5a134 100644
--- a/arch/mips/loongson32/common/reset.c
+++ b/arch/mips/loongson32/common/reset.c
@@ -9,12 +9,13 @@
9 9
10#include <linux/io.h> 10#include <linux/io.h>
11#include <linux/pm.h> 11#include <linux/pm.h>
12#include <linux/sizes.h>
12#include <asm/idle.h> 13#include <asm/idle.h>
13#include <asm/reboot.h> 14#include <asm/reboot.h>
14 15
15#include <loongson1.h> 16#include <loongson1.h>
16 17
17static void __iomem *wdt_base; 18static void __iomem *wdt_reg_base;
18 19
19static void ls1x_halt(void) 20static void ls1x_halt(void)
20{ 21{
@@ -26,9 +27,9 @@ static void ls1x_halt(void)
26 27
27static void ls1x_restart(char *command) 28static void ls1x_restart(char *command)
28{ 29{
29 __raw_writel(0x1, wdt_base + WDT_EN); 30 __raw_writel(0x1, wdt_reg_base + WDT_EN);
30 __raw_writel(0x1, wdt_base + WDT_TIMER); 31 __raw_writel(0x1, wdt_reg_base + WDT_TIMER);
31 __raw_writel(0x1, wdt_base + WDT_SET); 32 __raw_writel(0x1, wdt_reg_base + WDT_SET);
32 33
33 ls1x_halt(); 34 ls1x_halt();
34} 35}
@@ -40,8 +41,8 @@ static void ls1x_power_off(void)
40 41
41static int __init ls1x_reboot_setup(void) 42static int __init ls1x_reboot_setup(void)
42{ 43{
43 wdt_base = ioremap_nocache(LS1X_WDT_BASE, 0x0f); 44 wdt_reg_base = ioremap_nocache(LS1X_WDT_BASE, (SZ_4 + SZ_8));
44 if (!wdt_base) 45 if (!wdt_reg_base)
45 panic("Failed to remap watchdog registers"); 46 panic("Failed to remap watchdog registers");
46 47
47 _machine_restart = ls1x_restart; 48 _machine_restart = ls1x_restart;
diff --git a/arch/mips/loongson32/common/time.c b/arch/mips/loongson32/common/time.c
index 0996b025eeef..ff224f0020e5 100644
--- a/arch/mips/loongson32/common/time.c
+++ b/arch/mips/loongson32/common/time.c
@@ -9,6 +9,7 @@
9 9
10#include <linux/clk.h> 10#include <linux/clk.h>
11#include <linux/interrupt.h> 11#include <linux/interrupt.h>
12#include <linux/sizes.h>
12#include <asm/time.h> 13#include <asm/time.h>
13 14
14#include <loongson1.h> 15#include <loongson1.h>
@@ -35,25 +36,25 @@
35 36
36DEFINE_RAW_SPINLOCK(ls1x_timer_lock); 37DEFINE_RAW_SPINLOCK(ls1x_timer_lock);
37 38
38static void __iomem *timer_base; 39static void __iomem *timer_reg_base;
39static uint32_t ls1x_jiffies_per_tick; 40static uint32_t ls1x_jiffies_per_tick;
40 41
41static inline void ls1x_pwmtimer_set_period(uint32_t period) 42static inline void ls1x_pwmtimer_set_period(uint32_t period)
42{ 43{
43 __raw_writel(period, timer_base + PWM_HRC); 44 __raw_writel(period, timer_reg_base + PWM_HRC);
44 __raw_writel(period, timer_base + PWM_LRC); 45 __raw_writel(period, timer_reg_base + PWM_LRC);
45} 46}
46 47
47static inline void ls1x_pwmtimer_restart(void) 48static inline void ls1x_pwmtimer_restart(void)
48{ 49{
49 __raw_writel(0x0, timer_base + PWM_CNT); 50 __raw_writel(0x0, timer_reg_base + PWM_CNT);
50 __raw_writel(INT_EN | CNT_EN, timer_base + PWM_CTRL); 51 __raw_writel(INT_EN | CNT_EN, timer_reg_base + PWM_CTRL);
51} 52}
52 53
53void __init ls1x_pwmtimer_init(void) 54void __init ls1x_pwmtimer_init(void)
54{ 55{
55 timer_base = ioremap(LS1X_TIMER_BASE, 0xf); 56 timer_reg_base = ioremap_nocache(LS1X_TIMER_BASE, SZ_16);
56 if (!timer_base) 57 if (!timer_reg_base)
57 panic("Failed to remap timer registers"); 58 panic("Failed to remap timer registers");
58 59
59 ls1x_jiffies_per_tick = DIV_ROUND_CLOSEST(mips_hpt_frequency, HZ); 60 ls1x_jiffies_per_tick = DIV_ROUND_CLOSEST(mips_hpt_frequency, HZ);
@@ -86,7 +87,7 @@ static cycle_t ls1x_clocksource_read(struct clocksource *cs)
86 */ 87 */
87 jifs = jiffies; 88 jifs = jiffies;
88 /* read the count */ 89 /* read the count */
89 count = __raw_readl(timer_base + PWM_CNT); 90 count = __raw_readl(timer_reg_base + PWM_CNT);
90 91
91 /* 92 /*
92 * It's possible for count to appear to go the wrong way for this 93 * It's possible for count to appear to go the wrong way for this
@@ -131,7 +132,7 @@ static int ls1x_clockevent_set_state_periodic(struct clock_event_device *cd)
131 raw_spin_lock(&ls1x_timer_lock); 132 raw_spin_lock(&ls1x_timer_lock);
132 ls1x_pwmtimer_set_period(ls1x_jiffies_per_tick); 133 ls1x_pwmtimer_set_period(ls1x_jiffies_per_tick);
133 ls1x_pwmtimer_restart(); 134 ls1x_pwmtimer_restart();
134 __raw_writel(INT_EN | CNT_EN, timer_base + PWM_CTRL); 135 __raw_writel(INT_EN | CNT_EN, timer_reg_base + PWM_CTRL);
135 raw_spin_unlock(&ls1x_timer_lock); 136 raw_spin_unlock(&ls1x_timer_lock);
136 137
137 return 0; 138 return 0;
@@ -140,7 +141,7 @@ static int ls1x_clockevent_set_state_periodic(struct clock_event_device *cd)
140static int ls1x_clockevent_tick_resume(struct clock_event_device *cd) 141static int ls1x_clockevent_tick_resume(struct clock_event_device *cd)
141{ 142{
142 raw_spin_lock(&ls1x_timer_lock); 143 raw_spin_lock(&ls1x_timer_lock);
143 __raw_writel(INT_EN | CNT_EN, timer_base + PWM_CTRL); 144 __raw_writel(INT_EN | CNT_EN, timer_reg_base + PWM_CTRL);
144 raw_spin_unlock(&ls1x_timer_lock); 145 raw_spin_unlock(&ls1x_timer_lock);
145 146
146 return 0; 147 return 0;
@@ -149,8 +150,8 @@ static int ls1x_clockevent_tick_resume(struct clock_event_device *cd)
149static int ls1x_clockevent_set_state_shutdown(struct clock_event_device *cd) 150static int ls1x_clockevent_set_state_shutdown(struct clock_event_device *cd)
150{ 151{
151 raw_spin_lock(&ls1x_timer_lock); 152 raw_spin_lock(&ls1x_timer_lock);
152 __raw_writel(__raw_readl(timer_base + PWM_CTRL) & ~CNT_EN, 153 __raw_writel(__raw_readl(timer_reg_base + PWM_CTRL) & ~CNT_EN,
153 timer_base + PWM_CTRL); 154 timer_reg_base + PWM_CTRL);
154 raw_spin_unlock(&ls1x_timer_lock); 155 raw_spin_unlock(&ls1x_timer_lock);
155 156
156 return 0; 157 return 0;
@@ -220,7 +221,7 @@ void __init plat_time_init(void)
220 221
221#ifdef CONFIG_CEVT_CSRC_LS1X 222#ifdef CONFIG_CEVT_CSRC_LS1X
222 /* setup LS1X PWM timer */ 223 /* setup LS1X PWM timer */
223 clk = clk_get(NULL, "ls1x_pwmtimer"); 224 clk = clk_get(NULL, "ls1x-pwmtimer");
224 if (IS_ERR(clk)) 225 if (IS_ERR(clk))
225 panic("unable to get timer clock, err=%ld", PTR_ERR(clk)); 226 panic("unable to get timer clock, err=%ld", PTR_ERR(clk));
226 227
diff --git a/arch/mips/loongson32/ls1b/board.c b/arch/mips/loongson32/ls1b/board.c
index 58daeea25739..38a1d404be1b 100644
--- a/arch/mips/loongson32/ls1b/board.c
+++ b/arch/mips/loongson32/ls1b/board.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com> 2 * Copyright (c) 2011-2016 Zhang, Keguang <keguang.zhang@gmail.com>
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the 5 * under the terms of the GNU General Public License as published by the
@@ -7,26 +7,83 @@
7 * option) any later version. 7 * option) any later version.
8 */ 8 */
9 9
10#include <linux/leds.h>
11#include <linux/mtd/partitions.h>
12#include <linux/sizes.h>
13
14#include <loongson1.h>
15#include <dma.h>
16#include <nand.h>
10#include <platform.h> 17#include <platform.h>
11 18
19struct plat_ls1x_dma ls1x_dma_pdata = {
20 .nr_channels = 3,
21};
22
23static struct mtd_partition ls1x_nand_parts[] = {
24 {
25 .name = "kernel",
26 .offset = 0,
27 .size = SZ_16M,
28 },
29 {
30 .name = "rootfs",
31 .offset = MTDPART_OFS_APPEND,
32 .size = MTDPART_SIZ_FULL,
33 },
34};
35
36struct plat_ls1x_nand ls1x_nand_pdata = {
37 .parts = ls1x_nand_parts,
38 .nr_parts = ARRAY_SIZE(ls1x_nand_parts),
39 .hold_cycle = 0x2,
40 .wait_cycle = 0xc,
41};
42
43static const struct gpio_led ls1x_gpio_leds[] __initconst = {
44 {
45 .name = "LED9",
46 .default_trigger = "heartbeat",
47 .gpio = 38,
48 .active_low = 1,
49 .default_state = LEDS_GPIO_DEFSTATE_OFF,
50 }, {
51 .name = "LED6",
52 .default_trigger = "nand-disk",
53 .gpio = 39,
54 .active_low = 1,
55 .default_state = LEDS_GPIO_DEFSTATE_OFF,
56 },
57};
58
59static const struct gpio_led_platform_data ls1x_led_pdata __initconst = {
60 .num_leds = ARRAY_SIZE(ls1x_gpio_leds),
61 .leds = ls1x_gpio_leds,
62};
63
12static struct platform_device *ls1b_platform_devices[] __initdata = { 64static struct platform_device *ls1b_platform_devices[] __initdata = {
13 &ls1x_uart_pdev, 65 &ls1x_uart_pdev,
14 &ls1x_cpufreq_pdev, 66 &ls1x_cpufreq_pdev,
67 &ls1x_dma_pdev,
15 &ls1x_eth0_pdev, 68 &ls1x_eth0_pdev,
16 &ls1x_eth1_pdev, 69 &ls1x_eth1_pdev,
17 &ls1x_ehci_pdev, 70 &ls1x_ehci_pdev,
71 &ls1x_gpio0_pdev,
72 &ls1x_gpio1_pdev,
73 &ls1x_nand_pdev,
18 &ls1x_rtc_pdev, 74 &ls1x_rtc_pdev,
19}; 75};
20 76
21static int __init ls1b_platform_init(void) 77static int __init ls1b_platform_init(void)
22{ 78{
23 int err; 79 ls1x_serial_set_uartclk(&ls1x_uart_pdev);
80 ls1x_dma_set_platdata(&ls1x_dma_pdata);
81 ls1x_nand_set_platdata(&ls1x_nand_pdata);
24 82
25 ls1x_serial_setup(&ls1x_uart_pdev); 83 gpio_led_register_device(-1, &ls1x_led_pdata);
26 84
27 err = platform_add_devices(ls1b_platform_devices, 85 return platform_add_devices(ls1b_platform_devices,
28 ARRAY_SIZE(ls1b_platform_devices)); 86 ARRAY_SIZE(ls1b_platform_devices));
29 return err;
30} 87}
31 88
32arch_initcall(ls1b_platform_init); 89arch_initcall(ls1b_platform_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-10 18:37:08 -0400