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authorLinus Walleij <linus.walleij@linaro.org>2013-11-13 05:10:07 -0500
committerLinus Walleij <linus.walleij@linaro.org>2013-11-26 15:01:55 -0500
commit96fee13f0f11a7479a06e4c44aaa89ee77b9fafb (patch)
tree8beeb048607ef01803e8aee4e430e8b6fda2a44a
parent3bfdebbaebed8238ac7fb7934791b0231e0f1e65 (diff)
ARM: ux500: move I2C pin control to the device tree
This moves the static, device-tied pin control configuration out of the board file board-mop500-pins.c and into the device tree. Define possible states also for I2C4 even if it's not used by any board file at this time. Cc: Lee Jones <lee.jones@linaro.org> Cc: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat
-rw-r--r--arch/arm/boot/dts/ste-href-family-pinctrl.dtsi105
-rw-r--r--arch/arm/boot/dts/ste-href.dtsi21
-rw-r--r--arch/arm/boot/dts/ste-snowball.dts24
-rw-r--r--arch/arm/mach-ux500/board-mop500-pins.c22
4 files changed, 150 insertions, 22 deletions
diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
index d979de27b6e1..d2e63f3fb687 100644
--- a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
+++ b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
@@ -109,6 +109,111 @@
109 }; 109 };
110 }; 110 };
111 }; 111 };
112
113 /* Settings for all I2C default and sleep states */
114 i2c0 {
115 i2c0_default_mode: i2c_default {
116 default_mux {
117 ste,function = "i2c0";
118 ste,pins = "i2c0_a_1";
119 };
120 default_cfg1 {
121 ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
122 ste,config = <&in_pu>;
123 };
124 };
125
126 i2c0_sleep_mode: i2c_sleep {
127 sleep_cfg1 {
128 ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
129 ste,config = <&slpm_in_wkup_pdis>;
130 };
131 };
132 };
133
134 i2c1 {
135 i2c1_default_mode: i2c_default {
136 default_mux {
137 ste,function = "i2c1";
138 ste,pins = "i2c1_b_2";
139 };
140 default_cfg1 {
141 ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
142 ste,config = <&in_pu>;
143 };
144 };
145
146 i2c1_sleep_mode: i2c_sleep {
147 sleep_cfg1 {
148 ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
149 ste,config = <&slpm_in_wkup_pdis>;
150 };
151 };
152 };
153
154 i2c2 {
155 i2c2_default_mode: i2c_default {
156 default_mux {
157 ste,function = "i2c2";
158 ste,pins = "i2c2_b_2";
159 };
160 default_cfg1 {
161 ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
162 ste,config = <&in_pu>;
163 };
164 };
165
166 i2c2_sleep_mode: i2c_sleep {
167 sleep_cfg1 {
168 ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
169 ste,config = <&slpm_in_wkup_pdis>;
170 };
171 };
172 };
173
174 i2c3 {
175 i2c3_default_mode: i2c_default {
176 default_mux {
177 ste,function = "i2c3";
178 ste,pins = "i2c3_c_2";
179 };
180 default_cfg1 {
181 ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
182 ste,config = <&in_pu>;
183 };
184 };
185
186 i2c3_sleep_mode: i2c_sleep {
187 sleep_cfg1 {
188 ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
189 ste,config = <&slpm_in_wkup_pdis>;
190 };
191 };
192 };
193
194 /*
195 * Activating I2C4 will conflict with UART1 about the same pins so do not
196 * enable I2C4 and UART1 at the same time.
197 */
198 i2c4 {
199 i2c4_default_mode: i2c_default {
200 default_mux {
201 ste,function = "i2c4";
202 ste,pins = "i2c4_b_1";
203 };
204 default_cfg1 {
205 ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
206 ste,config = <&in_pu>;
207 };
208 };
209
210 i2c4_sleep_mode: i2c_sleep {
211 sleep_cfg1 {
212 ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
213 ste,config = <&slpm_in_wkup_pdis>;
214 };
215 };
216 };
112 }; 217 };
113 }; 218 };
114}; 219};
diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi
index 914a5f4399e5..1863241c911e 100644
--- a/arch/arm/boot/dts/ste-href.dtsi
+++ b/arch/arm/boot/dts/ste-href.dtsi
@@ -51,7 +51,22 @@
51 status = "okay"; 51 status = "okay";
52 }; 52 };
53 53
54 i2c@80004000 {
55 pinctrl-names = "default","sleep";
56 pinctrl-0 = <&i2c0_default_mode>;
57 pinctrl-1 = <&i2c0_sleep_mode>;
58 };
59
60 i2c@80122000 {
61 pinctrl-names = "default","sleep";
62 pinctrl-0 = <&i2c1_default_mode>;
63 pinctrl-1 = <&i2c1_sleep_mode>;
64 };
65
54 i2c@80128000 { 66 i2c@80128000 {
67 pinctrl-names = "default","sleep";
68 pinctrl-0 = <&i2c2_default_mode>;
69 pinctrl-1 = <&i2c2_sleep_mode>;
55 lp5521@33 { 70 lp5521@33 {
56 compatible = "national,lp5521"; 71 compatible = "national,lp5521";
57 reg = <0x33>; 72 reg = <0x33>;
@@ -95,6 +110,12 @@
95 }; 110 };
96 }; 111 };
97 112
113 i2c@80110000 {
114 pinctrl-names = "default","sleep";
115 pinctrl-0 = <&i2c3_default_mode>;
116 pinctrl-1 = <&i2c3_sleep_mode>;
117 };
118
98 // External Micro SD slot 119 // External Micro SD slot
99 sdi0_per1@80126000 { 120 sdi0_per1@80126000 {
100 arm,primecell-periphid = <0x10480180>; 121 arm,primecell-periphid = <0x10480180>;
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index 16d28863ef6e..f8df43e0791d 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -176,6 +176,30 @@
176 status = "okay"; 176 status = "okay";
177 }; 177 };
178 178
179 i2c@80004000 {
180 pinctrl-names = "default","sleep";
181 pinctrl-0 = <&i2c0_default_mode>;
182 pinctrl-1 = <&i2c0_sleep_mode>;
183 };
184
185 i2c@80122000 {
186 pinctrl-names = "default","sleep";
187 pinctrl-0 = <&i2c1_default_mode>;
188 pinctrl-1 = <&i2c1_sleep_mode>;
189 };
190
191 i2c@80128000 {
192 pinctrl-names = "default","sleep";
193 pinctrl-0 = <&i2c2_default_mode>;
194 pinctrl-1 = <&i2c2_sleep_mode>;
195 };
196
197 i2c@80110000 {
198 pinctrl-names = "default","sleep";
199 pinctrl-0 = <&i2c3_default_mode>;
200 pinctrl-1 = <&i2c3_sleep_mode>;
201 };
202
179 cpufreq-cooling { 203 cpufreq-cooling {
180 status = "okay"; 204 status = "okay";
181 }; 205 };
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index c6225191141f..1f1e53972063 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -61,8 +61,6 @@ BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED|
61 PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); 61 PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
62BIAS(slpm_out_hi_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_HIGH| 62BIAS(slpm_out_hi_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_HIGH|
63 PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); 63 PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
64BIAS(slpm_in_nopull_wkup_pdis, PIN_SLEEPMODE_ENABLED|
65 PIN_SLPM_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
66BIAS(slpm_in_pu_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_PULLUP| 64BIAS(slpm_in_pu_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_PULLUP|
67 PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED); 65 PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
68BIAS(out_lo_wkup_pdis, PIN_SLPM_OUTPUT_LOW| 66BIAS(out_lo_wkup_pdis, PIN_SLPM_OUTPUT_LOW|
@@ -391,26 +389,6 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
391 DB8500_PIN("GPIO69_E2", in_pu, "0-0070"), 389 DB8500_PIN("GPIO69_E2", in_pu, "0-0070"),
392 /* LCD VSI1 sleep state */ 390 /* LCD VSI1 sleep state */
393 DB8500_PIN_SLEEP("GPIO69_E2", slpm_in_wkup_pdis, "0-0070"), 391 DB8500_PIN_SLEEP("GPIO69_E2", slpm_in_wkup_pdis, "0-0070"),
394 /* Mux in i2c0 block, default state */
395 DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"),
396 /* i2c0 sleep state */
397 DB8500_PIN_SLEEP("GPIO147_C15", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SDA */
398 DB8500_PIN_SLEEP("GPIO148_B16", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SCL */
399 /* Mux in i2c1 block, default state */
400 DB8500_MUX("i2c1_b_2", "i2c1", "nmk-i2c.1"),
401 /* i2c1 sleep state */
402 DB8500_PIN_SLEEP("GPIO16_AD3", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SDA */
403 DB8500_PIN_SLEEP("GPIO17_AD4", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SCL */
404 /* Mux in i2c2 block, default state */
405 DB8500_MUX("i2c2_b_2", "i2c2", "nmk-i2c.2"),
406 /* i2c2 sleep state */
407 DB8500_PIN_SLEEP("GPIO10_AF5", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SDA */
408 DB8500_PIN_SLEEP("GPIO11_AG4", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SCL */
409 /* Mux in i2c3 block, default state */
410 DB8500_MUX("i2c3_c_2", "i2c3", "nmk-i2c.3"),
411 /* i2c3 sleep state */
412 DB8500_PIN_SLEEP("GPIO229_AG7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SDA */
413 DB8500_PIN_SLEEP("GPIO230_AF7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SCL */
414 /* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */ 392 /* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */
415 DB8500_MUX("mc0_a_1", "mc0", "sdi0"), 393 DB8500_MUX("mc0_a_1", "mc0", "sdi0"),
416 DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */ 394 DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-04 20:29:06 -0500