aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorMartin Schwidefsky <schwidefsky@de.ibm.com>2015-09-08 07:59:08 -0400
committerMartin Schwidefsky <schwidefsky@de.ibm.com>2015-09-17 07:43:41 -0400
commit88d64253785936d75323c74e7126d180e26de560 (patch)
tree5bb9b1a461547433b6f0c2957a88b16787e17103
parent72714841b705a5b9bccf37ee85a62352bee3a3ef (diff)
s390/hibernate: fix save and restore of vector registers
The swsusp_arch_suspend()/swsusp_arch_resume() functions currently only save and restore the floating point registers. If the task that started the hibernation process is using vector registers they can get lost. To fix this just call save_fpu_regs in swsusp_arch_suspend(), the restore will happen automatically on return to user space. Reported-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
-rw-r--r--arch/s390/kernel/swsusp.S38
1 files changed, 3 insertions, 35 deletions
diff --git a/arch/s390/kernel/swsusp.S b/arch/s390/kernel/swsusp.S
index ca6294645dd3..2d6b6e81f812 100644
--- a/arch/s390/kernel/swsusp.S
+++ b/arch/s390/kernel/swsusp.S
@@ -30,6 +30,9 @@ ENTRY(swsusp_arch_suspend)
30 aghi %r15,-STACK_FRAME_OVERHEAD 30 aghi %r15,-STACK_FRAME_OVERHEAD
31 stg %r1,__SF_BACKCHAIN(%r15) 31 stg %r1,__SF_BACKCHAIN(%r15)
32 32
33 /* Store FPU registers */
34 brasl %r14,save_fpu_regs
35
33 /* Deactivate DAT */ 36 /* Deactivate DAT */
34 stnsm __SF_EMPTY(%r15),0xfb 37 stnsm __SF_EMPTY(%r15),0xfb
35 38
@@ -47,23 +50,6 @@ ENTRY(swsusp_arch_suspend)
47 50
48 /* Store registers */ 51 /* Store registers */
49 mvc 0x318(4,%r1),__SF_EMPTY(%r15) /* move prefix to lowcore */ 52 mvc 0x318(4,%r1),__SF_EMPTY(%r15) /* move prefix to lowcore */
50 stfpc 0x31c(%r1) /* store fpu control */
51 std 0,0x200(%r1) /* store f0 */
52 std 1,0x208(%r1) /* store f1 */
53 std 2,0x210(%r1) /* store f2 */
54 std 3,0x218(%r1) /* store f3 */
55 std 4,0x220(%r1) /* store f4 */
56 std 5,0x228(%r1) /* store f5 */
57 std 6,0x230(%r1) /* store f6 */
58 std 7,0x238(%r1) /* store f7 */
59 std 8,0x240(%r1) /* store f8 */
60 std 9,0x248(%r1) /* store f9 */
61 std 10,0x250(%r1) /* store f10 */
62 std 11,0x258(%r1) /* store f11 */
63 std 12,0x260(%r1) /* store f12 */
64 std 13,0x268(%r1) /* store f13 */
65 std 14,0x270(%r1) /* store f14 */
66 std 15,0x278(%r1) /* store f15 */
67 stam %a0,%a15,0x340(%r1) /* store access registers */ 53 stam %a0,%a15,0x340(%r1) /* store access registers */
68 stctg %c0,%c15,0x380(%r1) /* store control registers */ 54 stctg %c0,%c15,0x380(%r1) /* store control registers */
69 stmg %r0,%r15,0x280(%r1) /* store general registers */ 55 stmg %r0,%r15,0x280(%r1) /* store general registers */
@@ -249,24 +235,6 @@ restore_registers:
249 lctlg %c0,%c15,0x380(%r13) /* load control registers */ 235 lctlg %c0,%c15,0x380(%r13) /* load control registers */
250 lam %a0,%a15,0x340(%r13) /* load access registers */ 236 lam %a0,%a15,0x340(%r13) /* load access registers */
251 237
252 lfpc 0x31c(%r13) /* load fpu control */
253 ld 0,0x200(%r13) /* load f0 */
254 ld 1,0x208(%r13) /* load f1 */
255 ld 2,0x210(%r13) /* load f2 */
256 ld 3,0x218(%r13) /* load f3 */
257 ld 4,0x220(%r13) /* load f4 */
258 ld 5,0x228(%r13) /* load f5 */
259 ld 6,0x230(%r13) /* load f6 */
260 ld 7,0x238(%r13) /* load f7 */
261 ld 8,0x240(%r13) /* load f8 */
262 ld 9,0x248(%r13) /* load f9 */
263 ld 10,0x250(%r13) /* load f10 */
264 ld 11,0x258(%r13) /* load f11 */
265 ld 12,0x260(%r13) /* load f12 */
266 ld 13,0x268(%r13) /* load f13 */
267 ld 14,0x270(%r13) /* load f14 */
268 ld 15,0x278(%r13) /* load f15 */
269
270 /* Load old stack */ 238 /* Load old stack */
271 lg %r15,0x2f8(%r13) 239 lg %r15,0x2f8(%r13)
272 240