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authorChen Feng <puck.chen@hisilicon.com>2016-06-19 23:50:06 -0400
committerPhilipp Zabel <p.zabel@pengutronix.de>2016-06-29 17:39:09 -0400
commit8768a26cea4c54eb8d38bc063fbfba7c60c571f4 (patch)
treeab9bb405b5d63f87a6156503e20c3e6d48d01215
parent339d00cb173a5eb283d3b8d617fa97a3a46ada2f (diff)
reset: hisilicon: Change to syscon register access
There are two reset controllers in hi6220 SoC: The peripheral reset controller bits are part of sysctrl registers. The media reset controller bits are part of mediactrl registers. So change register access to syscon way. And rename current reset controller to peripheral one. Signed-off-by: Chen Feng <puck.chen@hisilicon.com> Signed-off-by: Xia Qing <saberlily.xia@hisilicon.com> Signed-off-by: Xinliang Liu <xinliang.liu@linaro.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
-rw-r--r--drivers/reset/hisilicon/hi6220_reset.c85
1 files changed, 45 insertions, 40 deletions
diff --git a/drivers/reset/hisilicon/hi6220_reset.c b/drivers/reset/hisilicon/hi6220_reset.c
index 8f55fd4a2630..686fea9e2c54 100644
--- a/drivers/reset/hisilicon/hi6220_reset.c
+++ b/drivers/reset/hisilicon/hi6220_reset.c
@@ -1,7 +1,8 @@
1/* 1/*
2 * Hisilicon Hi6220 reset controller driver 2 * Hisilicon Hi6220 reset controller driver
3 * 3 *
4 * Copyright (c) 2015 Hisilicon Limited. 4 * Copyright (c) 2016 Linaro Limited.
5 * Copyright (c) 2015-2016 Hisilicon Limited.
5 * 6 *
6 * Author: Feng Chen <puck.chen@hisilicon.com> 7 * Author: Feng Chen <puck.chen@hisilicon.com>
7 * 8 *
@@ -15,81 +16,85 @@
15#include <linux/module.h> 16#include <linux/module.h>
16#include <linux/bitops.h> 17#include <linux/bitops.h>
17#include <linux/of.h> 18#include <linux/of.h>
19#include <linux/of_device.h>
20#include <linux/regmap.h>
21#include <linux/mfd/syscon.h>
18#include <linux/reset-controller.h> 22#include <linux/reset-controller.h>
19#include <linux/reset.h> 23#include <linux/reset.h>
20#include <linux/platform_device.h> 24#include <linux/platform_device.h>
21 25
22#define ASSERT_OFFSET 0x300 26#define PERIPH_ASSERT_OFFSET 0x300
23#define DEASSERT_OFFSET 0x304 27#define PERIPH_DEASSERT_OFFSET 0x304
24#define MAX_INDEX 0x509 28#define PERIPH_MAX_INDEX 0x509
25 29
26#define to_reset_data(x) container_of(x, struct hi6220_reset_data, rc_dev) 30#define to_reset_data(x) container_of(x, struct hi6220_reset_data, rc_dev)
27 31
28struct hi6220_reset_data { 32struct hi6220_reset_data {
29 void __iomem *assert_base; 33 struct reset_controller_dev rc_dev;
30 void __iomem *deassert_base; 34 struct regmap *regmap;
31 struct reset_controller_dev rc_dev;
32}; 35};
33 36
34static int hi6220_reset_assert(struct reset_controller_dev *rc_dev, 37static int hi6220_peripheral_assert(struct reset_controller_dev *rc_dev,
35 unsigned long idx) 38 unsigned long idx)
36{ 39{
37 struct hi6220_reset_data *data = to_reset_data(rc_dev); 40 struct hi6220_reset_data *data = to_reset_data(rc_dev);
41 struct regmap *regmap = data->regmap;
42 u32 bank = idx >> 8;
43 u32 offset = idx & 0xff;
44 u32 reg = PERIPH_ASSERT_OFFSET + bank * 0x10;
38 45
39 int bank = idx >> 8; 46 return regmap_write(regmap, reg, BIT(offset));
40 int offset = idx & 0xff;
41
42 writel(BIT(offset), data->assert_base + (bank * 0x10));
43
44 return 0;
45} 47}
46 48
47static int hi6220_reset_deassert(struct reset_controller_dev *rc_dev, 49static int hi6220_peripheral_deassert(struct reset_controller_dev *rc_dev,
48 unsigned long idx) 50 unsigned long idx)
49{ 51{
50 struct hi6220_reset_data *data = to_reset_data(rc_dev); 52 struct hi6220_reset_data *data = to_reset_data(rc_dev);
53 struct regmap *regmap = data->regmap;
54 u32 bank = idx >> 8;
55 u32 offset = idx & 0xff;
56 u32 reg = PERIPH_DEASSERT_OFFSET + bank * 0x10;
51 57
52 int bank = idx >> 8; 58 return regmap_write(regmap, reg, BIT(offset));
53 int offset = idx & 0xff;
54
55 writel(BIT(offset), data->deassert_base + (bank * 0x10));
56
57 return 0;
58} 59}
59 60
60static const struct reset_control_ops hi6220_reset_ops = { 61static const struct reset_control_ops hi6220_peripheral_reset_ops = {
61 .assert = hi6220_reset_assert, 62 .assert = hi6220_peripheral_assert,
62 .deassert = hi6220_reset_deassert, 63 .deassert = hi6220_peripheral_deassert,
63}; 64};
64 65
65static int hi6220_reset_probe(struct platform_device *pdev) 66static int hi6220_reset_probe(struct platform_device *pdev)
66{ 67{
68 struct device_node *np = pdev->dev.of_node;
69 struct device *dev = &pdev->dev;
67 struct hi6220_reset_data *data; 70 struct hi6220_reset_data *data;
68 struct resource *res; 71 struct regmap *regmap;
69 void __iomem *src_base;
70 72
71 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 73 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
72 if (!data) 74 if (!data)
73 return -ENOMEM; 75 return -ENOMEM;
74 76
75 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 77 regmap = syscon_node_to_regmap(np);
76 src_base = devm_ioremap_resource(&pdev->dev, res); 78 if (IS_ERR(regmap)) {
77 if (IS_ERR(src_base)) 79 dev_err(dev, "failed to get reset controller regmap\n");
78 return PTR_ERR(src_base); 80 return PTR_ERR(regmap);
81 }
79 82
80 data->assert_base = src_base + ASSERT_OFFSET; 83 data->regmap = regmap;
81 data->deassert_base = src_base + DEASSERT_OFFSET; 84 data->rc_dev.of_node = np;
82 data->rc_dev.nr_resets = MAX_INDEX; 85 data->rc_dev.ops = &hi6220_peripheral_reset_ops;
83 data->rc_dev.ops = &hi6220_reset_ops; 86 data->rc_dev.nr_resets = PERIPH_MAX_INDEX;
84 data->rc_dev.of_node = pdev->dev.of_node;
85 87
86 return reset_controller_register(&data->rc_dev); 88 return reset_controller_register(&data->rc_dev);
87} 89}
88 90
89static const struct of_device_id hi6220_reset_match[] = { 91static const struct of_device_id hi6220_reset_match[] = {
90 { .compatible = "hisilicon,hi6220-sysctrl" }, 92 {
91 { }, 93 .compatible = "hisilicon,hi6220-sysctrl",
94 },
95 { /* sentinel */ },
92}; 96};
97MODULE_DEVICE_TABLE(of, hi6220_reset_match);
93 98
94static struct platform_driver hi6220_reset_driver = { 99static struct platform_driver hi6220_reset_driver = {
95 .probe = hi6220_reset_probe, 100 .probe = hi6220_reset_probe,