arm64: Use 42-bit address space with 64K pages

This patch expands the VA_BITS to 42 when the 64K page configuration is
enabled allowing 2TB kernel linear mapping. Linux still uses 2 levels of
page tables in this configuration with pgd now being a full page.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>

4 files changed, 37 insertions, 7 deletions

diff --git a/Documentation/arm64/memory.txt b/Documentation/arm64/memory.txt
index f28899d5c83e..5e054bfe4dde 100644
--- a/Documentation/arm64/memory.txt
+++ b/Documentation/arm64/memory.txt
@@ -21,7 +21,7 @@ The swapper_pgd_dir address is written to TTBR1 and never written to
 TTBR0.
 
 
-AArch64 Linux memory layout:
+AArch64 Linux memory layout with 4KB pages:
 
 Start                   End                     Size            Use
 -----------------------------------------------------------------------
@@ -46,6 +46,31 @@ ffffffbffc000000	ffffffbfffffffff	  64MB		modules
 ffffffc000000000        ffffffffffffffff         256GB          kernel logical memory map
 
 
+AArch64 Linux memory layout with 64KB pages:
+
+Start                   End                     Size            Use
+-----------------------------------------------------------------------
+0000000000000000        000003ffffffffff           4TB          user
+
+fffffc0000000000        fffffdfbfffeffff          ~2TB          vmalloc
+
+fffffdfbffff0000        fffffdfbffffffff          64KB          [guard page]
+
+fffffdfc00000000        fffffdfdffffffff           8GB          vmemmap
+
+fffffdfe00000000        fffffdfffbbfffff          ~8GB          [guard, future vmmemap]
+
+fffffdfffbc00000        fffffdfffbdfffff           2MB          earlyprintk device
+
+fffffdfffbe00000        fffffdfffbe0ffff          64KB          PCI I/O space
+
+fffffdfffbe10000        fffffdfffbffffff          ~2MB          [guard]
+
+fffffdfffc000000        fffffdffffffffff          64MB          modules
+
+fffffe0000000000        ffffffffffffffff           2TB          kernel logical memory map
+
+
 Translation table lookup with 4KB pages:
 
 +--------+--------+--------+--------+--------+--------+--------+--------+
diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
index 20925bcf4e2a..37762175896f 100644
--- a/arch/arm64/include/asm/memory.h
+++ b/arch/arm64/include/asm/memory.h
@@ -33,18 +33,23 @@
 #define UL(x) _AC(x, UL)
 
 /*
- * PAGE_OFFSET - the virtual address of the start of the kernel image.
+ * PAGE_OFFSET - the virtual address of the start of the kernel image (top
+ *               (VA_BITS - 1))
  * VA_BITS - the maximum number of bits for virtual addresses.
  * TASK_SIZE - the maximum size of a user space task.
  * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area.
  * The module space lives between the addresses given by TASK_SIZE
  * and PAGE_OFFSET - it must be within 128MB of the kernel text.
  */
-#define PAGE_OFFSET             UL(0xffffffc000000000)
+#ifdef CONFIG_ARM64_64K_PAGES
+#define VA_BITS                 (42)
+#else
+#define VA_BITS                 (39)
+#endif
+#define PAGE_OFFSET             (UL(0xffffffffffffffff) << (VA_BITS - 1))
 #define MODULES_END             (PAGE_OFFSET)
 #define MODULES_VADDR           (MODULES_END - SZ_64M)
 #define EARLYCON_IOBASE         (MODULES_VADDR - SZ_4M)
-#define VA_BITS                 (39)
 #define TASK_SIZE_64            (UL(1) << VA_BITS)
 
 #ifdef CONFIG_COMPAT
diff --git a/arch/arm64/include/asm/pgtable-2level-hwdef.h b/arch/arm64/include/asm/pgtable-2level-hwdef.h
index 0a8ed3f94e93..2593b490c56a 100644
--- a/arch/arm64/include/asm/pgtable-2level-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-2level-hwdef.h
@@ -21,10 +21,10 @@
  * 8192 entries of 8 bytes each, occupying a 64KB page. Levels 0 and 1 are not
  * used. The 2nd level table (PGD for Linux) can cover a range of 4TB, each
  * entry representing 512MB. The user and kernel address spaces are limited to
- * 512GB and therefore we only use 1024 entries in the PGD.
+ * 4TB in the 64KB page configuration.
  */
 #define PTRS_PER_PTE            8192
-#define PTRS_PER_PGD            1024
+#define PTRS_PER_PGD            8192
 
 /*
  * PGDIR_SHIFT determines the size a top-level page table entry can map.
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index f0bebc5e22cd..17bd3af0a117 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -33,7 +33,7 @@
 /*
  * VMALLOC and SPARSEMEM_VMEMMAP ranges.
  */
-#define VMALLOC_START           UL(0xffffff8000000000)
+#define VMALLOC_START           (UL(0xffffffffffffffff) << VA_BITS)
 #define VMALLOC_END             (PAGE_OFFSET - UL(0x400000000) - SZ_64K)
 
 #define vmemmap                 ((struct page *)(VMALLOC_END + SZ_64K))