clk: qcom: gdsc: Add GDSCs in msm8974 MMCC

Add the GDSC instances that exist as part of msm8974 MMCC block

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

3 files changed, 81 insertions, 0 deletions

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index a6fcb1ddb567..edab1724537b 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -98,6 +98,7 @@ config MSM_GCC_8974
 config MSM_MMCC_8974
         tristate "MSM8974 Multimedia Clock Controller"
         select MSM_GCC_8974
+        select QCOM_GDSC
         depends on COMMON_CLK_QCOM
         help
           Support for the multimedia clock controller on msm8974 devices.
diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
index 197700e3b2c9..fe8320dc41db 100644
--- a/drivers/clk/qcom/mmcc-msm8974.c
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -31,6 +31,7 @@
 #include "clk-rcg.h"
 #include "clk-branch.h"
 #include "reset.h"
+#include "gdsc.h"
 
 enum {
         P_XO,
@@ -2342,6 +2343,66 @@ static struct pll_config mmpll3_config = {
         .aux_output_mask = BIT(1),
 };
 
+static struct gdsc venus0_gdsc = {
+        .gdscr = 0x1024,
+        .cxcs = (unsigned int []){ 0x1028 },
+        .cxc_count = 1,
+        .resets = (unsigned int []){ VENUS0_RESET },
+        .reset_count = 1,
+        .pd = {
+                .name = "venus0",
+        },
+        .pwrsts = PWRSTS_ON,
+};
+
+static struct gdsc mdss_gdsc = {
+        .gdscr = 0x2304,
+        .cxcs = (unsigned int []){ 0x231c, 0x2320 },
+        .cxc_count = 2,
+        .pd = {
+                .name = "mdss",
+        },
+        .pwrsts = PWRSTS_RET_ON,
+};
+
+static struct gdsc camss_jpeg_gdsc = {
+        .gdscr = 0x35a4,
+        .cxcs = (unsigned int []){ 0x35a8, 0x35ac, 0x35b0 },
+        .cxc_count = 3,
+        .pd = {
+                .name = "camss_jpeg",
+        },
+        .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc camss_vfe_gdsc = {
+        .gdscr = 0x36a4,
+        .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x3704, 0x3714, 0x36b0 },
+        .cxc_count = 5,
+        .pd = {
+                .name = "camss_vfe",
+        },
+        .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc oxili_gdsc = {
+        .gdscr = 0x4024,
+        .cxcs = (unsigned int []){ 0x4028 },
+        .cxc_count = 1,
+        .pd = {
+                .name = "oxili",
+        },
+        .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc oxilicx_gdsc = {
+        .gdscr = 0x4034,
+        .pd = {
+                .name = "oxilicx",
+        },
+        .pwrsts = PWRSTS_OFF_ON,
+};
+
 static struct clk_regmap *mmcc_msm8974_clocks[] = {
         [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
         [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
@@ -2518,6 +2579,15 @@ static const struct qcom_reset_map mmcc_msm8974_resets[] = {
         [OCMEMNOC_RESET] = { 0x50b0 },
 };
 
+static struct gdsc *mmcc_msm8974_gdscs[] = {
+        [VENUS0_GDSC] = &venus0_gdsc,
+        [MDSS_GDSC] = &mdss_gdsc,
+        [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
+        [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
+        [OXILI_GDSC] = &oxili_gdsc,
+        [OXILICX_GDSC] = &oxilicx_gdsc,
+};
+
 static const struct regmap_config mmcc_msm8974_regmap_config = {
         .reg_bits       = 32,
         .reg_stride     = 4,
@@ -2532,6 +2602,8 @@ static const struct qcom_cc_desc mmcc_msm8974_desc = {
         .num_clks = ARRAY_SIZE(mmcc_msm8974_clocks),
         .resets = mmcc_msm8974_resets,
         .num_resets = ARRAY_SIZE(mmcc_msm8974_resets),
+        .gdscs = mmcc_msm8974_gdscs,
+        .num_gdscs = ARRAY_SIZE(mmcc_msm8974_gdscs),
 };
 
 static const struct of_device_id mmcc_msm8974_match_table[] = {
diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8974.h b/include/dt-bindings/clock/qcom,mmcc-msm8974.h
index 032ed87ef0f3..28651e54c9ae 100644
--- a/include/dt-bindings/clock/qcom,mmcc-msm8974.h
+++ b/include/dt-bindings/clock/qcom,mmcc-msm8974.h
@@ -158,4 +158,12 @@
 #define SPDM_RM_AXI                                     141
 #define SPDM_RM_OCMEMNOC                                142
 
+/* gdscs */
+#define VENUS0_GDSC                                     0
+#define MDSS_GDSC                                       1
+#define CAMSS_JPEG_GDSC                                 2
+#define CAMSS_VFE_GDSC                                  3
+#define OXILI_GDSC                                      4
+#define OXILICX_GDSC                                    5
+
 #endif