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authorMasahiro Yamada <yamada.masahiro@socionext.com>2016-09-16 03:40:04 -0400
committerStephen Boyd <sboyd@codeaurora.org>2016-09-16 19:31:38 -0400
commit7f4d3b52b6b69f274006cc65984672bfa7fd8b92 (patch)
tree3a59713a605973d3f1d283aa94997c7f5cf27ea2
parent734d82f4a678e897a3197b3e61313e32c9e77f46 (diff)
clk: uniphier: add clock data for UniPhier SoCs
Add clock data arrays for all UniPhier SoCs with a binding document. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/uniphier-clock.txt134
-rw-r--r--drivers/clk/uniphier/Makefile3
-rw-r--r--drivers/clk/uniphier/clk-uniphier-core.c91
-rw-r--r--drivers/clk/uniphier/clk-uniphier-mio.c101
-rw-r--r--drivers/clk/uniphier/clk-uniphier-peri.c57
-rw-r--r--drivers/clk/uniphier/clk-uniphier-sys.c151
-rw-r--r--drivers/clk/uniphier/clk-uniphier.h13
7 files changed, 550 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/uniphier-clock.txt b/Documentation/devicetree/bindings/clock/uniphier-clock.txt
new file mode 100644
index 000000000000..c7179d3b5c33
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/uniphier-clock.txt
@@ -0,0 +1,134 @@
1UniPhier clock controller
2
3
4System clock
5------------
6
7Required properties:
8- compatible: should be one of the following:
9 "socionext,uniphier-sld3-clock" - for sLD3 SoC.
10 "socionext,uniphier-ld4-clock" - for LD4 SoC.
11 "socionext,uniphier-pro4-clock" - for Pro4 SoC.
12 "socionext,uniphier-sld8-clock" - for sLD8 SoC.
13 "socionext,uniphier-pro5-clock" - for Pro5 SoC.
14 "socionext,uniphier-pxs2-clock" - for PXs2/LD6b SoC.
15 "socionext,uniphier-ld11-clock" - for LD11 SoC.
16 "socionext,uniphier-ld20-clock" - for LD20 SoC.
17- #clock-cells: should be 1.
18
19Example:
20
21 sysctrl@61840000 {
22 compatible = "socionext,uniphier-sysctrl",
23 "simple-mfd", "syscon";
24 reg = <0x61840000 0x4000>;
25
26 clock {
27 compatible = "socionext,uniphier-ld20-clock";
28 #clock-cells = <1>;
29 };
30
31 other nodes ...
32 };
33
34Provided clocks:
35
36 8: ST DMAC
3712: GIO (Giga bit stream I/O)
3814: USB3 ch0 host
3915: USB3 ch1 host
4016: USB3 ch0 PHY0
4117: USB3 ch0 PHY1
4220: USB3 ch1 PHY0
4321: USB3 ch1 PHY1
44
45
46Media I/O (MIO) clock
47---------------------
48
49Required properties:
50- compatible: should be one of the following:
51 "socionext,uniphier-sld3-mio-clock" - for sLD3 SoC.
52 "socionext,uniphier-ld4-mio-clock" - for LD4 SoC.
53 "socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.
54 "socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.
55 "socionext,uniphier-pro5-mio-clock" - for Pro5 SoC.
56 "socionext,uniphier-pxs2-mio-clock" - for PXs2/LD6b SoC.
57 "socionext,uniphier-ld11-mio-clock" - for LD11 SoC.
58 "socionext,uniphier-ld20-mio-clock" - for LD20 SoC.
59- #clock-cells: should be 1.
60
61Example:
62
63 mioctrl@59810000 {
64 compatible = "socionext,uniphier-mioctrl",
65 "simple-mfd", "syscon";
66 reg = <0x59810000 0x800>;
67
68 clock {
69 compatible = "socionext,uniphier-ld20-mio-clock";
70 #clock-cells = <1>;
71 };
72
73 other nodes ...
74 };
75
76Provided clocks:
77
78 0: SD ch0 host
79 1: eMMC host
80 2: SD ch1 host
81 7: MIO DMAC
82 8: USB2 ch0 host
83 9: USB2 ch1 host
8410: USB2 ch2 host
8511: USB2 ch3 host
8612: USB2 ch0 PHY
8713: USB2 ch1 PHY
8814: USB2 ch2 PHY
8915: USB2 ch3 PHY
90
91
92Peripheral clock
93----------------
94
95Required properties:
96- compatible: should be one of the following:
97 "socionext,uniphier-sld3-peri-clock" - for sLD3 SoC.
98 "socionext,uniphier-ld4-peri-clock" - for LD4 SoC.
99 "socionext,uniphier-pro4-peri-clock" - for Pro4 SoC.
100 "socionext,uniphier-sld8-peri-clock" - for sLD8 SoC.
101 "socionext,uniphier-pro5-peri-clock" - for Pro5 SoC.
102 "socionext,uniphier-pxs2-peri-clock" - for PXs2/LD6b SoC.
103 "socionext,uniphier-ld11-peri-clock" - for LD11 SoC.
104 "socionext,uniphier-ld20-peri-clock" - for LD20 SoC.
105- #clock-cells: should be 1.
106
107Example:
108
109 perictrl@59820000 {
110 compatible = "socionext,uniphier-perictrl",
111 "simple-mfd", "syscon";
112 reg = <0x59820000 0x200>;
113
114 clock {
115 compatible = "socionext,uniphier-ld20-peri-clock";
116 #clock-cells = <1>;
117 };
118
119 other nodes ...
120 };
121
122Provided clocks:
123
124 0: UART ch0
125 1: UART ch1
126 2: UART ch2
127 3: UART ch3
128 4: I2C ch0
129 5: I2C ch1
130 6: I2C ch2
131 7: I2C ch3
132 8: I2C ch4
133 9: I2C ch5
13410: I2C ch6
diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile
index 88a28cad86b1..f27b360329ca 100644
--- a/drivers/clk/uniphier/Makefile
+++ b/drivers/clk/uniphier/Makefile
@@ -3,3 +3,6 @@ obj-y += clk-uniphier-fixed-factor.o
3obj-y += clk-uniphier-fixed-rate.o 3obj-y += clk-uniphier-fixed-rate.o
4obj-y += clk-uniphier-gate.o 4obj-y += clk-uniphier-gate.o
5obj-y += clk-uniphier-mux.o 5obj-y += clk-uniphier-mux.o
6obj-y += clk-uniphier-sys.o
7obj-y += clk-uniphier-mio.o
8obj-y += clk-uniphier-peri.o
diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c
index a6e2a9404c7d..5ffb898d0839 100644
--- a/drivers/clk/uniphier/clk-uniphier-core.c
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -109,6 +109,97 @@ static int uniphier_clk_remove(struct platform_device *pdev)
109} 109}
110 110
111static const struct of_device_id uniphier_clk_match[] = { 111static const struct of_device_id uniphier_clk_match[] = {
112 /* System clock */
113 {
114 .compatible = "socionext,uniphier-ld4-clock",
115 .data = uniphier_ld4_sys_clk_data,
116 },
117 {
118 .compatible = "socionext,uniphier-pro4-clock",
119 .data = uniphier_pro4_sys_clk_data,
120 },
121 {
122 .compatible = "socionext,uniphier-sld8-clock",
123 .data = uniphier_sld8_sys_clk_data,
124 },
125 {
126 .compatible = "socionext,uniphier-pro5-clock",
127 .data = uniphier_pro5_sys_clk_data,
128 },
129 {
130 .compatible = "socionext,uniphier-pxs2-clock",
131 .data = uniphier_pxs2_sys_clk_data,
132 },
133 {
134 .compatible = "socionext,uniphier-ld11-clock",
135 .data = uniphier_ld11_sys_clk_data,
136 },
137 {
138 .compatible = "socionext,uniphier-ld20-clock",
139 .data = uniphier_ld20_sys_clk_data,
140 },
141 /* Media I/O clock */
142 {
143 .compatible = "socionext,uniphier-sld3-mio-clock",
144 .data = uniphier_sld3_mio_clk_data,
145 },
146 {
147 .compatible = "socionext,uniphier-ld4-mio-clock",
148 .data = uniphier_sld3_mio_clk_data,
149 },
150 {
151 .compatible = "socionext,uniphier-pro4-mio-clock",
152 .data = uniphier_sld3_mio_clk_data,
153 },
154 {
155 .compatible = "socionext,uniphier-sld8-mio-clock",
156 .data = uniphier_sld3_mio_clk_data,
157 },
158 {
159 .compatible = "socionext,uniphier-pro5-mio-clock",
160 .data = uniphier_pro5_mio_clk_data,
161 },
162 {
163 .compatible = "socionext,uniphier-pxs2-mio-clock",
164 .data = uniphier_pro5_mio_clk_data,
165 },
166 {
167 .compatible = "socionext,uniphier-ld11-mio-clock",
168 .data = uniphier_sld3_mio_clk_data,
169 },
170 {
171 .compatible = "socionext,uniphier-ld20-mio-clock",
172 .data = uniphier_pro5_mio_clk_data,
173 },
174 /* Peripheral clock */
175 {
176 .compatible = "socionext,uniphier-ld4-peri-clock",
177 .data = uniphier_ld4_peri_clk_data,
178 },
179 {
180 .compatible = "socionext,uniphier-pro4-peri-clock",
181 .data = uniphier_pro4_peri_clk_data,
182 },
183 {
184 .compatible = "socionext,uniphier-sld8-peri-clock",
185 .data = uniphier_ld4_peri_clk_data,
186 },
187 {
188 .compatible = "socionext,uniphier-pro5-peri-clock",
189 .data = uniphier_pro4_peri_clk_data,
190 },
191 {
192 .compatible = "socionext,uniphier-pxs2-peri-clock",
193 .data = uniphier_pro4_peri_clk_data,
194 },
195 {
196 .compatible = "socionext,uniphier-ld11-peri-clock",
197 .data = uniphier_pro4_peri_clk_data,
198 },
199 {
200 .compatible = "socionext,uniphier-ld20-peri-clock",
201 .data = uniphier_pro4_peri_clk_data,
202 },
112 { /* sentinel */ } 203 { /* sentinel */ }
113}; 204};
114 205
diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c
new file mode 100644
index 000000000000..6aa7ec768d0b
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-mio.c
@@ -0,0 +1,101 @@
1/*
2 * Copyright (C) 2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include "clk-uniphier.h"
17
18#define UNIPHIER_MIO_CLK_SD_FIXED \
19 UNIPHIER_CLK_FACTOR("sd-44m", -1, "sd-133m", 1, 3), \
20 UNIPHIER_CLK_FACTOR("sd-33m", -1, "sd-200m", 1, 6), \
21 UNIPHIER_CLK_FACTOR("sd-50m", -1, "sd-200m", 1, 4), \
22 UNIPHIER_CLK_FACTOR("sd-67m", -1, "sd-200m", 1, 3), \
23 UNIPHIER_CLK_FACTOR("sd-100m", -1, "sd-200m", 1, 2), \
24 UNIPHIER_CLK_FACTOR("sd-40m", -1, "sd-200m", 1, 5), \
25 UNIPHIER_CLK_FACTOR("sd-25m", -1, "sd-200m", 1, 8), \
26 UNIPHIER_CLK_FACTOR("sd-22m", -1, "sd-133m", 1, 6)
27
28#define UNIPHIER_MIO_CLK_SD(_idx, ch) \
29 { \
30 .name = "sd" #ch "-sel", \
31 .type = UNIPHIER_CLK_TYPE_MUX, \
32 .idx = -1, \
33 .data.mux = { \
34 .parent_names = { \
35 "sd-44m", \
36 "sd-33m", \
37 "sd-50m", \
38 "sd-67m", \
39 "sd-100m", \
40 "sd-40m", \
41 "sd-25m", \
42 "sd-22m", \
43 }, \
44 .num_parents = 8, \
45 .reg = 0x30 + 0x200 * (ch), \
46 .masks = { \
47 0x00031000, \
48 0x00031000, \
49 0x00031000, \
50 0x00031000, \
51 0x00001300, \
52 0x00001300, \
53 0x00001300, \
54 0x00001300, \
55 }, \
56 .vals = { \
57 0x00000000, \
58 0x00010000, \
59 0x00020000, \
60 0x00030000, \
61 0x00001000, \
62 0x00001100, \
63 0x00001200, \
64 0x00001300, \
65 }, \
66 }, \
67 }, \
68 UNIPHIER_CLK_GATE("sd" #ch, (_idx), "sd" #ch "-sel", 0x20 + 0x200 * (ch), 8)
69
70#define UNIPHIER_MIO_CLK_USB2(idx, ch) \
71 UNIPHIER_CLK_GATE("usb2" #ch, (idx), "usb2", 0x20 + 0x200 * (ch), 28)
72
73#define UNIPHIER_MIO_CLK_USB2_PHY(idx, ch) \
74 UNIPHIER_CLK_GATE("usb2" #ch "-phy", (idx), "usb2", 0x20 + 0x200 * (ch), 29)
75
76#define UNIPHIER_MIO_CLK_DMAC(idx) \
77 UNIPHIER_CLK_GATE("miodmac", (idx), "stdmac", 0x20, 25)
78
79const struct uniphier_clk_data uniphier_sld3_mio_clk_data[] = {
80 UNIPHIER_MIO_CLK_SD_FIXED,
81 UNIPHIER_MIO_CLK_SD(0, 0),
82 UNIPHIER_MIO_CLK_SD(1, 1),
83 UNIPHIER_MIO_CLK_SD(2, 2),
84 UNIPHIER_MIO_CLK_DMAC(7),
85 UNIPHIER_MIO_CLK_USB2(8, 0),
86 UNIPHIER_MIO_CLK_USB2(9, 1),
87 UNIPHIER_MIO_CLK_USB2(10, 2),
88 UNIPHIER_MIO_CLK_USB2(11, 3),
89 UNIPHIER_MIO_CLK_USB2_PHY(12, 0),
90 UNIPHIER_MIO_CLK_USB2_PHY(13, 1),
91 UNIPHIER_MIO_CLK_USB2_PHY(14, 2),
92 UNIPHIER_MIO_CLK_USB2_PHY(15, 3),
93 { /* sentinel */ }
94};
95
96const struct uniphier_clk_data uniphier_pro5_mio_clk_data[] = {
97 UNIPHIER_MIO_CLK_SD_FIXED,
98 UNIPHIER_MIO_CLK_SD(0, 0),
99 UNIPHIER_MIO_CLK_SD(1, 1),
100 { /* sentinel */ }
101};
diff --git a/drivers/clk/uniphier/clk-uniphier-peri.c b/drivers/clk/uniphier/clk-uniphier-peri.c
new file mode 100644
index 000000000000..521c80e9a06f
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-peri.c
@@ -0,0 +1,57 @@
1/*
2 * Copyright (C) 2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include "clk-uniphier.h"
17
18#define UNIPHIER_PERI_CLK_UART(idx, ch) \
19 UNIPHIER_CLK_GATE("uart" #ch, (idx), "uart", 0x24, 19 + (ch))
20
21#define UNIPHIER_PERI_CLK_I2C_COMMON \
22 UNIPHIER_CLK_GATE("i2c-common", -1, "i2c", 0x20, 1)
23
24#define UNIPHIER_PERI_CLK_I2C(idx, ch) \
25 UNIPHIER_CLK_GATE("i2c" #ch, (idx), "i2c-common", 0x24, 5 + (ch))
26
27#define UNIPHIER_PERI_CLK_FI2C(idx, ch) \
28 UNIPHIER_CLK_GATE("i2c" #ch, (idx), "i2c", 0x24, 24 + (ch))
29
30const struct uniphier_clk_data uniphier_ld4_peri_clk_data[] = {
31 UNIPHIER_PERI_CLK_UART(0, 0),
32 UNIPHIER_PERI_CLK_UART(1, 1),
33 UNIPHIER_PERI_CLK_UART(2, 2),
34 UNIPHIER_PERI_CLK_UART(3, 3),
35 UNIPHIER_PERI_CLK_I2C_COMMON,
36 UNIPHIER_PERI_CLK_I2C(4, 0),
37 UNIPHIER_PERI_CLK_I2C(5, 1),
38 UNIPHIER_PERI_CLK_I2C(6, 2),
39 UNIPHIER_PERI_CLK_I2C(7, 3),
40 UNIPHIER_PERI_CLK_I2C(8, 4),
41 { /* sentinel */ }
42};
43
44const struct uniphier_clk_data uniphier_pro4_peri_clk_data[] = {
45 UNIPHIER_PERI_CLK_UART(0, 0),
46 UNIPHIER_PERI_CLK_UART(1, 1),
47 UNIPHIER_PERI_CLK_UART(2, 2),
48 UNIPHIER_PERI_CLK_UART(3, 3),
49 UNIPHIER_PERI_CLK_FI2C(4, 0),
50 UNIPHIER_PERI_CLK_FI2C(5, 1),
51 UNIPHIER_PERI_CLK_FI2C(6, 2),
52 UNIPHIER_PERI_CLK_FI2C(7, 3),
53 UNIPHIER_PERI_CLK_FI2C(8, 4),
54 UNIPHIER_PERI_CLK_FI2C(9, 5),
55 UNIPHIER_PERI_CLK_FI2C(10, 6),
56 { /* sentinel */ }
57};
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
new file mode 100644
index 000000000000..5d029991047d
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -0,0 +1,151 @@
1/*
2 * Copyright (C) 2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/stddef.h>
17
18#include "clk-uniphier.h"
19
20#define UNIPHIER_SLD3_SYS_CLK_SD \
21 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
22 UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
23
24#define UNIPHIER_PRO5_SYS_CLK_SD \
25 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
26 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
27
28#define UNIPHIER_LD20_SYS_CLK_SD \
29 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
30 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
31
32#define UNIPHIER_SLD3_SYS_CLK_STDMAC(idx) \
33 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x2104, 10)
34
35#define UNIPHIER_LD11_SYS_CLK_STDMAC(idx) \
36 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8)
37
38#define UNIPHIER_PRO4_SYS_CLK_GIO(idx) \
39 UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6)
40
41#define UNIPHIER_PRO4_SYS_CLK_USB3(idx, ch) \
42 UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch))
43
44const struct uniphier_clk_data uniphier_sld3_sys_clk_data[] = {
45 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
46 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
47 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
48 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
49 UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16),
50 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
51 UNIPHIER_SLD3_SYS_CLK_SD,
52 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
53 UNIPHIER_SLD3_SYS_CLK_STDMAC(8),
54 { /* sentinel */ }
55};
56
57const struct uniphier_clk_data uniphier_ld4_sys_clk_data[] = {
58 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
59 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
60 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
61 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
62 UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16),
63 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
64 UNIPHIER_SLD3_SYS_CLK_SD,
65 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
66 UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */
67 { /* sentinel */ }
68};
69
70const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = {
71 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
72 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
73 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
74 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
75 UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8),
76 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32),
77 UNIPHIER_SLD3_SYS_CLK_SD,
78 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
79 UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* HSC, MIO, RLE */
80 UNIPHIER_PRO4_SYS_CLK_GIO(12), /* Ether, SATA, USB3 */
81 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
82 UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
83 { /* sentinel */ }
84};
85
86const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = {
87 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
88 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
89 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
90 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 20),
91 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
92 UNIPHIER_SLD3_SYS_CLK_SD,
93 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
94 UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */
95 { /* sentinel */ }
96};
97
98const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = {
99 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1), /* 2400 MHz */
100 UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1), /* 2560 MHz */
101 UNIPHIER_CLK_FACTOR("dapll2", -1, "ref", 144, 125), /* 2949.12 MHz */
102 UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40),
103 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
104 UNIPHIER_PRO5_SYS_CLK_SD,
105 UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* HSC */
106 UNIPHIER_PRO4_SYS_CLK_GIO(12), /* PCIe, USB3 */
107 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
108 UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
109 { /* sentinel */ }
110};
111
112const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
113 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 96, 1), /* 2400 MHz */
114 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 27),
115 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
116 UNIPHIER_PRO5_SYS_CLK_SD,
117 UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* HSC, RLE */
118 /* GIO is always clock-enabled: no function for 0x2104 bit6 */
119 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
120 UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
121 /* The document mentions 0x2104 bit 18, but not functional */
122 UNIPHIER_CLK_GATE("usb30-phy", 16, NULL, 0x2104, 19),
123 UNIPHIER_CLK_GATE("usb31-phy", 20, NULL, 0x2104, 20),
124 { /* sentinel */ }
125};
126
127const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = {
128 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
129 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
130 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
131 UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC, MIO */
132 UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25),
133 { /* sentinel */ }
134};
135
136const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
137 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
138 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
139 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
140 UNIPHIER_LD20_SYS_CLK_SD,
141 UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC */
142 /* GIO is always clock-enabled: no function for 0x210c bit5 */
143 /*
144 * clock for USB Link is enabled by the logic "OR" of bit 14 and bit 15.
145 * We do not use bit 15 here.
146 */
147 UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14),
148 UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 12),
149 UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 13),
150 { /* sentinel */ }
151};
diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h
index 3e354e907f4e..3ae184062388 100644
--- a/drivers/clk/uniphier/clk-uniphier.h
+++ b/drivers/clk/uniphier/clk-uniphier.h
@@ -106,4 +106,17 @@ struct clk_hw *uniphier_clk_register_mux(struct device *dev,
106 const char *name, 106 const char *name,
107 const struct uniphier_clk_mux_data *data); 107 const struct uniphier_clk_mux_data *data);
108 108
109extern const struct uniphier_clk_data uniphier_sld3_sys_clk_data[];
110extern const struct uniphier_clk_data uniphier_ld4_sys_clk_data[];
111extern const struct uniphier_clk_data uniphier_pro4_sys_clk_data[];
112extern const struct uniphier_clk_data uniphier_sld8_sys_clk_data[];
113extern const struct uniphier_clk_data uniphier_pro5_sys_clk_data[];
114extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[];
115extern const struct uniphier_clk_data uniphier_ld11_sys_clk_data[];
116extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[];
117extern const struct uniphier_clk_data uniphier_sld3_mio_clk_data[];
118extern const struct uniphier_clk_data uniphier_pro5_mio_clk_data[];
119extern const struct uniphier_clk_data uniphier_ld4_peri_clk_data[];
120extern const struct uniphier_clk_data uniphier_pro4_peri_clk_data[];
121
109#endif /* __CLK_UNIPHIER_H__ */ 122#endif /* __CLK_UNIPHIER_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-13 23:58:03 -0400