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authorAlex Deucher <alexander.deucher@amd.com>2016-06-13 18:59:17 -0400
committerAlex Deucher <alexander.deucher@amd.com>2016-06-13 18:59:17 -0400
commit7c4021d403ca72ce52d39c17d8154974521a82be (patch)
treea8f2fa1b0ee40bb83ef92fa45e47d76794786847
parent8b18300c13a1e08e152f6b6a430faac84f986231 (diff)
Revert "drm/amdgpu: add pipeline sync while vmid switch in same ctx"
This reverts commit 2ba272d7bde27e1db2cf1c6cee49b01b7ea08989. The issue fixed by this patch is specific to compute rings and the previous patch was enough. Additionally, this patch as been traced to strange behavior on some CZ systems so we might as well drop it.
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c9
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c6
3 files changed, 6 insertions, 13 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 70af26d97d28..e055d5be1c3c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -799,7 +799,6 @@ struct amdgpu_ring {
799 unsigned cond_exe_offs; 799 unsigned cond_exe_offs;
800 u64 cond_exe_gpu_addr; 800 u64 cond_exe_gpu_addr;
801 volatile u32 *cond_exe_cpu_addr; 801 volatile u32 *cond_exe_cpu_addr;
802 int vmid;
803}; 802};
804 803
805/* 804/*
@@ -937,8 +936,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring,
937 unsigned vm_id, uint64_t pd_addr, 936 unsigned vm_id, uint64_t pd_addr,
938 uint32_t gds_base, uint32_t gds_size, 937 uint32_t gds_base, uint32_t gds_size,
939 uint32_t gws_base, uint32_t gws_size, 938 uint32_t gws_base, uint32_t gws_size,
940 uint32_t oa_base, uint32_t oa_size, 939 uint32_t oa_base, uint32_t oa_size);
941 bool vmid_switch);
942void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id); 940void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);
943uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 941uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
944int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, 942int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 7a0b1e50f293..34e35423b78e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -122,7 +122,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
122 bool skip_preamble, need_ctx_switch; 122 bool skip_preamble, need_ctx_switch;
123 unsigned patch_offset = ~0; 123 unsigned patch_offset = ~0;
124 struct amdgpu_vm *vm; 124 struct amdgpu_vm *vm;
125 int vmid = 0, old_vmid = ring->vmid;
126 struct fence *hwf; 125 struct fence *hwf;
127 uint64_t ctx; 126 uint64_t ctx;
128 127
@@ -136,11 +135,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
136 if (job) { 135 if (job) {
137 vm = job->vm; 136 vm = job->vm;
138 ctx = job->ctx; 137 ctx = job->ctx;
139 vmid = job->vm_id;
140 } else { 138 } else {
141 vm = NULL; 139 vm = NULL;
142 ctx = 0; 140 ctx = 0;
143 vmid = 0;
144 } 141 }
145 142
146 if (!ring->ready) { 143 if (!ring->ready) {
@@ -166,8 +163,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
166 r = amdgpu_vm_flush(ring, job->vm_id, job->vm_pd_addr, 163 r = amdgpu_vm_flush(ring, job->vm_id, job->vm_pd_addr,
167 job->gds_base, job->gds_size, 164 job->gds_base, job->gds_size,
168 job->gws_base, job->gws_size, 165 job->gws_base, job->gws_size,
169 job->oa_base, job->oa_size, 166 job->oa_base, job->oa_size);
170 (ring->current_ctx == ctx) && (old_vmid != vmid));
171 if (r) { 167 if (r) {
172 amdgpu_ring_undo(ring); 168 amdgpu_ring_undo(ring);
173 return r; 169 return r;
@@ -184,6 +180,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
184 need_ctx_switch = ring->current_ctx != ctx; 180 need_ctx_switch = ring->current_ctx != ctx;
185 for (i = 0; i < num_ibs; ++i) { 181 for (i = 0; i < num_ibs; ++i) {
186 ib = &ibs[i]; 182 ib = &ibs[i];
183
187 /* drop preamble IBs if we don't have a context switch */ 184 /* drop preamble IBs if we don't have a context switch */
188 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && skip_preamble) 185 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && skip_preamble)
189 continue; 186 continue;
@@ -191,7 +188,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
191 amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0, 188 amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0,
192 need_ctx_switch); 189 need_ctx_switch);
193 need_ctx_switch = false; 190 need_ctx_switch = false;
194 ring->vmid = vmid;
195 } 191 }
196 192
197 if (ring->funcs->emit_hdp_invalidate) 193 if (ring->funcs->emit_hdp_invalidate)
@@ -202,7 +198,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
202 dev_err(adev->dev, "failed to emit fence (%d)\n", r); 198 dev_err(adev->dev, "failed to emit fence (%d)\n", r);
203 if (job && job->vm_id) 199 if (job && job->vm_id)
204 amdgpu_vm_reset_id(adev, job->vm_id); 200 amdgpu_vm_reset_id(adev, job->vm_id);
205 ring->vmid = old_vmid;
206 amdgpu_ring_undo(ring); 201 amdgpu_ring_undo(ring);
207 return r; 202 return r;
208 } 203 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 62a4c127620f..9f36ed30ba11 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -298,8 +298,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring,
298 unsigned vm_id, uint64_t pd_addr, 298 unsigned vm_id, uint64_t pd_addr,
299 uint32_t gds_base, uint32_t gds_size, 299 uint32_t gds_base, uint32_t gds_size,
300 uint32_t gws_base, uint32_t gws_size, 300 uint32_t gws_base, uint32_t gws_size,
301 uint32_t oa_base, uint32_t oa_size, 301 uint32_t oa_base, uint32_t oa_size)
302 bool vmid_switch)
303{ 302{
304 struct amdgpu_device *adev = ring->adev; 303 struct amdgpu_device *adev = ring->adev;
305 struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id]; 304 struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id];
@@ -313,7 +312,8 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring,
313 int r; 312 int r;
314 313
315 if (ring->funcs->emit_pipeline_sync && ( 314 if (ring->funcs->emit_pipeline_sync && (
316 pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed || vmid_switch)) 315 pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed ||
316 ring->type == AMDGPU_RING_TYPE_COMPUTE))
317 amdgpu_ring_emit_pipeline_sync(ring); 317 amdgpu_ring_emit_pipeline_sync(ring);
318 318
319 if (ring->funcs->emit_vm_flush && 319 if (ring->funcs->emit_vm_flush &&