davinci_mdio: Correct bitmask for clock divider value

The CLKDIV bitfield in the MDIO Control Register is a 16 bit field,
therefore the CLKDIV value may range from 0 to 0xffff.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c
index af8b8fc39eb2..2757c7d6e633 100644
--- a/drivers/net/ethernet/ti/davinci_mdio.c
+++ b/drivers/net/ethernet/ti/davinci_mdio.c
@@ -53,7 +53,7 @@ struct davinci_mdio_regs {
         u32     control;
 #define CONTROL_IDLE            BIT(31)
 #define CONTROL_ENABLE          BIT(30)
-#define CONTROL_MAX_DIV         (0xff)
+#define CONTROL_MAX_DIV         (0xffff)
 
         u32     alive;
         u32     link;