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authorYoshinori Sato <ysato@users.sourceforge.jp>2015-05-31 10:34:22 -0400
committerYoshinori Sato <ysato@users.sourceforge.jp>2015-11-08 08:44:39 -0500
commit780ffcd51cb287174e2d5cfe5ece2a7e73db6f37 (patch)
tree9d273982765208e2daf023d8e3a52713ba019de6
parent75078de4ac2901315b77dd813ae2bcb6a5fc1238 (diff)
h8300: register address fix
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
-rw-r--r--arch/h8300/boot/dts/edosk2674.dts6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/h8300/boot/dts/edosk2674.dts b/arch/h8300/boot/dts/edosk2674.dts
index dfb5c102f8da..4ce9fa874a57 100644
--- a/arch/h8300/boot/dts/edosk2674.dts
+++ b/arch/h8300/boot/dts/edosk2674.dts
@@ -7,7 +7,7 @@
7 7
8 chosen { 8 chosen {
9 bootargs = "console=ttySC2,38400"; 9 bootargs = "console=ttySC2,38400";
10 stdout-path = <&sci2>; 10 stdout-path = &sci2;
11 }; 11 };
12 aliases { 12 aliases {
13 serial0 = &sci0; 13 serial0 = &sci0;
@@ -25,13 +25,13 @@
25 compatible = "renesas,h8s2678-pll-clock"; 25 compatible = "renesas,h8s2678-pll-clock";
26 clocks = <&xclk>; 26 clocks = <&xclk>;
27 #clock-cells = <0>; 27 #clock-cells = <0>;
28 reg = <0xfee03b 2>, <0xfee045 2>; 28 reg = <0xffff3b 1>, <0xffff45 1>;
29 }; 29 };
30 core_clk: core_clk { 30 core_clk: core_clk {
31 compatible = "renesas,h8300-div-clock"; 31 compatible = "renesas,h8300-div-clock";
32 clocks = <&pllclk>; 32 clocks = <&pllclk>;
33 #clock-cells = <0>; 33 #clock-cells = <0>;
34 reg = <0xfee03b 2>; 34 reg = <0xffff3b 1>;
35 renesas,width = <3>; 35 renesas,width = <3>;
36 }; 36 };
37 fclk: fclk { 37 fclk: fclk {