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authorEzequiel Garcia <ezequiel@vanguardiasur.com.ar>2016-03-02 09:30:16 -0500
committerMauro Carvalho Chehab <mchehab@osg.samsung.com>2016-04-20 12:37:32 -0400
commit704a84ccdbf19fdce9adfda0b936dfdcac52fa49 (patch)
treef26e7c092581d921245d49a3ca90b95b6c66248f
parent0ff59f3190ba7b380ca4387dab5eb69d2b8f4d23 (diff)
[media] media: Support Intersil/Techwell TW686x-based video capture cards
This commit introduces the support for the Techwell TW686x video capture IC. This hardware supports a few DMA modes, including scatter-gather and frame (contiguous). This commit makes little use of the DMA engine and instead has a memcpy based implementation. DMA frame and scatter-gather modes support may be added in the future. Currently supported chips: - TW6864 (4 video channels), - TW6865 (4 video channels, not tested, second generation chip), - TW6868 (8 video channels but only 4 first channels using built-in video decoder are supported, not tested), - TW6869 (8 video channels, second generation chip). [mchehab@osg.samsung.com: make checkpatch happy by using "unsigned int" instead of just "unsigned"] Cc: Krzysztof Halasa <khalasa@piap.pl> Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Tested-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Diffstat
-rw-r--r--MAINTAINERS8
-rw-r--r--drivers/media/pci/Kconfig1
-rw-r--r--drivers/media/pci/Makefile1
-rw-r--r--drivers/media/pci/tw686x/Kconfig18
-rw-r--r--drivers/media/pci/tw686x/Makefile3
-rw-r--r--drivers/media/pci/tw686x/tw686x-audio.c386
-rw-r--r--drivers/media/pci/tw686x/tw686x-core.c415
-rw-r--r--drivers/media/pci/tw686x/tw686x-regs.h122
-rw-r--r--drivers/media/pci/tw686x/tw686x-video.c927
-rw-r--r--drivers/media/pci/tw686x/tw686x.h158
10 files changed, 2039 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 2ec50793c3ba..bfcb7ea42e20 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11258,6 +11258,14 @@ W: https://linuxtv.org
11258S: Odd Fixes 11258S: Odd Fixes
11259F: drivers/media/pci/tw68/ 11259F: drivers/media/pci/tw68/
11260 11260
11261TW686X VIDEO4LINUX DRIVER
11262M: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
11263L: linux-media@vger.kernel.org
11264T: git git://linuxtv.org/media_tree.git
11265W: http://linuxtv.org
11266S: Maintained
11267F: drivers/media/pci/tw686x/
11268
11261TPM DEVICE DRIVER 11269TPM DEVICE DRIVER
11262M: Peter Huewe <peterhuewe@gmx.de> 11270M: Peter Huewe <peterhuewe@gmx.de>
11263M: Marcel Selhorst <tpmdd@selhorst.net> 11271M: Marcel Selhorst <tpmdd@selhorst.net>
diff --git a/drivers/media/pci/Kconfig b/drivers/media/pci/Kconfig
index 48a611bc3e18..4f6467fbaeb4 100644
--- a/drivers/media/pci/Kconfig
+++ b/drivers/media/pci/Kconfig
@@ -14,6 +14,7 @@ source "drivers/media/pci/meye/Kconfig"
14source "drivers/media/pci/solo6x10/Kconfig" 14source "drivers/media/pci/solo6x10/Kconfig"
15source "drivers/media/pci/sta2x11/Kconfig" 15source "drivers/media/pci/sta2x11/Kconfig"
16source "drivers/media/pci/tw68/Kconfig" 16source "drivers/media/pci/tw68/Kconfig"
17source "drivers/media/pci/tw686x/Kconfig"
17source "drivers/media/pci/zoran/Kconfig" 18source "drivers/media/pci/zoran/Kconfig"
18endif 19endif
19 20
diff --git a/drivers/media/pci/Makefile b/drivers/media/pci/Makefile
index 5f8aacb8b9b8..2e54c36441f7 100644
--- a/drivers/media/pci/Makefile
+++ b/drivers/media/pci/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_VIDEO_BT848) += bt8xx/
25obj-$(CONFIG_VIDEO_SAA7134) += saa7134/ 25obj-$(CONFIG_VIDEO_SAA7134) += saa7134/
26obj-$(CONFIG_VIDEO_SAA7164) += saa7164/ 26obj-$(CONFIG_VIDEO_SAA7164) += saa7164/
27obj-$(CONFIG_VIDEO_TW68) += tw68/ 27obj-$(CONFIG_VIDEO_TW68) += tw68/
28obj-$(CONFIG_VIDEO_TW686X) += tw686x/
28obj-$(CONFIG_VIDEO_DT3155) += dt3155/ 29obj-$(CONFIG_VIDEO_DT3155) += dt3155/
29obj-$(CONFIG_VIDEO_MEYE) += meye/ 30obj-$(CONFIG_VIDEO_MEYE) += meye/
30obj-$(CONFIG_STA2X11_VIP) += sta2x11/ 31obj-$(CONFIG_STA2X11_VIP) += sta2x11/
diff --git a/drivers/media/pci/tw686x/Kconfig b/drivers/media/pci/tw686x/Kconfig
new file mode 100644
index 000000000000..fb8536974052
--- /dev/null
+++ b/drivers/media/pci/tw686x/Kconfig
@@ -0,0 +1,18 @@
1config VIDEO_TW686X
2 tristate "Intersil/Techwell TW686x video capture cards"
3 depends on PCI && VIDEO_DEV && VIDEO_V4L2 && SND
4 depends on HAS_DMA
5 select VIDEOBUF2_VMALLOC
6 select SND_PCM
7 help
8 Support for Intersil/Techwell TW686x-based frame grabber cards.
9
10 Currently supported chips:
11 - TW6864 (4 video channels),
12 - TW6865 (4 video channels, not tested, second generation chip),
13 - TW6868 (8 video channels but only 4 first channels using
14 built-in video decoder are supported, not tested),
15 - TW6869 (8 video channels, second generation chip).
16
17 To compile this driver as a module, choose M here: the module
18 will be named tw686x.
diff --git a/drivers/media/pci/tw686x/Makefile b/drivers/media/pci/tw686x/Makefile
new file mode 100644
index 000000000000..99819542b733
--- /dev/null
+++ b/drivers/media/pci/tw686x/Makefile
@@ -0,0 +1,3 @@
1tw686x-objs := tw686x-core.o tw686x-video.o tw686x-audio.o
2
3obj-$(CONFIG_VIDEO_TW686X) += tw686x.o
diff --git a/drivers/media/pci/tw686x/tw686x-audio.c b/drivers/media/pci/tw686x/tw686x-audio.c
new file mode 100644
index 000000000000..91459ab715b2
--- /dev/null
+++ b/drivers/media/pci/tw686x/tw686x-audio.c
@@ -0,0 +1,386 @@
1/*
2 * Copyright (C) 2015 VanguardiaSur - www.vanguardiasur.com.ar
3 *
4 * Based on the audio support from the tw6869 driver:
5 * Copyright 2015 www.starterkit.ru <info@starterkit.ru>
6 *
7 * Based on:
8 * Driver for Intersil|Techwell TW6869 based DVR cards
9 * (c) 2011-12 liran <jli11@intersil.com> [Intersil|Techwell China]
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of version 2 of the GNU General Public License
13 * as published by the Free Software Foundation.
14 */
15
16#include <linux/types.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/kmod.h>
21#include <linux/mutex.h>
22#include <linux/pci.h>
23#include <linux/delay.h>
24
25#include <sound/core.h>
26#include <sound/initval.h>
27#include <sound/pcm.h>
28#include <sound/control.h>
29#include "tw686x.h"
30#include "tw686x-regs.h"
31
32#define AUDIO_CHANNEL_OFFSET 8
33
34void tw686x_audio_irq(struct tw686x_dev *dev, unsigned long requests,
35 unsigned int pb_status)
36{
37 unsigned long flags;
38 unsigned int ch, pb;
39
40 for_each_set_bit(ch, &requests, max_channels(dev)) {
41 struct tw686x_audio_channel *ac = &dev->audio_channels[ch];
42 struct tw686x_audio_buf *done = NULL;
43 struct tw686x_audio_buf *next = NULL;
44 struct tw686x_dma_desc *desc;
45
46 pb = !!(pb_status & BIT(AUDIO_CHANNEL_OFFSET + ch));
47
48 spin_lock_irqsave(&ac->lock, flags);
49
50 /* Sanity check */
51 if (!ac->ss || !ac->curr_bufs[0] || !ac->curr_bufs[1]) {
52 spin_unlock_irqrestore(&ac->lock, flags);
53 continue;
54 }
55
56 if (!list_empty(&ac->buf_list)) {
57 next = list_first_entry(&ac->buf_list,
58 struct tw686x_audio_buf, list);
59 list_move_tail(&next->list, &ac->buf_list);
60 done = ac->curr_bufs[!pb];
61 ac->curr_bufs[pb] = next;
62 }
63 spin_unlock_irqrestore(&ac->lock, flags);
64
65 desc = &ac->dma_descs[pb];
66 if (done && next && desc->virt) {
67 memcpy(done->virt, desc->virt, desc->size);
68 ac->ptr = done->dma - ac->buf[0].dma;
69 snd_pcm_period_elapsed(ac->ss);
70 }
71 }
72}
73
74static int tw686x_pcm_hw_params(struct snd_pcm_substream *ss,
75 struct snd_pcm_hw_params *hw_params)
76{
77 return snd_pcm_lib_malloc_pages(ss, params_buffer_bytes(hw_params));
78}
79
80static int tw686x_pcm_hw_free(struct snd_pcm_substream *ss)
81{
82 return snd_pcm_lib_free_pages(ss);
83}
84
85/*
86 * The audio device rate is global and shared among all
87 * capture channels. The driver makes no effort to prevent
88 * rate modifications. User is free change the rate, but it
89 * means changing the rate for all capture sub-devices.
90 */
91static const struct snd_pcm_hardware tw686x_capture_hw = {
92 .info = (SNDRV_PCM_INFO_MMAP |
93 SNDRV_PCM_INFO_INTERLEAVED |
94 SNDRV_PCM_INFO_BLOCK_TRANSFER |
95 SNDRV_PCM_INFO_MMAP_VALID),
96 .formats = SNDRV_PCM_FMTBIT_S16_LE,
97 .rates = SNDRV_PCM_RATE_8000_48000,
98 .rate_min = 8000,
99 .rate_max = 48000,
100 .channels_min = 1,
101 .channels_max = 1,
102 .buffer_bytes_max = TW686X_AUDIO_PAGE_MAX * TW686X_AUDIO_PAGE_SZ,
103 .period_bytes_min = TW686X_AUDIO_PAGE_SZ,
104 .period_bytes_max = TW686X_AUDIO_PAGE_SZ,
105 .periods_min = TW686X_AUDIO_PERIODS_MIN,
106 .periods_max = TW686X_AUDIO_PERIODS_MAX,
107};
108
109static int tw686x_pcm_open(struct snd_pcm_substream *ss)
110{
111 struct tw686x_dev *dev = snd_pcm_substream_chip(ss);
112 struct tw686x_audio_channel *ac = &dev->audio_channels[ss->number];
113 struct snd_pcm_runtime *rt = ss->runtime;
114 int err;
115
116 ac->ss = ss;
117 rt->hw = tw686x_capture_hw;
118
119 err = snd_pcm_hw_constraint_integer(rt, SNDRV_PCM_HW_PARAM_PERIODS);
120 if (err < 0)
121 return err;
122
123 return 0;
124}
125
126static int tw686x_pcm_close(struct snd_pcm_substream *ss)
127{
128 struct tw686x_dev *dev = snd_pcm_substream_chip(ss);
129 struct tw686x_audio_channel *ac = &dev->audio_channels[ss->number];
130
131 ac->ss = NULL;
132 return 0;
133}
134
135static int tw686x_pcm_prepare(struct snd_pcm_substream *ss)
136{
137 struct tw686x_dev *dev = snd_pcm_substream_chip(ss);
138 struct tw686x_audio_channel *ac = &dev->audio_channels[ss->number];
139 struct snd_pcm_runtime *rt = ss->runtime;
140 unsigned int period_size = snd_pcm_lib_period_bytes(ss);
141 struct tw686x_audio_buf *p_buf, *b_buf;
142 unsigned long flags;
143 int i;
144
145 spin_lock_irqsave(&dev->lock, flags);
146 tw686x_disable_channel(dev, AUDIO_CHANNEL_OFFSET + ac->ch);
147 spin_unlock_irqrestore(&dev->lock, flags);
148
149 if (dev->audio_rate != rt->rate) {
150 u32 reg;
151
152 dev->audio_rate = rt->rate;
153 reg = ((125000000 / rt->rate) << 16) +
154 ((125000000 % rt->rate) << 16) / rt->rate;
155
156 reg_write(dev, AUDIO_CONTROL2, reg);
157 }
158
159 if (period_size != TW686X_AUDIO_PAGE_SZ ||
160 rt->periods < TW686X_AUDIO_PERIODS_MIN ||
161 rt->periods > TW686X_AUDIO_PERIODS_MAX) {
162 return -EINVAL;
163 }
164
165 spin_lock_irqsave(&ac->lock, flags);
166 INIT_LIST_HEAD(&ac->buf_list);
167
168 for (i = 0; i < rt->periods; i++) {
169 ac->buf[i].dma = rt->dma_addr + period_size * i;
170 ac->buf[i].virt = rt->dma_area + period_size * i;
171 INIT_LIST_HEAD(&ac->buf[i].list);
172 list_add_tail(&ac->buf[i].list, &ac->buf_list);
173 }
174
175 p_buf = list_first_entry(&ac->buf_list, struct tw686x_audio_buf, list);
176 list_move_tail(&p_buf->list, &ac->buf_list);
177
178 b_buf = list_first_entry(&ac->buf_list, struct tw686x_audio_buf, list);
179 list_move_tail(&b_buf->list, &ac->buf_list);
180
181 ac->curr_bufs[0] = p_buf;
182 ac->curr_bufs[1] = b_buf;
183 ac->ptr = 0;
184 spin_unlock_irqrestore(&ac->lock, flags);
185
186 return 0;
187}
188
189static int tw686x_pcm_trigger(struct snd_pcm_substream *ss, int cmd)
190{
191 struct tw686x_dev *dev = snd_pcm_substream_chip(ss);
192 struct tw686x_audio_channel *ac = &dev->audio_channels[ss->number];
193 unsigned long flags;
194 int err = 0;
195
196 switch (cmd) {
197 case SNDRV_PCM_TRIGGER_START:
198 if (ac->curr_bufs[0] && ac->curr_bufs[1]) {
199 spin_lock_irqsave(&dev->lock, flags);
200 tw686x_enable_channel(dev,
201 AUDIO_CHANNEL_OFFSET + ac->ch);
202 spin_unlock_irqrestore(&dev->lock, flags);
203
204 mod_timer(&dev->dma_delay_timer,
205 jiffies + msecs_to_jiffies(100));
206 } else {
207 err = -EIO;
208 }
209 break;
210 case SNDRV_PCM_TRIGGER_STOP:
211 spin_lock_irqsave(&dev->lock, flags);
212 tw686x_disable_channel(dev, AUDIO_CHANNEL_OFFSET + ac->ch);
213 spin_unlock_irqrestore(&dev->lock, flags);
214
215 spin_lock_irqsave(&ac->lock, flags);
216 ac->curr_bufs[0] = NULL;
217 ac->curr_bufs[1] = NULL;
218 spin_unlock_irqrestore(&ac->lock, flags);
219 break;
220 default:
221 err = -EINVAL;
222 }
223 return err;
224}
225
226static snd_pcm_uframes_t tw686x_pcm_pointer(struct snd_pcm_substream *ss)
227{
228 struct tw686x_dev *dev = snd_pcm_substream_chip(ss);
229 struct tw686x_audio_channel *ac = &dev->audio_channels[ss->number];
230
231 return bytes_to_frames(ss->runtime, ac->ptr);
232}
233
234static struct snd_pcm_ops tw686x_pcm_ops = {
235 .open = tw686x_pcm_open,
236 .close = tw686x_pcm_close,
237 .ioctl = snd_pcm_lib_ioctl,
238 .hw_params = tw686x_pcm_hw_params,
239 .hw_free = tw686x_pcm_hw_free,
240 .prepare = tw686x_pcm_prepare,
241 .trigger = tw686x_pcm_trigger,
242 .pointer = tw686x_pcm_pointer,
243};
244
245static int tw686x_snd_pcm_init(struct tw686x_dev *dev)
246{
247 struct snd_card *card = dev->snd_card;
248 struct snd_pcm *pcm;
249 struct snd_pcm_substream *ss;
250 unsigned int i;
251 int err;
252
253 err = snd_pcm_new(card, card->driver, 0, 0, max_channels(dev), &pcm);
254 if (err < 0)
255 return err;
256
257 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &tw686x_pcm_ops);
258 snd_pcm_chip(pcm) = dev;
259 pcm->info_flags = 0;
260 strlcpy(pcm->name, "tw686x PCM", sizeof(pcm->name));
261
262 for (i = 0, ss = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
263 ss; ss = ss->next, i++)
264 snprintf(ss->name, sizeof(ss->name), "vch%u audio", i);
265
266 return snd_pcm_lib_preallocate_pages_for_all(pcm,
267 SNDRV_DMA_TYPE_DEV,
268 snd_dma_pci_data(dev->pci_dev),
269 TW686X_AUDIO_PAGE_MAX * TW686X_AUDIO_PAGE_SZ,
270 TW686X_AUDIO_PAGE_MAX * TW686X_AUDIO_PAGE_SZ);
271}
272
273static void tw686x_audio_dma_free(struct tw686x_dev *dev,
274 struct tw686x_audio_channel *ac)
275{
276 int pb;
277
278 for (pb = 0; pb < 2; pb++) {
279 if (!ac->dma_descs[pb].virt)
280 continue;
281 pci_free_consistent(dev->pci_dev, ac->dma_descs[pb].size,
282 ac->dma_descs[pb].virt,
283 ac->dma_descs[pb].phys);
284 ac->dma_descs[pb].virt = NULL;
285 }
286}
287
288static int tw686x_audio_dma_alloc(struct tw686x_dev *dev,
289 struct tw686x_audio_channel *ac)
290{
291 int pb;
292
293 for (pb = 0; pb < 2; pb++) {
294 u32 reg = pb ? ADMA_B_ADDR[ac->ch] : ADMA_P_ADDR[ac->ch];
295 void *virt;
296
297 virt = pci_alloc_consistent(dev->pci_dev, TW686X_AUDIO_PAGE_SZ,
298 &ac->dma_descs[pb].phys);
299 if (!virt) {
300 dev_err(&dev->pci_dev->dev,
301 "dma%d: unable to allocate audio DMA %s-buffer\n",
302 ac->ch, pb ? "B" : "P");
303 return -ENOMEM;
304 }
305 ac->dma_descs[pb].virt = virt;
306 ac->dma_descs[pb].size = TW686X_AUDIO_PAGE_SZ;
307 reg_write(dev, reg, ac->dma_descs[pb].phys);
308 }
309 return 0;
310}
311
312void tw686x_audio_free(struct tw686x_dev *dev)
313{
314 unsigned long flags;
315 u32 dma_ch_mask;
316 u32 dma_cmd;
317
318 spin_lock_irqsave(&dev->lock, flags);
319 dma_cmd = reg_read(dev, DMA_CMD);
320 dma_ch_mask = reg_read(dev, DMA_CHANNEL_ENABLE);
321 reg_write(dev, DMA_CMD, dma_cmd & ~0xff00);
322 reg_write(dev, DMA_CHANNEL_ENABLE, dma_ch_mask & ~0xff00);
323 spin_unlock_irqrestore(&dev->lock, flags);
324
325 if (!dev->snd_card)
326 return;
327 snd_card_free(dev->snd_card);
328 dev->snd_card = NULL;
329}
330
331int tw686x_audio_init(struct tw686x_dev *dev)
332{
333 struct pci_dev *pci_dev = dev->pci_dev;
334 struct snd_card *card;
335 int err, ch;
336
337 /*
338 * AUDIO_CONTROL1
339 * DMA byte length [31:19] = 4096 (i.e. ALSA period)
340 * External audio enable [0] = enabled
341 */
342 reg_write(dev, AUDIO_CONTROL1, 0x80000001);
343
344 err = snd_card_new(&pci_dev->dev, SNDRV_DEFAULT_IDX1,
345 SNDRV_DEFAULT_STR1,
346 THIS_MODULE, 0, &card);
347 if (err < 0)
348 return err;
349
350 dev->snd_card = card;
351 strlcpy(card->driver, "tw686x", sizeof(card->driver));
352 strlcpy(card->shortname, "tw686x", sizeof(card->shortname));
353 strlcpy(card->longname, pci_name(pci_dev), sizeof(card->longname));
354 snd_card_set_dev(card, &pci_dev->dev);
355
356 for (ch = 0; ch < max_channels(dev); ch++) {
357 struct tw686x_audio_channel *ac;
358
359 ac = &dev->audio_channels[ch];
360 spin_lock_init(&ac->lock);
361 ac->dev = dev;
362 ac->ch = ch;
363
364 err = tw686x_audio_dma_alloc(dev, ac);
365 if (err < 0)
366 goto err_cleanup;
367 }
368
369 err = tw686x_snd_pcm_init(dev);
370 if (err < 0)
371 goto err_cleanup;
372
373 err = snd_card_register(card);
374 if (!err)
375 return 0;
376
377err_cleanup:
378 for (ch = 0; ch < max_channels(dev); ch++) {
379 if (!dev->audio_channels[ch].dev)
380 continue;
381 tw686x_audio_dma_free(dev, &dev->audio_channels[ch]);
382 }
383 snd_card_free(card);
384 dev->snd_card = NULL;
385 return err;
386}
diff --git a/drivers/media/pci/tw686x/tw686x-core.c b/drivers/media/pci/tw686x/tw686x-core.c
new file mode 100644
index 000000000000..cf53b0e97be2
--- /dev/null
+++ b/drivers/media/pci/tw686x/tw686x-core.c
@@ -0,0 +1,415 @@
1/*
2 * Copyright (C) 2015 VanguardiaSur - www.vanguardiasur.com.ar
3 *
4 * Based on original driver by Krzysztof Ha?asa:
5 * Copyright (C) 2015 Industrial Research Institute for Automation
6 * and Measurements PIAP
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License
10 * as published by the Free Software Foundation.
11 *
12 * Notes
13 * -----
14 *
15 * 1. Under stress-testing, it has been observed that the PCIe link
16 * goes down, without reason. Therefore, the driver takes special care
17 * to allow device hot-unplugging.
18 *
19 * 2. TW686X devices are capable of setting a few different DMA modes,
20 * including: scatter-gather, field and frame modes. However,
21 * under stress testings it has been found that the machine can
22 * freeze completely if DMA registers are programmed while streaming
23 * is active.
24 * This driver tries to access hardware registers as infrequently
25 * as possible by:
26 * i. allocating fixed DMA buffers and memcpy'ing into
27 * vmalloc'ed buffers
28 * ii. using a timer to mitigate the rate of DMA reset operations,
29 * on DMA channels error.
30 */
31
32#include <linux/init.h>
33#include <linux/interrupt.h>
34#include <linux/delay.h>
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci_ids.h>
38#include <linux/slab.h>
39#include <linux/timer.h>
40
41#include "tw686x.h"
42#include "tw686x-regs.h"
43
44/*
45 * This module parameter allows to control the DMA_TIMER_INTERVAL value.
46 * The DMA_TIMER_INTERVAL register controls the minimum DMA interrupt
47 * time span (iow, the maximum DMA interrupt rate) thus allowing for
48 * IRQ coalescing.
49 *
50 * The chip datasheet does not mention a time unit for this value, so
51 * users wanting fine-grain control over the interrupt rate should
52 * determine the desired value through testing.
53 */
54static u32 dma_interval = 0x00098968;
55module_param(dma_interval, int, 0444);
56MODULE_PARM_DESC(dma_interval, "Minimum time span for DMA interrupting host");
57
58void tw686x_disable_channel(struct tw686x_dev *dev, unsigned int channel)
59{
60 u32 dma_en = reg_read(dev, DMA_CHANNEL_ENABLE);
61 u32 dma_cmd = reg_read(dev, DMA_CMD);
62
63 dma_en &= ~BIT(channel);
64 dma_cmd &= ~BIT(channel);
65
66 /* Must remove it from pending too */
67 dev->pending_dma_en &= ~BIT(channel);
68 dev->pending_dma_cmd &= ~BIT(channel);
69
70 /* Stop DMA if no channels are enabled */
71 if (!dma_en)
72 dma_cmd = 0;
73 reg_write(dev, DMA_CHANNEL_ENABLE, dma_en);
74 reg_write(dev, DMA_CMD, dma_cmd);
75}
76
77void tw686x_enable_channel(struct tw686x_dev *dev, unsigned int channel)
78{
79 u32 dma_en = reg_read(dev, DMA_CHANNEL_ENABLE);
80 u32 dma_cmd = reg_read(dev, DMA_CMD);
81
82 dev->pending_dma_en |= dma_en | BIT(channel);
83 dev->pending_dma_cmd |= dma_cmd | DMA_CMD_ENABLE | BIT(channel);
84}
85
86/*
87 * The purpose of this awful hack is to avoid enabling the DMA
88 * channels "too fast" which makes some TW686x devices very
89 * angry and freeze the CPU (see note 1).
90 */
91static void tw686x_dma_delay(unsigned long data)
92{
93 struct tw686x_dev *dev = (struct tw686x_dev *)data;
94 unsigned long flags;
95
96 spin_lock_irqsave(&dev->lock, flags);
97
98 reg_write(dev, DMA_CHANNEL_ENABLE, dev->pending_dma_en);
99 reg_write(dev, DMA_CMD, dev->pending_dma_cmd);
100 dev->pending_dma_en = 0;
101 dev->pending_dma_cmd = 0;
102
103 spin_unlock_irqrestore(&dev->lock, flags);
104}
105
106static void tw686x_reset_channels(struct tw686x_dev *dev, unsigned int ch_mask)
107{
108 u32 dma_en, dma_cmd;
109
110 dma_en = reg_read(dev, DMA_CHANNEL_ENABLE);
111 dma_cmd = reg_read(dev, DMA_CMD);
112
113 /*
114 * Save pending register status, the timer will
115 * restore them.
116 */
117 dev->pending_dma_en |= dma_en;
118 dev->pending_dma_cmd |= dma_cmd;
119
120 /* Disable the reset channels */
121 reg_write(dev, DMA_CHANNEL_ENABLE, dma_en & ~ch_mask);
122
123 if ((dma_en & ~ch_mask) == 0) {
124 dev_dbg(&dev->pci_dev->dev, "reset: stopping DMA\n");
125 dma_cmd &= ~DMA_CMD_ENABLE;
126 }
127 reg_write(dev, DMA_CMD, dma_cmd & ~ch_mask);
128}
129
130static irqreturn_t tw686x_irq(int irq, void *dev_id)
131{
132 struct tw686x_dev *dev = (struct tw686x_dev *)dev_id;
133 unsigned int video_requests, audio_requests, reset_ch;
134 u32 fifo_status, fifo_signal, fifo_ov, fifo_bad, fifo_errors;
135 u32 int_status, dma_en, video_en, pb_status;
136 unsigned long flags;
137
138 int_status = reg_read(dev, INT_STATUS); /* cleared on read */
139 fifo_status = reg_read(dev, VIDEO_FIFO_STATUS);
140
141 /* INT_STATUS does not include FIFO_STATUS errors! */
142 if (!int_status && !TW686X_FIFO_ERROR(fifo_status))
143 return IRQ_NONE;
144
145 if (int_status & INT_STATUS_DMA_TOUT) {
146 dev_dbg(&dev->pci_dev->dev,
147 "DMA timeout. Resetting DMA for all channels\n");
148 reset_ch = ~0;
149 goto reset_channels;
150 }
151
152 spin_lock_irqsave(&dev->lock, flags);
153 dma_en = reg_read(dev, DMA_CHANNEL_ENABLE);
154 spin_unlock_irqrestore(&dev->lock, flags);
155
156 video_en = dma_en & 0xff;
157 fifo_signal = ~(fifo_status & 0xff) & video_en;
158 fifo_ov = fifo_status >> 24;
159 fifo_bad = fifo_status >> 16;
160
161 /* Mask of channels with signal and FIFO errors */
162 fifo_errors = fifo_signal & (fifo_ov | fifo_bad);
163
164 reset_ch = 0;
165 pb_status = reg_read(dev, PB_STATUS);
166
167 /* Coalesce video frame/error events */
168 video_requests = (int_status & video_en) | fifo_errors;
169 audio_requests = (int_status & dma_en) >> 8;
170
171 if (video_requests)
172 tw686x_video_irq(dev, video_requests, pb_status,
173 fifo_status, &reset_ch);
174 if (audio_requests)
175 tw686x_audio_irq(dev, audio_requests, pb_status);
176
177reset_channels:
178 if (reset_ch) {
179 spin_lock_irqsave(&dev->lock, flags);
180 tw686x_reset_channels(dev, reset_ch);
181 spin_unlock_irqrestore(&dev->lock, flags);
182 mod_timer(&dev->dma_delay_timer,
183 jiffies + msecs_to_jiffies(100));
184 }
185
186 return IRQ_HANDLED;
187}
188
189static void tw686x_dev_release(struct v4l2_device *v4l2_dev)
190{
191 struct tw686x_dev *dev = container_of(v4l2_dev, struct tw686x_dev,
192 v4l2_dev);
193 unsigned int ch;
194
195 for (ch = 0; ch < max_channels(dev); ch++)
196 v4l2_ctrl_handler_free(&dev->video_channels[ch].ctrl_handler);
197
198 v4l2_device_unregister(&dev->v4l2_dev);
199
200 kfree(dev->audio_channels);
201 kfree(dev->video_channels);
202 kfree(dev);
203}
204
205static int tw686x_probe(struct pci_dev *pci_dev,
206 const struct pci_device_id *pci_id)
207{
208 struct tw686x_dev *dev;
209 int err;
210
211 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
212 if (!dev)
213 return -ENOMEM;
214 dev->type = pci_id->driver_data;
215 sprintf(dev->name, "tw%04X", pci_dev->device);
216
217 dev->video_channels = kcalloc(max_channels(dev),
218 sizeof(*dev->video_channels), GFP_KERNEL);
219 if (!dev->video_channels) {
220 err = -ENOMEM;
221 goto free_dev;
222 }
223
224 dev->audio_channels = kcalloc(max_channels(dev),
225 sizeof(*dev->audio_channels), GFP_KERNEL);
226 if (!dev->audio_channels) {
227 err = -ENOMEM;
228 goto free_video;
229 }
230
231 pr_info("%s: PCI %s, IRQ %d, MMIO 0x%lx\n", dev->name,
232 pci_name(pci_dev), pci_dev->irq,
233 (unsigned long)pci_resource_start(pci_dev, 0));
234
235 dev->pci_dev = pci_dev;
236 if (pci_enable_device(pci_dev)) {
237 err = -EIO;
238 goto free_audio;
239 }
240
241 pci_set_master(pci_dev);
242 err = pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32));
243 if (err) {
244 dev_err(&pci_dev->dev, "32-bit PCI DMA not supported\n");
245 err = -EIO;
246 goto disable_pci;
247 }
248
249 err = pci_request_regions(pci_dev, dev->name);
250 if (err) {
251 dev_err(&pci_dev->dev, "unable to request PCI region\n");
252 goto disable_pci;
253 }
254
255 dev->mmio = pci_ioremap_bar(pci_dev, 0);
256 if (!dev->mmio) {
257 dev_err(&pci_dev->dev, "unable to remap PCI region\n");
258 err = -ENOMEM;
259 goto free_region;
260 }
261
262 /* Reset all subsystems */
263 reg_write(dev, SYS_SOFT_RST, 0x0f);
264 mdelay(1);
265
266 reg_write(dev, SRST[0], 0x3f);
267 if (max_channels(dev) > 4)
268 reg_write(dev, SRST[1], 0x3f);
269
270 /* Disable the DMA engine */
271 reg_write(dev, DMA_CMD, 0);
272 reg_write(dev, DMA_CHANNEL_ENABLE, 0);
273
274 /* Enable DMA FIFO overflow and pointer check */
275 reg_write(dev, DMA_CONFIG, 0xffffff04);
276 reg_write(dev, DMA_CHANNEL_TIMEOUT, 0x140c8584);
277 reg_write(dev, DMA_TIMER_INTERVAL, dma_interval);
278
279 spin_lock_init(&dev->lock);
280
281 err = request_irq(pci_dev->irq, tw686x_irq, IRQF_SHARED,
282 dev->name, dev);
283 if (err < 0) {
284 dev_err(&pci_dev->dev, "unable to request interrupt\n");
285 goto iounmap;
286 }
287
288 setup_timer(&dev->dma_delay_timer,
289 tw686x_dma_delay, (unsigned long) dev);
290
291 /*
292 * This must be set right before initializing v4l2_dev.
293 * It's used to release resources after the last handle
294 * held is released.
295 */
296 dev->v4l2_dev.release = tw686x_dev_release;
297 err = tw686x_video_init(dev);
298 if (err) {
299 dev_err(&pci_dev->dev, "can't register video\n");
300 goto free_irq;
301 }
302
303 err = tw686x_audio_init(dev);
304 if (err)
305 dev_warn(&pci_dev->dev, "can't register audio\n");
306
307 pci_set_drvdata(pci_dev, dev);
308 return 0;
309
310free_irq:
311 free_irq(pci_dev->irq, dev);
312iounmap:
313 pci_iounmap(pci_dev, dev->mmio);
314free_region:
315 pci_release_regions(pci_dev);
316disable_pci:
317 pci_disable_device(pci_dev);
318free_audio:
319 kfree(dev->audio_channels);
320free_video:
321 kfree(dev->video_channels);
322free_dev:
323 kfree(dev);
324 return err;
325}
326
327static void tw686x_remove(struct pci_dev *pci_dev)
328{
329 struct tw686x_dev *dev = pci_get_drvdata(pci_dev);
330 unsigned long flags;
331
332 /* This guarantees the IRQ handler is no longer running,
333 * which means we can kiss good-bye some resources.
334 */
335 free_irq(pci_dev->irq, dev);
336
337 tw686x_video_free(dev);
338 tw686x_audio_free(dev);
339 del_timer_sync(&dev->dma_delay_timer);
340
341 pci_iounmap(pci_dev, dev->mmio);
342 pci_release_regions(pci_dev);
343 pci_disable_device(pci_dev);
344
345 /*
346 * Setting pci_dev to NULL allows to detect hardware is no longer
347 * available and will be used by vb2_ops. This is required because
348 * the device sometimes hot-unplugs itself as the result of a PCIe
349 * link down.
350 * The lock is really important here.
351 */
352 spin_lock_irqsave(&dev->lock, flags);
353 dev->pci_dev = NULL;
354 spin_unlock_irqrestore(&dev->lock, flags);
355
356 /*
357 * This calls tw686x_dev_release if it's the last reference.
358 * Otherwise, release is postponed until there are no users left.
359 */
360 v4l2_device_put(&dev->v4l2_dev);
361}
362
363/*
364 * On TW6864 and TW6868, all channels share the pair of video DMA SG tables,
365 * with 10-bit start_idx and end_idx determining start and end of frame buffer
366 * for particular channel.
367 * TW6868 with all its 8 channels would be problematic (only 127 SG entries per
368 * channel) but we support only 4 channels on this chip anyway (the first
369 * 4 channels are driven with internal video decoder, the other 4 would require
370 * an external TW286x part).
371 *
372 * On TW6865 and TW6869, each channel has its own DMA SG table, with indexes
373 * starting with 0. Both chips have complete sets of internal video decoders
374 * (respectively 4 or 8-channel).
375 *
376 * All chips have separate SG tables for two video frames.
377 */
378
379/* driver_data is number of A/V channels */
380static const struct pci_device_id tw686x_pci_tbl[] = {
381 {
382 PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, 0x6864),
383 .driver_data = 4
384 },
385 {
386 PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, 0x6865), /* not tested */
387 .driver_data = 4 | TYPE_SECOND_GEN
388 },
389 /*
390 * TW6868 supports 8 A/V channels with an external TW2865 chip;
391 * not supported by the driver.
392 */
393 {
394 PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, 0x6868), /* not tested */
395 .driver_data = 4
396 },
397 {
398 PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, 0x6869),
399 .driver_data = 8 | TYPE_SECOND_GEN},
400 {}
401};
402MODULE_DEVICE_TABLE(pci, tw686x_pci_tbl);
403
404static struct pci_driver tw686x_pci_driver = {
405 .name = "tw686x",
406 .id_table = tw686x_pci_tbl,
407 .probe = tw686x_probe,
408 .remove = tw686x_remove,
409};
410module_pci_driver(tw686x_pci_driver);
411
412MODULE_DESCRIPTION("Driver for video frame grabber cards based on Intersil/Techwell TW686[4589]");
413MODULE_AUTHOR("Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>");
414MODULE_AUTHOR("Krzysztof Ha?asa <khalasa@piap.pl>");
415MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/pci/tw686x/tw686x-regs.h b/drivers/media/pci/tw686x/tw686x-regs.h
new file mode 100644
index 000000000000..fcef586a4c8c
--- /dev/null
+++ b/drivers/media/pci/tw686x/tw686x-regs.h
@@ -0,0 +1,122 @@
1/* DMA controller registers */
2#define REG8_1(a0) ((const u16[8]) { a0, a0 + 1, a0 + 2, a0 + 3, \
3 a0 + 4, a0 + 5, a0 + 6, a0 + 7})
4#define REG8_2(a0) ((const u16[8]) { a0, a0 + 2, a0 + 4, a0 + 6, \
5 a0 + 8, a0 + 0xa, a0 + 0xc, a0 + 0xe})
6#define REG8_8(a0) ((const u16[8]) { a0, a0 + 8, a0 + 0x10, a0 + 0x18, \
7 a0 + 0x20, a0 + 0x28, a0 + 0x30, \
8 a0 + 0x38})
9#define INT_STATUS 0x00
10#define PB_STATUS 0x01
11#define DMA_CMD 0x02
12#define VIDEO_FIFO_STATUS 0x03
13#define VIDEO_CHANNEL_ID 0x04
14#define VIDEO_PARSER_STATUS 0x05
15#define SYS_SOFT_RST 0x06
16#define DMA_PAGE_TABLE0_ADDR ((const u16[8]) { 0x08, 0xd0, 0xd2, 0xd4, \
17 0xd6, 0xd8, 0xda, 0xdc })
18#define DMA_PAGE_TABLE1_ADDR ((const u16[8]) { 0x09, 0xd1, 0xd3, 0xd5, \
19 0xd7, 0xd9, 0xdb, 0xdd })
20#define DMA_CHANNEL_ENABLE 0x0a
21#define DMA_CONFIG 0x0b
22#define DMA_TIMER_INTERVAL 0x0c
23#define DMA_CHANNEL_TIMEOUT 0x0d
24#define VDMA_CHANNEL_CONFIG REG8_1(0x10)
25#define ADMA_P_ADDR REG8_2(0x18)
26#define ADMA_B_ADDR REG8_2(0x19)
27#define DMA10_P_ADDR 0x28
28#define DMA10_B_ADDR 0x29
29#define VIDEO_CONTROL1 0x2a
30#define VIDEO_CONTROL2 0x2b
31#define AUDIO_CONTROL1 0x2c
32#define AUDIO_CONTROL2 0x2d
33#define PHASE_REF 0x2e
34#define GPIO_REG 0x2f
35#define INTL_HBAR_CTRL REG8_1(0x30)
36#define AUDIO_CONTROL3 0x38
37#define VIDEO_FIELD_CTRL REG8_1(0x39)
38#define HSCALER_CTRL REG8_1(0x42)
39#define VIDEO_SIZE REG8_1(0x4A)
40#define VIDEO_SIZE_F2 REG8_1(0x52)
41#define MD_CONF REG8_1(0x60)
42#define MD_INIT REG8_1(0x68)
43#define MD_MAP0 REG8_1(0x70)
44#define VDMA_P_ADDR REG8_8(0x80) /* not used in DMA SG mode */
45#define VDMA_WHP REG8_8(0x81)
46#define VDMA_B_ADDR REG8_8(0x82)
47#define VDMA_F2_P_ADDR REG8_8(0x84)
48#define VDMA_F2_WHP REG8_8(0x85)
49#define VDMA_F2_B_ADDR REG8_8(0x86)
50#define EP_REG_ADDR 0xfe
51#define EP_REG_DATA 0xff
52
53/* Video decoder registers */
54#define VDREG8(a0) ((const u16[8]) { \
55 a0 + 0x000, a0 + 0x010, a0 + 0x020, a0 + 0x030, \
56 a0 + 0x100, a0 + 0x110, a0 + 0x120, a0 + 0x130})
57#define VIDSTAT VDREG8(0x100)
58#define BRIGHT VDREG8(0x101)
59#define CONTRAST VDREG8(0x102)
60#define SHARPNESS VDREG8(0x103)
61#define SAT_U VDREG8(0x104)
62#define SAT_V VDREG8(0x105)
63#define HUE VDREG8(0x106)
64#define CROP_HI VDREG8(0x107)
65#define VDELAY_LO VDREG8(0x108)
66#define VACTIVE_LO VDREG8(0x109)
67#define HDELAY_LO VDREG8(0x10a)
68#define HACTIVE_LO VDREG8(0x10b)
69#define MVSN VDREG8(0x10c)
70#define STATUS2 VDREG8(0x10d)
71#define SDT VDREG8(0x10e)
72#define SDT_EN VDREG8(0x10f)
73
74#define VSCALE_LO VDREG8(0x144)
75#define SCALE_HI VDREG8(0x145)
76#define HSCALE_LO VDREG8(0x146)
77#define F2CROP_HI VDREG8(0x147)
78#define F2VDELAY_LO VDREG8(0x148)
79#define F2VACTIVE_LO VDREG8(0x149)
80#define F2HDELAY_LO VDREG8(0x14a)
81#define F2HACTIVE_LO VDREG8(0x14b)
82#define F2VSCALE_LO VDREG8(0x14c)
83#define F2SCALE_HI VDREG8(0x14d)
84#define F2HSCALE_LO VDREG8(0x14e)
85#define F2CNT VDREG8(0x14f)
86
87#define VDREG2(a0) ((const u16[2]) { a0, a0 + 0x100 })
88#define SRST VDREG2(0x180)
89#define ACNTL VDREG2(0x181)
90#define ACNTL2 VDREG2(0x182)
91#define CNTRL1 VDREG2(0x183)
92#define CKHY VDREG2(0x184)
93#define SHCOR VDREG2(0x185)
94#define CORING VDREG2(0x186)
95#define CLMPG VDREG2(0x187)
96#define IAGC VDREG2(0x188)
97#define VCTRL1 VDREG2(0x18f)
98#define MISC1 VDREG2(0x194)
99#define LOOP VDREG2(0x195)
100#define MISC2 VDREG2(0x196)
101
102#define CLMD VDREG2(0x197)
103#define ANPWRDOWN VDREG2(0x1ce)
104#define AIGAIN ((const u16[8]) { 0x1d0, 0x1d1, 0x1d2, 0x1d3, \
105 0x2d0, 0x2d1, 0x2d2, 0x2d3 })
106
107#define SYS_MODE_DMA_SHIFT 13
108
109#define DMA_CMD_ENABLE BIT(31)
110#define INT_STATUS_DMA_TOUT BIT(17)
111#define TW686X_VIDSTAT_HLOCK BIT(6)
112#define TW686X_VIDSTAT_VDLOSS BIT(7)
113
114#define TW686X_STD_NTSC_M 0
115#define TW686X_STD_PAL 1
116#define TW686X_STD_SECAM 2
117#define TW686X_STD_NTSC_443 3
118#define TW686X_STD_PAL_M 4
119#define TW686X_STD_PAL_CN 5
120#define TW686X_STD_PAL_60 6
121
122#define TW686X_FIFO_ERROR(x) (x & ~(0xff))
diff --git a/drivers/media/pci/tw686x/tw686x-video.c b/drivers/media/pci/tw686x/tw686x-video.c
new file mode 100644
index 000000000000..35ad8e650717
--- /dev/null
+++ b/drivers/media/pci/tw686x/tw686x-video.c
@@ -0,0 +1,927 @@
1/*
2 * Copyright (C) 2015 VanguardiaSur - www.vanguardiasur.com.ar
3 *
4 * Based on original driver by Krzysztof Ha?asa:
5 * Copyright (C) 2015 Industrial Research Institute for Automation
6 * and Measurements PIAP
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License
10 * as published by the Free Software Foundation.
11 *
12 */
13
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/list.h>
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/slab.h>
20#include <media/v4l2-common.h>
21#include <media/v4l2-event.h>
22#include <media/videobuf2-vmalloc.h>
23#include "tw686x.h"
24#include "tw686x-regs.h"
25
26#define TW686X_INPUTS_PER_CH 4
27#define TW686X_VIDEO_WIDTH 720
28#define TW686X_VIDEO_HEIGHT(id) ((id & V4L2_STD_625_50) ? 576 : 480)
29
30static const struct tw686x_format formats[] = {
31 {
32 .fourcc = V4L2_PIX_FMT_UYVY,
33 .mode = 0,
34 .depth = 16,
35 }, {
36 .fourcc = V4L2_PIX_FMT_RGB565,
37 .mode = 5,
38 .depth = 16,
39 }, {
40 .fourcc = V4L2_PIX_FMT_YUYV,
41 .mode = 6,
42 .depth = 16,
43 }
44};
45
46static unsigned int tw686x_fields_map(v4l2_std_id std, unsigned int fps)
47{
48 static const unsigned int map[15] = {
49 0x00000000, 0x00000001, 0x00004001, 0x00104001, 0x00404041,
50 0x01041041, 0x01104411, 0x01111111, 0x04444445, 0x04511445,
51 0x05145145, 0x05151515, 0x05515455, 0x05551555, 0x05555555
52 };
53
54 static const unsigned int std_625_50[26] = {
55 0, 1, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7,
56 8, 8, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 0
57 };
58
59 static const unsigned int std_525_60[31] = {
60 0, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
61 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 0, 0
62 };
63
64 unsigned int i =
65 (std & V4L2_STD_625_50) ? std_625_50[fps] : std_525_60[fps];
66
67 return map[i];
68}
69
70static void tw686x_set_framerate(struct tw686x_video_channel *vc,
71 unsigned int fps)
72{
73 unsigned int map;
74
75 if (vc->fps == fps)
76 return;
77
78 map = tw686x_fields_map(vc->video_standard, fps) << 1;
79 map |= map << 1;
80 if (map > 0)
81 map |= BIT(31);
82 reg_write(vc->dev, VIDEO_FIELD_CTRL[vc->ch], map);
83 vc->fps = fps;
84}
85
86static const struct tw686x_format *format_by_fourcc(unsigned int fourcc)
87{
88 unsigned int cnt;
89
90 for (cnt = 0; cnt < ARRAY_SIZE(formats); cnt++)
91 if (formats[cnt].fourcc == fourcc)
92 return &formats[cnt];
93 return NULL;
94}
95
96static int tw686x_queue_setup(struct vb2_queue *vq,
97 unsigned int *nbuffers, unsigned int *nplanes,
98 unsigned int sizes[], void *alloc_ctxs[])
99{
100 struct tw686x_video_channel *vc = vb2_get_drv_priv(vq);
101 unsigned int szimage =
102 (vc->width * vc->height * vc->format->depth) >> 3;
103
104 /*
105 * Let's request at least three buffers: two for the
106 * DMA engine and one for userspace.
107 */
108 if (vq->num_buffers + *nbuffers < 3)
109 *nbuffers = 3 - vq->num_buffers;
110
111 if (*nplanes) {
112 if (*nplanes != 1 || sizes[0] < szimage)
113 return -EINVAL;
114 return 0;
115 }
116
117 sizes[0] = szimage;
118 *nplanes = 1;
119 return 0;
120}
121
122static void tw686x_buf_queue(struct vb2_buffer *vb)
123{
124 struct tw686x_video_channel *vc = vb2_get_drv_priv(vb->vb2_queue);
125 struct tw686x_dev *dev = vc->dev;
126 struct pci_dev *pci_dev;
127 unsigned long flags;
128 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
129 struct tw686x_v4l2_buf *buf =
130 container_of(vbuf, struct tw686x_v4l2_buf, vb);
131
132 /* Check device presence */
133 spin_lock_irqsave(&dev->lock, flags);
134 pci_dev = dev->pci_dev;
135 spin_unlock_irqrestore(&dev->lock, flags);
136 if (!pci_dev) {
137 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
138 return;
139 }
140
141 spin_lock_irqsave(&vc->qlock, flags);
142 list_add_tail(&buf->list, &vc->vidq_queued);
143 spin_unlock_irqrestore(&vc->qlock, flags);
144}
145
146/*
147 * We can call this even when alloc_dma failed for the given channel
148 */
149static void tw686x_free_dma(struct tw686x_video_channel *vc, unsigned int pb)
150{
151 struct tw686x_dma_desc *desc = &vc->dma_descs[pb];
152 struct tw686x_dev *dev = vc->dev;
153 struct pci_dev *pci_dev;
154 unsigned long flags;
155
156 /* Check device presence. Shouldn't really happen! */
157 spin_lock_irqsave(&dev->lock, flags);
158 pci_dev = dev->pci_dev;
159 spin_unlock_irqrestore(&dev->lock, flags);
160 if (!pci_dev) {
161 WARN(1, "trying to deallocate on missing device\n");
162 return;
163 }
164
165 if (desc->virt) {
166 pci_free_consistent(dev->pci_dev, desc->size,
167 desc->virt, desc->phys);
168 desc->virt = NULL;
169 }
170}
171
172static int tw686x_alloc_dma(struct tw686x_video_channel *vc, unsigned int pb)
173{
174 struct tw686x_dev *dev = vc->dev;
175 u32 reg = pb ? VDMA_B_ADDR[vc->ch] : VDMA_P_ADDR[vc->ch];
176 unsigned int len;
177 void *virt;
178
179 WARN(vc->dma_descs[pb].virt,
180 "Allocating buffer but previous still here\n");
181
182 len = (vc->width * vc->height * vc->format->depth) >> 3;
183 virt = pci_alloc_consistent(dev->pci_dev, len,
184 &vc->dma_descs[pb].phys);
185 if (!virt) {
186 v4l2_err(&dev->v4l2_dev,
187 "dma%d: unable to allocate %s-buffer\n",
188 vc->ch, pb ? "B" : "P");
189 return -ENOMEM;
190 }
191 vc->dma_descs[pb].size = len;
192 vc->dma_descs[pb].virt = virt;
193 reg_write(dev, reg, vc->dma_descs[pb].phys);
194
195 return 0;
196}
197
198static void tw686x_buffer_refill(struct tw686x_video_channel *vc,
199 unsigned int pb)
200{
201 struct tw686x_v4l2_buf *buf;
202
203 while (!list_empty(&vc->vidq_queued)) {
204
205 buf = list_first_entry(&vc->vidq_queued,
206 struct tw686x_v4l2_buf, list);
207 list_del(&buf->list);
208
209 vc->curr_bufs[pb] = buf;
210 return;
211 }
212 vc->curr_bufs[pb] = NULL;
213}
214
215static void tw686x_clear_queue(struct tw686x_video_channel *vc,
216 enum vb2_buffer_state state)
217{
218 unsigned int pb;
219
220 while (!list_empty(&vc->vidq_queued)) {
221 struct tw686x_v4l2_buf *buf;
222
223 buf = list_first_entry(&vc->vidq_queued,
224 struct tw686x_v4l2_buf, list);
225 list_del(&buf->list);
226 vb2_buffer_done(&buf->vb.vb2_buf, state);
227 }
228
229 for (pb = 0; pb < 2; pb++) {
230 if (vc->curr_bufs[pb])
231 vb2_buffer_done(&vc->curr_bufs[pb]->vb.vb2_buf, state);
232 vc->curr_bufs[pb] = NULL;
233 }
234}
235
236static int tw686x_start_streaming(struct vb2_queue *vq, unsigned int count)
237{
238 struct tw686x_video_channel *vc = vb2_get_drv_priv(vq);
239 struct tw686x_dev *dev = vc->dev;
240 struct pci_dev *pci_dev;
241 unsigned long flags;
242 int pb, err;
243
244 /* Check device presence */
245 spin_lock_irqsave(&dev->lock, flags);
246 pci_dev = dev->pci_dev;
247 spin_unlock_irqrestore(&dev->lock, flags);
248 if (!pci_dev) {
249 err = -ENODEV;
250 goto err_clear_queue;
251 }
252
253 spin_lock_irqsave(&vc->qlock, flags);
254
255 /* Sanity check */
256 if (!vc->dma_descs[0].virt || !vc->dma_descs[1].virt) {
257 spin_unlock_irqrestore(&vc->qlock, flags);
258 v4l2_err(&dev->v4l2_dev,
259 "video%d: refusing to start without DMA buffers\n",
260 vc->num);
261 err = -ENOMEM;
262 goto err_clear_queue;
263 }
264
265 for (pb = 0; pb < 2; pb++)
266 tw686x_buffer_refill(vc, pb);
267 spin_unlock_irqrestore(&vc->qlock, flags);
268
269 vc->sequence = 0;
270 vc->pb = 0;
271
272 spin_lock_irqsave(&dev->lock, flags);
273 tw686x_enable_channel(dev, vc->ch);
274 spin_unlock_irqrestore(&dev->lock, flags);
275
276 mod_timer(&dev->dma_delay_timer, jiffies + msecs_to_jiffies(100));
277
278 return 0;
279
280err_clear_queue:
281 spin_lock_irqsave(&vc->qlock, flags);
282 tw686x_clear_queue(vc, VB2_BUF_STATE_QUEUED);
283 spin_unlock_irqrestore(&vc->qlock, flags);
284 return err;
285}
286
287static void tw686x_stop_streaming(struct vb2_queue *vq)
288{
289 struct tw686x_video_channel *vc = vb2_get_drv_priv(vq);
290 struct tw686x_dev *dev = vc->dev;
291 struct pci_dev *pci_dev;
292 unsigned long flags;
293
294 /* Check device presence */
295 spin_lock_irqsave(&dev->lock, flags);
296 pci_dev = dev->pci_dev;
297 spin_unlock_irqrestore(&dev->lock, flags);
298 if (pci_dev)
299 tw686x_disable_channel(dev, vc->ch);
300
301 spin_lock_irqsave(&vc->qlock, flags);
302 tw686x_clear_queue(vc, VB2_BUF_STATE_ERROR);
303 spin_unlock_irqrestore(&vc->qlock, flags);
304}
305
306static int tw686x_buf_prepare(struct vb2_buffer *vb)
307{
308 struct tw686x_video_channel *vc = vb2_get_drv_priv(vb->vb2_queue);
309 unsigned int size =
310 (vc->width * vc->height * vc->format->depth) >> 3;
311
312 if (vb2_plane_size(vb, 0) < size)
313 return -EINVAL;
314 vb2_set_plane_payload(vb, 0, size);
315 return 0;
316}
317
318static struct vb2_ops tw686x_video_qops = {
319 .queue_setup = tw686x_queue_setup,
320 .buf_queue = tw686x_buf_queue,
321 .buf_prepare = tw686x_buf_prepare,
322 .start_streaming = tw686x_start_streaming,
323 .stop_streaming = tw686x_stop_streaming,
324 .wait_prepare = vb2_ops_wait_prepare,
325 .wait_finish = vb2_ops_wait_finish,
326};
327
328static int tw686x_s_ctrl(struct v4l2_ctrl *ctrl)
329{
330 struct tw686x_video_channel *vc;
331 struct tw686x_dev *dev;
332 unsigned int ch;
333
334 vc = container_of(ctrl->handler, struct tw686x_video_channel,
335 ctrl_handler);
336 dev = vc->dev;
337 ch = vc->ch;
338
339 switch (ctrl->id) {
340 case V4L2_CID_BRIGHTNESS:
341 reg_write(dev, BRIGHT[ch], ctrl->val & 0xff);
342 return 0;
343
344 case V4L2_CID_CONTRAST:
345 reg_write(dev, CONTRAST[ch], ctrl->val);
346 return 0;
347
348 case V4L2_CID_SATURATION:
349 reg_write(dev, SAT_U[ch], ctrl->val);
350 reg_write(dev, SAT_V[ch], ctrl->val);
351 return 0;
352
353 case V4L2_CID_HUE:
354 reg_write(dev, HUE[ch], ctrl->val & 0xff);
355 return 0;
356 }
357
358 return -EINVAL;
359}
360
361static const struct v4l2_ctrl_ops ctrl_ops = {
362 .s_ctrl = tw686x_s_ctrl,
363};
364
365static int tw686x_g_fmt_vid_cap(struct file *file, void *priv,
366 struct v4l2_format *f)
367{
368 struct tw686x_video_channel *vc = video_drvdata(file);
369
370 f->fmt.pix.width = vc->width;
371 f->fmt.pix.height = vc->height;
372 f->fmt.pix.field = V4L2_FIELD_INTERLACED;
373 f->fmt.pix.pixelformat = vc->format->fourcc;
374 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
375 f->fmt.pix.bytesperline = (f->fmt.pix.width * vc->format->depth) / 8;
376 f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline;
377 return 0;
378}
379
380static int tw686x_try_fmt_vid_cap(struct file *file, void *priv,
381 struct v4l2_format *f)
382{
383 struct tw686x_video_channel *vc = video_drvdata(file);
384 unsigned int video_height = TW686X_VIDEO_HEIGHT(vc->video_standard);
385 const struct tw686x_format *format;
386
387 format = format_by_fourcc(f->fmt.pix.pixelformat);
388 if (!format) {
389 format = &formats[0];
390 f->fmt.pix.pixelformat = format->fourcc;
391 }
392
393 if (f->fmt.pix.width <= TW686X_VIDEO_WIDTH / 2)
394 f->fmt.pix.width = TW686X_VIDEO_WIDTH / 2;
395 else
396 f->fmt.pix.width = TW686X_VIDEO_WIDTH;
397
398 if (f->fmt.pix.height <= video_height / 2)
399 f->fmt.pix.height = video_height / 2;
400 else
401 f->fmt.pix.height = video_height;
402
403 f->fmt.pix.bytesperline = (f->fmt.pix.width * format->depth) / 8;
404 f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline;
405 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
406 f->fmt.pix.field = V4L2_FIELD_INTERLACED;
407
408 return 0;
409}
410
411static int tw686x_s_fmt_vid_cap(struct file *file, void *priv,
412 struct v4l2_format *f)
413{
414 struct tw686x_video_channel *vc = video_drvdata(file);
415 u32 val, width, line_width, height;
416 unsigned long bitsperframe;
417 int err, pb;
418
419 if (vb2_is_busy(&vc->vidq))
420 return -EBUSY;
421
422 bitsperframe = vc->width * vc->height * vc->format->depth;
423 err = tw686x_try_fmt_vid_cap(file, priv, f);
424 if (err)
425 return err;
426
427 vc->format = format_by_fourcc(f->fmt.pix.pixelformat);
428 vc->width = f->fmt.pix.width;
429 vc->height = f->fmt.pix.height;
430
431 /* We need new DMA buffers if the framesize has changed */
432 if (bitsperframe != vc->width * vc->height * vc->format->depth) {
433 for (pb = 0; pb < 2; pb++)
434 tw686x_free_dma(vc, pb);
435
436 for (pb = 0; pb < 2; pb++) {
437 err = tw686x_alloc_dma(vc, pb);
438 if (err) {
439 if (pb > 0)
440 tw686x_free_dma(vc, 0);
441 return err;
442 }
443 }
444 }
445
446 val = reg_read(vc->dev, VDMA_CHANNEL_CONFIG[vc->ch]);
447
448 if (vc->width <= TW686X_VIDEO_WIDTH / 2)
449 val |= BIT(23);
450 else
451 val &= ~BIT(23);
452
453 if (vc->height <= TW686X_VIDEO_HEIGHT(vc->video_standard) / 2)
454 val |= BIT(24);
455 else
456 val &= ~BIT(24);
457
458 val &= ~(0x7 << 20);
459 val |= vc->format->mode << 20;
460 reg_write(vc->dev, VDMA_CHANNEL_CONFIG[vc->ch], val);
461
462 /* Program the DMA frame size */
463 width = (vc->width * 2) & 0x7ff;
464 height = vc->height / 2;
465 line_width = (vc->width * 2) & 0x7ff;
466 val = (height << 22) | (line_width << 11) | width;
467 reg_write(vc->dev, VDMA_WHP[vc->ch], val);
468 return 0;
469}
470
471static int tw686x_querycap(struct file *file, void *priv,
472 struct v4l2_capability *cap)
473{
474 struct tw686x_video_channel *vc = video_drvdata(file);
475 struct tw686x_dev *dev = vc->dev;
476
477 strlcpy(cap->driver, "tw686x", sizeof(cap->driver));
478 strlcpy(cap->card, dev->name, sizeof(cap->card));
479 snprintf(cap->bus_info, sizeof(cap->bus_info),
480 "PCI:%s", pci_name(dev->pci_dev));
481 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING |
482 V4L2_CAP_READWRITE;
483 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
484 return 0;
485}
486
487static int tw686x_s_std(struct file *file, void *priv, v4l2_std_id id)
488{
489 struct tw686x_video_channel *vc = video_drvdata(file);
490 struct v4l2_format f;
491 u32 val, ret;
492
493 if (vc->video_standard == id)
494 return 0;
495
496 if (vb2_is_busy(&vc->vidq))
497 return -EBUSY;
498
499 if (id & V4L2_STD_NTSC)
500 val = 0;
501 else if (id & V4L2_STD_PAL)
502 val = 1;
503 else if (id & V4L2_STD_SECAM)
504 val = 2;
505 else if (id & V4L2_STD_NTSC_443)
506 val = 3;
507 else if (id & V4L2_STD_PAL_M)
508 val = 4;
509 else if (id & V4L2_STD_PAL_Nc)
510 val = 5;
511 else if (id & V4L2_STD_PAL_60)
512 val = 6;
513 else
514 return -EINVAL;
515
516 vc->video_standard = id;
517 reg_write(vc->dev, SDT[vc->ch], val);
518
519 val = reg_read(vc->dev, VIDEO_CONTROL1);
520 if (id & V4L2_STD_625_50)
521 val |= (1 << (SYS_MODE_DMA_SHIFT + vc->ch));
522 else
523 val &= ~(1 << (SYS_MODE_DMA_SHIFT + vc->ch));
524 reg_write(vc->dev, VIDEO_CONTROL1, val);
525
526 /*
527 * Adjust format after V4L2_STD_525_60/V4L2_STD_625_50 change,
528 * calling g_fmt and s_fmt will sanitize the height
529 * according to the standard.
530 */
531 ret = tw686x_g_fmt_vid_cap(file, priv, &f);
532 if (!ret)
533 tw686x_s_fmt_vid_cap(file, priv, &f);
534 return 0;
535}
536
537static int tw686x_querystd(struct file *file, void *priv, v4l2_std_id *std)
538{
539 struct tw686x_video_channel *vc = video_drvdata(file);
540 struct tw686x_dev *dev = vc->dev;
541 unsigned int old_std, detected_std = 0;
542 unsigned long end;
543
544 if (vb2_is_streaming(&vc->vidq))
545 return -EBUSY;
546
547 /* Enable and start standard detection */
548 old_std = reg_read(dev, SDT[vc->ch]);
549 reg_write(dev, SDT[vc->ch], 0x7);
550 reg_write(dev, SDT_EN[vc->ch], 0xff);
551
552 end = jiffies + msecs_to_jiffies(500);
553 while (time_is_after_jiffies(end)) {
554
555 detected_std = reg_read(dev, SDT[vc->ch]);
556 if (!(detected_std & BIT(7)))
557 break;
558 msleep(100);
559 }
560 reg_write(dev, SDT[vc->ch], old_std);
561
562 /* Exit if still busy */
563 if (detected_std & BIT(7))
564 return 0;
565
566 detected_std = (detected_std >> 4) & 0x7;
567 switch (detected_std) {
568 case TW686X_STD_NTSC_M:
569 *std &= V4L2_STD_NTSC;
570 break;
571 case TW686X_STD_NTSC_443:
572 *std &= V4L2_STD_NTSC_443;
573 break;
574 case TW686X_STD_PAL_M:
575 *std &= V4L2_STD_PAL_M;
576 break;
577 case TW686X_STD_PAL_60:
578 *std &= V4L2_STD_PAL_60;
579 break;
580 case TW686X_STD_PAL:
581 *std &= V4L2_STD_PAL;
582 break;
583 case TW686X_STD_PAL_CN:
584 *std &= V4L2_STD_PAL_Nc;
585 break;
586 case TW686X_STD_SECAM:
587 *std &= V4L2_STD_SECAM;
588 break;
589 default:
590 *std = 0;
591 }
592 return 0;
593}
594
595static int tw686x_g_std(struct file *file, void *priv, v4l2_std_id *id)
596{
597 struct tw686x_video_channel *vc = video_drvdata(file);
598
599 *id = vc->video_standard;
600 return 0;
601}
602
603static int tw686x_enum_fmt_vid_cap(struct file *file, void *priv,
604 struct v4l2_fmtdesc *f)
605{
606 if (f->index >= ARRAY_SIZE(formats))
607 return -EINVAL;
608 f->pixelformat = formats[f->index].fourcc;
609 return 0;
610}
611
612static int tw686x_s_input(struct file *file, void *priv, unsigned int i)
613{
614 struct tw686x_video_channel *vc = video_drvdata(file);
615 u32 val;
616
617 if (i >= TW686X_INPUTS_PER_CH)
618 return -EINVAL;
619 if (i == vc->input)
620 return 0;
621 /*
622 * Not sure we are able to support on the fly input change
623 */
624 if (vb2_is_busy(&vc->vidq))
625 return -EBUSY;
626
627 vc->input = i;
628
629 val = reg_read(vc->dev, VDMA_CHANNEL_CONFIG[vc->ch]);
630 val &= ~(0x3 << 30);
631 val |= i << 30;
632 reg_write(vc->dev, VDMA_CHANNEL_CONFIG[vc->ch], val);
633 return 0;
634}
635
636static int tw686x_g_input(struct file *file, void *priv, unsigned int *i)
637{
638 struct tw686x_video_channel *vc = video_drvdata(file);
639
640 *i = vc->input;
641 return 0;
642}
643
644static int tw686x_enum_input(struct file *file, void *priv,
645 struct v4l2_input *i)
646{
647 struct tw686x_video_channel *vc = video_drvdata(file);
648 unsigned int vidstat;
649
650 if (i->index >= TW686X_INPUTS_PER_CH)
651 return -EINVAL;
652
653 snprintf(i->name, sizeof(i->name), "Composite%d", i->index);
654 i->type = V4L2_INPUT_TYPE_CAMERA;
655 i->std = vc->device->tvnorms;
656 i->capabilities = V4L2_IN_CAP_STD;
657
658 vidstat = reg_read(vc->dev, VIDSTAT[vc->ch]);
659 i->status = 0;
660 if (vidstat & TW686X_VIDSTAT_VDLOSS)
661 i->status |= V4L2_IN_ST_NO_SIGNAL;
662 if (!(vidstat & TW686X_VIDSTAT_HLOCK))
663 i->status |= V4L2_IN_ST_NO_H_LOCK;
664
665 return 0;
666}
667
668const struct v4l2_file_operations tw686x_video_fops = {
669 .owner = THIS_MODULE,
670 .open = v4l2_fh_open,
671 .unlocked_ioctl = video_ioctl2,
672 .release = vb2_fop_release,
673 .poll = vb2_fop_poll,
674 .read = vb2_fop_read,
675 .mmap = vb2_fop_mmap,
676};
677
678const struct v4l2_ioctl_ops tw686x_video_ioctl_ops = {
679 .vidioc_querycap = tw686x_querycap,
680 .vidioc_g_fmt_vid_cap = tw686x_g_fmt_vid_cap,
681 .vidioc_s_fmt_vid_cap = tw686x_s_fmt_vid_cap,
682 .vidioc_enum_fmt_vid_cap = tw686x_enum_fmt_vid_cap,
683 .vidioc_try_fmt_vid_cap = tw686x_try_fmt_vid_cap,
684
685 .vidioc_querystd = tw686x_querystd,
686 .vidioc_g_std = tw686x_g_std,
687 .vidioc_s_std = tw686x_s_std,
688
689 .vidioc_enum_input = tw686x_enum_input,
690 .vidioc_g_input = tw686x_g_input,
691 .vidioc_s_input = tw686x_s_input,
692
693 .vidioc_reqbufs = vb2_ioctl_reqbufs,
694 .vidioc_querybuf = vb2_ioctl_querybuf,
695 .vidioc_qbuf = vb2_ioctl_qbuf,
696 .vidioc_dqbuf = vb2_ioctl_dqbuf,
697 .vidioc_create_bufs = vb2_ioctl_create_bufs,
698 .vidioc_streamon = vb2_ioctl_streamon,
699 .vidioc_streamoff = vb2_ioctl_streamoff,
700 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
701
702 .vidioc_log_status = v4l2_ctrl_log_status,
703 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
704 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
705};
706
707static void tw686x_buffer_copy(struct tw686x_video_channel *vc,
708 unsigned int pb, struct vb2_v4l2_buffer *vb)
709{
710 struct tw686x_dma_desc *desc = &vc->dma_descs[pb];
711 struct vb2_buffer *vb2_buf = &vb->vb2_buf;
712
713 vb->field = V4L2_FIELD_INTERLACED;
714 vb->sequence = vc->sequence++;
715
716 memcpy(vb2_plane_vaddr(vb2_buf, 0), desc->virt, desc->size);
717 vb2_buf->timestamp = ktime_get_ns();
718 vb2_buffer_done(vb2_buf, VB2_BUF_STATE_DONE);
719}
720
721void tw686x_video_irq(struct tw686x_dev *dev, unsigned long requests,
722 unsigned int pb_status, unsigned int fifo_status,
723 unsigned int *reset_ch)
724{
725 struct tw686x_video_channel *vc;
726 struct vb2_v4l2_buffer *vb;
727 unsigned long flags;
728 unsigned int ch, pb;
729
730 for_each_set_bit(ch, &requests, max_channels(dev)) {
731 vc = &dev->video_channels[ch];
732
733 /*
734 * This can either be a blue frame (with signal-lost bit set)
735 * or a good frame (with signal-lost bit clear). If we have just
736 * got signal, then this channel needs resetting.
737 */
738 if (vc->no_signal && !(fifo_status & BIT(ch))) {
739 v4l2_printk(KERN_DEBUG, &dev->v4l2_dev,
740 "video%d: signal recovered\n", vc->num);
741 vc->no_signal = false;
742 *reset_ch |= BIT(ch);
743 vc->pb = 0;
744 continue;
745 }
746 vc->no_signal = !!(fifo_status & BIT(ch));
747
748 /* Check FIFO errors only if there's signal */
749 if (!vc->no_signal) {
750 u32 fifo_ov, fifo_bad;
751
752 fifo_ov = (fifo_status >> 24) & BIT(ch);
753 fifo_bad = (fifo_status >> 16) & BIT(ch);
754 if (fifo_ov || fifo_bad) {
755 /* Mark this channel for reset */
756 v4l2_printk(KERN_DEBUG, &dev->v4l2_dev,
757 "video%d: FIFO error\n", vc->num);
758 *reset_ch |= BIT(ch);
759 vc->pb = 0;
760 continue;
761 }
762 }
763
764 pb = !!(pb_status & BIT(ch));
765 if (vc->pb != pb) {
766 /* Mark this channel for reset */
767 v4l2_printk(KERN_DEBUG, &dev->v4l2_dev,
768 "video%d: unexpected p-b buffer!\n",
769 vc->num);
770 *reset_ch |= BIT(ch);
771 vc->pb = 0;
772 continue;
773 }
774
775 /* handle video stream */
776 spin_lock_irqsave(&vc->qlock, flags);
777 if (vc->curr_bufs[pb]) {
778 vb = &vc->curr_bufs[pb]->vb;
779 tw686x_buffer_copy(vc, pb, vb);
780 }
781 vc->pb = !pb;
782 tw686x_buffer_refill(vc, pb);
783 spin_unlock_irqrestore(&vc->qlock, flags);
784 }
785}
786
787void tw686x_video_free(struct tw686x_dev *dev)
788{
789 unsigned int ch, pb;
790
791 for (ch = 0; ch < max_channels(dev); ch++) {
792 struct tw686x_video_channel *vc = &dev->video_channels[ch];
793
794 if (vc->device)
795 video_unregister_device(vc->device);
796
797 for (pb = 0; pb < 2; pb++)
798 tw686x_free_dma(vc, pb);
799 }
800}
801
802int tw686x_video_init(struct tw686x_dev *dev)
803{
804 unsigned int ch, val, pb;
805 int err;
806
807 err = v4l2_device_register(&dev->pci_dev->dev, &dev->v4l2_dev);
808 if (err)
809 return err;
810
811 for (ch = 0; ch < max_channels(dev); ch++) {
812 struct tw686x_video_channel *vc = &dev->video_channels[ch];
813 struct video_device *vdev;
814
815 mutex_init(&vc->vb_mutex);
816 spin_lock_init(&vc->qlock);
817 INIT_LIST_HEAD(&vc->vidq_queued);
818
819 vc->dev = dev;
820 vc->ch = ch;
821
822 /* default settings */
823 vc->format = &formats[0];
824 vc->video_standard = V4L2_STD_NTSC;
825 vc->width = TW686X_VIDEO_WIDTH;
826 vc->height = TW686X_VIDEO_HEIGHT(vc->video_standard);
827 vc->input = 0;
828
829 reg_write(vc->dev, SDT[ch], 0);
830 tw686x_set_framerate(vc, 30);
831
832 reg_write(dev, VDELAY_LO[ch], 0x14);
833 reg_write(dev, HACTIVE_LO[ch], 0xd0);
834 reg_write(dev, VIDEO_SIZE[ch], 0);
835
836 for (pb = 0; pb < 2; pb++) {
837 err = tw686x_alloc_dma(vc, pb);
838 if (err)
839 goto error;
840 }
841
842 vc->vidq.io_modes = VB2_READ | VB2_MMAP | VB2_DMABUF;
843 vc->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
844 vc->vidq.drv_priv = vc;
845 vc->vidq.buf_struct_size = sizeof(struct tw686x_v4l2_buf);
846 vc->vidq.ops = &tw686x_video_qops;
847 vc->vidq.mem_ops = &vb2_vmalloc_memops;
848 vc->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
849 vc->vidq.min_buffers_needed = 2;
850 vc->vidq.lock = &vc->vb_mutex;
851
852 err = vb2_queue_init(&vc->vidq);
853 if (err) {
854 v4l2_err(&dev->v4l2_dev,
855 "dma%d: cannot init vb2 queue\n", ch);
856 goto error;
857 }
858
859 err = v4l2_ctrl_handler_init(&vc->ctrl_handler, 4);
860 if (err) {
861 v4l2_err(&dev->v4l2_dev,
862 "dma%d: cannot init ctrl handler\n", ch);
863 goto error;
864 }
865 v4l2_ctrl_new_std(&vc->ctrl_handler, &ctrl_ops,
866 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
867 v4l2_ctrl_new_std(&vc->ctrl_handler, &ctrl_ops,
868 V4L2_CID_CONTRAST, 0, 255, 1, 100);
869 v4l2_ctrl_new_std(&vc->ctrl_handler, &ctrl_ops,
870 V4L2_CID_SATURATION, 0, 255, 1, 128);
871 v4l2_ctrl_new_std(&vc->ctrl_handler, &ctrl_ops,
872 V4L2_CID_HUE, -128, 127, 1, 0);
873 err = vc->ctrl_handler.error;
874 if (err)
875 goto error;
876
877 err = v4l2_ctrl_handler_setup(&vc->ctrl_handler);
878 if (err)
879 goto error;
880
881 vdev = video_device_alloc();
882 if (!vdev) {
883 v4l2_err(&dev->v4l2_dev,
884 "dma%d: unable to allocate device\n", ch);
885 err = -ENOMEM;
886 goto error;
887 }
888
889 snprintf(vdev->name, sizeof(vdev->name), "%s video", dev->name);
890 vdev->fops = &tw686x_video_fops;
891 vdev->ioctl_ops = &tw686x_video_ioctl_ops;
892 vdev->release = video_device_release;
893 vdev->v4l2_dev = &dev->v4l2_dev;
894 vdev->queue = &vc->vidq;
895 vdev->tvnorms = V4L2_STD_525_60 | V4L2_STD_625_50;
896 vdev->minor = -1;
897 vdev->lock = &vc->vb_mutex;
898 vdev->ctrl_handler = &vc->ctrl_handler;
899 vc->device = vdev;
900 video_set_drvdata(vdev, vc);
901
902 err = video_register_device(vdev, VFL_TYPE_GRABBER, -1);
903 if (err < 0)
904 goto error;
905 vc->num = vdev->num;
906 }
907
908 /* Set DMA frame mode on all channels. Only supported mode for now. */
909 val = TW686X_DEF_PHASE_REF;
910 for (ch = 0; ch < max_channels(dev); ch++)
911 val |= TW686X_FRAME_MODE << (16 + ch * 2);
912 reg_write(dev, PHASE_REF, val);
913
914 reg_write(dev, MISC2[0], 0xe7);
915 reg_write(dev, VCTRL1[0], 0xcc);
916 reg_write(dev, LOOP[0], 0xa5);
917 if (max_channels(dev) > 4) {
918 reg_write(dev, VCTRL1[1], 0xcc);
919 reg_write(dev, LOOP[1], 0xa5);
920 reg_write(dev, MISC2[1], 0xe7);
921 }
922 return 0;
923
924error:
925 tw686x_video_free(dev);
926 return err;
927}
diff --git a/drivers/media/pci/tw686x/tw686x.h b/drivers/media/pci/tw686x/tw686x.h
new file mode 100644
index 000000000000..44b5755acf02
--- /dev/null
+++ b/drivers/media/pci/tw686x/tw686x.h
@@ -0,0 +1,158 @@
1/*
2 * Copyright (C) 2015 VanguardiaSur - www.vanguardiasur.com.ar
3 *
4 * Copyright (C) 2015 Industrial Research Institute for Automation
5 * and Measurements PIAP
6 * Written by Krzysztof Ha?asa
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License
10 * as published by the Free Software Foundation.
11 */
12
13#include <linux/mutex.h>
14#include <linux/pci.h>
15#include <linux/timer.h>
16#include <linux/videodev2.h>
17#include <media/v4l2-common.h>
18#include <media/v4l2-ctrls.h>
19#include <media/v4l2-device.h>
20#include <media/v4l2-ioctl.h>
21#include <media/videobuf2-v4l2.h>
22#include <sound/pcm.h>
23
24#include "tw686x-regs.h"
25
26#define TYPE_MAX_CHANNELS 0x0f
27#define TYPE_SECOND_GEN 0x10
28#define TW686X_DEF_PHASE_REF 0x1518
29
30#define TW686X_FIELD_MODE 0x3
31#define TW686X_FRAME_MODE 0x2
32/* 0x1 is reserved */
33#define TW686X_SG_MODE 0x0
34
35#define TW686X_AUDIO_PAGE_SZ 4096
36#define TW686X_AUDIO_PAGE_MAX 16
37#define TW686X_AUDIO_PERIODS_MIN 2
38#define TW686X_AUDIO_PERIODS_MAX TW686X_AUDIO_PAGE_MAX
39
40struct tw686x_format {
41 char *name;
42 unsigned int fourcc;
43 unsigned int depth;
44 unsigned int mode;
45};
46
47struct tw686x_dma_desc {
48 dma_addr_t phys;
49 void *virt;
50 unsigned int size;
51};
52
53struct tw686x_audio_buf {
54 dma_addr_t dma;
55 void *virt;
56 struct list_head list;
57};
58
59struct tw686x_v4l2_buf {
60 struct vb2_v4l2_buffer vb;
61 struct list_head list;
62};
63
64struct tw686x_audio_channel {
65 struct tw686x_dev *dev;
66 struct snd_pcm_substream *ss;
67 unsigned int ch;
68 struct tw686x_audio_buf *curr_bufs[2];
69 struct tw686x_dma_desc dma_descs[2];
70 dma_addr_t ptr;
71
72 struct tw686x_audio_buf buf[TW686X_AUDIO_PAGE_MAX];
73 struct list_head buf_list;
74 spinlock_t lock;
75};
76
77struct tw686x_video_channel {
78 struct tw686x_dev *dev;
79
80 struct vb2_queue vidq;
81 struct list_head vidq_queued;
82 struct video_device *device;
83 struct tw686x_v4l2_buf *curr_bufs[2];
84 struct tw686x_dma_desc dma_descs[2];
85
86 struct v4l2_ctrl_handler ctrl_handler;
87 const struct tw686x_format *format;
88 struct mutex vb_mutex;
89 spinlock_t qlock;
90 v4l2_std_id video_standard;
91 unsigned int width, height;
92 unsigned int h_halve, v_halve;
93 unsigned int ch;
94 unsigned int num;
95 unsigned int fps;
96 unsigned int input;
97 unsigned int sequence;
98 unsigned int pb;
99 bool no_signal;
100};
101
102/**
103 * struct tw686x_dev - global device status
104 * @lock: spinlock controlling access to the
105 * shared device registers (DMA enable/disable).
106 */
107struct tw686x_dev {
108 spinlock_t lock;
109
110 struct v4l2_device v4l2_dev;
111 struct snd_card *snd_card;
112
113 char name[32];
114 unsigned int type;
115 struct pci_dev *pci_dev;
116 __u32 __iomem *mmio;
117
118 void *alloc_ctx;
119
120 struct tw686x_video_channel *video_channels;
121 struct tw686x_audio_channel *audio_channels;
122
123 int audio_rate; /* per-device value */
124
125 struct timer_list dma_delay_timer;
126 u32 pending_dma_en; /* must be protected by lock */
127 u32 pending_dma_cmd; /* must be protected by lock */
128};
129
130static inline uint32_t reg_read(struct tw686x_dev *dev, unsigned int reg)
131{
132 return readl(dev->mmio + reg);
133}
134
135static inline void reg_write(struct tw686x_dev *dev, unsigned int reg,
136 uint32_t value)
137{
138 writel(value, dev->mmio + reg);
139}
140
141static inline unsigned int max_channels(struct tw686x_dev *dev)
142{
143 return dev->type & TYPE_MAX_CHANNELS; /* 4 or 8 channels */
144}
145
146void tw686x_enable_channel(struct tw686x_dev *dev, unsigned int channel);
147void tw686x_disable_channel(struct tw686x_dev *dev, unsigned int channel);
148
149int tw686x_video_init(struct tw686x_dev *dev);
150void tw686x_video_free(struct tw686x_dev *dev);
151void tw686x_video_irq(struct tw686x_dev *dev, unsigned long requests,
152 unsigned int pb_status, unsigned int fifo_status,
153 unsigned int *reset_ch);
154
155int tw686x_audio_init(struct tw686x_dev *dev);
156void tw686x_audio_free(struct tw686x_dev *dev);
157void tw686x_audio_irq(struct tw686x_dev *dev, unsigned long requests,
158 unsigned int pb_status);
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-11 17:03:17 -0400