diff options
author | Mikko Perttunen <mperttunen@nvidia.com> | 2015-03-12 10:47:55 -0400 |
---|---|---|
committer | Thierry Reding <treding@nvidia.com> | 2015-05-04 08:21:21 -0400 |
commit | 6ea2609ab386f6bfeebc39e1418b7497a9deb55c (patch) | |
tree | dbb31e0eb394cfa6079e1bfbadf571b5dc772f12 | |
parent | 405990c7e834913554482538321f16f457dda50e (diff) |
soc/tegra: fuse: Add RAM code reader helper
Needed for the EMC and MC drivers to know what timings from the DT to
use.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r-- | drivers/soc/tegra/fuse/tegra-apbmisc.c | 21 | ||||
-rw-r--r-- | include/soc/tegra/fuse.h | 1 |
2 files changed, 22 insertions, 0 deletions
diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fuse/tegra-apbmisc.c index 3bf5aba4caaa..73fad05d8f2c 100644 --- a/drivers/soc/tegra/fuse/tegra-apbmisc.c +++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c | |||
@@ -28,8 +28,15 @@ | |||
28 | #define APBMISC_SIZE 0x64 | 28 | #define APBMISC_SIZE 0x64 |
29 | #define FUSE_SKU_INFO 0x10 | 29 | #define FUSE_SKU_INFO 0x10 |
30 | 30 | ||
31 | #define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT 4 | ||
32 | #define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG \ | ||
33 | (0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT) | ||
34 | #define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT \ | ||
35 | (0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT) | ||
36 | |||
31 | static void __iomem *apbmisc_base; | 37 | static void __iomem *apbmisc_base; |
32 | static void __iomem *strapping_base; | 38 | static void __iomem *strapping_base; |
39 | static bool long_ram_code; | ||
33 | 40 | ||
34 | u32 tegra_read_chipid(void) | 41 | u32 tegra_read_chipid(void) |
35 | { | 42 | { |
@@ -54,6 +61,18 @@ u32 tegra_read_straps(void) | |||
54 | return 0; | 61 | return 0; |
55 | } | 62 | } |
56 | 63 | ||
64 | u32 tegra_read_ram_code(void) | ||
65 | { | ||
66 | u32 straps = tegra_read_straps(); | ||
67 | |||
68 | if (long_ram_code) | ||
69 | straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG; | ||
70 | else | ||
71 | straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT; | ||
72 | |||
73 | return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT; | ||
74 | } | ||
75 | |||
57 | static const struct of_device_id apbmisc_match[] __initconst = { | 76 | static const struct of_device_id apbmisc_match[] __initconst = { |
58 | { .compatible = "nvidia,tegra20-apbmisc", }, | 77 | { .compatible = "nvidia,tegra20-apbmisc", }, |
59 | {}, | 78 | {}, |
@@ -112,4 +131,6 @@ void __init tegra_init_apbmisc(void) | |||
112 | strapping_base = of_iomap(np, 1); | 131 | strapping_base = of_iomap(np, 1); |
113 | if (!strapping_base) | 132 | if (!strapping_base) |
114 | pr_err("ioremap tegra strapping_base failed\n"); | 133 | pr_err("ioremap tegra strapping_base failed\n"); |
134 | |||
135 | long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code"); | ||
115 | } | 136 | } |
diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h index b5f7b5f8d008..b019e3465f11 100644 --- a/include/soc/tegra/fuse.h +++ b/include/soc/tegra/fuse.h | |||
@@ -56,6 +56,7 @@ struct tegra_sku_info { | |||
56 | }; | 56 | }; |
57 | 57 | ||
58 | u32 tegra_read_straps(void); | 58 | u32 tegra_read_straps(void); |
59 | u32 tegra_read_ram_code(void); | ||
59 | u32 tegra_read_chipid(void); | 60 | u32 tegra_read_chipid(void); |
60 | int tegra_fuse_readl(unsigned long offset, u32 *value); | 61 | int tegra_fuse_readl(unsigned long offset, u32 *value); |
61 | 62 | ||