spi: sun4i: fix FIFO limit

When testing SPI without DMA I noticed that filling the FIFO on the
spi controller causes timeout.

Always leave room for one byte in the FIFO.

Signed-off-by: Michal Suchanek <hramrach@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org

1 files changed, 10 insertions, 3 deletions

diff --git a/drivers/spi/spi-sun4i.c b/drivers/spi/spi-sun4i.c
index 1ddd9e2309b6..e7e4aecb3295 100644
--- a/drivers/spi/spi-sun4i.c
+++ b/drivers/spi/spi-sun4i.c
@@ -179,7 +179,10 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
 
         /* We don't support transfer larger than the FIFO */
         if (tfr->len > SUN4I_FIFO_DEPTH)
-                return -EINVAL;
+                return -EMSGSIZE;
+
+        if (tfr->tx_buf && tfr->len >= SUN4I_FIFO_DEPTH)
+                return -EMSGSIZE;
 
         reinit_completion(&sspi->done);
         sspi->tx_buf = tfr->tx_buf;
@@ -269,8 +272,12 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
         sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len));
         sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len));
 
-        /* Fill the TX FIFO */
-        sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
+        /*
+         * Fill the TX FIFO
+         * Filling the FIFO fully causes timeout for some reason
+         * at least on spi2 on A10s
+         */
+        sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1);
 
         /* Enable the interrupts */
         sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, SUN4I_INT_CTL_TC);