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authorBen Skeggs <bskeggs@redhat.com>2015-08-20 00:54:17 -0400
committerBen Skeggs <bskeggs@redhat.com>2015-08-27 22:40:35 -0400
commit6cf813fb26640ef539051fb7f965af8c9ff10d92 (patch)
treecbb7d8fa7199ad86a1b4b26458c17cb54136736c
parent7974dd1bdb43aaf5b45a915c6b439d11733450fc (diff)
drm/nouveau/device: prepare for new-style subdevs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/core/device.h50
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/core/engine.c10
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/core/ioctl.c25
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/core/object.c48
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/core/subdev.c39
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c8
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h4
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/base.c2251
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c41
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c40
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c36
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c19
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c26
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c23
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c24
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c39
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c48
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h36
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/user.c4
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/falcon.c4
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c8
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c8
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c4
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c8
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c4
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c4
28 files changed, 2378 insertions, 437 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
index eb843e3ff005..3786982c1360 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
@@ -84,9 +84,9 @@ struct nvkm_device {
84 84
85 struct nvkm_event event; 85 struct nvkm_event event;
86 86
87 const char *cname;
88 u64 disable_mask; 87 u64 disable_mask;
89 88
89 const struct nvkm_device_chip *chip;
90 enum { 90 enum {
91 NV_04 = 0x04, 91 NV_04 = 0x04,
92 NV_10 = 0x10, 92 NV_10 = 0x10,
@@ -104,7 +104,6 @@ struct nvkm_device {
104 u32 crystal; 104 u32 crystal;
105 105
106 struct nvkm_oclass *oclass[NVDEV_SUBDEV_NR]; 106 struct nvkm_oclass *oclass[NVDEV_SUBDEV_NR];
107 struct nvkm_object *subdev[NVDEV_SUBDEV_NR];
108 107
109 struct { 108 struct {
110 struct notifier_block nb; 109 struct notifier_block nb;
@@ -153,6 +152,9 @@ struct nvkm_device {
153 struct nouveau_platform_gpu *gpu; 152 struct nouveau_platform_gpu *gpu;
154}; 153};
155 154
155struct nvkm_subdev *nvkm_device_subdev(struct nvkm_device *, int index);
156struct nvkm_engine *nvkm_device_engine(struct nvkm_device *, int index);
157
156struct nvkm_device_func { 158struct nvkm_device_func {
157 struct nvkm_device_pci *(*pci)(struct nvkm_device *); 159 struct nvkm_device_pci *(*pci)(struct nvkm_device *);
158 struct nvkm_device_tegra *(*tegra)(struct nvkm_device *); 160 struct nvkm_device_tegra *(*tegra)(struct nvkm_device *);
@@ -164,6 +166,50 @@ struct nvkm_device_func {
164struct nvkm_device_quirk { 166struct nvkm_device_quirk {
165}; 167};
166 168
169struct nvkm_device_chip {
170 const char *name;
171
172 int (*bar )(struct nvkm_device *, int idx, struct nvkm_bar **);
173 int (*bios )(struct nvkm_device *, int idx, struct nvkm_bios **);
174 int (*bus )(struct nvkm_device *, int idx, struct nvkm_bus **);
175 int (*clk )(struct nvkm_device *, int idx, struct nvkm_clk **);
176 int (*devinit)(struct nvkm_device *, int idx, struct nvkm_devinit **);
177 int (*fb )(struct nvkm_device *, int idx, struct nvkm_fb **);
178 int (*fuse )(struct nvkm_device *, int idx, struct nvkm_fuse **);
179 int (*gpio )(struct nvkm_device *, int idx, struct nvkm_gpio **);
180 int (*i2c )(struct nvkm_device *, int idx, struct nvkm_i2c **);
181 int (*ibus )(struct nvkm_device *, int idx, struct nvkm_subdev **);
182 int (*imem )(struct nvkm_device *, int idx, struct nvkm_instmem **);
183 int (*ltc )(struct nvkm_device *, int idx, struct nvkm_ltc **);
184 int (*mc )(struct nvkm_device *, int idx, struct nvkm_mc **);
185 int (*mmu )(struct nvkm_device *, int idx, struct nvkm_mmu **);
186 int (*mxm )(struct nvkm_device *, int idx, struct nvkm_subdev **);
187 int (*pmu )(struct nvkm_device *, int idx, struct nvkm_pmu **);
188 int (*therm )(struct nvkm_device *, int idx, struct nvkm_therm **);
189 int (*timer )(struct nvkm_device *, int idx, struct nvkm_timer **);
190 int (*volt )(struct nvkm_device *, int idx, struct nvkm_volt **);
191
192 int (*bsp )(struct nvkm_device *, int idx, struct nvkm_engine **);
193 int (*ce[3] )(struct nvkm_device *, int idx, struct nvkm_engine **);
194 int (*cipher )(struct nvkm_device *, int idx, struct nvkm_engine **);
195 int (*disp )(struct nvkm_device *, int idx, struct nvkm_disp **);
196 int (*dma )(struct nvkm_device *, int idx, struct nvkm_dmaeng **);
197 int (*fifo )(struct nvkm_device *, int idx, struct nvkm_fifo **);
198 int (*gr )(struct nvkm_device *, int idx, struct nvkm_gr **);
199 int (*ifb )(struct nvkm_device *, int idx, struct nvkm_engine **);
200 int (*me )(struct nvkm_device *, int idx, struct nvkm_engine **);
201 int (*mpeg )(struct nvkm_device *, int idx, struct nvkm_engine **);
202 int (*msenc )(struct nvkm_device *, int idx, struct nvkm_engine **);
203 int (*mspdec )(struct nvkm_device *, int idx, struct nvkm_engine **);
204 int (*msppp )(struct nvkm_device *, int idx, struct nvkm_engine **);
205 int (*msvld )(struct nvkm_device *, int idx, struct nvkm_engine **);
206 int (*pm )(struct nvkm_device *, int idx, struct nvkm_pm **);
207 int (*sec )(struct nvkm_device *, int idx, struct nvkm_engine **);
208 int (*sw )(struct nvkm_device *, int idx, struct nvkm_sw **);
209 int (*vic )(struct nvkm_device *, int idx, struct nvkm_engine **);
210 int (*vp )(struct nvkm_device *, int idx, struct nvkm_engine **);
211};
212
167struct nvkm_device *nvkm_device_find(u64 name); 213struct nvkm_device *nvkm_device_find(u64 name);
168int nvkm_device_list(u64 *name, int size); 214int nvkm_device_list(u64 *name, int size);
169 215
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/engine.c b/drivers/gpu/drm/nouveau/nvkm/core/engine.c
index 07559e7c4c4c..eabd271f68b3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/engine.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/engine.c
@@ -68,6 +68,8 @@ static int
68nvkm_engine_fini(struct nvkm_subdev *obj, bool suspend) 68nvkm_engine_fini(struct nvkm_subdev *obj, bool suspend)
69{ 69{
70 struct nvkm_engine *engine = container_of(obj, typeof(*engine), subdev); 70 struct nvkm_engine *engine = container_of(obj, typeof(*engine), subdev);
71 if (engine->subdev.object.oclass)
72 return engine->subdev.object.oclass->ofuncs->fini(&engine->subdev.object, suspend);
71 if (engine->func->fini) 73 if (engine->func->fini)
72 return engine->func->fini(engine, suspend); 74 return engine->func->fini(engine, suspend);
73 return 0; 75 return 0;
@@ -86,6 +88,9 @@ nvkm_engine_init(struct nvkm_subdev *obj)
86 return ret; 88 return ret;
87 } 89 }
88 90
91 if (engine->subdev.object.oclass)
92 return engine->subdev.object.oclass->ofuncs->init(&engine->subdev.object);
93
89 if (engine->func->oneinit && !engine->subdev.oneinit) { 94 if (engine->func->oneinit && !engine->subdev.oneinit) {
90 nvkm_trace(subdev, "one-time init running...\n"); 95 nvkm_trace(subdev, "one-time init running...\n");
91 time = ktime_to_us(ktime_get()); 96 time = ktime_to_us(ktime_get());
@@ -110,6 +115,10 @@ static void *
110nvkm_engine_dtor(struct nvkm_subdev *obj) 115nvkm_engine_dtor(struct nvkm_subdev *obj)
111{ 116{
112 struct nvkm_engine *engine = container_of(obj, typeof(*engine), subdev); 117 struct nvkm_engine *engine = container_of(obj, typeof(*engine), subdev);
118 if (engine->subdev.object.oclass) {
119 engine->subdev.object.oclass->ofuncs->dtor(&engine->subdev.object);
120 return NULL;
121 }
113 if (engine->func->dtor) 122 if (engine->func->dtor)
114 return engine->func->dtor(engine); 123 return engine->func->dtor(engine);
115 return engine; 124 return engine;
@@ -201,5 +210,6 @@ nvkm_engine_create_(struct nvkm_object *parent, struct nvkm_object *engobj,
201 210
202 INIT_LIST_HEAD(&engine->contexts); 211 INIT_LIST_HEAD(&engine->contexts);
203 spin_lock_init(&engine->lock); 212 spin_lock_init(&engine->lock);
213 engine->subdev.func = &nvkm_engine_func;
204 return 0; 214 return 0;
205} 215}
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c
index 6e5ff942a6da..d9c26e40ae32 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c
@@ -91,7 +91,7 @@ nvkm_ioctl_new(struct nvkm_handle *handle, void *data, u32 size)
91 struct nvkm_object *engctx = NULL; 91 struct nvkm_object *engctx = NULL;
92 struct nvkm_object *object = NULL; 92 struct nvkm_object *object = NULL;
93 struct nvkm_parent *parent; 93 struct nvkm_parent *parent;
94 struct nvkm_object *engine; 94 struct nvkm_engine *engine;
95 struct nvkm_oclass *oclass; 95 struct nvkm_oclass *oclass;
96 u32 _handle, _oclass; 96 u32 _handle, _oclass;
97 int ret; 97 int ret;
@@ -117,7 +117,8 @@ nvkm_ioctl_new(struct nvkm_handle *handle, void *data, u32 size)
117 parent = nv_parent(handle->object); 117 parent = nv_parent(handle->object);
118 118
119 /* check that parent supports the requested subclass */ 119 /* check that parent supports the requested subclass */
120 ret = nvkm_parent_sclass(&parent->object, _oclass, &engine, &oclass); 120 ret = nvkm_parent_sclass(&parent->object, _oclass,
121 (struct nvkm_object **)&engine, &oclass);
121 if (ret) { 122 if (ret) {
122 nvif_debug(&parent->object, "illegal class 0x%04x\n", _oclass); 123 nvif_debug(&parent->object, "illegal class 0x%04x\n", _oclass);
123 goto fail_class; 124 goto fail_class;
@@ -128,18 +129,20 @@ nvkm_ioctl_new(struct nvkm_handle *handle, void *data, u32 size)
128 * state calculated at init (ie. default context construction) 129 * state calculated at init (ie. default context construction)
129 */ 130 */
130 if (engine) { 131 if (engine) {
131 ret = nvkm_object_inc(engine); 132 engine = nvkm_engine_ref(engine);
132 if (ret) 133 if (IS_ERR(engine)) {
134 ret = PTR_ERR(engine);
135 engine = NULL;
133 goto fail_class; 136 goto fail_class;
137 }
134 } 138 }
135 139
136 /* if engine requires it, create a context object to insert 140 /* if engine requires it, create a context object to insert
137 * between the parent and its children (eg. PGRAPH context) 141 * between the parent and its children (eg. PGRAPH context)
138 */ 142 */
139 if (engine && nv_engine(engine)->cclass) { 143 if (engine && engine->cclass) {
140 ret = nvkm_object_old(&parent->object, engine, 144 ret = nvkm_object_old(&parent->object, &engine->subdev.object,
141 nv_engine(engine)->cclass, 145 engine->cclass, data, size, &engctx);
142 data, size, &engctx);
143 if (ret) 146 if (ret)
144 goto fail_engctx; 147 goto fail_engctx;
145 } else { 148 } else {
@@ -147,7 +150,8 @@ nvkm_ioctl_new(struct nvkm_handle *handle, void *data, u32 size)
147 } 150 }
148 151
149 /* finally, create new object and bind it to its handle */ 152 /* finally, create new object and bind it to its handle */
150 ret = nvkm_object_old(engctx, engine, oclass, data, size, &object); 153 ret = nvkm_object_old(engctx, &engine->subdev.object, oclass,
154 data, size, &object);
151 client->data = object; 155 client->data = object;
152 if (ret) 156 if (ret)
153 goto fail_ctor; 157 goto fail_ctor;
@@ -178,8 +182,7 @@ fail_init:
178fail_ctor: 182fail_ctor:
179 nvkm_object_ref(NULL, &engctx); 183 nvkm_object_ref(NULL, &engctx);
180fail_engctx: 184fail_engctx:
181 if (engine) 185 nvkm_engine_unref(&engine);
182 nvkm_object_dec(engine, false);
183fail_class: 186fail_class:
184 return ret; 187 return ret;
185} 188}
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/object.c b/drivers/gpu/drm/nouveau/nvkm/core/object.c
index 0abee7816874..0680eae072cf 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/object.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/object.c
@@ -201,6 +201,7 @@ nvkm_object_del(struct nvkm_object **pobject)
201 if (object && !WARN_ON(!object->func)) { 201 if (object && !WARN_ON(!object->func)) {
202 if (object->func->dtor) 202 if (object->func->dtor)
203 *pobject = object->func->dtor(object); 203 *pobject = object->func->dtor(object);
204 nvkm_engine_unref(&object->engine);
204 kfree(*pobject); 205 kfree(*pobject);
205 *pobject = NULL; 206 *pobject = NULL;
206 } 207 }
@@ -212,7 +213,7 @@ nvkm_object_ctor(const struct nvkm_object_func *func,
212{ 213{
213 object->func = func; 214 object->func = func;
214 object->client = oclass->client; 215 object->client = oclass->client;
215 object->engine = oclass->engine; 216 object->engine = nvkm_engine_ref(oclass->engine);
216 object->oclass_name = oclass->base.oclass; 217 object->oclass_name = oclass->base.oclass;
217 object->handle = oclass->handle; 218 object->handle = oclass->handle;
218 object->parent = oclass->parent; 219 object->parent = oclass->parent;
@@ -251,10 +252,11 @@ nvkm_object_new(const struct nvkm_oclass *oclass, void *data, u32 size,
251} 252}
252 253
253int 254int
254nvkm_object_create_(struct nvkm_object *parent, struct nvkm_object *engine, 255nvkm_object_create_(struct nvkm_object *parent, struct nvkm_object *engobj,
255 struct nvkm_oclass *oclass, u32 pclass, 256 struct nvkm_oclass *oclass, u32 pclass,
256 int size, void **pobject) 257 int size, void **pobject)
257{ 258{
259 struct nvkm_engine *engine = engobj ? nv_engine(engobj) : NULL;
258 struct nvkm_object *object; 260 struct nvkm_object *object;
259 261
260 object = *pobject = kzalloc(size, GFP_KERNEL); 262 object = *pobject = kzalloc(size, GFP_KERNEL);
@@ -262,7 +264,7 @@ nvkm_object_create_(struct nvkm_object *parent, struct nvkm_object *engine,
262 return -ENOMEM; 264 return -ENOMEM;
263 265
264 nvkm_object_ref(parent, &object->parent); 266 nvkm_object_ref(parent, &object->parent);
265 nvkm_object_ref(engine, (struct nvkm_object **)&object->engine); 267 object->engine = nvkm_engine_ref(engine);
266 object->oclass = oclass; 268 object->oclass = oclass;
267 object->pclass = pclass; 269 object->pclass = pclass;
268 atomic_set(&object->refcount, 1); 270 atomic_set(&object->refcount, 1);
@@ -287,7 +289,7 @@ _nvkm_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
287void 289void
288nvkm_object_destroy(struct nvkm_object *object) 290nvkm_object_destroy(struct nvkm_object *object)
289{ 291{
290 nvkm_object_ref(NULL, (struct nvkm_object **)&object->engine); 292 nvkm_engine_unref(&object->engine);
291 nvkm_object_ref(NULL, &object->parent); 293 nvkm_object_ref(NULL, &object->parent);
292 kfree(object); 294 kfree(object);
293} 295}
@@ -333,7 +335,8 @@ nvkm_object_old(struct nvkm_object *parent, struct nvkm_object *engine,
333 } 335 }
334 336
335 if (ret == 0) { 337 if (ret == 0) {
336 atomic_set(&object->refcount, 1); 338 if (!nv_iclass(object, NV_SUBDEV_CLASS))
339 atomic_set(&object->refcount, 1);
337 } 340 }
338 341
339 return 0; 342 return 0;
@@ -370,14 +373,6 @@ nvkm_object_inc(struct nvkm_object *object)
370 goto fail_parent; 373 goto fail_parent;
371 } 374 }
372 375
373 if (object->engine) {
374 mutex_lock(&nv_subdev(object->engine)->mutex);
375 ret = nvkm_object_inc(&object->engine->subdev.object);
376 mutex_unlock(&nv_subdev(object->engine)->mutex);
377 if (ret)
378 goto fail_engine;
379 }
380
381 ret = nvkm_object_init(object); 376 ret = nvkm_object_init(object);
382 atomic_set(&object->usecount, 1); 377 atomic_set(&object->usecount, 1);
383 if (ret) 378 if (ret)
@@ -386,12 +381,6 @@ nvkm_object_inc(struct nvkm_object *object)
386 return 0; 381 return 0;
387 382
388fail_self: 383fail_self:
389 if (object->engine) {
390 mutex_lock(&nv_subdev(object->engine)->mutex);
391 nvkm_object_dec(&object->engine->subdev.object, false);
392 mutex_unlock(&nv_subdev(object->engine)->mutex);
393 }
394fail_engine:
395 if (object->parent) 384 if (object->parent)
396 nvkm_object_dec(object->parent, false); 385 nvkm_object_dec(object->parent, false);
397fail_parent: 386fail_parent:
@@ -405,12 +394,6 @@ nvkm_object_decf(struct nvkm_object *object)
405 nvkm_object_fini(object, false); 394 nvkm_object_fini(object, false);
406 atomic_set(&object->usecount, 0); 395 atomic_set(&object->usecount, 0);
407 396
408 if (object->engine) {
409 mutex_lock(&nv_subdev(object->engine)->mutex);
410 nvkm_object_dec(&object->engine->subdev.object, false);
411 mutex_unlock(&nv_subdev(object->engine)->mutex);
412 }
413
414 if (object->parent) 397 if (object->parent)
415 nvkm_object_dec(object->parent, false); 398 nvkm_object_dec(object->parent, false);
416 399
@@ -427,14 +410,6 @@ nvkm_object_decs(struct nvkm_object *object)
427 if (ret) 410 if (ret)
428 return ret; 411 return ret;
429 412
430 if (object->engine) {
431 mutex_lock(&nv_subdev(object->engine)->mutex);
432 ret = nvkm_object_dec(&object->engine->subdev.object, true);
433 mutex_unlock(&nv_subdev(object->engine)->mutex);
434 if (ret)
435 goto fail_engine;
436 }
437
438 if (object->parent) { 413 if (object->parent) {
439 ret = nvkm_object_dec(object->parent, true); 414 ret = nvkm_object_dec(object->parent, true);
440 if (ret) 415 if (ret)
@@ -444,13 +419,6 @@ nvkm_object_decs(struct nvkm_object *object)
444 return 0; 419 return 0;
445 420
446fail_parent: 421fail_parent:
447 if (object->engine) {
448 mutex_lock(&nv_subdev(object->engine)->mutex);
449 nvkm_object_inc(&object->engine->subdev.object);
450 mutex_unlock(&nv_subdev(object->engine)->mutex);
451 }
452
453fail_engine:
454 nvkm_object_init(object); 422 nvkm_object_init(object);
455 423
456 return ret; 424 return ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/subdev.c b/drivers/gpu/drm/nouveau/nvkm/core/subdev.c
index 5af13d8be2f5..b0647c233478 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/subdev.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/subdev.c
@@ -74,6 +74,12 @@ nvkm_subdev_name[64] = {
74void 74void
75nvkm_subdev_intr(struct nvkm_subdev *subdev) 75nvkm_subdev_intr(struct nvkm_subdev *subdev)
76{ 76{
77 if (subdev->object.oclass) {
78 if (subdev->intr)
79 subdev->intr(subdev);
80 return;
81 }
82
77 if (subdev->func->intr) 83 if (subdev->func->intr)
78 subdev->func->intr(subdev); 84 subdev->func->intr(subdev);
79} 85}
@@ -85,10 +91,18 @@ nvkm_subdev_fini(struct nvkm_subdev *subdev, bool suspend)
85 const char *action = suspend ? "suspend" : "fini"; 91 const char *action = suspend ? "suspend" : "fini";
86 u32 pmc_enable = subdev->pmc_enable; 92 u32 pmc_enable = subdev->pmc_enable;
87 s64 time; 93 s64 time;
94 int ret;
88 95
89 nvkm_trace(subdev, "%s running...\n", action); 96 nvkm_trace(subdev, "%s running...\n", action);
90 time = ktime_to_us(ktime_get()); 97 time = ktime_to_us(ktime_get());
91 98
99 if (!subdev->func) {
100 ret = subdev->object.oclass->ofuncs->fini(&subdev->object, suspend);
101 if (ret)
102 return ret;
103 goto done;
104 }
105
92 if (subdev->func->fini) { 106 if (subdev->func->fini) {
93 int ret = subdev->func->fini(subdev, suspend); 107 int ret = subdev->func->fini(subdev, suspend);
94 if (ret) { 108 if (ret) {
@@ -104,6 +118,7 @@ nvkm_subdev_fini(struct nvkm_subdev *subdev, bool suspend)
104 nvkm_rd32(device, 0x000200); 118 nvkm_rd32(device, 0x000200);
105 } 119 }
106 120
121done:
107 time = ktime_to_us(ktime_get()) - time; 122 time = ktime_to_us(ktime_get()) - time;
108 nvkm_trace(subdev, "%s completed in %lldus\n", action, time); 123 nvkm_trace(subdev, "%s completed in %lldus\n", action, time);
109 return 0; 124 return 0;
@@ -117,7 +132,7 @@ nvkm_subdev_preinit(struct nvkm_subdev *subdev)
117 nvkm_trace(subdev, "preinit running...\n"); 132 nvkm_trace(subdev, "preinit running...\n");
118 time = ktime_to_us(ktime_get()); 133 time = ktime_to_us(ktime_get());
119 134
120 if (subdev->func->preinit) { 135 if (!subdev->object.oclass && subdev->func->preinit) {
121 int ret = subdev->func->preinit(subdev); 136 int ret = subdev->func->preinit(subdev);
122 if (ret) { 137 if (ret) {
123 nvkm_error(subdev, "preinit failed, %d\n", ret); 138 nvkm_error(subdev, "preinit failed, %d\n", ret);
@@ -139,6 +154,13 @@ nvkm_subdev_init(struct nvkm_subdev *subdev)
139 nvkm_trace(subdev, "init running...\n"); 154 nvkm_trace(subdev, "init running...\n");
140 time = ktime_to_us(ktime_get()); 155 time = ktime_to_us(ktime_get());
141 156
157 if (!subdev->func) {
158 ret = subdev->object.oclass->ofuncs->init(&subdev->object);
159 if (ret)
160 return ret;
161 goto done;
162 }
163
142 if (subdev->func->oneinit && !subdev->oneinit) { 164 if (subdev->func->oneinit && !subdev->oneinit) {
143 s64 time; 165 s64 time;
144 nvkm_trace(subdev, "one-time init running...\n"); 166 nvkm_trace(subdev, "one-time init running...\n");
@@ -162,6 +184,7 @@ nvkm_subdev_init(struct nvkm_subdev *subdev)
162 } 184 }
163 } 185 }
164 186
187done:
165 time = ktime_to_us(ktime_get()) - time; 188 time = ktime_to_us(ktime_get()) - time;
166 nvkm_trace(subdev, "init completed in %lldus\n", time); 189 nvkm_trace(subdev, "init completed in %lldus\n", time);
167 return 0; 190 return 0;
@@ -172,6 +195,12 @@ nvkm_subdev_del(struct nvkm_subdev **psubdev)
172{ 195{
173 struct nvkm_subdev *subdev = *psubdev; 196 struct nvkm_subdev *subdev = *psubdev;
174 s64 time; 197 s64 time;
198
199 if (subdev && subdev->object.oclass) {
200 subdev->object.oclass->ofuncs->dtor(&subdev->object);
201 return;
202 }
203
175 if (subdev && !WARN_ON(!subdev->func)) { 204 if (subdev && !WARN_ON(!subdev->func)) {
176 nvkm_trace(subdev, "destroy running...\n"); 205 nvkm_trace(subdev, "destroy running...\n");
177 time = ktime_to_us(ktime_get()); 206 time = ktime_to_us(ktime_get());
@@ -211,8 +240,10 @@ nvkm_subdev(void *obj, int idx)
211 struct nvkm_object *object = nv_object(obj); 240 struct nvkm_object *object = nv_object(obj);
212 while (object && !nv_iclass(object, NV_SUBDEV_CLASS)) 241 while (object && !nv_iclass(object, NV_SUBDEV_CLASS))
213 object = object->parent; 242 object = object->parent;
214 if (object == NULL || !object->parent || nv_subidx(nv_subdev(object)) != idx) 243 if (object == NULL || !object->parent || nv_subidx(nv_subdev(object)) != idx) {
215 object = nv_device(obj)->subdev[idx]; 244 struct nvkm_device *device = nv_device(obj);
245 return nvkm_device_subdev(device, idx);
246 }
216 return object ? nv_subdev(object) : NULL; 247 return object ? nv_subdev(object) : NULL;
217} 248}
218 249
@@ -266,8 +297,6 @@ _nvkm_subdev_fini(struct nvkm_object *object, bool suspend)
266void 297void
267nvkm_subdev_destroy(struct nvkm_subdev *subdev) 298nvkm_subdev_destroy(struct nvkm_subdev *subdev)
268{ 299{
269 int subidx = nv_hclass(subdev) & 0xff;
270 nv_device(subdev)->subdev[subidx] = NULL;
271 nvkm_object_destroy(&subdev->object); 300 nvkm_object_destroy(&subdev->object);
272} 301}
273 302
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c
index f42706e1d5db..fdca90bc8f0e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c
@@ -40,21 +40,19 @@ nvkm_acpi_ntfy(struct notifier_block *nb, unsigned long val, void *data)
40} 40}
41#endif 41#endif
42 42
43int 43void
44nvkm_acpi_fini(struct nvkm_device *device, bool suspend) 44nvkm_acpi_fini(struct nvkm_device *device)
45{ 45{
46#ifdef CONFIG_ACPI 46#ifdef CONFIG_ACPI
47 unregister_acpi_notifier(&device->acpi.nb); 47 unregister_acpi_notifier(&device->acpi.nb);
48#endif 48#endif
49 return 0;
50} 49}
51 50
52int 51void
53nvkm_acpi_init(struct nvkm_device *device) 52nvkm_acpi_init(struct nvkm_device *device)
54{ 53{
55#ifdef CONFIG_ACPI 54#ifdef CONFIG_ACPI
56 device->acpi.nb.notifier_call = nvkm_acpi_ntfy; 55 device->acpi.nb.notifier_call = nvkm_acpi_ntfy;
57 register_acpi_notifier(&device->acpi.nb); 56 register_acpi_notifier(&device->acpi.nb);
58#endif 57#endif
59 return 0;
60} 58}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h b/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h
index 82dd359ddfa4..1bbe76e0740a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h
@@ -3,6 +3,6 @@
3#include <core/os.h> 3#include <core/os.h>
4struct nvkm_device; 4struct nvkm_device;
5 5
6int nvkm_acpi_init(struct nvkm_device *); 6void nvkm_acpi_init(struct nvkm_device *);
7int nvkm_acpi_fini(struct nvkm_device *, bool); 7void nvkm_acpi_fini(struct nvkm_device *);
8#endif 8#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index c7d8e2902c6c..b3f333602582 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -67,6 +67,1916 @@ nvkm_device_list(u64 *name, int size)
67 return nr; 67 return nr;
68} 68}
69 69
70static const struct nvkm_device_chip
71null_chipset = {
72 .name = "NULL",
73// .bios = nvkm_bios_new,
74};
75
76static const struct nvkm_device_chip
77nv4_chipset = {
78 .name = "NV04",
79// .bios = nvkm_bios_new,
80// .bus = nv04_bus_new,
81// .clk = nv04_clk_new,
82// .devinit = nv04_devinit_new,
83// .fb = nv04_fb_new,
84// .i2c = nv04_i2c_new,
85// .imem = nv04_instmem_new,
86// .mc = nv04_mc_new,
87// .mmu = nv04_mmu_new,
88// .timer = nv04_timer_new,
89// .disp = nv04_disp_new,
90// .dma = nv04_dma_new,
91// .fifo = nv04_fifo_new,
92// .gr = nv04_gr_new,
93// .sw = nv04_sw_new,
94};
95
96static const struct nvkm_device_chip
97nv5_chipset = {
98 .name = "NV05",
99// .bios = nvkm_bios_new,
100// .bus = nv04_bus_new,
101// .clk = nv04_clk_new,
102// .devinit = nv05_devinit_new,
103// .fb = nv04_fb_new,
104// .i2c = nv04_i2c_new,
105// .imem = nv04_instmem_new,
106// .mc = nv04_mc_new,
107// .mmu = nv04_mmu_new,
108// .timer = nv04_timer_new,
109// .disp = nv04_disp_new,
110// .dma = nv04_dma_new,
111// .fifo = nv04_fifo_new,
112// .gr = nv04_gr_new,
113// .sw = nv04_sw_new,
114};
115
116static const struct nvkm_device_chip
117nv10_chipset = {
118 .name = "NV10",
119// .bios = nvkm_bios_new,
120// .bus = nv04_bus_new,
121// .clk = nv04_clk_new,
122// .devinit = nv10_devinit_new,
123// .fb = nv10_fb_new,
124// .gpio = nv10_gpio_new,
125// .i2c = nv04_i2c_new,
126// .imem = nv04_instmem_new,
127// .mc = nv04_mc_new,
128// .mmu = nv04_mmu_new,
129// .timer = nv04_timer_new,
130// .disp = nv04_disp_new,
131// .dma = nv04_dma_new,
132// .gr = nv10_gr_new,
133};
134
135static const struct nvkm_device_chip
136nv11_chipset = {
137 .name = "NV11",
138// .bios = nvkm_bios_new,
139// .bus = nv04_bus_new,
140// .clk = nv04_clk_new,
141// .devinit = nv10_devinit_new,
142// .fb = nv10_fb_new,
143// .gpio = nv10_gpio_new,
144// .i2c = nv04_i2c_new,
145// .imem = nv04_instmem_new,
146// .mc = nv04_mc_new,
147// .mmu = nv04_mmu_new,
148// .timer = nv04_timer_new,
149// .disp = nv04_disp_new,
150// .dma = nv04_dma_new,
151// .fifo = nv10_fifo_new,
152// .gr = nv10_gr_new,
153// .sw = nv10_sw_new,
154};
155
156static const struct nvkm_device_chip
157nv15_chipset = {
158 .name = "NV15",
159// .bios = nvkm_bios_new,
160// .bus = nv04_bus_new,
161// .clk = nv04_clk_new,
162// .devinit = nv10_devinit_new,
163// .fb = nv10_fb_new,
164// .gpio = nv10_gpio_new,
165// .i2c = nv04_i2c_new,
166// .imem = nv04_instmem_new,
167// .mc = nv04_mc_new,
168// .mmu = nv04_mmu_new,
169// .timer = nv04_timer_new,
170// .disp = nv04_disp_new,
171// .dma = nv04_dma_new,
172// .fifo = nv10_fifo_new,
173// .gr = nv10_gr_new,
174// .sw = nv10_sw_new,
175};
176
177static const struct nvkm_device_chip
178nv17_chipset = {
179 .name = "NV17",
180// .bios = nvkm_bios_new,
181// .bus = nv04_bus_new,
182// .clk = nv04_clk_new,
183// .devinit = nv10_devinit_new,
184// .fb = nv10_fb_new,
185// .gpio = nv10_gpio_new,
186// .i2c = nv04_i2c_new,
187// .imem = nv04_instmem_new,
188// .mc = nv04_mc_new,
189// .mmu = nv04_mmu_new,
190// .timer = nv04_timer_new,
191// .disp = nv04_disp_new,
192// .dma = nv04_dma_new,
193// .fifo = nv17_fifo_new,
194// .gr = nv10_gr_new,
195// .sw = nv10_sw_new,
196};
197
198static const struct nvkm_device_chip
199nv18_chipset = {
200 .name = "NV18",
201// .bios = nvkm_bios_new,
202// .bus = nv04_bus_new,
203// .clk = nv04_clk_new,
204// .devinit = nv10_devinit_new,
205// .fb = nv10_fb_new,
206// .gpio = nv10_gpio_new,
207// .i2c = nv04_i2c_new,
208// .imem = nv04_instmem_new,
209// .mc = nv04_mc_new,
210// .mmu = nv04_mmu_new,
211// .timer = nv04_timer_new,
212// .disp = nv04_disp_new,
213// .dma = nv04_dma_new,
214// .fifo = nv17_fifo_new,
215// .gr = nv10_gr_new,
216// .sw = nv10_sw_new,
217};
218
219static const struct nvkm_device_chip
220nv1a_chipset = {
221 .name = "nForce",
222// .bios = nvkm_bios_new,
223// .bus = nv04_bus_new,
224// .clk = nv04_clk_new,
225// .devinit = nv1a_devinit_new,
226// .fb = nv1a_fb_new,
227// .gpio = nv10_gpio_new,
228// .i2c = nv04_i2c_new,
229// .imem = nv04_instmem_new,
230// .mc = nv04_mc_new,
231// .mmu = nv04_mmu_new,
232// .timer = nv04_timer_new,
233// .disp = nv04_disp_new,
234// .dma = nv04_dma_new,
235// .fifo = nv10_fifo_new,
236// .gr = nv10_gr_new,
237// .sw = nv10_sw_new,
238};
239
240static const struct nvkm_device_chip
241nv1f_chipset = {
242 .name = "nForce2",
243// .bios = nvkm_bios_new,
244// .bus = nv04_bus_new,
245// .clk = nv04_clk_new,
246// .devinit = nv1a_devinit_new,
247// .fb = nv1a_fb_new,
248// .gpio = nv10_gpio_new,
249// .i2c = nv04_i2c_new,
250// .imem = nv04_instmem_new,
251// .mc = nv04_mc_new,
252// .mmu = nv04_mmu_new,
253// .timer = nv04_timer_new,
254// .disp = nv04_disp_new,
255// .dma = nv04_dma_new,
256// .fifo = nv17_fifo_new,
257// .gr = nv10_gr_new,
258// .sw = nv10_sw_new,
259};
260
261static const struct nvkm_device_chip
262nv20_chipset = {
263 .name = "NV20",
264// .bios = nvkm_bios_new,
265// .bus = nv04_bus_new,
266// .clk = nv04_clk_new,
267// .devinit = nv20_devinit_new,
268// .fb = nv20_fb_new,
269// .gpio = nv10_gpio_new,
270// .i2c = nv04_i2c_new,
271// .imem = nv04_instmem_new,
272// .mc = nv04_mc_new,
273// .mmu = nv04_mmu_new,
274// .timer = nv04_timer_new,
275// .disp = nv04_disp_new,
276// .dma = nv04_dma_new,
277// .fifo = nv17_fifo_new,
278// .gr = nv20_gr_new,
279// .sw = nv10_sw_new,
280};
281
282static const struct nvkm_device_chip
283nv25_chipset = {
284 .name = "NV25",
285// .bios = nvkm_bios_new,
286// .bus = nv04_bus_new,
287// .clk = nv04_clk_new,
288// .devinit = nv20_devinit_new,
289// .fb = nv25_fb_new,
290// .gpio = nv10_gpio_new,
291// .i2c = nv04_i2c_new,
292// .imem = nv04_instmem_new,
293// .mc = nv04_mc_new,
294// .mmu = nv04_mmu_new,
295// .timer = nv04_timer_new,
296// .disp = nv04_disp_new,
297// .dma = nv04_dma_new,
298// .fifo = nv17_fifo_new,
299// .gr = nv25_gr_new,
300// .sw = nv10_sw_new,
301};
302
303static const struct nvkm_device_chip
304nv28_chipset = {
305 .name = "NV28",
306// .bios = nvkm_bios_new,
307// .bus = nv04_bus_new,
308// .clk = nv04_clk_new,
309// .devinit = nv20_devinit_new,
310// .fb = nv25_fb_new,
311// .gpio = nv10_gpio_new,
312// .i2c = nv04_i2c_new,
313// .imem = nv04_instmem_new,
314// .mc = nv04_mc_new,
315// .mmu = nv04_mmu_new,
316// .timer = nv04_timer_new,
317// .disp = nv04_disp_new,
318// .dma = nv04_dma_new,
319// .fifo = nv17_fifo_new,
320// .gr = nv25_gr_new,
321// .sw = nv10_sw_new,
322};
323
324static const struct nvkm_device_chip
325nv2a_chipset = {
326 .name = "NV2A",
327// .bios = nvkm_bios_new,
328// .bus = nv04_bus_new,
329// .clk = nv04_clk_new,
330// .devinit = nv20_devinit_new,
331// .fb = nv25_fb_new,
332// .gpio = nv10_gpio_new,
333// .i2c = nv04_i2c_new,
334// .imem = nv04_instmem_new,
335// .mc = nv04_mc_new,
336// .mmu = nv04_mmu_new,
337// .timer = nv04_timer_new,
338// .disp = nv04_disp_new,
339// .dma = nv04_dma_new,
340// .fifo = nv17_fifo_new,
341// .gr = nv2a_gr_new,
342// .sw = nv10_sw_new,
343};
344
345static const struct nvkm_device_chip
346nv30_chipset = {
347 .name = "NV30",
348// .bios = nvkm_bios_new,
349// .bus = nv04_bus_new,
350// .clk = nv04_clk_new,
351// .devinit = nv20_devinit_new,
352// .fb = nv30_fb_new,
353// .gpio = nv10_gpio_new,
354// .i2c = nv04_i2c_new,
355// .imem = nv04_instmem_new,
356// .mc = nv04_mc_new,
357// .mmu = nv04_mmu_new,
358// .timer = nv04_timer_new,
359// .disp = nv04_disp_new,
360// .dma = nv04_dma_new,
361// .fifo = nv17_fifo_new,
362// .gr = nv30_gr_new,
363// .sw = nv10_sw_new,
364};
365
366static const struct nvkm_device_chip
367nv31_chipset = {
368 .name = "NV31",
369// .bios = nvkm_bios_new,
370// .bus = nv31_bus_new,
371// .clk = nv04_clk_new,
372// .devinit = nv20_devinit_new,
373// .fb = nv30_fb_new,
374// .gpio = nv10_gpio_new,
375// .i2c = nv04_i2c_new,
376// .imem = nv04_instmem_new,
377// .mc = nv04_mc_new,
378// .mmu = nv04_mmu_new,
379// .timer = nv04_timer_new,
380// .disp = nv04_disp_new,
381// .dma = nv04_dma_new,
382// .fifo = nv17_fifo_new,
383// .gr = nv30_gr_new,
384// .mpeg = nv31_mpeg_new,
385// .sw = nv10_sw_new,
386};
387
388static const struct nvkm_device_chip
389nv34_chipset = {
390 .name = "NV34",
391// .bios = nvkm_bios_new,
392// .bus = nv31_bus_new,
393// .clk = nv04_clk_new,
394// .devinit = nv10_devinit_new,
395// .fb = nv10_fb_new,
396// .gpio = nv10_gpio_new,
397// .i2c = nv04_i2c_new,
398// .imem = nv04_instmem_new,
399// .mc = nv04_mc_new,
400// .mmu = nv04_mmu_new,
401// .timer = nv04_timer_new,
402// .disp = nv04_disp_new,
403// .dma = nv04_dma_new,
404// .fifo = nv17_fifo_new,
405// .gr = nv34_gr_new,
406// .mpeg = nv31_mpeg_new,
407// .sw = nv10_sw_new,
408};
409
410static const struct nvkm_device_chip
411nv35_chipset = {
412 .name = "NV35",
413// .bios = nvkm_bios_new,
414// .bus = nv04_bus_new,
415// .clk = nv04_clk_new,
416// .devinit = nv20_devinit_new,
417// .fb = nv35_fb_new,
418// .gpio = nv10_gpio_new,
419// .i2c = nv04_i2c_new,
420// .imem = nv04_instmem_new,
421// .mc = nv04_mc_new,
422// .mmu = nv04_mmu_new,
423// .timer = nv04_timer_new,
424// .disp = nv04_disp_new,
425// .dma = nv04_dma_new,
426// .fifo = nv17_fifo_new,
427// .gr = nv35_gr_new,
428// .sw = nv10_sw_new,
429};
430
431static const struct nvkm_device_chip
432nv36_chipset = {
433 .name = "NV36",
434// .bios = nvkm_bios_new,
435// .bus = nv31_bus_new,
436// .clk = nv04_clk_new,
437// .devinit = nv20_devinit_new,
438// .fb = nv36_fb_new,
439// .gpio = nv10_gpio_new,
440// .i2c = nv04_i2c_new,
441// .imem = nv04_instmem_new,
442// .mc = nv04_mc_new,
443// .mmu = nv04_mmu_new,
444// .timer = nv04_timer_new,
445// .disp = nv04_disp_new,
446// .dma = nv04_dma_new,
447// .fifo = nv17_fifo_new,
448// .gr = nv35_gr_new,
449// .mpeg = nv31_mpeg_new,
450// .sw = nv10_sw_new,
451};
452
453static const struct nvkm_device_chip
454nv40_chipset = {
455 .name = "NV40",
456// .bios = nvkm_bios_new,
457// .bus = nv31_bus_new,
458// .clk = nv40_clk_new,
459// .devinit = nv1a_devinit_new,
460// .fb = nv40_fb_new,
461// .gpio = nv10_gpio_new,
462// .i2c = nv04_i2c_new,
463// .imem = nv40_instmem_new,
464// .mc = nv40_mc_new,
465// .mmu = nv04_mmu_new,
466// .therm = nv40_therm_new,
467// .timer = nv04_timer_new,
468// .volt = nv40_volt_new,
469// .disp = nv04_disp_new,
470// .dma = nv04_dma_new,
471// .fifo = nv40_fifo_new,
472// .gr = nv40_gr_new,
473// .mpeg = nv40_mpeg_new,
474// .pm = nv40_pm_new,
475// .sw = nv10_sw_new,
476};
477
478static const struct nvkm_device_chip
479nv41_chipset = {
480 .name = "NV41",
481// .bios = nvkm_bios_new,
482// .bus = nv31_bus_new,
483// .clk = nv40_clk_new,
484// .devinit = nv1a_devinit_new,
485// .fb = nv41_fb_new,
486// .gpio = nv10_gpio_new,
487// .i2c = nv04_i2c_new,
488// .imem = nv40_instmem_new,
489// .mc = nv40_mc_new,
490// .mmu = nv41_mmu_new,
491// .therm = nv40_therm_new,
492// .timer = nv04_timer_new,
493// .volt = nv40_volt_new,
494// .disp = nv04_disp_new,
495// .dma = nv04_dma_new,
496// .fifo = nv40_fifo_new,
497// .gr = nv40_gr_new,
498// .mpeg = nv40_mpeg_new,
499// .pm = nv40_pm_new,
500// .sw = nv10_sw_new,
501};
502
503static const struct nvkm_device_chip
504nv42_chipset = {
505 .name = "NV42",
506// .bios = nvkm_bios_new,
507// .bus = nv31_bus_new,
508// .clk = nv40_clk_new,
509// .devinit = nv1a_devinit_new,
510// .fb = nv41_fb_new,
511// .gpio = nv10_gpio_new,
512// .i2c = nv04_i2c_new,
513// .imem = nv40_instmem_new,
514// .mc = nv40_mc_new,
515// .mmu = nv41_mmu_new,
516// .therm = nv40_therm_new,
517// .timer = nv04_timer_new,
518// .volt = nv40_volt_new,
519// .disp = nv04_disp_new,
520// .dma = nv04_dma_new,
521// .fifo = nv40_fifo_new,
522// .gr = nv40_gr_new,
523// .mpeg = nv40_mpeg_new,
524// .pm = nv40_pm_new,
525// .sw = nv10_sw_new,
526};
527
528static const struct nvkm_device_chip
529nv43_chipset = {
530 .name = "NV43",
531// .bios = nvkm_bios_new,
532// .bus = nv31_bus_new,
533// .clk = nv40_clk_new,
534// .devinit = nv1a_devinit_new,
535// .fb = nv41_fb_new,
536// .gpio = nv10_gpio_new,
537// .i2c = nv04_i2c_new,
538// .imem = nv40_instmem_new,
539// .mc = nv40_mc_new,
540// .mmu = nv41_mmu_new,
541// .therm = nv40_therm_new,
542// .timer = nv04_timer_new,
543// .volt = nv40_volt_new,
544// .disp = nv04_disp_new,
545// .dma = nv04_dma_new,
546// .fifo = nv40_fifo_new,
547// .gr = nv40_gr_new,
548// .mpeg = nv40_mpeg_new,
549// .pm = nv40_pm_new,
550// .sw = nv10_sw_new,
551};
552
553static const struct nvkm_device_chip
554nv44_chipset = {
555 .name = "NV44",
556// .bios = nvkm_bios_new,
557// .bus = nv31_bus_new,
558// .clk = nv40_clk_new,
559// .devinit = nv1a_devinit_new,
560// .fb = nv44_fb_new,
561// .gpio = nv10_gpio_new,
562// .i2c = nv04_i2c_new,
563// .imem = nv40_instmem_new,
564// .mc = nv44_mc_new,
565// .mmu = nv44_mmu_new,
566// .therm = nv40_therm_new,
567// .timer = nv04_timer_new,
568// .volt = nv40_volt_new,
569// .disp = nv04_disp_new,
570// .dma = nv04_dma_new,
571// .fifo = nv40_fifo_new,
572// .gr = nv40_gr_new,
573// .mpeg = nv44_mpeg_new,
574// .pm = nv40_pm_new,
575// .sw = nv10_sw_new,
576};
577
578static const struct nvkm_device_chip
579nv45_chipset = {
580 .name = "NV45",
581// .bios = nvkm_bios_new,
582// .bus = nv31_bus_new,
583// .clk = nv40_clk_new,
584// .devinit = nv1a_devinit_new,
585// .fb = nv40_fb_new,
586// .gpio = nv10_gpio_new,
587// .i2c = nv04_i2c_new,
588// .imem = nv40_instmem_new,
589// .mc = nv40_mc_new,
590// .mmu = nv04_mmu_new,
591// .therm = nv40_therm_new,
592// .timer = nv04_timer_new,
593// .volt = nv40_volt_new,
594// .disp = nv04_disp_new,
595// .dma = nv04_dma_new,
596// .fifo = nv40_fifo_new,
597// .gr = nv40_gr_new,
598// .mpeg = nv44_mpeg_new,
599// .pm = nv40_pm_new,
600// .sw = nv10_sw_new,
601};
602
603static const struct nvkm_device_chip
604nv46_chipset = {
605 .name = "G72",
606// .bios = nvkm_bios_new,
607// .bus = nv31_bus_new,
608// .clk = nv40_clk_new,
609// .devinit = nv1a_devinit_new,
610// .fb = nv46_fb_new,
611// .gpio = nv10_gpio_new,
612// .i2c = nv04_i2c_new,
613// .imem = nv40_instmem_new,
614// .mc = nv44_mc_new,
615// .mmu = nv44_mmu_new,
616// .therm = nv40_therm_new,
617// .timer = nv04_timer_new,
618// .volt = nv40_volt_new,
619// .disp = nv04_disp_new,
620// .dma = nv04_dma_new,
621// .fifo = nv40_fifo_new,
622// .gr = nv40_gr_new,
623// .mpeg = nv44_mpeg_new,
624// .pm = nv40_pm_new,
625// .sw = nv10_sw_new,
626};
627
628static const struct nvkm_device_chip
629nv47_chipset = {
630 .name = "G70",
631// .bios = nvkm_bios_new,
632// .bus = nv31_bus_new,
633// .clk = nv40_clk_new,
634// .devinit = nv1a_devinit_new,
635// .fb = nv47_fb_new,
636// .gpio = nv10_gpio_new,
637// .i2c = nv04_i2c_new,
638// .imem = nv40_instmem_new,
639// .mc = nv40_mc_new,
640// .mmu = nv41_mmu_new,
641// .therm = nv40_therm_new,
642// .timer = nv04_timer_new,
643// .volt = nv40_volt_new,
644// .disp = nv04_disp_new,
645// .dma = nv04_dma_new,
646// .fifo = nv40_fifo_new,
647// .gr = nv40_gr_new,
648// .mpeg = nv44_mpeg_new,
649// .pm = nv40_pm_new,
650// .sw = nv10_sw_new,
651};
652
653static const struct nvkm_device_chip
654nv49_chipset = {
655 .name = "G71",
656// .bios = nvkm_bios_new,
657// .bus = nv31_bus_new,
658// .clk = nv40_clk_new,
659// .devinit = nv1a_devinit_new,
660// .fb = nv49_fb_new,
661// .gpio = nv10_gpio_new,
662// .i2c = nv04_i2c_new,
663// .imem = nv40_instmem_new,
664// .mc = nv40_mc_new,
665// .mmu = nv41_mmu_new,
666// .therm = nv40_therm_new,
667// .timer = nv04_timer_new,
668// .volt = nv40_volt_new,
669// .disp = nv04_disp_new,
670// .dma = nv04_dma_new,
671// .fifo = nv40_fifo_new,
672// .gr = nv40_gr_new,
673// .mpeg = nv44_mpeg_new,
674// .pm = nv40_pm_new,
675// .sw = nv10_sw_new,
676};
677
678static const struct nvkm_device_chip
679nv4a_chipset = {
680 .name = "NV44A",
681// .bios = nvkm_bios_new,
682// .bus = nv31_bus_new,
683// .clk = nv40_clk_new,
684// .devinit = nv1a_devinit_new,
685// .fb = nv44_fb_new,
686// .gpio = nv10_gpio_new,
687// .i2c = nv04_i2c_new,
688// .imem = nv40_instmem_new,
689// .mc = nv44_mc_new,
690// .mmu = nv44_mmu_new,
691// .therm = nv40_therm_new,
692// .timer = nv04_timer_new,
693// .volt = nv40_volt_new,
694// .disp = nv04_disp_new,
695// .dma = nv04_dma_new,
696// .fifo = nv40_fifo_new,
697// .gr = nv40_gr_new,
698// .mpeg = nv44_mpeg_new,
699// .pm = nv40_pm_new,
700// .sw = nv10_sw_new,
701};
702
703static const struct nvkm_device_chip
704nv4b_chipset = {
705 .name = "G73",
706// .bios = nvkm_bios_new,
707// .bus = nv31_bus_new,
708// .clk = nv40_clk_new,
709// .devinit = nv1a_devinit_new,
710// .fb = nv49_fb_new,
711// .gpio = nv10_gpio_new,
712// .i2c = nv04_i2c_new,
713// .imem = nv40_instmem_new,
714// .mc = nv40_mc_new,
715// .mmu = nv41_mmu_new,
716// .therm = nv40_therm_new,
717// .timer = nv04_timer_new,
718// .volt = nv40_volt_new,
719// .disp = nv04_disp_new,
720// .dma = nv04_dma_new,
721// .fifo = nv40_fifo_new,
722// .gr = nv40_gr_new,
723// .mpeg = nv44_mpeg_new,
724// .pm = nv40_pm_new,
725// .sw = nv10_sw_new,
726};
727
728static const struct nvkm_device_chip
729nv4c_chipset = {
730 .name = "C61",
731// .bios = nvkm_bios_new,
732// .bus = nv31_bus_new,
733// .clk = nv40_clk_new,
734// .devinit = nv1a_devinit_new,
735// .fb = nv46_fb_new,
736// .gpio = nv10_gpio_new,
737// .i2c = nv04_i2c_new,
738// .imem = nv40_instmem_new,
739// .mc = nv4c_mc_new,
740// .mmu = nv44_mmu_new,
741// .therm = nv40_therm_new,
742// .timer = nv04_timer_new,
743// .volt = nv40_volt_new,
744// .disp = nv04_disp_new,
745// .dma = nv04_dma_new,
746// .fifo = nv40_fifo_new,
747// .gr = nv40_gr_new,
748// .mpeg = nv44_mpeg_new,
749// .pm = nv40_pm_new,
750// .sw = nv10_sw_new,
751};
752
753static const struct nvkm_device_chip
754nv4e_chipset = {
755 .name = "C51",
756// .bios = nvkm_bios_new,
757// .bus = nv31_bus_new,
758// .clk = nv40_clk_new,
759// .devinit = nv1a_devinit_new,
760// .fb = nv4e_fb_new,
761// .gpio = nv10_gpio_new,
762// .i2c = nv4e_i2c_new,
763// .imem = nv40_instmem_new,
764// .mc = nv4c_mc_new,
765// .mmu = nv44_mmu_new,
766// .therm = nv40_therm_new,
767// .timer = nv04_timer_new,
768// .volt = nv40_volt_new,
769// .disp = nv04_disp_new,
770// .dma = nv04_dma_new,
771// .fifo = nv40_fifo_new,
772// .gr = nv40_gr_new,
773// .mpeg = nv44_mpeg_new,
774// .pm = nv40_pm_new,
775// .sw = nv10_sw_new,
776};
777
778static const struct nvkm_device_chip
779nv50_chipset = {
780 .name = "G80",
781// .bar = nv50_bar_new,
782// .bios = nvkm_bios_new,
783// .bus = nv50_bus_new,
784// .clk = nv50_clk_new,
785// .devinit = nv50_devinit_new,
786// .fb = nv50_fb_new,
787// .fuse = nv50_fuse_new,
788// .gpio = nv50_gpio_new,
789// .i2c = nv50_i2c_new,
790// .imem = nv50_instmem_new,
791// .mc = nv50_mc_new,
792// .mmu = nv50_mmu_new,
793// .mxm = nv50_mxm_new,
794// .therm = nv50_therm_new,
795// .timer = nv04_timer_new,
796// .volt = nv40_volt_new,
797// .disp = nv50_disp_new,
798// .dma = nv50_dma_new,
799// .fifo = nv50_fifo_new,
800// .gr = nv50_gr_new,
801// .mpeg = nv50_mpeg_new,
802// .pm = nv50_pm_new,
803// .sw = nv50_sw_new,
804};
805
806static const struct nvkm_device_chip
807nv63_chipset = {
808 .name = "C73",
809// .bios = nvkm_bios_new,
810// .bus = nv31_bus_new,
811// .clk = nv40_clk_new,
812// .devinit = nv1a_devinit_new,
813// .fb = nv46_fb_new,
814// .gpio = nv10_gpio_new,
815// .i2c = nv04_i2c_new,
816// .imem = nv40_instmem_new,
817// .mc = nv4c_mc_new,
818// .mmu = nv44_mmu_new,
819// .therm = nv40_therm_new,
820// .timer = nv04_timer_new,
821// .volt = nv40_volt_new,
822// .disp = nv04_disp_new,
823// .dma = nv04_dma_new,
824// .fifo = nv40_fifo_new,
825// .gr = nv40_gr_new,
826// .mpeg = nv44_mpeg_new,
827// .pm = nv40_pm_new,
828// .sw = nv10_sw_new,
829};
830
831static const struct nvkm_device_chip
832nv67_chipset = {
833 .name = "C67",
834// .bios = nvkm_bios_new,
835// .bus = nv31_bus_new,
836// .clk = nv40_clk_new,
837// .devinit = nv1a_devinit_new,
838// .fb = nv46_fb_new,
839// .gpio = nv10_gpio_new,
840// .i2c = nv04_i2c_new,
841// .imem = nv40_instmem_new,
842// .mc = nv4c_mc_new,
843// .mmu = nv44_mmu_new,
844// .therm = nv40_therm_new,
845// .timer = nv04_timer_new,
846// .volt = nv40_volt_new,
847// .disp = nv04_disp_new,
848// .dma = nv04_dma_new,
849// .fifo = nv40_fifo_new,
850// .gr = nv40_gr_new,
851// .mpeg = nv44_mpeg_new,
852// .pm = nv40_pm_new,
853// .sw = nv10_sw_new,
854};
855
856static const struct nvkm_device_chip
857nv68_chipset = {
858 .name = "C68",
859// .bios = nvkm_bios_new,
860// .bus = nv31_bus_new,
861// .clk = nv40_clk_new,
862// .devinit = nv1a_devinit_new,
863// .fb = nv46_fb_new,
864// .gpio = nv10_gpio_new,
865// .i2c = nv04_i2c_new,
866// .imem = nv40_instmem_new,
867// .mc = nv4c_mc_new,
868// .mmu = nv44_mmu_new,
869// .therm = nv40_therm_new,
870// .timer = nv04_timer_new,
871// .volt = nv40_volt_new,
872// .disp = nv04_disp_new,
873// .dma = nv04_dma_new,
874// .fifo = nv40_fifo_new,
875// .gr = nv40_gr_new,
876// .mpeg = nv44_mpeg_new,
877// .pm = nv40_pm_new,
878// .sw = nv10_sw_new,
879};
880
881static const struct nvkm_device_chip
882nv84_chipset = {
883 .name = "G84",
884// .bar = nv50_bar_new,
885// .bios = nvkm_bios_new,
886// .bus = nv50_bus_new,
887// .clk = g84_clk_new,
888// .devinit = g84_devinit_new,
889// .fb = g84_fb_new,
890// .fuse = nv50_fuse_new,
891// .gpio = nv50_gpio_new,
892// .i2c = nv50_i2c_new,
893// .imem = nv50_instmem_new,
894// .mc = nv50_mc_new,
895// .mmu = nv50_mmu_new,
896// .mxm = nv50_mxm_new,
897// .therm = g84_therm_new,
898// .timer = nv04_timer_new,
899// .volt = nv40_volt_new,
900// .bsp = g84_bsp_new,
901// .cipher = g84_cipher_new,
902// .disp = g84_disp_new,
903// .dma = nv50_dma_new,
904// .fifo = g84_fifo_new,
905// .gr = nv50_gr_new,
906// .mpeg = g84_mpeg_new,
907// .pm = g84_pm_new,
908// .sw = nv50_sw_new,
909// .vp = g84_vp_new,
910};
911
912static const struct nvkm_device_chip
913nv86_chipset = {
914 .name = "G86",
915// .bar = nv50_bar_new,
916// .bios = nvkm_bios_new,
917// .bus = nv50_bus_new,
918// .clk = g84_clk_new,
919// .devinit = g84_devinit_new,
920// .fb = g84_fb_new,
921// .fuse = nv50_fuse_new,
922// .gpio = nv50_gpio_new,
923// .i2c = nv50_i2c_new,
924// .imem = nv50_instmem_new,
925// .mc = nv50_mc_new,
926// .mmu = nv50_mmu_new,
927// .mxm = nv50_mxm_new,
928// .therm = g84_therm_new,
929// .timer = nv04_timer_new,
930// .volt = nv40_volt_new,
931// .bsp = g84_bsp_new,
932// .cipher = g84_cipher_new,
933// .disp = g84_disp_new,
934// .dma = nv50_dma_new,
935// .fifo = g84_fifo_new,
936// .gr = nv50_gr_new,
937// .mpeg = g84_mpeg_new,
938// .pm = g84_pm_new,
939// .sw = nv50_sw_new,
940// .vp = g84_vp_new,
941};
942
943static const struct nvkm_device_chip
944nv92_chipset = {
945 .name = "G92",
946// .bar = nv50_bar_new,
947// .bios = nvkm_bios_new,
948// .bus = nv50_bus_new,
949// .clk = g84_clk_new,
950// .devinit = g84_devinit_new,
951// .fb = g84_fb_new,
952// .fuse = nv50_fuse_new,
953// .gpio = nv50_gpio_new,
954// .i2c = nv50_i2c_new,
955// .imem = nv50_instmem_new,
956// .mc = nv50_mc_new,
957// .mmu = nv50_mmu_new,
958// .mxm = nv50_mxm_new,
959// .therm = g84_therm_new,
960// .timer = nv04_timer_new,
961// .volt = nv40_volt_new,
962// .bsp = g84_bsp_new,
963// .cipher = g84_cipher_new,
964// .disp = g84_disp_new,
965// .dma = nv50_dma_new,
966// .fifo = g84_fifo_new,
967// .gr = nv50_gr_new,
968// .mpeg = g84_mpeg_new,
969// .pm = g84_pm_new,
970// .sw = nv50_sw_new,
971// .vp = g84_vp_new,
972};
973
974static const struct nvkm_device_chip
975nv94_chipset = {
976 .name = "G94",
977// .bar = nv50_bar_new,
978// .bios = nvkm_bios_new,
979// .bus = g94_bus_new,
980// .clk = g84_clk_new,
981// .devinit = g84_devinit_new,
982// .fb = g84_fb_new,
983// .fuse = nv50_fuse_new,
984// .gpio = g94_gpio_new,
985// .i2c = g94_i2c_new,
986// .imem = nv50_instmem_new,
987// .mc = g94_mc_new,
988// .mmu = nv50_mmu_new,
989// .mxm = nv50_mxm_new,
990// .therm = g84_therm_new,
991// .timer = nv04_timer_new,
992// .volt = nv40_volt_new,
993// .bsp = g84_bsp_new,
994// .cipher = g84_cipher_new,
995// .disp = g94_disp_new,
996// .dma = nv50_dma_new,
997// .fifo = g84_fifo_new,
998// .gr = nv50_gr_new,
999// .mpeg = g84_mpeg_new,
1000// .pm = g84_pm_new,
1001// .sw = nv50_sw_new,
1002// .vp = g84_vp_new,
1003};
1004
1005static const struct nvkm_device_chip
1006nv96_chipset = {
1007 .name = "G96",
1008// .bios = nvkm_bios_new,
1009// .gpio = g94_gpio_new,
1010// .i2c = g94_i2c_new,
1011// .fuse = nv50_fuse_new,
1012// .clk = g84_clk_new,
1013// .therm = g84_therm_new,
1014// .mxm = nv50_mxm_new,
1015// .devinit = g84_devinit_new,
1016// .mc = g94_mc_new,
1017// .bus = g94_bus_new,
1018// .timer = nv04_timer_new,
1019// .fb = g84_fb_new,
1020// .imem = nv50_instmem_new,
1021// .mmu = nv50_mmu_new,
1022// .bar = nv50_bar_new,
1023// .volt = nv40_volt_new,
1024// .dma = nv50_dma_new,
1025// .fifo = g84_fifo_new,
1026// .sw = nv50_sw_new,
1027// .gr = nv50_gr_new,
1028// .mpeg = g84_mpeg_new,
1029// .vp = g84_vp_new,
1030// .cipher = g84_cipher_new,
1031// .bsp = g84_bsp_new,
1032// .disp = g94_disp_new,
1033// .pm = g84_pm_new,
1034};
1035
1036static const struct nvkm_device_chip
1037nv98_chipset = {
1038 .name = "G98",
1039// .bios = nvkm_bios_new,
1040// .gpio = g94_gpio_new,
1041// .i2c = g94_i2c_new,
1042// .fuse = nv50_fuse_new,
1043// .clk = g84_clk_new,
1044// .therm = g84_therm_new,
1045// .mxm = nv50_mxm_new,
1046// .devinit = g98_devinit_new,
1047// .mc = g98_mc_new,
1048// .bus = g94_bus_new,
1049// .timer = nv04_timer_new,
1050// .fb = g84_fb_new,
1051// .imem = nv50_instmem_new,
1052// .mmu = nv50_mmu_new,
1053// .bar = nv50_bar_new,
1054// .volt = nv40_volt_new,
1055// .dma = nv50_dma_new,
1056// .fifo = g84_fifo_new,
1057// .sw = nv50_sw_new,
1058// .gr = nv50_gr_new,
1059// .mspdec = g98_mspdec_new,
1060// .sec = g98_sec_new,
1061// .msvld = g98_msvld_new,
1062// .msppp = g98_msppp_new,
1063// .disp = g94_disp_new,
1064// .pm = g84_pm_new,
1065};
1066
1067static const struct nvkm_device_chip
1068nva0_chipset = {
1069 .name = "GT200",
1070// .bar = nv50_bar_new,
1071// .bios = nvkm_bios_new,
1072// .bus = g94_bus_new,
1073// .clk = g84_clk_new,
1074// .devinit = g84_devinit_new,
1075// .fb = g84_fb_new,
1076// .fuse = nv50_fuse_new,
1077// .gpio = g94_gpio_new,
1078// .i2c = nv50_i2c_new,
1079// .imem = nv50_instmem_new,
1080// .mc = g98_mc_new,
1081// .mmu = nv50_mmu_new,
1082// .mxm = nv50_mxm_new,
1083// .therm = g84_therm_new,
1084// .timer = nv04_timer_new,
1085// .volt = nv40_volt_new,
1086// .bsp = g84_bsp_new,
1087// .cipher = g84_cipher_new,
1088// .disp = gt200_disp_new,
1089// .dma = nv50_dma_new,
1090// .fifo = g84_fifo_new,
1091// .gr = nv50_gr_new,
1092// .mpeg = g84_mpeg_new,
1093// .pm = gt200_pm_new,
1094// .sw = nv50_sw_new,
1095// .vp = g84_vp_new,
1096};
1097
1098static const struct nvkm_device_chip
1099nva3_chipset = {
1100 .name = "GT215",
1101// .bar = nv50_bar_new,
1102// .bios = nvkm_bios_new,
1103// .bus = g94_bus_new,
1104// .clk = gt215_clk_new,
1105// .devinit = gt215_devinit_new,
1106// .fb = gt215_fb_new,
1107// .fuse = nv50_fuse_new,
1108// .gpio = g94_gpio_new,
1109// .i2c = g94_i2c_new,
1110// .imem = nv50_instmem_new,
1111// .mc = g98_mc_new,
1112// .mmu = nv50_mmu_new,
1113// .mxm = nv50_mxm_new,
1114// .pmu = gt215_pmu_new,
1115// .therm = gt215_therm_new,
1116// .timer = nv04_timer_new,
1117// .volt = nv40_volt_new,
1118// .ce[0] = gt215_ce_new,
1119// .disp = gt215_disp_new,
1120// .dma = nv50_dma_new,
1121// .fifo = g84_fifo_new,
1122// .gr = nv50_gr_new,
1123// .mpeg = g84_mpeg_new,
1124// .mspdec = g98_mspdec_new,
1125// .msppp = g98_msppp_new,
1126// .msvld = g98_msvld_new,
1127// .pm = gt215_pm_new,
1128// .sw = nv50_sw_new,
1129};
1130
1131static const struct nvkm_device_chip
1132nva5_chipset = {
1133 .name = "GT216",
1134// .bar = nv50_bar_new,
1135// .bios = nvkm_bios_new,
1136// .bus = g94_bus_new,
1137// .clk = gt215_clk_new,
1138// .devinit = gt215_devinit_new,
1139// .fb = gt215_fb_new,
1140// .fuse = nv50_fuse_new,
1141// .gpio = g94_gpio_new,
1142// .i2c = g94_i2c_new,
1143// .imem = nv50_instmem_new,
1144// .mc = g98_mc_new,
1145// .mmu = nv50_mmu_new,
1146// .mxm = nv50_mxm_new,
1147// .pmu = gt215_pmu_new,
1148// .therm = gt215_therm_new,
1149// .timer = nv04_timer_new,
1150// .volt = nv40_volt_new,
1151// .ce[0] = gt215_ce_new,
1152// .disp = gt215_disp_new,
1153// .dma = nv50_dma_new,
1154// .fifo = g84_fifo_new,
1155// .gr = nv50_gr_new,
1156// .mspdec = g98_mspdec_new,
1157// .msppp = g98_msppp_new,
1158// .msvld = g98_msvld_new,
1159// .pm = gt215_pm_new,
1160// .sw = nv50_sw_new,
1161};
1162
1163static const struct nvkm_device_chip
1164nva8_chipset = {
1165 .name = "GT218",
1166// .bar = nv50_bar_new,
1167// .bios = nvkm_bios_new,
1168// .bus = g94_bus_new,
1169// .clk = gt215_clk_new,
1170// .devinit = gt215_devinit_new,
1171// .fb = gt215_fb_new,
1172// .fuse = nv50_fuse_new,
1173// .gpio = g94_gpio_new,
1174// .i2c = g94_i2c_new,
1175// .imem = nv50_instmem_new,
1176// .mc = g98_mc_new,
1177// .mmu = nv50_mmu_new,
1178// .mxm = nv50_mxm_new,
1179// .pmu = gt215_pmu_new,
1180// .therm = gt215_therm_new,
1181// .timer = nv04_timer_new,
1182// .volt = nv40_volt_new,
1183// .ce[0] = gt215_ce_new,
1184// .disp = gt215_disp_new,
1185// .dma = nv50_dma_new,
1186// .fifo = g84_fifo_new,
1187// .gr = nv50_gr_new,
1188// .mspdec = g98_mspdec_new,
1189// .msppp = g98_msppp_new,
1190// .msvld = g98_msvld_new,
1191// .pm = gt215_pm_new,
1192// .sw = nv50_sw_new,
1193};
1194
1195static const struct nvkm_device_chip
1196nvaa_chipset = {
1197 .name = "MCP77/MCP78",
1198// .bar = nv50_bar_new,
1199// .bios = nvkm_bios_new,
1200// .bus = g94_bus_new,
1201// .clk = mcp77_clk_new,
1202// .devinit = g98_devinit_new,
1203// .fb = mcp77_fb_new,
1204// .fuse = nv50_fuse_new,
1205// .gpio = g94_gpio_new,
1206// .i2c = g94_i2c_new,
1207// .imem = nv50_instmem_new,
1208// .mc = g98_mc_new,
1209// .mmu = nv50_mmu_new,
1210// .mxm = nv50_mxm_new,
1211// .therm = g84_therm_new,
1212// .timer = nv04_timer_new,
1213// .volt = nv40_volt_new,
1214// .disp = g94_disp_new,
1215// .dma = nv50_dma_new,
1216// .fifo = g84_fifo_new,
1217// .gr = nv50_gr_new,
1218// .mspdec = g98_mspdec_new,
1219// .msppp = g98_msppp_new,
1220// .msvld = g98_msvld_new,
1221// .pm = g84_pm_new,
1222// .sec = g98_sec_new,
1223// .sw = nv50_sw_new,
1224};
1225
1226static const struct nvkm_device_chip
1227nvac_chipset = {
1228 .name = "MCP79/MCP7A",
1229// .bar = nv50_bar_new,
1230// .bios = nvkm_bios_new,
1231// .bus = g94_bus_new,
1232// .clk = mcp77_clk_new,
1233// .devinit = g98_devinit_new,
1234// .fb = mcp77_fb_new,
1235// .fuse = nv50_fuse_new,
1236// .gpio = g94_gpio_new,
1237// .i2c = g94_i2c_new,
1238// .imem = nv50_instmem_new,
1239// .mc = g98_mc_new,
1240// .mmu = nv50_mmu_new,
1241// .mxm = nv50_mxm_new,
1242// .therm = g84_therm_new,
1243// .timer = nv04_timer_new,
1244// .volt = nv40_volt_new,
1245// .disp = g94_disp_new,
1246// .dma = nv50_dma_new,
1247// .fifo = g84_fifo_new,
1248// .gr = nv50_gr_new,
1249// .mspdec = g98_mspdec_new,
1250// .msppp = g98_msppp_new,
1251// .msvld = g98_msvld_new,
1252// .pm = g84_pm_new,
1253// .sec = g98_sec_new,
1254// .sw = nv50_sw_new,
1255};
1256
1257static const struct nvkm_device_chip
1258nvaf_chipset = {
1259 .name = "MCP89",
1260// .bar = nv50_bar_new,
1261// .bios = nvkm_bios_new,
1262// .bus = g94_bus_new,
1263// .clk = gt215_clk_new,
1264// .devinit = mcp89_devinit_new,
1265// .fb = mcp89_fb_new,
1266// .fuse = nv50_fuse_new,
1267// .gpio = g94_gpio_new,
1268// .i2c = g94_i2c_new,
1269// .imem = nv50_instmem_new,
1270// .mc = g98_mc_new,
1271// .mmu = nv50_mmu_new,
1272// .mxm = nv50_mxm_new,
1273// .pmu = gt215_pmu_new,
1274// .therm = gt215_therm_new,
1275// .timer = nv04_timer_new,
1276// .volt = nv40_volt_new,
1277// .ce[0] = gt215_ce_new,
1278// .disp = gt215_disp_new,
1279// .dma = nv50_dma_new,
1280// .fifo = g84_fifo_new,
1281// .gr = nv50_gr_new,
1282// .mspdec = g98_mspdec_new,
1283// .msppp = g98_msppp_new,
1284// .msvld = g98_msvld_new,
1285// .pm = gt215_pm_new,
1286// .sw = nv50_sw_new,
1287};
1288
1289static const struct nvkm_device_chip
1290nvc0_chipset = {
1291 .name = "GF100",
1292// .bar = gf100_bar_new,
1293// .bios = nvkm_bios_new,
1294// .bus = gf100_bus_new,
1295// .clk = gf100_clk_new,
1296// .devinit = gf100_devinit_new,
1297// .fb = gf100_fb_new,
1298// .fuse = gf100_fuse_new,
1299// .gpio = g94_gpio_new,
1300// .i2c = g94_i2c_new,
1301// .ibus = gf100_ibus_new,
1302// .imem = nv50_instmem_new,
1303// .ltc = gf100_ltc_new,
1304// .mc = gf100_mc_new,
1305// .mmu = gf100_mmu_new,
1306// .mxm = nv50_mxm_new,
1307// .pmu = gf100_pmu_new,
1308// .therm = gt215_therm_new,
1309// .timer = nv04_timer_new,
1310// .volt = nv40_volt_new,
1311// .ce[0] = gf100_ce0_new,
1312// .ce[1] = gf100_ce1_new,
1313// .disp = gt215_disp_new,
1314// .dma = gf100_dma_new,
1315// .fifo = gf100_fifo_new,
1316// .gr = gf100_gr_new,
1317// .mspdec = gf100_mspdec_new,
1318// .msppp = gf100_msppp_new,
1319// .msvld = gf100_msvld_new,
1320// .pm = gf100_pm_new,
1321// .sw = gf100_sw_new,
1322};
1323
1324static const struct nvkm_device_chip
1325nvc1_chipset = {
1326 .name = "GF108",
1327// .bar = gf100_bar_new,
1328// .bios = nvkm_bios_new,
1329// .bus = gf100_bus_new,
1330// .clk = gf100_clk_new,
1331// .devinit = gf100_devinit_new,
1332// .fb = gf100_fb_new,
1333// .fuse = gf100_fuse_new,
1334// .gpio = g94_gpio_new,
1335// .i2c = g94_i2c_new,
1336// .ibus = gf100_ibus_new,
1337// .imem = nv50_instmem_new,
1338// .ltc = gf100_ltc_new,
1339// .mc = gf106_mc_new,
1340// .mmu = gf100_mmu_new,
1341// .mxm = nv50_mxm_new,
1342// .pmu = gf100_pmu_new,
1343// .therm = gt215_therm_new,
1344// .timer = nv04_timer_new,
1345// .volt = nv40_volt_new,
1346// .ce[0] = gf100_ce0_new,
1347// .disp = gt215_disp_new,
1348// .dma = gf100_dma_new,
1349// .fifo = gf100_fifo_new,
1350// .gr = gf108_gr_new,
1351// .mspdec = gf100_mspdec_new,
1352// .msppp = gf100_msppp_new,
1353// .msvld = gf100_msvld_new,
1354// .pm = gf108_pm_new,
1355// .sw = gf100_sw_new,
1356};
1357
1358static const struct nvkm_device_chip
1359nvc3_chipset = {
1360 .name = "GF106",
1361// .bar = gf100_bar_new,
1362// .bios = nvkm_bios_new,
1363// .bus = gf100_bus_new,
1364// .clk = gf100_clk_new,
1365// .devinit = gf100_devinit_new,
1366// .fb = gf100_fb_new,
1367// .fuse = gf100_fuse_new,
1368// .gpio = g94_gpio_new,
1369// .i2c = g94_i2c_new,
1370// .ibus = gf100_ibus_new,
1371// .imem = nv50_instmem_new,
1372// .ltc = gf100_ltc_new,
1373// .mc = gf106_mc_new,
1374// .mmu = gf100_mmu_new,
1375// .mxm = nv50_mxm_new,
1376// .pmu = gf100_pmu_new,
1377// .therm = gt215_therm_new,
1378// .timer = nv04_timer_new,
1379// .volt = nv40_volt_new,
1380// .ce[0] = gf100_ce0_new,
1381// .disp = gt215_disp_new,
1382// .dma = gf100_dma_new,
1383// .fifo = gf100_fifo_new,
1384// .gr = gf104_gr_new,
1385// .mspdec = gf100_mspdec_new,
1386// .msppp = gf100_msppp_new,
1387// .msvld = gf100_msvld_new,
1388// .pm = gf100_pm_new,
1389// .sw = gf100_sw_new,
1390};
1391
1392static const struct nvkm_device_chip
1393nvc4_chipset = {
1394 .name = "GF104",
1395// .bar = gf100_bar_new,
1396// .bios = nvkm_bios_new,
1397// .bus = gf100_bus_new,
1398// .clk = gf100_clk_new,
1399// .devinit = gf100_devinit_new,
1400// .fb = gf100_fb_new,
1401// .fuse = gf100_fuse_new,
1402// .gpio = g94_gpio_new,
1403// .i2c = g94_i2c_new,
1404// .ibus = gf100_ibus_new,
1405// .imem = nv50_instmem_new,
1406// .ltc = gf100_ltc_new,
1407// .mc = gf100_mc_new,
1408// .mmu = gf100_mmu_new,
1409// .mxm = nv50_mxm_new,
1410// .pmu = gf100_pmu_new,
1411// .therm = gt215_therm_new,
1412// .timer = nv04_timer_new,
1413// .volt = nv40_volt_new,
1414// .ce[0] = gf100_ce0_new,
1415// .ce[1] = gf100_ce1_new,
1416// .disp = gt215_disp_new,
1417// .dma = gf100_dma_new,
1418// .fifo = gf100_fifo_new,
1419// .gr = gf104_gr_new,
1420// .mspdec = gf100_mspdec_new,
1421// .msppp = gf100_msppp_new,
1422// .msvld = gf100_msvld_new,
1423// .pm = gf100_pm_new,
1424// .sw = gf100_sw_new,
1425};
1426
1427static const struct nvkm_device_chip
1428nvc8_chipset = {
1429 .name = "GF110",
1430// .bar = gf100_bar_new,
1431// .bios = nvkm_bios_new,
1432// .bus = gf100_bus_new,
1433// .clk = gf100_clk_new,
1434// .devinit = gf100_devinit_new,
1435// .fb = gf100_fb_new,
1436// .fuse = gf100_fuse_new,
1437// .gpio = g94_gpio_new,
1438// .i2c = g94_i2c_new,
1439// .ibus = gf100_ibus_new,
1440// .imem = nv50_instmem_new,
1441// .ltc = gf100_ltc_new,
1442// .mc = gf100_mc_new,
1443// .mmu = gf100_mmu_new,
1444// .mxm = nv50_mxm_new,
1445// .pmu = gf100_pmu_new,
1446// .therm = gt215_therm_new,
1447// .timer = nv04_timer_new,
1448// .volt = nv40_volt_new,
1449// .ce[0] = gf100_ce0_new,
1450// .ce[1] = gf100_ce1_new,
1451// .disp = gt215_disp_new,
1452// .dma = gf100_dma_new,
1453// .fifo = gf100_fifo_new,
1454// .gr = gf110_gr_new,
1455// .mspdec = gf100_mspdec_new,
1456// .msppp = gf100_msppp_new,
1457// .msvld = gf100_msvld_new,
1458// .pm = gf100_pm_new,
1459// .sw = gf100_sw_new,
1460};
1461
1462static const struct nvkm_device_chip
1463nvce_chipset = {
1464 .name = "GF114",
1465// .bar = gf100_bar_new,
1466// .bios = nvkm_bios_new,
1467// .bus = gf100_bus_new,
1468// .clk = gf100_clk_new,
1469// .devinit = gf100_devinit_new,
1470// .fb = gf100_fb_new,
1471// .fuse = gf100_fuse_new,
1472// .gpio = g94_gpio_new,
1473// .i2c = g94_i2c_new,
1474// .ibus = gf100_ibus_new,
1475// .imem = nv50_instmem_new,
1476// .ltc = gf100_ltc_new,
1477// .mc = gf100_mc_new,
1478// .mmu = gf100_mmu_new,
1479// .mxm = nv50_mxm_new,
1480// .pmu = gf100_pmu_new,
1481// .therm = gt215_therm_new,
1482// .timer = nv04_timer_new,
1483// .volt = nv40_volt_new,
1484// .ce[0] = gf100_ce0_new,
1485// .ce[1] = gf100_ce1_new,
1486// .disp = gt215_disp_new,
1487// .dma = gf100_dma_new,
1488// .fifo = gf100_fifo_new,
1489// .gr = gf104_gr_new,
1490// .mspdec = gf100_mspdec_new,
1491// .msppp = gf100_msppp_new,
1492// .msvld = gf100_msvld_new,
1493// .pm = gf100_pm_new,
1494// .sw = gf100_sw_new,
1495};
1496
1497static const struct nvkm_device_chip
1498nvcf_chipset = {
1499 .name = "GF116",
1500// .bar = gf100_bar_new,
1501// .bios = nvkm_bios_new,
1502// .bus = gf100_bus_new,
1503// .clk = gf100_clk_new,
1504// .devinit = gf100_devinit_new,
1505// .fb = gf100_fb_new,
1506// .fuse = gf100_fuse_new,
1507// .gpio = g94_gpio_new,
1508// .i2c = g94_i2c_new,
1509// .ibus = gf100_ibus_new,
1510// .imem = nv50_instmem_new,
1511// .ltc = gf100_ltc_new,
1512// .mc = gf106_mc_new,
1513// .mmu = gf100_mmu_new,
1514// .mxm = nv50_mxm_new,
1515// .pmu = gf100_pmu_new,
1516// .therm = gt215_therm_new,
1517// .timer = nv04_timer_new,
1518// .volt = nv40_volt_new,
1519// .ce[0] = gf100_ce0_new,
1520// .disp = gt215_disp_new,
1521// .dma = gf100_dma_new,
1522// .fifo = gf100_fifo_new,
1523// .gr = gf104_gr_new,
1524// .mspdec = gf100_mspdec_new,
1525// .msppp = gf100_msppp_new,
1526// .msvld = gf100_msvld_new,
1527// .pm = gf100_pm_new,
1528// .sw = gf100_sw_new,
1529};
1530
1531static const struct nvkm_device_chip
1532nvd7_chipset = {
1533 .name = "GF117",
1534// .bar = gf100_bar_new,
1535// .bios = nvkm_bios_new,
1536// .bus = gf100_bus_new,
1537// .clk = gf100_clk_new,
1538// .devinit = gf100_devinit_new,
1539// .fb = gf100_fb_new,
1540// .fuse = gf100_fuse_new,
1541// .gpio = gf110_gpio_new,
1542// .i2c = gf117_i2c_new,
1543// .ibus = gf100_ibus_new,
1544// .imem = nv50_instmem_new,
1545// .ltc = gf100_ltc_new,
1546// .mc = gf106_mc_new,
1547// .mmu = gf100_mmu_new,
1548// .mxm = nv50_mxm_new,
1549// .therm = gf110_therm_new,
1550// .timer = nv04_timer_new,
1551// .ce[0] = gf100_ce0_new,
1552// .disp = gf119_disp_new,
1553// .dma = gf119_dma_new,
1554// .fifo = gf100_fifo_new,
1555// .gr = gf117_gr_new,
1556// .mspdec = gf100_mspdec_new,
1557// .msppp = gf100_msppp_new,
1558// .msvld = gf100_msvld_new,
1559// .pm = gf117_pm_new,
1560// .sw = gf100_sw_new,
1561};
1562
1563static const struct nvkm_device_chip
1564nvd9_chipset = {
1565 .name = "GF119",
1566// .bar = gf100_bar_new,
1567// .bios = nvkm_bios_new,
1568// .bus = gf100_bus_new,
1569// .clk = gf100_clk_new,
1570// .devinit = gf100_devinit_new,
1571// .fb = gf100_fb_new,
1572// .fuse = gf100_fuse_new,
1573// .gpio = gf110_gpio_new,
1574// .i2c = gf110_i2c_new,
1575// .ibus = gf100_ibus_new,
1576// .imem = nv50_instmem_new,
1577// .ltc = gf100_ltc_new,
1578// .mc = gf106_mc_new,
1579// .mmu = gf100_mmu_new,
1580// .mxm = nv50_mxm_new,
1581// .pmu = gf110_pmu_new,
1582// .therm = gf110_therm_new,
1583// .timer = nv04_timer_new,
1584// .volt = nv40_volt_new,
1585// .ce[0] = gf100_ce0_new,
1586// .disp = gf119_disp_new,
1587// .dma = gf119_dma_new,
1588// .fifo = gf100_fifo_new,
1589// .gr = gf119_gr_new,
1590// .mspdec = gf100_mspdec_new,
1591// .msppp = gf100_msppp_new,
1592// .msvld = gf100_msvld_new,
1593// .pm = gf117_pm_new,
1594// .sw = gf100_sw_new,
1595};
1596
1597static const struct nvkm_device_chip
1598nve4_chipset = {
1599 .name = "GK104",
1600// .bar = gf100_bar_new,
1601// .bios = nvkm_bios_new,
1602// .bus = gf100_bus_new,
1603// .clk = gk104_clk_new,
1604// .devinit = gf100_devinit_new,
1605// .fb = gk104_fb_new,
1606// .fuse = gf100_fuse_new,
1607// .gpio = gk104_gpio_new,
1608// .i2c = gk104_i2c_new,
1609// .ibus = gk104_ibus_new,
1610// .imem = nv50_instmem_new,
1611// .ltc = gk104_ltc_new,
1612// .mc = gf106_mc_new,
1613// .mmu = gf100_mmu_new,
1614// .mxm = nv50_mxm_new,
1615// .pmu = gk104_pmu_new,
1616// .therm = gf110_therm_new,
1617// .timer = nv04_timer_new,
1618// .volt = nv40_volt_new,
1619// .ce[0] = gk104_ce0_new,
1620// .ce[1] = gk104_ce1_new,
1621// .ce[2] = gk104_ce2_new,
1622// .disp = gk104_disp_new,
1623// .dma = gf119_dma_new,
1624// .fifo = gk104_fifo_new,
1625// .gr = gk104_gr_new,
1626// .mspdec = gk104_mspdec_new,
1627// .msppp = gf100_msppp_new,
1628// .msvld = gk104_msvld_new,
1629// .pm = gk104_pm_new,
1630// .sw = gf100_sw_new,
1631};
1632
1633static const struct nvkm_device_chip
1634nve6_chipset = {
1635 .name = "GK106",
1636// .bar = gf100_bar_new,
1637// .bios = nvkm_bios_new,
1638// .bus = gf100_bus_new,
1639// .clk = gk104_clk_new,
1640// .devinit = gf100_devinit_new,
1641// .fb = gk104_fb_new,
1642// .fuse = gf100_fuse_new,
1643// .gpio = gk104_gpio_new,
1644// .i2c = gk104_i2c_new,
1645// .ibus = gk104_ibus_new,
1646// .imem = nv50_instmem_new,
1647// .ltc = gk104_ltc_new,
1648// .mc = gf106_mc_new,
1649// .mmu = gf100_mmu_new,
1650// .mxm = nv50_mxm_new,
1651// .pmu = gk104_pmu_new,
1652// .therm = gf110_therm_new,
1653// .timer = nv04_timer_new,
1654// .volt = nv40_volt_new,
1655// .ce[0] = gk104_ce0_new,
1656// .ce[1] = gk104_ce1_new,
1657// .ce[2] = gk104_ce2_new,
1658// .disp = gk104_disp_new,
1659// .dma = gf119_dma_new,
1660// .fifo = gk104_fifo_new,
1661// .gr = gk104_gr_new,
1662// .mspdec = gk104_mspdec_new,
1663// .msppp = gf100_msppp_new,
1664// .msvld = gk104_msvld_new,
1665// .pm = gk104_pm_new,
1666// .sw = gf100_sw_new,
1667};
1668
1669static const struct nvkm_device_chip
1670nve7_chipset = {
1671 .name = "GK107",
1672// .bar = gf100_bar_new,
1673// .bios = nvkm_bios_new,
1674// .bus = gf100_bus_new,
1675// .clk = gk104_clk_new,
1676// .devinit = gf100_devinit_new,
1677// .fb = gk104_fb_new,
1678// .fuse = gf100_fuse_new,
1679// .gpio = gk104_gpio_new,
1680// .i2c = gk104_i2c_new,
1681// .ibus = gk104_ibus_new,
1682// .imem = nv50_instmem_new,
1683// .ltc = gk104_ltc_new,
1684// .mc = gf106_mc_new,
1685// .mmu = gf100_mmu_new,
1686// .mxm = nv50_mxm_new,
1687// .pmu = gf110_pmu_new,
1688// .therm = gf110_therm_new,
1689// .timer = nv04_timer_new,
1690// .volt = nv40_volt_new,
1691// .ce[0] = gk104_ce0_new,
1692// .ce[1] = gk104_ce1_new,
1693// .ce[2] = gk104_ce2_new,
1694// .disp = gk104_disp_new,
1695// .dma = gf119_dma_new,
1696// .fifo = gk104_fifo_new,
1697// .gr = gk104_gr_new,
1698// .mspdec = gk104_mspdec_new,
1699// .msppp = gf100_msppp_new,
1700// .msvld = gk104_msvld_new,
1701// .pm = gk104_pm_new,
1702// .sw = gf100_sw_new,
1703};
1704
1705static const struct nvkm_device_chip
1706nvea_chipset = {
1707 .name = "GK20A",
1708// .bar = gk20a_bar_new,
1709// .bus = gf100_bus_new,
1710// .clk = gk20a_clk_new,
1711// .fb = gk20a_fb_new,
1712// .fuse = gf100_fuse_new,
1713// .ibus = gk20a_ibus_new,
1714// .imem = gk20a_instmem_new,
1715// .ltc = gk104_ltc_new,
1716// .mc = gk20a_mc_new,
1717// .mmu = gf100_mmu_new,
1718// .pmu = gk20a_pmu_new,
1719// .timer = gk20a_timer_new,
1720// .volt = gk20a_volt_new,
1721// .ce[2] = gk104_ce2_new,
1722// .dma = gf119_dma_new,
1723// .fifo = gk20a_fifo_new,
1724// .gr = gk20a_gr_new,
1725// .pm = gk104_pm_new,
1726// .sw = gf100_sw_new,
1727};
1728
1729static const struct nvkm_device_chip
1730nvf0_chipset = {
1731 .name = "GK110",
1732// .bar = gf100_bar_new,
1733// .bios = nvkm_bios_new,
1734// .bus = gf100_bus_new,
1735// .clk = gk104_clk_new,
1736// .devinit = gf100_devinit_new,
1737// .fb = gk104_fb_new,
1738// .fuse = gf100_fuse_new,
1739// .gpio = gk104_gpio_new,
1740// .i2c = gk104_i2c_new,
1741// .ibus = gk104_ibus_new,
1742// .imem = nv50_instmem_new,
1743// .ltc = gk104_ltc_new,
1744// .mc = gf106_mc_new,
1745// .mmu = gf100_mmu_new,
1746// .mxm = nv50_mxm_new,
1747// .pmu = gk110_pmu_new,
1748// .therm = gf110_therm_new,
1749// .timer = nv04_timer_new,
1750// .volt = nv40_volt_new,
1751// .ce[0] = gk104_ce0_new,
1752// .ce[1] = gk104_ce1_new,
1753// .ce[2] = gk104_ce2_new,
1754// .disp = gk110_disp_new,
1755// .dma = gf119_dma_new,
1756// .fifo = gk104_fifo_new,
1757// .gr = gk110_gr_new,
1758// .mspdec = gk104_mspdec_new,
1759// .msppp = gf100_msppp_new,
1760// .msvld = gk104_msvld_new,
1761// .pm = gk110_pm_new,
1762// .sw = gf100_sw_new,
1763};
1764
1765static const struct nvkm_device_chip
1766nvf1_chipset = {
1767 .name = "GK110B",
1768// .bar = gf100_bar_new,
1769// .bios = nvkm_bios_new,
1770// .bus = gf100_bus_new,
1771// .clk = gk104_clk_new,
1772// .devinit = gf100_devinit_new,
1773// .fb = gk104_fb_new,
1774// .fuse = gf100_fuse_new,
1775// .gpio = gk104_gpio_new,
1776// .i2c = gf110_i2c_new,
1777// .ibus = gk104_ibus_new,
1778// .imem = nv50_instmem_new,
1779// .ltc = gk104_ltc_new,
1780// .mc = gf106_mc_new,
1781// .mmu = gf100_mmu_new,
1782// .mxm = nv50_mxm_new,
1783// .pmu = gk110_pmu_new,
1784// .therm = gf110_therm_new,
1785// .timer = nv04_timer_new,
1786// .volt = nv40_volt_new,
1787// .ce[0] = gk104_ce0_new,
1788// .ce[1] = gk104_ce1_new,
1789// .ce[2] = gk104_ce2_new,
1790// .disp = gk110_disp_new,
1791// .dma = gf119_dma_new,
1792// .fifo = gk104_fifo_new,
1793// .gr = gk110b_gr_new,
1794// .mspdec = gk104_mspdec_new,
1795// .msppp = gf100_msppp_new,
1796// .msvld = gk104_msvld_new,
1797// .pm = gk110_pm_new,
1798// .sw = gf100_sw_new,
1799};
1800
1801static const struct nvkm_device_chip
1802nv106_chipset = {
1803 .name = "GK208B",
1804// .bar = gf100_bar_new,
1805// .bios = nvkm_bios_new,
1806// .bus = gf100_bus_new,
1807// .clk = gk104_clk_new,
1808// .devinit = gf100_devinit_new,
1809// .fb = gk104_fb_new,
1810// .fuse = gf100_fuse_new,
1811// .gpio = gk104_gpio_new,
1812// .i2c = gk104_i2c_new,
1813// .ibus = gk104_ibus_new,
1814// .imem = nv50_instmem_new,
1815// .ltc = gk104_ltc_new,
1816// .mc = gk20a_mc_new,
1817// .mmu = gf100_mmu_new,
1818// .mxm = nv50_mxm_new,
1819// .pmu = gk208_pmu_new,
1820// .therm = gf110_therm_new,
1821// .timer = nv04_timer_new,
1822// .volt = nv40_volt_new,
1823// .ce[0] = gk104_ce0_new,
1824// .ce[1] = gk104_ce1_new,
1825// .ce[2] = gk104_ce2_new,
1826// .disp = gk110_disp_new,
1827// .dma = gf119_dma_new,
1828// .fifo = gk208_fifo_new,
1829// .gr = gk208_gr_new,
1830// .mspdec = gk104_mspdec_new,
1831// .msppp = gf100_msppp_new,
1832// .msvld = gk104_msvld_new,
1833// .sw = gf100_sw_new,
1834};
1835
1836static const struct nvkm_device_chip
1837nv108_chipset = {
1838 .name = "GK208",
1839// .bar = gf100_bar_new,
1840// .bios = nvkm_bios_new,
1841// .bus = gf100_bus_new,
1842// .clk = gk104_clk_new,
1843// .devinit = gf100_devinit_new,
1844// .fb = gk104_fb_new,
1845// .fuse = gf100_fuse_new,
1846// .gpio = gk104_gpio_new,
1847// .i2c = gk104_i2c_new,
1848// .ibus = gk104_ibus_new,
1849// .imem = nv50_instmem_new,
1850// .ltc = gk104_ltc_new,
1851// .mc = gk20a_mc_new,
1852// .mmu = gf100_mmu_new,
1853// .mxm = nv50_mxm_new,
1854// .pmu = gk208_pmu_new,
1855// .therm = gf110_therm_new,
1856// .timer = nv04_timer_new,
1857// .volt = nv40_volt_new,
1858// .ce[0] = gk104_ce0_new,
1859// .ce[1] = gk104_ce1_new,
1860// .ce[2] = gk104_ce2_new,
1861// .disp = gk110_disp_new,
1862// .dma = gf119_dma_new,
1863// .fifo = gk208_fifo_new,
1864// .gr = gk208_gr_new,
1865// .mspdec = gk104_mspdec_new,
1866// .msppp = gf100_msppp_new,
1867// .msvld = gk104_msvld_new,
1868// .sw = gf100_sw_new,
1869};
1870
1871static const struct nvkm_device_chip
1872nv117_chipset = {
1873 .name = "GM107",
1874// .bar = gf100_bar_new,
1875// .bios = nvkm_bios_new,
1876// .bus = gf100_bus_new,
1877// .clk = gk104_clk_new,
1878// .devinit = gm107_devinit_new,
1879// .fb = gm107_fb_new,
1880// .fuse = gm107_fuse_new,
1881// .gpio = gk104_gpio_new,
1882// .i2c = gf110_i2c_new,
1883// .ibus = gk104_ibus_new,
1884// .imem = nv50_instmem_new,
1885// .ltc = gm107_ltc_new,
1886// .mc = gk20a_mc_new,
1887// .mmu = gf100_mmu_new,
1888// .mxm = nv50_mxm_new,
1889// .pmu = gk208_pmu_new,
1890// .therm = gm107_therm_new,
1891// .timer = gk20a_timer_new,
1892// .ce[0] = gk104_ce0_new,
1893// .ce[2] = gk104_ce2_new,
1894// .disp = gm107_disp_new,
1895// .dma = gf119_dma_new,
1896// .fifo = gk208_fifo_new,
1897// .gr = gm107_gr_new,
1898// .sw = gf100_sw_new,
1899};
1900
1901static const struct nvkm_device_chip
1902nv124_chipset = {
1903 .name = "GM204",
1904// .bar = gf100_bar_new,
1905// .bios = nvkm_bios_new,
1906// .bus = gf100_bus_new,
1907// .devinit = gm204_devinit_new,
1908// .fb = gm107_fb_new,
1909// .fuse = gm107_fuse_new,
1910// .gpio = gk104_gpio_new,
1911// .i2c = gm204_i2c_new,
1912// .ibus = gk104_ibus_new,
1913// .imem = nv50_instmem_new,
1914// .ltc = gm107_ltc_new,
1915// .mc = gk20a_mc_new,
1916// .mmu = gf100_mmu_new,
1917// .mxm = nv50_mxm_new,
1918// .pmu = gk208_pmu_new,
1919// .timer = gk20a_timer_new,
1920// .ce[0] = gm204_ce0_new,
1921// .ce[1] = gm204_ce1_new,
1922// .ce[2] = gm204_ce2_new,
1923// .disp = gm204_disp_new,
1924// .dma = gf119_dma_new,
1925// .fifo = gm204_fifo_new,
1926// .gr = gm204_gr_new,
1927// .sw = gf100_sw_new,
1928};
1929
1930static const struct nvkm_device_chip
1931nv126_chipset = {
1932 .name = "GM206",
1933// .bar = gf100_bar_new,
1934// .bios = nvkm_bios_new,
1935// .bus = gf100_bus_new,
1936// .devinit = gm204_devinit_new,
1937// .fb = gm107_fb_new,
1938// .fuse = gm107_fuse_new,
1939// .gpio = gk104_gpio_new,
1940// .i2c = gm204_i2c_new,
1941// .ibus = gk104_ibus_new,
1942// .imem = nv50_instmem_new,
1943// .ltc = gm107_ltc_new,
1944// .mc = gk20a_mc_new,
1945// .mmu = gf100_mmu_new,
1946// .mxm = nv50_mxm_new,
1947// .pmu = gk208_pmu_new,
1948// .timer = gk20a_timer_new,
1949// .ce[0] = gm204_ce0_new,
1950// .ce[1] = gm204_ce1_new,
1951// .ce[2] = gm204_ce2_new,
1952// .disp = gm204_disp_new,
1953// .dma = gf119_dma_new,
1954// .fifo = gm204_fifo_new,
1955// .gr = gm206_gr_new,
1956// .sw = gf100_sw_new,
1957};
1958
1959static const struct nvkm_device_chip
1960nv12b_chipset = {
1961 .name = "GM20B",
1962// .bar = gk20a_bar_new,
1963// .bus = gf100_bus_new,
1964// .fb = gk20a_fb_new,
1965// .fuse = gm107_fuse_new,
1966// .ibus = gk20a_ibus_new,
1967// .imem = gk20a_instmem_new,
1968// .ltc = gm107_ltc_new,
1969// .mc = gk20a_mc_new,
1970// .mmu = gf100_mmu_new,
1971// .mmu = gf100_mmu_new,
1972// .timer = gk20a_timer_new,
1973// .ce[2] = gm204_ce2_new,
1974// .dma = gf119_dma_new,
1975// .fifo = gm20b_fifo_new,
1976// .gr = gm20b_gr_new,
1977// .sw = gf100_sw_new,
1978};
1979
70#include <core/parent.h> 1980#include <core/parent.h>
71#include <core/client.h> 1981#include <core/client.h>
72 1982
@@ -116,45 +2026,129 @@ nvkm_device_event_func = {
116 .ctor = nvkm_device_event_ctor, 2026 .ctor = nvkm_device_event_ctor,
117}; 2027};
118 2028
2029struct nvkm_subdev *
2030nvkm_device_subdev(struct nvkm_device *device, int index)
2031{
2032 struct nvkm_engine *engine;
2033
2034 if (device->disable_mask & (1ULL << index))
2035 return NULL;
2036
2037 switch (index) {
2038#define _(n,p,m) case NVDEV_SUBDEV_##n: if (p) return (m); break
2039 _(BAR , device->bar , &device->bar->subdev);
2040 _(VBIOS , device->bios , &device->bios->subdev);
2041 _(BUS , device->bus , &device->bus->subdev);
2042 _(CLK , device->clk , &device->clk->subdev);
2043 _(DEVINIT, device->devinit, &device->devinit->subdev);
2044 _(FB , device->fb , &device->fb->subdev);
2045 _(FUSE , device->fuse , &device->fuse->subdev);
2046 _(GPIO , device->gpio , &device->gpio->subdev);
2047 _(I2C , device->i2c , &device->i2c->subdev);
2048 _(IBUS , device->ibus , device->ibus);
2049 _(INSTMEM, device->imem , &device->imem->subdev);
2050 _(LTC , device->ltc , &device->ltc->subdev);
2051 _(MC , device->mc , &device->mc->subdev);
2052 _(MMU , device->mmu , &device->mmu->subdev);
2053 _(MXM , device->mxm , device->mxm);
2054 _(PMU , device->pmu , &device->pmu->subdev);
2055 _(THERM , device->therm , &device->therm->subdev);
2056 _(TIMER , device->timer , &device->timer->subdev);
2057 _(VOLT , device->volt , &device->volt->subdev);
2058#undef _
2059 default:
2060 engine = nvkm_device_engine(device, index);
2061 if (engine)
2062 return &engine->subdev;
2063 break;
2064 }
2065 return NULL;
2066}
2067
2068struct nvkm_engine *
2069nvkm_device_engine(struct nvkm_device *device, int index)
2070{
2071 if (device->disable_mask & (1ULL << index))
2072 return NULL;
2073
2074 switch (index) {
2075#define _(n,p,m) case NVDEV_ENGINE_##n: if (p) return (m); break
2076 _(BSP , device->bsp , device->bsp);
2077 _(CE0 , device->ce[0] , device->ce[0]);
2078 _(CE1 , device->ce[1] , device->ce[1]);
2079 _(CE2 , device->ce[2] , device->ce[2]);
2080 _(CIPHER , device->cipher , device->cipher);
2081 _(DISP , device->disp , &device->disp->engine);
2082 _(DMAOBJ , device->dma , &device->dma->engine);
2083 _(FIFO , device->fifo , &device->fifo->engine);
2084 _(GR , device->gr , &device->gr->engine);
2085 _(IFB , device->ifb , device->ifb);
2086 _(ME , device->me , device->me);
2087 _(MPEG , device->mpeg , device->mpeg);
2088 _(MSENC , device->msenc , device->msenc);
2089 _(MSPDEC , device->mspdec , device->mspdec);
2090 _(MSPPP , device->msppp , device->msppp);
2091 _(MSVLD , device->msvld , device->msvld);
2092 _(PM , device->pm , &device->pm->engine);
2093 _(SEC , device->sec , device->sec);
2094 _(SW , device->sw , &device->sw->engine);
2095 _(VIC , device->vic , device->vic);
2096 _(VP , device->vp , device->vp);
2097#undef _
2098 default:
2099 WARN_ON(1);
2100 break;
2101 }
2102 return NULL;
2103}
2104
119int 2105int
120nvkm_device_fini(struct nvkm_device *device, bool suspend) 2106nvkm_device_fini(struct nvkm_device *device, bool suspend)
121{ 2107{
122 struct nvkm_object *subdev; 2108 const char *action = suspend ? "suspend" : "fini";
2109 struct nvkm_subdev *subdev;
123 int ret, i; 2110 int ret, i;
2111 s64 time;
2112
2113 nvdev_trace(device, "%s running...\n", action);
2114 time = ktime_to_us(ktime_get());
2115
2116 nvkm_acpi_fini(device);
124 2117
125 for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) { 2118 for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) {
126 if ((subdev = device->subdev[i])) { 2119 if ((subdev = nvkm_device_subdev(device, i))) {
127 if (!nv_iclass(subdev, NV_ENGINE_CLASS)) { 2120 ret = nvkm_subdev_fini(subdev, suspend);
128 ret = nvkm_object_dec(subdev, suspend); 2121 if (ret && suspend)
129 if (ret && suspend) 2122 goto fail;
130 goto fail;
131 }
132 } 2123 }
133 } 2124 }
134 2125
135 ret = nvkm_acpi_fini(device, suspend);
136 2126
137 if (device->func->fini) 2127 if (device->func->fini)
138 device->func->fini(device, suspend); 2128 device->func->fini(device, suspend);
2129
2130 time = ktime_to_us(ktime_get()) - time;
2131 nvdev_trace(device, "%s completed in %lldus...\n", action, time);
2132 return 0;
2133
139fail: 2134fail:
140 for (; ret && i < NVDEV_SUBDEV_NR; i++) { 2135 do {
141 if ((subdev = device->subdev[i])) { 2136 if ((subdev = nvkm_device_subdev(device, i))) {
142 if (!nv_iclass(subdev, NV_ENGINE_CLASS)) { 2137 int rret = nvkm_subdev_init(subdev);
143 ret = nvkm_object_inc(subdev); 2138 if (rret)
144 if (ret) { 2139 nvkm_fatal(subdev, "failed restart, %d\n", ret);
145 /* XXX */
146 }
147 }
148 } 2140 }
149 } 2141 } while (++i < NVDEV_SUBDEV_NR);
150 2142
2143 nvdev_trace(device, "%s failed with %d\n", action, ret);
151 return ret; 2144 return ret;
152} 2145}
153 2146
154int 2147static int
155nvkm_device_preinit(struct nvkm_device *device) 2148nvkm_device_preinit(struct nvkm_device *device)
156{ 2149{
157 int ret; 2150 struct nvkm_subdev *subdev;
2151 int ret, i;
158 s64 time; 2152 s64 time;
159 2153
160 nvdev_trace(device, "preinit running...\n"); 2154 nvdev_trace(device, "preinit running...\n");
@@ -166,6 +2160,16 @@ nvkm_device_preinit(struct nvkm_device *device)
166 goto fail; 2160 goto fail;
167 } 2161 }
168 2162
2163 for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
2164 if ((subdev = nvkm_device_subdev(device, i))) {
2165 ret = nvkm_subdev_preinit(subdev);
2166 if (ret)
2167 goto fail;
2168 }
2169 }
2170
2171 /*XXX: devinit */
2172
169 time = ktime_to_us(ktime_get()) - time; 2173 time = ktime_to_us(ktime_get()) - time;
170 nvdev_trace(device, "preinit completed in %lldus\n", time); 2174 nvdev_trace(device, "preinit completed in %lldus\n", time);
171 return 0; 2175 return 0;
@@ -178,19 +2182,21 @@ fail:
178int 2182int
179nvkm_device_init(struct nvkm_device *device) 2183nvkm_device_init(struct nvkm_device *device)
180{ 2184{
181 struct nvkm_object *subdev; 2185 struct nvkm_subdev *subdev;
182 int ret, i = 0, c; 2186 int ret, i = 0, c;
2187 s64 time;
183 2188
184 ret = nvkm_device_preinit(device); 2189 ret = nvkm_device_preinit(device);
185 if (ret) 2190 if (ret)
186 return ret; 2191 return ret;
187 2192
188 ret = nvkm_acpi_init(device); 2193 nvkm_device_fini(device, false);
189 if (ret) 2194
190 goto fail; 2195 nvdev_trace(device, "init running...\n");
2196 time = ktime_to_us(ktime_get());
191 2197
192 for (i = 0, c = 0; i < NVDEV_SUBDEV_NR; i++) { 2198 for (i = 0, c = 0; i < NVDEV_SUBDEV_NR; i++) {
193#define _(s,m) case s: if (device->oclass[s] && !device->subdev[s]) { \ 2199#define _(s,m) case s: if (device->oclass[s] && !device->m) { \
194 ret = nvkm_object_old(nv_object(device), NULL, \ 2200 ret = nvkm_object_old(nv_object(device), NULL, \
195 device->oclass[s], NULL, (s), \ 2201 device->oclass[s], NULL, (s), \
196 (struct nvkm_object **)&device->m); \ 2202 (struct nvkm_object **)&device->m); \
@@ -200,7 +2206,6 @@ nvkm_device_init(struct nvkm_device *device)
200 } \ 2206 } \
201 if (ret) \ 2207 if (ret) \
202 goto fail; \ 2208 goto fail; \
203 device->subdev[s] = (struct nvkm_object *)device->m; \
204} break 2209} break
205 switch (i) { 2210 switch (i) {
206 _(NVDEV_SUBDEV_BAR , bar); 2211 _(NVDEV_SUBDEV_BAR , bar);
@@ -259,29 +2264,27 @@ nvkm_device_init(struct nvkm_device *device)
259 * subdev in turn as they're created. 2264 * subdev in turn as they're created.
260 */ 2265 */
261 while (i >= NVDEV_SUBDEV_DEVINIT_LAST && c <= i) { 2266 while (i >= NVDEV_SUBDEV_DEVINIT_LAST && c <= i) {
262 struct nvkm_object *subdev = device->subdev[c++]; 2267 if ((subdev = nvkm_device_subdev(device, c++))) {
263 if (subdev && !nv_iclass(subdev, NV_ENGINE_CLASS)) { 2268 ret = nvkm_subdev_init(subdev);
264 ret = nvkm_object_inc(subdev);
265 if (ret) 2269 if (ret)
266 goto fail; 2270 goto fail;
267 } else
268 if (subdev) {
269 nvkm_subdev_reset(subdev);
270 } 2271 }
271 } 2272 }
272 } 2273 }
273 2274
274 ret = 0; 2275 nvkm_acpi_init(device);
2276
2277 time = ktime_to_us(ktime_get()) - time;
2278 nvdev_trace(device, "init completed in %lldus\n", time);
2279 return 0;
2280
275fail: 2281fail:
276 for (--i; ret && i >= 0; i--) { 2282 do {
277 if ((subdev = device->subdev[i])) { 2283 if ((subdev = nvkm_device_subdev(device, i)))
278 if (!nv_iclass(subdev, NV_ENGINE_CLASS)) 2284 nvkm_subdev_fini(subdev, false);
279 nvkm_object_dec(subdev, false); 2285 } while (--i >= 0);
280 }
281 }
282 2286
283 if (ret) 2287 nvdev_error(device, "init failed with %d\n", ret);
284 nvkm_acpi_fini(device, false);
285 return ret; 2288 return ret;
286} 2289}
287 2290
@@ -333,8 +2336,12 @@ nvkm_device_del(struct nvkm_device **pdevice)
333 int i; 2336 int i;
334 if (device) { 2337 if (device) {
335 mutex_lock(&nv_devices_mutex); 2338 mutex_lock(&nv_devices_mutex);
336 for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) 2339 device->disable_mask = 0;
337 nvkm_object_ref(NULL, &device->subdev[i]); 2340 for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) {
2341 struct nvkm_subdev *subdev =
2342 nvkm_device_subdev(device, i);
2343 nvkm_subdev_del(&subdev);
2344 }
338 2345
339 nvkm_event_fini(&device->event); 2346 nvkm_event_fini(&device->event);
340 2347
@@ -363,6 +2370,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
363 bool detect, bool mmio, u64 subdev_mask, 2370 bool detect, bool mmio, u64 subdev_mask,
364 struct nvkm_device *device) 2371 struct nvkm_device *device)
365{ 2372{
2373 struct nvkm_subdev *subdev;
366 u64 mmio_base, mmio_size; 2374 u64 mmio_base, mmio_size;
367 u32 boot0, strap; 2375 u32 boot0, strap;
368 void __iomem *map; 2376 void __iomem *map;
@@ -373,13 +2381,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
373 if (nvkm_device_find_locked(handle)) 2381 if (nvkm_device_find_locked(handle))
374 goto done; 2382 goto done;
375 2383
376 ret = nvkm_engine_ctor(&nvkm_device_func, device, 0, 0,
377 true, &device->engine);
378 device->engine.subdev.object.parent = NULL;
379 device->func = func; 2384 device->func = func;
380 if (ret)
381 goto done;
382
383 device->quirk = quirk; 2385 device->quirk = quirk;
384 switch (type) { 2386 switch (type) {
385 case NVKM_BUS_PCI: 2387 case NVKM_BUS_PCI:
@@ -395,9 +2397,14 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
395 device->cfgopt = cfg; 2397 device->cfgopt = cfg;
396 device->dbgopt = dbg; 2398 device->dbgopt = dbg;
397 device->name = name; 2399 device->name = name;
398
399 list_add_tail(&device->head, &nv_devices); 2400 list_add_tail(&device->head, &nv_devices);
400 2401
2402 ret = nvkm_engine_ctor(&nvkm_device_func, device, 0, 0,
2403 true, &device->engine);
2404 device->engine.subdev.object.parent = NULL;
2405 if (ret)
2406 goto done;
2407
401 ret = nvkm_event_init(&nvkm_device_event_func, 1, 1, &device->event); 2408 ret = nvkm_event_init(&nvkm_device_event_func, 1, 1, &device->event);
402 if (ret) 2409 if (ret)
403 goto done; 2410 goto done;
@@ -482,12 +2489,83 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
482 break; 2489 break;
483 } 2490 }
484 2491
485 if (ret) { 2492 switch (!ret * device->chipset) {
2493 case 0x004: device->chip = &nv4_chipset; break;
2494 case 0x005: device->chip = &nv5_chipset; break;
2495 case 0x010: device->chip = &nv10_chipset; break;
2496 case 0x011: device->chip = &nv11_chipset; break;
2497 case 0x015: device->chip = &nv15_chipset; break;
2498 case 0x017: device->chip = &nv17_chipset; break;
2499 case 0x018: device->chip = &nv18_chipset; break;
2500 case 0x01a: device->chip = &nv1a_chipset; break;
2501 case 0x01f: device->chip = &nv1f_chipset; break;
2502 case 0x020: device->chip = &nv20_chipset; break;
2503 case 0x025: device->chip = &nv25_chipset; break;
2504 case 0x028: device->chip = &nv28_chipset; break;
2505 case 0x02a: device->chip = &nv2a_chipset; break;
2506 case 0x030: device->chip = &nv30_chipset; break;
2507 case 0x031: device->chip = &nv31_chipset; break;
2508 case 0x034: device->chip = &nv34_chipset; break;
2509 case 0x035: device->chip = &nv35_chipset; break;
2510 case 0x036: device->chip = &nv36_chipset; break;
2511 case 0x040: device->chip = &nv40_chipset; break;
2512 case 0x041: device->chip = &nv41_chipset; break;
2513 case 0x042: device->chip = &nv42_chipset; break;
2514 case 0x043: device->chip = &nv43_chipset; break;
2515 case 0x044: device->chip = &nv44_chipset; break;
2516 case 0x045: device->chip = &nv45_chipset; break;
2517 case 0x046: device->chip = &nv46_chipset; break;
2518 case 0x047: device->chip = &nv47_chipset; break;
2519 case 0x049: device->chip = &nv49_chipset; break;
2520 case 0x04a: device->chip = &nv4a_chipset; break;
2521 case 0x04b: device->chip = &nv4b_chipset; break;
2522 case 0x04c: device->chip = &nv4c_chipset; break;
2523 case 0x04e: device->chip = &nv4e_chipset; break;
2524 case 0x050: device->chip = &nv50_chipset; break;
2525 case 0x063: device->chip = &nv63_chipset; break;
2526 case 0x067: device->chip = &nv67_chipset; break;
2527 case 0x068: device->chip = &nv68_chipset; break;
2528 case 0x084: device->chip = &nv84_chipset; break;
2529 case 0x086: device->chip = &nv86_chipset; break;
2530 case 0x092: device->chip = &nv92_chipset; break;
2531 case 0x094: device->chip = &nv94_chipset; break;
2532 case 0x096: device->chip = &nv96_chipset; break;
2533 case 0x098: device->chip = &nv98_chipset; break;
2534 case 0x0a0: device->chip = &nva0_chipset; break;
2535 case 0x0a3: device->chip = &nva3_chipset; break;
2536 case 0x0a5: device->chip = &nva5_chipset; break;
2537 case 0x0a8: device->chip = &nva8_chipset; break;
2538 case 0x0aa: device->chip = &nvaa_chipset; break;
2539 case 0x0ac: device->chip = &nvac_chipset; break;
2540 case 0x0af: device->chip = &nvaf_chipset; break;
2541 case 0x0c0: device->chip = &nvc0_chipset; break;
2542 case 0x0c1: device->chip = &nvc1_chipset; break;
2543 case 0x0c3: device->chip = &nvc3_chipset; break;
2544 case 0x0c4: device->chip = &nvc4_chipset; break;
2545 case 0x0c8: device->chip = &nvc8_chipset; break;
2546 case 0x0ce: device->chip = &nvce_chipset; break;
2547 case 0x0cf: device->chip = &nvcf_chipset; break;
2548 case 0x0d7: device->chip = &nvd7_chipset; break;
2549 case 0x0d9: device->chip = &nvd9_chipset; break;
2550 case 0x0e4: device->chip = &nve4_chipset; break;
2551 case 0x0e6: device->chip = &nve6_chipset; break;
2552 case 0x0e7: device->chip = &nve7_chipset; break;
2553 case 0x0ea: device->chip = &nvea_chipset; break;
2554 case 0x0f0: device->chip = &nvf0_chipset; break;
2555 case 0x0f1: device->chip = &nvf1_chipset; break;
2556 case 0x106: device->chip = &nv106_chipset; break;
2557 case 0x108: device->chip = &nv108_chipset; break;
2558 case 0x117: device->chip = &nv117_chipset; break;
2559 case 0x124: device->chip = &nv124_chipset; break;
2560 case 0x126: device->chip = &nv126_chipset; break;
2561 case 0x12b: device->chip = &nv12b_chipset; break;
2562 default:
486 nvdev_error(device, "unknown chipset (%08x)\n", boot0); 2563 nvdev_error(device, "unknown chipset (%08x)\n", boot0);
487 goto done; 2564 goto done;
488 } 2565 }
489 2566
490 nvdev_info(device, "NVIDIA %s (%08x)\n", device->cname, boot0); 2567 nvdev_info(device, "NVIDIA %s (%08x)\n",
2568 device->chip->name, boot0);
491 2569
492 /* determine frequency of timing crystal */ 2570 /* determine frequency of timing crystal */
493 if ( device->card_type <= NV_10 || device->chipset < 0x17 || 2571 if ( device->card_type <= NV_10 || device->chipset < 0x17 ||
@@ -503,10 +2581,13 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
503 case 0x00400040: device->crystal = 25000; break; 2581 case 0x00400040: device->crystal = 25000; break;
504 } 2582 }
505 } else { 2583 } else {
506 device->cname = "NULL"; 2584 device->chip = &null_chipset;
507 device->oclass[NVDEV_SUBDEV_VBIOS] = &nvkm_bios_oclass; 2585 device->oclass[NVDEV_SUBDEV_VBIOS] = &nvkm_bios_oclass;
508 } 2586 }
509 2587
2588 if (!device->name)
2589 device->name = device->chip->name;
2590
510 if (mmio) { 2591 if (mmio) {
511 device->pri = ioremap(mmio_base, mmio_size); 2592 device->pri = ioremap(mmio_base, mmio_size);
512 if (!device->pri) { 2593 if (!device->pri) {
@@ -523,6 +2604,72 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
523 2604
524 atomic_set(&device->engine.subdev.object.usecount, 2); 2605 atomic_set(&device->engine.subdev.object.usecount, 2);
525 mutex_init(&device->mutex); 2606 mutex_init(&device->mutex);
2607
2608 for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
2609#define _(s,m) case s: \
2610 if (device->chip->m && (subdev_mask & (1ULL << (s)))) { \
2611 ret = device->chip->m(device, (s), &device->m); \
2612 if (ret) { \
2613 subdev = nvkm_device_subdev(device, (s)); \
2614 nvkm_subdev_del(&subdev); \
2615 device->m = NULL; \
2616 if (ret != -ENODEV) { \
2617 nvdev_error(device, "%s ctor failed, %d\n", \
2618 nvkm_subdev_name[s], ret); \
2619 goto done; \
2620 } \
2621 } \
2622 } \
2623 break
2624 switch (i) {
2625 _(NVDEV_SUBDEV_BAR , bar);
2626 _(NVDEV_SUBDEV_VBIOS , bios);
2627 _(NVDEV_SUBDEV_BUS , bus);
2628 _(NVDEV_SUBDEV_CLK , clk);
2629 _(NVDEV_SUBDEV_DEVINIT, devinit);
2630 _(NVDEV_SUBDEV_FB , fb);
2631 _(NVDEV_SUBDEV_FUSE , fuse);
2632 _(NVDEV_SUBDEV_GPIO , gpio);
2633 _(NVDEV_SUBDEV_I2C , i2c);
2634 _(NVDEV_SUBDEV_IBUS , ibus);
2635 _(NVDEV_SUBDEV_INSTMEM, imem);
2636 _(NVDEV_SUBDEV_LTC , ltc);
2637 _(NVDEV_SUBDEV_MC , mc);
2638 _(NVDEV_SUBDEV_MMU , mmu);
2639 _(NVDEV_SUBDEV_MXM , mxm);
2640 _(NVDEV_SUBDEV_PMU , pmu);
2641 _(NVDEV_SUBDEV_THERM , therm);
2642 _(NVDEV_SUBDEV_TIMER , timer);
2643 _(NVDEV_SUBDEV_VOLT , volt);
2644 _(NVDEV_ENGINE_BSP , bsp);
2645 _(NVDEV_ENGINE_CE0 , ce[0]);
2646 _(NVDEV_ENGINE_CE1 , ce[1]);
2647 _(NVDEV_ENGINE_CE2 , ce[2]);
2648 _(NVDEV_ENGINE_CIPHER , cipher);
2649 _(NVDEV_ENGINE_DISP , disp);
2650 _(NVDEV_ENGINE_DMAOBJ , dma);
2651 _(NVDEV_ENGINE_FIFO , fifo);
2652 _(NVDEV_ENGINE_GR , gr);
2653 _(NVDEV_ENGINE_IFB , ifb);
2654 _(NVDEV_ENGINE_ME , me);
2655 _(NVDEV_ENGINE_MPEG , mpeg);
2656 _(NVDEV_ENGINE_MSENC , msenc);
2657 _(NVDEV_ENGINE_MSPDEC , mspdec);
2658 _(NVDEV_ENGINE_MSPPP , msppp);
2659 _(NVDEV_ENGINE_MSVLD , msvld);
2660 _(NVDEV_ENGINE_PM , pm);
2661 _(NVDEV_ENGINE_SEC , sec);
2662 _(NVDEV_ENGINE_SW , sw);
2663 _(NVDEV_ENGINE_VIC , vic);
2664 _(NVDEV_ENGINE_VP , vp);
2665 default:
2666 WARN_ON(1);
2667 continue;
2668 }
2669#undef _
2670 }
2671
2672 ret = 0;
526done: 2673done:
527 mutex_unlock(&nv_devices_mutex); 2674 mutex_unlock(&nv_devices_mutex);
528 return ret; 2675 return ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
index d8ddd228491a..cc152e78d0b2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
@@ -23,44 +23,11 @@
23 */ 23 */
24#include "priv.h" 24#include "priv.h"
25 25
26#include <subdev/bios.h>
27#include <subdev/bus.h>
28#include <subdev/gpio.h>
29#include <subdev/i2c.h>
30#include <subdev/fuse.h>
31#include <subdev/clk.h>
32#include <subdev/therm.h>
33#include <subdev/mxm.h>
34#include <subdev/devinit.h>
35#include <subdev/mc.h>
36#include <subdev/timer.h>
37#include <subdev/fb.h>
38#include <subdev/ltc.h>
39#include <subdev/ibus.h>
40#include <subdev/instmem.h>
41#include <subdev/mmu.h>
42#include <subdev/bar.h>
43#include <subdev/pmu.h>
44#include <subdev/volt.h>
45
46#include <engine/dmaobj.h>
47#include <engine/fifo.h>
48#include <engine/sw.h>
49#include <engine/gr.h>
50#include <engine/mspdec.h>
51#include <engine/bsp.h>
52#include <engine/msvld.h>
53#include <engine/msppp.h>
54#include <engine/ce.h>
55#include <engine/disp.h>
56#include <engine/pm.h>
57
58int 26int
59gf100_identify(struct nvkm_device *device) 27gf100_identify(struct nvkm_device *device)
60{ 28{
61 switch (device->chipset) { 29 switch (device->chipset) {
62 case 0xc0: 30 case 0xc0:
63 device->cname = "GF100";
64 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 31 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
65 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; 32 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
66 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; 33 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
@@ -93,7 +60,6 @@ gf100_identify(struct nvkm_device *device)
93 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 60 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
94 break; 61 break;
95 case 0xc4: 62 case 0xc4:
96 device->cname = "GF104";
97 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 63 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
98 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; 64 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
99 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; 65 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
@@ -126,7 +92,6 @@ gf100_identify(struct nvkm_device *device)
126 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 92 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
127 break; 93 break;
128 case 0xc3: 94 case 0xc3:
129 device->cname = "GF106";
130 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 95 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
131 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; 96 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
132 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; 97 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
@@ -158,7 +123,6 @@ gf100_identify(struct nvkm_device *device)
158 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 123 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
159 break; 124 break;
160 case 0xce: 125 case 0xce:
161 device->cname = "GF114";
162 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 126 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
163 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; 127 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
164 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; 128 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
@@ -191,7 +155,6 @@ gf100_identify(struct nvkm_device *device)
191 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 155 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
192 break; 156 break;
193 case 0xcf: 157 case 0xcf:
194 device->cname = "GF116";
195 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 158 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
196 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; 159 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
197 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; 160 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
@@ -223,7 +186,6 @@ gf100_identify(struct nvkm_device *device)
223 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 186 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
224 break; 187 break;
225 case 0xc1: 188 case 0xc1:
226 device->cname = "GF108";
227 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 189 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
228 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; 190 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
229 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; 191 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
@@ -255,7 +217,6 @@ gf100_identify(struct nvkm_device *device)
255 device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass; 217 device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass;
256 break; 218 break;
257 case 0xc8: 219 case 0xc8:
258 device->cname = "GF110";
259 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 220 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
260 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; 221 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
261 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; 222 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
@@ -288,7 +249,6 @@ gf100_identify(struct nvkm_device *device)
288 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 249 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
289 break; 250 break;
290 case 0xd9: 251 case 0xd9:
291 device->cname = "GF119";
292 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 252 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
293 device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass; 253 device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass;
294 device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass; 254 device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass;
@@ -320,7 +280,6 @@ gf100_identify(struct nvkm_device *device)
320 device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass; 280 device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass;
321 break; 281 break;
322 case 0xd7: 282 case 0xd7:
323 device->cname = "GF117";
324 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 283 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
325 device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass; 284 device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass;
326 device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass; 285 device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
index 4e0d30944359..8811a40e8727 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
@@ -23,44 +23,11 @@
23 */ 23 */
24#include "priv.h" 24#include "priv.h"
25 25
26#include <subdev/bios.h>
27#include <subdev/bus.h>
28#include <subdev/gpio.h>
29#include <subdev/i2c.h>
30#include <subdev/fuse.h>
31#include <subdev/clk.h>
32#include <subdev/therm.h>
33#include <subdev/mxm.h>
34#include <subdev/devinit.h>
35#include <subdev/mc.h>
36#include <subdev/timer.h>
37#include <subdev/fb.h>
38#include <subdev/ltc.h>
39#include <subdev/ibus.h>
40#include <subdev/instmem.h>
41#include <subdev/mmu.h>
42#include <subdev/bar.h>
43#include <subdev/pmu.h>
44#include <subdev/volt.h>
45
46#include <engine/dmaobj.h>
47#include <engine/fifo.h>
48#include <engine/sw.h>
49#include <engine/gr.h>
50#include <engine/disp.h>
51#include <engine/ce.h>
52#include <engine/bsp.h>
53#include <engine/msvld.h>
54#include <engine/mspdec.h>
55#include <engine/msppp.h>
56#include <engine/pm.h>
57
58int 26int
59gk104_identify(struct nvkm_device *device) 27gk104_identify(struct nvkm_device *device)
60{ 28{
61 switch (device->chipset) { 29 switch (device->chipset) {
62 case 0xe4: 30 case 0xe4:
63 device->cname = "GK104";
64 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 31 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
65 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; 32 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
66 device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; 33 device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
@@ -94,7 +61,6 @@ gk104_identify(struct nvkm_device *device)
94 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; 61 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
95 break; 62 break;
96 case 0xe7: 63 case 0xe7:
97 device->cname = "GK107";
98 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 64 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
99 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; 65 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
100 device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; 66 device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
@@ -128,7 +94,6 @@ gk104_identify(struct nvkm_device *device)
128 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; 94 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
129 break; 95 break;
130 case 0xe6: 96 case 0xe6:
131 device->cname = "GK106";
132 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 97 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
133 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; 98 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
134 device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; 99 device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
@@ -162,7 +127,6 @@ gk104_identify(struct nvkm_device *device)
162 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; 127 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
163 break; 128 break;
164 case 0xea: 129 case 0xea:
165 device->cname = "GK20A";
166 device->oclass[NVDEV_SUBDEV_CLK ] = &gk20a_clk_oclass; 130 device->oclass[NVDEV_SUBDEV_CLK ] = &gk20a_clk_oclass;
167 device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; 131 device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
168 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; 132 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
@@ -184,7 +148,6 @@ gk104_identify(struct nvkm_device *device)
184 device->oclass[NVDEV_SUBDEV_PMU ] = gk20a_pmu_oclass; 148 device->oclass[NVDEV_SUBDEV_PMU ] = gk20a_pmu_oclass;
185 break; 149 break;
186 case 0xf0: 150 case 0xf0:
187 device->cname = "GK110";
188 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 151 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
189 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; 152 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
190 device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; 153 device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
@@ -218,7 +181,6 @@ gk104_identify(struct nvkm_device *device)
218 device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; 181 device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
219 break; 182 break;
220 case 0xf1: 183 case 0xf1:
221 device->cname = "GK110B";
222 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 184 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
223 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; 185 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
224 device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass; 186 device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass;
@@ -252,7 +214,6 @@ gk104_identify(struct nvkm_device *device)
252 device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; 214 device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
253 break; 215 break;
254 case 0x106: 216 case 0x106:
255 device->cname = "GK208B";
256 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 217 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
257 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; 218 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
258 device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; 219 device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
@@ -285,7 +246,6 @@ gk104_identify(struct nvkm_device *device)
285 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; 246 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
286 break; 247 break;
287 case 0x108: 248 case 0x108:
288 device->cname = "GK208";
289 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 249 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
290 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; 250 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
291 device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; 251 device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index cd979543cdff..41bfec2dd63a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -23,44 +23,11 @@
23 */ 23 */
24#include "priv.h" 24#include "priv.h"
25 25
26#include <subdev/bios.h>
27#include <subdev/bus.h>
28#include <subdev/gpio.h>
29#include <subdev/i2c.h>
30#include <subdev/fuse.h>
31#include <subdev/clk.h>
32#include <subdev/therm.h>
33#include <subdev/mxm.h>
34#include <subdev/devinit.h>
35#include <subdev/mc.h>
36#include <subdev/timer.h>
37#include <subdev/fb.h>
38#include <subdev/ltc.h>
39#include <subdev/ibus.h>
40#include <subdev/instmem.h>
41#include <subdev/mmu.h>
42#include <subdev/bar.h>
43#include <subdev/pmu.h>
44#include <subdev/volt.h>
45
46#include <engine/dmaobj.h>
47#include <engine/fifo.h>
48#include <engine/sw.h>
49#include <engine/gr.h>
50#include <engine/disp.h>
51#include <engine/ce.h>
52#include <engine/bsp.h>
53#include <engine/msvld.h>
54#include <engine/mspdec.h>
55#include <engine/msppp.h>
56#include <engine/pm.h>
57
58int 26int
59gm100_identify(struct nvkm_device *device) 27gm100_identify(struct nvkm_device *device)
60{ 28{
61 switch (device->chipset) { 29 switch (device->chipset) {
62 case 0x117: 30 case 0x117:
63 device->cname = "GM107";
64 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 31 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
65 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; 32 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
66 device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass; 33 device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass;
@@ -100,7 +67,6 @@ gm100_identify(struct nvkm_device *device)
100#endif 67#endif
101 break; 68 break;
102 case 0x124: 69 case 0x124:
103 device->cname = "GM204";
104 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 70 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
105 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; 71 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
106 device->oclass[NVDEV_SUBDEV_I2C ] = gm204_i2c_oclass; 72 device->oclass[NVDEV_SUBDEV_I2C ] = gm204_i2c_oclass;
@@ -141,7 +107,6 @@ gm100_identify(struct nvkm_device *device)
141#endif 107#endif
142 break; 108 break;
143 case 0x126: 109 case 0x126:
144 device->cname = "GM206";
145 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 110 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
146 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; 111 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
147 device->oclass[NVDEV_SUBDEV_I2C ] = gm204_i2c_oclass; 112 device->oclass[NVDEV_SUBDEV_I2C ] = gm204_i2c_oclass;
@@ -182,7 +147,6 @@ gm100_identify(struct nvkm_device *device)
182#endif 147#endif
183 break; 148 break;
184 case 0x12b: 149 case 0x12b:
185 device->cname = "GM20B";
186 150
187 device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; 151 device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
188 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; 152 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
index ec357da766e5..5245b78794f9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
@@ -23,29 +23,11 @@
23 */ 23 */
24#include "priv.h" 24#include "priv.h"
25 25
26#include <subdev/bios.h>
27#include <subdev/bus.h>
28#include <subdev/i2c.h>
29#include <subdev/clk.h>
30#include <subdev/devinit.h>
31#include <subdev/mc.h>
32#include <subdev/timer.h>
33#include <subdev/fb.h>
34#include <subdev/instmem.h>
35#include <subdev/mmu.h>
36
37#include <engine/dmaobj.h>
38#include <engine/fifo.h>
39#include <engine/sw.h>
40#include <engine/gr.h>
41#include <engine/disp.h>
42
43int 26int
44nv04_identify(struct nvkm_device *device) 27nv04_identify(struct nvkm_device *device)
45{ 28{
46 switch (device->chipset) { 29 switch (device->chipset) {
47 case 0x04: 30 case 0x04:
48 device->cname = "NV04";
49 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 31 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
50 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 32 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
51 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; 33 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@@ -63,7 +45,6 @@ nv04_identify(struct nvkm_device *device)
63 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 45 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
64 break; 46 break;
65 case 0x05: 47 case 0x05:
66 device->cname = "NV05";
67 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 48 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
68 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 49 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
69 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; 50 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
index 37997e848d29..3794c53cfbda 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
@@ -23,30 +23,11 @@
23 */ 23 */
24#include "priv.h" 24#include "priv.h"
25 25
26#include <subdev/bios.h>
27#include <subdev/bus.h>
28#include <subdev/gpio.h>
29#include <subdev/i2c.h>
30#include <subdev/clk.h>
31#include <subdev/devinit.h>
32#include <subdev/mc.h>
33#include <subdev/timer.h>
34#include <subdev/fb.h>
35#include <subdev/instmem.h>
36#include <subdev/mmu.h>
37
38#include <engine/dmaobj.h>
39#include <engine/fifo.h>
40#include <engine/sw.h>
41#include <engine/gr.h>
42#include <engine/disp.h>
43
44int 26int
45nv10_identify(struct nvkm_device *device) 27nv10_identify(struct nvkm_device *device)
46{ 28{
47 switch (device->chipset) { 29 switch (device->chipset) {
48 case 0x10: 30 case 0x10:
49 device->cname = "NV10";
50 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 31 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
51 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 32 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
52 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 33 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -63,7 +44,6 @@ nv10_identify(struct nvkm_device *device)
63 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 44 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
64 break; 45 break;
65 case 0x15: 46 case 0x15:
66 device->cname = "NV15";
67 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 47 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
68 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 48 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
69 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 49 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -82,7 +62,6 @@ nv10_identify(struct nvkm_device *device)
82 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 62 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
83 break; 63 break;
84 case 0x16: 64 case 0x16:
85 device->cname = "NV16";
86 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 65 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
87 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 66 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
88 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 67 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -101,7 +80,6 @@ nv10_identify(struct nvkm_device *device)
101 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 80 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
102 break; 81 break;
103 case 0x1a: 82 case 0x1a:
104 device->cname = "nForce";
105 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 83 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
106 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 84 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
107 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 85 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -120,7 +98,6 @@ nv10_identify(struct nvkm_device *device)
120 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 98 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
121 break; 99 break;
122 case 0x11: 100 case 0x11:
123 device->cname = "NV11";
124 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 101 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
125 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 102 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
126 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 103 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -139,7 +116,6 @@ nv10_identify(struct nvkm_device *device)
139 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 116 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
140 break; 117 break;
141 case 0x17: 118 case 0x17:
142 device->cname = "NV17";
143 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 119 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
144 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 120 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
145 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 121 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -158,7 +134,6 @@ nv10_identify(struct nvkm_device *device)
158 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 134 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
159 break; 135 break;
160 case 0x1f: 136 case 0x1f:
161 device->cname = "nForce2";
162 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 137 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
163 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 138 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
164 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 139 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -177,7 +152,6 @@ nv10_identify(struct nvkm_device *device)
177 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 152 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
178 break; 153 break;
179 case 0x18: 154 case 0x18:
180 device->cname = "NV18";
181 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 155 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
182 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 156 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
183 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 157 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
index a0d414dcc1fd..9acdadeea0ca 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
@@ -23,31 +23,11 @@
23 */ 23 */
24#include "priv.h" 24#include "priv.h"
25 25
26#include <subdev/bios.h>
27#include <subdev/bus.h>
28#include <subdev/gpio.h>
29#include <subdev/i2c.h>
30#include <subdev/clk.h>
31#include <subdev/therm.h>
32#include <subdev/devinit.h>
33#include <subdev/mc.h>
34#include <subdev/timer.h>
35#include <subdev/fb.h>
36#include <subdev/instmem.h>
37#include <subdev/mmu.h>
38
39#include <engine/dmaobj.h>
40#include <engine/fifo.h>
41#include <engine/sw.h>
42#include <engine/gr.h>
43#include <engine/disp.h>
44
45int 26int
46nv20_identify(struct nvkm_device *device) 27nv20_identify(struct nvkm_device *device)
47{ 28{
48 switch (device->chipset) { 29 switch (device->chipset) {
49 case 0x20: 30 case 0x20:
50 device->cname = "NV20";
51 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 31 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
52 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 32 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
53 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 33 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -66,7 +46,6 @@ nv20_identify(struct nvkm_device *device)
66 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 46 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
67 break; 47 break;
68 case 0x25: 48 case 0x25:
69 device->cname = "NV25";
70 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 49 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
71 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 50 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
72 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 51 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -85,7 +64,6 @@ nv20_identify(struct nvkm_device *device)
85 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 64 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
86 break; 65 break;
87 case 0x28: 66 case 0x28:
88 device->cname = "NV28";
89 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 67 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
90 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 68 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
91 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 69 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -104,7 +82,6 @@ nv20_identify(struct nvkm_device *device)
104 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 82 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
105 break; 83 break;
106 case 0x2a: 84 case 0x2a:
107 device->cname = "NV2A";
108 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 85 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
109 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 86 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
110 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 87 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
index ea1739739e5f..3d687d760601 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
@@ -23,31 +23,11 @@
23 */ 23 */
24#include "priv.h" 24#include "priv.h"
25 25
26#include <subdev/bios.h>
27#include <subdev/bus.h>
28#include <subdev/gpio.h>
29#include <subdev/i2c.h>
30#include <subdev/clk.h>
31#include <subdev/devinit.h>
32#include <subdev/mc.h>
33#include <subdev/timer.h>
34#include <subdev/fb.h>
35#include <subdev/instmem.h>
36#include <subdev/mmu.h>
37
38#include <engine/dmaobj.h>
39#include <engine/fifo.h>
40#include <engine/sw.h>
41#include <engine/gr.h>
42#include <engine/mpeg.h>
43#include <engine/disp.h>
44
45int 26int
46nv30_identify(struct nvkm_device *device) 27nv30_identify(struct nvkm_device *device)
47{ 28{
48 switch (device->chipset) { 29 switch (device->chipset) {
49 case 0x30: 30 case 0x30:
50 device->cname = "NV30";
51 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 31 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
52 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 32 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
53 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 33 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -66,7 +46,6 @@ nv30_identify(struct nvkm_device *device)
66 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 46 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
67 break; 47 break;
68 case 0x35: 48 case 0x35:
69 device->cname = "NV35";
70 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 49 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
71 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 50 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
72 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 51 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -85,7 +64,6 @@ nv30_identify(struct nvkm_device *device)
85 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 64 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
86 break; 65 break;
87 case 0x31: 66 case 0x31:
88 device->cname = "NV31";
89 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 67 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
90 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 68 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
91 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 69 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -105,7 +83,6 @@ nv30_identify(struct nvkm_device *device)
105 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 83 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
106 break; 84 break;
107 case 0x36: 85 case 0x36:
108 device->cname = "NV36";
109 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 86 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
110 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 87 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
111 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 88 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -125,7 +102,6 @@ nv30_identify(struct nvkm_device *device)
125 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 102 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
126 break; 103 break;
127 case 0x34: 104 case 0x34:
128 device->cname = "NV34";
129 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 105 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
130 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 106 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
131 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 107 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
index 9c7aa8d0ebd4..35fb2f92d171 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
@@ -23,35 +23,11 @@
23 */ 23 */
24#include "priv.h" 24#include "priv.h"
25 25
26#include <subdev/bios.h>
27#include <subdev/bus.h>
28#include <subdev/mmu.h>
29#include <subdev/gpio.h>
30#include <subdev/i2c.h>
31#include <subdev/clk.h>
32#include <subdev/therm.h>
33#include <subdev/devinit.h>
34#include <subdev/mc.h>
35#include <subdev/timer.h>
36#include <subdev/fb.h>
37#include <subdev/instmem.h>
38#include <subdev/mmu.h>
39#include <subdev/volt.h>
40
41#include <engine/dmaobj.h>
42#include <engine/fifo.h>
43#include <engine/sw.h>
44#include <engine/gr.h>
45#include <engine/mpeg.h>
46#include <engine/disp.h>
47#include <engine/pm.h>
48
49int 26int
50nv40_identify(struct nvkm_device *device) 27nv40_identify(struct nvkm_device *device)
51{ 28{
52 switch (device->chipset) { 29 switch (device->chipset) {
53 case 0x40: 30 case 0x40:
54 device->cname = "NV40";
55 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 31 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
56 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 32 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
57 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 33 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -74,7 +50,6 @@ nv40_identify(struct nvkm_device *device)
74 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 50 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
75 break; 51 break;
76 case 0x41: 52 case 0x41:
77 device->cname = "NV41";
78 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 53 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
79 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 54 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
80 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 55 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -97,7 +72,6 @@ nv40_identify(struct nvkm_device *device)
97 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 72 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
98 break; 73 break;
99 case 0x42: 74 case 0x42:
100 device->cname = "NV42";
101 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 75 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
102 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 76 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
103 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 77 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -120,7 +94,6 @@ nv40_identify(struct nvkm_device *device)
120 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 94 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
121 break; 95 break;
122 case 0x43: 96 case 0x43:
123 device->cname = "NV43";
124 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 97 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
125 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 98 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
126 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 99 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -143,7 +116,6 @@ nv40_identify(struct nvkm_device *device)
143 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 116 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
144 break; 117 break;
145 case 0x45: 118 case 0x45:
146 device->cname = "NV45";
147 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 119 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
148 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 120 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
149 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 121 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -166,7 +138,6 @@ nv40_identify(struct nvkm_device *device)
166 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 138 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
167 break; 139 break;
168 case 0x47: 140 case 0x47:
169 device->cname = "G70";
170 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 141 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
171 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 142 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
172 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 143 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -189,7 +160,6 @@ nv40_identify(struct nvkm_device *device)
189 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 160 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
190 break; 161 break;
191 case 0x49: 162 case 0x49:
192 device->cname = "G71";
193 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 163 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
194 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 164 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
195 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 165 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -212,7 +182,6 @@ nv40_identify(struct nvkm_device *device)
212 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 182 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
213 break; 183 break;
214 case 0x4b: 184 case 0x4b:
215 device->cname = "G73";
216 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 185 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
217 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 186 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
218 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 187 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -235,7 +204,6 @@ nv40_identify(struct nvkm_device *device)
235 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 204 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
236 break; 205 break;
237 case 0x44: 206 case 0x44:
238 device->cname = "NV44";
239 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 207 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
240 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 208 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
241 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 209 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -258,7 +226,6 @@ nv40_identify(struct nvkm_device *device)
258 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 226 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
259 break; 227 break;
260 case 0x46: 228 case 0x46:
261 device->cname = "G72";
262 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 229 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
263 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 230 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
264 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 231 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -281,7 +248,6 @@ nv40_identify(struct nvkm_device *device)
281 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 248 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
282 break; 249 break;
283 case 0x4a: 250 case 0x4a:
284 device->cname = "NV44A";
285 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 251 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
286 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 252 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
287 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 253 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -304,7 +270,6 @@ nv40_identify(struct nvkm_device *device)
304 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 270 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
305 break; 271 break;
306 case 0x4c: 272 case 0x4c:
307 device->cname = "C61";
308 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 273 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
309 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 274 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
310 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 275 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -327,7 +292,6 @@ nv40_identify(struct nvkm_device *device)
327 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 292 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
328 break; 293 break;
329 case 0x4e: 294 case 0x4e:
330 device->cname = "C51";
331 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 295 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
332 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 296 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
333 device->oclass[NVDEV_SUBDEV_I2C ] = nv4e_i2c_oclass; 297 device->oclass[NVDEV_SUBDEV_I2C ] = nv4e_i2c_oclass;
@@ -350,7 +314,6 @@ nv40_identify(struct nvkm_device *device)
350 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 314 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
351 break; 315 break;
352 case 0x63: 316 case 0x63:
353 device->cname = "C73";
354 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 317 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
355 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 318 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
356 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 319 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -373,7 +336,6 @@ nv40_identify(struct nvkm_device *device)
373 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 336 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
374 break; 337 break;
375 case 0x67: 338 case 0x67:
376 device->cname = "C67";
377 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 339 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
378 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 340 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
379 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 341 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
@@ -396,7 +358,6 @@ nv40_identify(struct nvkm_device *device)
396 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 358 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
397 break; 359 break;
398 case 0x68: 360 case 0x68:
399 device->cname = "C68";
400 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 361 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
401 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 362 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
402 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 363 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 3c97dba02fc4..56a443a1c74e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -23,46 +23,11 @@
23 */ 23 */
24#include "priv.h" 24#include "priv.h"
25 25
26#include <subdev/bios.h>
27#include <subdev/bus.h>
28#include <subdev/gpio.h>
29#include <subdev/i2c.h>
30#include <subdev/fuse.h>
31#include <subdev/clk.h>
32#include <subdev/therm.h>
33#include <subdev/mxm.h>
34#include <subdev/devinit.h>
35#include <subdev/mc.h>
36#include <subdev/timer.h>
37#include <subdev/fb.h>
38#include <subdev/instmem.h>
39#include <subdev/mmu.h>
40#include <subdev/bar.h>
41#include <subdev/pmu.h>
42#include <subdev/volt.h>
43
44#include <engine/dmaobj.h>
45#include <engine/fifo.h>
46#include <engine/sw.h>
47#include <engine/gr.h>
48#include <engine/mpeg.h>
49#include <engine/vp.h>
50#include <engine/cipher.h>
51#include <engine/sec.h>
52#include <engine/bsp.h>
53#include <engine/msvld.h>
54#include <engine/mspdec.h>
55#include <engine/msppp.h>
56#include <engine/ce.h>
57#include <engine/disp.h>
58#include <engine/pm.h>
59
60int 26int
61nv50_identify(struct nvkm_device *device) 27nv50_identify(struct nvkm_device *device)
62{ 28{
63 switch (device->chipset) { 29 switch (device->chipset) {
64 case 0x50: 30 case 0x50:
65 device->cname = "G80";
66 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 31 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
67 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; 32 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
68 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; 33 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
@@ -88,7 +53,6 @@ nv50_identify(struct nvkm_device *device)
88 device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass; 53 device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass;
89 break; 54 break;
90 case 0x84: 55 case 0x84:
91 device->cname = "G84";
92 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 56 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
93 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; 57 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
94 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; 58 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
@@ -117,7 +81,6 @@ nv50_identify(struct nvkm_device *device)
117 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 81 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
118 break; 82 break;
119 case 0x86: 83 case 0x86:
120 device->cname = "G86";
121 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 84 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
122 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; 85 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
123 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; 86 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
@@ -146,7 +109,6 @@ nv50_identify(struct nvkm_device *device)
146 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 109 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
147 break; 110 break;
148 case 0x92: 111 case 0x92:
149 device->cname = "G92";
150 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 112 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
151 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; 113 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
152 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; 114 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
@@ -175,7 +137,6 @@ nv50_identify(struct nvkm_device *device)
175 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 137 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
176 break; 138 break;
177 case 0x94: 139 case 0x94:
178 device->cname = "G94";
179 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 140 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
180 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; 141 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
181 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; 142 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
@@ -204,7 +165,6 @@ nv50_identify(struct nvkm_device *device)
204 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 165 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
205 break; 166 break;
206 case 0x96: 167 case 0x96:
207 device->cname = "G96";
208 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 168 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
209 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; 169 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
210 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; 170 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
@@ -233,7 +193,6 @@ nv50_identify(struct nvkm_device *device)
233 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 193 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
234 break; 194 break;
235 case 0x98: 195 case 0x98:
236 device->cname = "G98";
237 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 196 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
238 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; 197 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
239 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; 198 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
@@ -262,7 +221,6 @@ nv50_identify(struct nvkm_device *device)
262 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 221 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
263 break; 222 break;
264 case 0xa0: 223 case 0xa0:
265 device->cname = "G200";
266 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 224 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
267 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; 225 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
268 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; 226 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
@@ -291,7 +249,6 @@ nv50_identify(struct nvkm_device *device)
291 device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass; 249 device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass;
292 break; 250 break;
293 case 0xaa: 251 case 0xaa:
294 device->cname = "MCP77/MCP78";
295 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 252 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
296 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; 253 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
297 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; 254 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
@@ -320,7 +277,6 @@ nv50_identify(struct nvkm_device *device)
320 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 277 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
321 break; 278 break;
322 case 0xac: 279 case 0xac:
323 device->cname = "MCP79/MCP7A";
324 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 280 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
325 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; 281 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
326 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; 282 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
@@ -349,7 +305,6 @@ nv50_identify(struct nvkm_device *device)
349 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 305 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
350 break; 306 break;
351 case 0xa3: 307 case 0xa3:
352 device->cname = "GT215";
353 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 308 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
354 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; 309 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
355 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; 310 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
@@ -380,7 +335,6 @@ nv50_identify(struct nvkm_device *device)
380 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; 335 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
381 break; 336 break;
382 case 0xa5: 337 case 0xa5:
383 device->cname = "GT216";
384 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 338 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
385 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; 339 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
386 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; 340 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
@@ -410,7 +364,6 @@ nv50_identify(struct nvkm_device *device)
410 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; 364 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
411 break; 365 break;
412 case 0xa8: 366 case 0xa8:
413 device->cname = "GT218";
414 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 367 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
415 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; 368 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
416 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; 369 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
@@ -440,7 +393,6 @@ nv50_identify(struct nvkm_device *device)
440 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; 393 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
441 break; 394 break;
442 case 0xaf: 395 case 0xaf:
443 device->cname = "MCP89";
444 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 396 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
445 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; 397 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
446 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; 398 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h
index df9c1550301f..59e902662408 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h
@@ -2,6 +2,42 @@
2#define __NVKM_DEVICE_PRIV_H__ 2#define __NVKM_DEVICE_PRIV_H__
3#include <core/device.h> 3#include <core/device.h>
4 4
5#include <subdev/bar.h>
6#include <subdev/bios.h>
7#include <subdev/bus.h>
8#include <subdev/clk.h>
9#include <subdev/devinit.h>
10#include <subdev/fb.h>
11#include <subdev/fuse.h>
12#include <subdev/gpio.h>
13#include <subdev/i2c.h>
14#include <subdev/ibus.h>
15#include <subdev/instmem.h>
16#include <subdev/ltc.h>
17#include <subdev/mc.h>
18#include <subdev/mmu.h>
19#include <subdev/mxm.h>
20#include <subdev/pmu.h>
21#include <subdev/therm.h>
22#include <subdev/timer.h>
23#include <subdev/volt.h>
24
25#include <engine/bsp.h>
26#include <engine/ce.h>
27#include <engine/cipher.h>
28#include <engine/disp.h>
29#include <engine/dmaobj.h>
30#include <engine/fifo.h>
31#include <engine/gr.h>
32#include <engine/mpeg.h>
33#include <engine/mspdec.h>
34#include <engine/msppp.h>
35#include <engine/msvld.h>
36#include <engine/pm.h>
37#include <engine/sec.h>
38#include <engine/sw.h>
39#include <engine/vp.h>
40
5int nvkm_device_ctor(const struct nvkm_device_func *, 41int nvkm_device_ctor(const struct nvkm_device_func *,
6 const struct nvkm_device_quirk *, 42 const struct nvkm_device_quirk *,
7 void *, enum nv_bus_type type, u64 handle, 43 void *, enum nv_bus_type type, u64 handle,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c
index cb3f3deefb01..0df54c657469 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c
@@ -107,8 +107,8 @@ nvkm_udevice_info(struct nvkm_object *object, void *data, u32 size)
107 if (imem && args->v0.ram_size > 0) 107 if (imem && args->v0.ram_size > 0)
108 args->v0.ram_user = args->v0.ram_user - imem->reserved; 108 args->v0.ram_user = args->v0.ram_user - imem->reserved;
109 109
110 strncpy(args->v0.chip, device->cname, sizeof(args->v0.chip)); 110 strncpy(args->v0.chip, device->chip->name, sizeof(args->v0.chip));
111 strncpy(args->v0.name, device->cname, sizeof(args->v0.name)); 111 strncpy(args->v0.name, device->name, sizeof(args->v0.name));
112 return 0; 112 return 0;
113} 113}
114 114
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
index 52f6a6e49216..ac39cb7e7299 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
@@ -138,7 +138,7 @@ _nvkm_falcon_init(struct nvkm_object *object)
138 ret = request_firmware(&fw, name, nv_device_base(device)); 138 ret = request_firmware(&fw, name, nv_device_base(device));
139 if (ret) { 139 if (ret) {
140 nvkm_error(subdev, "unable to load firmware data\n"); 140 nvkm_error(subdev, "unable to load firmware data\n");
141 return ret; 141 return -ENODEV;
142 } 142 }
143 143
144 falcon->data.data = vmemdup(fw->data, fw->size); 144 falcon->data.data = vmemdup(fw->data, fw->size);
@@ -153,7 +153,7 @@ _nvkm_falcon_init(struct nvkm_object *object)
153 ret = request_firmware(&fw, name, nv_device_base(device)); 153 ret = request_firmware(&fw, name, nv_device_base(device));
154 if (ret) { 154 if (ret) {
155 nvkm_error(subdev, "unable to load firmware code\n"); 155 nvkm_error(subdev, "unable to load firmware code\n");
156 return ret; 156 return -ENODEV;
157 } 157 }
158 158
159 falcon->code.data = vmemdup(fw->data, fw->size); 159 falcon->code.data = vmemdup(fw->data, fw->size);
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
index 975a2547b8cd..ba6b390a1fef 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
@@ -435,7 +435,7 @@ gf100_fifo_recover_work(struct work_struct *work)
435{ 435{
436 struct gf100_fifo *fifo = container_of(work, typeof(*fifo), fault); 436 struct gf100_fifo *fifo = container_of(work, typeof(*fifo), fault);
437 struct nvkm_device *device = fifo->base.engine.subdev.device; 437 struct nvkm_device *device = fifo->base.engine.subdev.device;
438 struct nvkm_object *engine; 438 struct nvkm_engine *engine;
439 unsigned long flags; 439 unsigned long flags;
440 u32 engn, engm = 0; 440 u32 engn, engm = 0;
441 u64 mask, todo; 441 u64 mask, todo;
@@ -450,9 +450,9 @@ gf100_fifo_recover_work(struct work_struct *work)
450 nvkm_mask(device, 0x002630, engm, engm); 450 nvkm_mask(device, 0x002630, engm, engm);
451 451
452 for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) { 452 for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) {
453 if ((engine = (void *)nvkm_engine(fifo, engn))) { 453 if ((engine = nvkm_device_engine(device, engn))) {
454 nvkm_object_fini(engine, false); 454 nvkm_subdev_fini(&engine->subdev, false);
455 WARN_ON(nvkm_object_init(engine)); 455 WARN_ON(nvkm_subdev_init(&engine->subdev));
456 } 456 }
457 } 457 }
458 458
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
index 216205cdf115..62b3de4e9353 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
@@ -481,7 +481,7 @@ gk104_fifo_recover_work(struct work_struct *work)
481{ 481{
482 struct gk104_fifo *fifo = container_of(work, typeof(*fifo), fault); 482 struct gk104_fifo *fifo = container_of(work, typeof(*fifo), fault);
483 struct nvkm_device *device = fifo->base.engine.subdev.device; 483 struct nvkm_device *device = fifo->base.engine.subdev.device;
484 struct nvkm_object *engine; 484 struct nvkm_engine *engine;
485 unsigned long flags; 485 unsigned long flags;
486 u32 engn, engm = 0; 486 u32 engn, engm = 0;
487 u64 mask, todo; 487 u64 mask, todo;
@@ -496,9 +496,9 @@ gk104_fifo_recover_work(struct work_struct *work)
496 nvkm_mask(device, 0x002630, engm, engm); 496 nvkm_mask(device, 0x002630, engm, engm);
497 497
498 for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) { 498 for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) {
499 if ((engine = (void *)nvkm_engine(fifo, engn))) { 499 if ((engine = nvkm_device_engine(device, engn))) {
500 nvkm_object_fini(engine, false); 500 nvkm_subdev_fini(&engine->subdev, false);
501 WARN_ON(nvkm_object_init(engine)); 501 WARN_ON(nvkm_subdev_init(&engine->subdev));
502 } 502 }
503 gk104_fifo_runlist_update(fifo, gk104_fifo_engidx(fifo, engn)); 503 gk104_fifo_runlist_update(fifo, gk104_fifo_engidx(fifo, engn));
504 } 504 }
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
index 6afdb20cf304..1e712355a70b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
@@ -1601,7 +1601,7 @@ gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname,
1601 int i; 1601 int i;
1602 1602
1603 /* Convert device name to lowercase */ 1603 /* Convert device name to lowercase */
1604 strncpy(cname, device->cname, sizeof(cname)); 1604 strncpy(cname, device->chip->name, sizeof(cname));
1605 cname[sizeof(cname) - 1] = '\0'; 1605 cname[sizeof(cname) - 1] = '\0';
1606 i = strlen(cname); 1606 i = strlen(cname);
1607 while (i) { 1607 while (i) {
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c
index a441fd3b69bc..b3ae0d96ddb0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c
@@ -638,8 +638,8 @@ nvkm_perfctx_dtor(struct nvkm_object *object)
638 struct nvkm_pm *pm = (void *)object->engine; 638 struct nvkm_pm *pm = (void *)object->engine;
639 struct nvkm_perfctx *ctx = (void *)object; 639 struct nvkm_perfctx *ctx = (void *)object;
640 640
641 mutex_lock(&nv_subdev(pm)->mutex);
642 nvkm_gpuobj_destroy(&ctx->base); 641 nvkm_gpuobj_destroy(&ctx->base);
642 mutex_lock(&nv_subdev(pm)->mutex);
643 if (pm->context == ctx) 643 if (pm->context == ctx)
644 pm->context = NULL; 644 pm->context = NULL;
645 mutex_unlock(&nv_subdev(pm)->mutex); 645 mutex_unlock(&nv_subdev(pm)->mutex);
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c
index 3b57f50db4de..ab6aecf29f4b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c
@@ -40,8 +40,8 @@ nv04_bus_intr(struct nvkm_subdev *subdev)
40 40
41 if (stat & 0x00000110) { 41 if (stat & 0x00000110) {
42 struct nvkm_gpio *gpio = device->gpio; 42 struct nvkm_gpio *gpio = device->gpio;
43 if (gpio && gpio->subdev.intr) 43 if (gpio)
44 gpio->subdev.intr(&gpio->subdev); 44 nvkm_subdev_intr(&gpio->subdev);
45 stat &= ~0x00000110; 45 stat &= ~0x00000110;
46 nvkm_wr32(device, 0x001100, 0x00000110); 46 nvkm_wr32(device, 0x001100, 0x00000110);
47 } 47 }
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c
index e99d7a20f90e..2e5340a2c94d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c
@@ -36,8 +36,8 @@ nv31_bus_intr(struct nvkm_subdev *subdev)
36 36
37 if (gpio) { 37 if (gpio) {
38 struct nvkm_gpio *gpio = device->gpio; 38 struct nvkm_gpio *gpio = device->gpio;
39 if (gpio && gpio->subdev.intr) 39 if (gpio)
40 gpio->subdev.intr(&gpio->subdev); 40 nvkm_subdev_intr(&gpio->subdev);
41 } 41 }
42 42
43 if (stat & 0x00000008) { /* NV41- */ 43 if (stat & 0x00000008) { /* NV41- */
@@ -54,8 +54,8 @@ nv31_bus_intr(struct nvkm_subdev *subdev)
54 54
55 if (stat & 0x00070000) { 55 if (stat & 0x00070000) {
56 struct nvkm_therm *therm = device->therm; 56 struct nvkm_therm *therm = device->therm;
57 if (therm && therm->subdev.intr) 57 if (therm)
58 therm->subdev.intr(&therm->subdev); 58 nvkm_subdev_intr(&therm->subdev);
59 stat &= ~0x00070000; 59 stat &= ~0x00070000;
60 nvkm_wr32(device, 0x001100, 0x00070000); 60 nvkm_wr32(device, 0x001100, 0x00070000);
61 } 61 }
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c
index 47d1e436bd44..3948ec73d31a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c
@@ -69,8 +69,8 @@ nv50_bus_intr(struct nvkm_subdev *subdev)
69 69
70 if (stat & 0x00010000) { 70 if (stat & 0x00010000) {
71 struct nvkm_therm *therm = device->therm; 71 struct nvkm_therm *therm = device->therm;
72 if (therm && therm->subdev.intr) 72 if (therm)
73 therm->subdev.intr(&therm->subdev); 73 nvkm_subdev_intr(&therm->subdev);
74 stat &= ~0x00010000; 74 stat &= ~0x00010000;
75 nvkm_wr32(device, 0x001100, 0x00010000); 75 nvkm_wr32(device, 0x001100, 0x00010000);
76 } 76 }
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
index f861a02d8d59..ee4c34f4b9c4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
@@ -65,8 +65,8 @@ nvkm_mc_intr(int irq, void *arg)
65 while (map->stat) { 65 while (map->stat) {
66 if (intr & map->stat) { 66 if (intr & map->stat) {
67 unit = nvkm_subdev(mc, map->unit); 67 unit = nvkm_subdev(mc, map->unit);
68 if (unit && unit->intr) 68 if (unit)
69 unit->intr(unit); 69 nvkm_subdev_intr(unit);
70 stat &= ~map->stat; 70 stat &= ~map->stat;
71 } 71 }
72 map++; 72 map++;
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 13:33:14 -0500