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authorBeniamino Galvani <b.galvani@gmail.com>2015-01-17 13:15:14 -0500
committerLinus Walleij <linus.walleij@linaro.org>2015-01-26 03:13:00 -0500
commit6ac730951104a437bf828683bcf9ba66336c4fa7 (patch)
treea83997a2551349a70f57cbe8d611df5867e23143
parent40b9e4fa752cae81e2ca448d8ef252264732a00f (diff)
pinctrl: add driver for Amlogic Meson SoCs
This is a driver for the pinmux and GPIO controller available in Amlogic Meson SoCs. It currently supports only Meson8, however the common code should be generic enough to work also for other SoCs after having defined the proper set of functions and groups. GPIO interrupts are not supported at the moment due to lack of documentation. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat
-rw-r--r--drivers/pinctrl/Kconfig8
-rw-r--r--drivers/pinctrl/Makefile1
-rw-r--r--drivers/pinctrl/meson/Makefile2
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson.c761
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson.h209
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson8.c1089
-rw-r--r--include/dt-bindings/gpio/meson8-gpio.h157
7 files changed, 2227 insertions, 0 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index e738cca15a2c..ee9f44ad7f02 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -96,6 +96,14 @@ config PINCTRL_FALCON
96 depends on SOC_FALCON 96 depends on SOC_FALCON
97 depends on PINCTRL_LANTIQ 97 depends on PINCTRL_LANTIQ
98 98
99config PINCTRL_MESON
100 bool
101 select PINMUX
102 select PINCONF
103 select GENERIC_PINCONF
104 select OF_GPIO
105 select REGMAP_MMIO
106
99config PINCTRL_ROCKCHIP 107config PINCTRL_ROCKCHIP
100 bool 108 bool
101 select PINMUX 109 select PINMUX
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 6c28bd623612..0475206dd600 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
17obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o 17obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
18obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o 18obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
19obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o 19obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
20obj-$(CONFIG_PINCTRL_MESON) += meson/
20obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o 21obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
21obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o 22obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
22obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o 23obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
new file mode 100644
index 000000000000..eafc216067a4
--- /dev/null
+++ b/drivers/pinctrl/meson/Makefile
@@ -0,0 +1,2 @@
1obj-y += pinctrl-meson8.o
2obj-y += pinctrl-meson.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
new file mode 100644
index 000000000000..a2bf49ce16e7
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -0,0 +1,761 @@
1/*
2 * Pin controller and GPIO driver for Amlogic Meson SoCs
3 *
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * You should have received a copy of the GNU General Public License
11 * along with this program. If not, see <http://www.gnu.org/licenses/>.
12 */
13
14/*
15 * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO,
16 * BOOT,CARD for meson6 and X,Y,DV,H,Z,AO,BOOT,CARD for meson8) and
17 * each bank has a variable number of pins.
18 *
19 * The AO bank is special because it belongs to the Always-On power
20 * domain which can't be powered off; the bank also uses a set of
21 * registers different from the other banks.
22 *
23 * For each of the two power domains (regular and always-on) there are
24 * 4 different register ranges that control the following properties
25 * of the pins:
26 * 1) pin muxing
27 * 2) pull enable/disable
28 * 3) pull up/down
29 * 4) GPIO direction, output value, input value
30 *
31 * In some cases the register ranges for pull enable and pull
32 * direction are the same and thus there are only 3 register ranges.
33 *
34 * Every pinmux group can be enabled by a specific bit in the first
35 * register range of the domain; when all groups for a given pin are
36 * disabled the pin acts as a GPIO.
37 *
38 * For the pull and GPIO configuration every bank uses a contiguous
39 * set of bits in the register sets described above; the same register
40 * can be shared by more banks with different offsets.
41 *
42 * In addition to this there are some registers shared between all
43 * banks that control the IRQ functionality. This feature is not
44 * supported at the moment by the driver.
45 */
46
47#include <linux/device.h>
48#include <linux/gpio.h>
49#include <linux/init.h>
50#include <linux/io.h>
51#include <linux/module.h>
52#include <linux/of.h>
53#include <linux/of_address.h>
54#include <linux/pinctrl/pinconf-generic.h>
55#include <linux/pinctrl/pinconf.h>
56#include <linux/pinctrl/pinctrl.h>
57#include <linux/pinctrl/pinmux.h>
58#include <linux/platform_device.h>
59#include <linux/regmap.h>
60#include <linux/seq_file.h>
61
62#include "../core.h"
63#include "../pinctrl-utils.h"
64#include "pinctrl-meson.h"
65
66/**
67 * meson_get_bank() - find the bank containing a given pin
68 *
69 * @domain: the domain containing the pin
70 * @pin: the pin number
71 * @bank: the found bank
72 *
73 * Return: 0 on success, a negative value on error
74 */
75static int meson_get_bank(struct meson_domain *domain, unsigned int pin,
76 struct meson_bank **bank)
77{
78 int i;
79
80 for (i = 0; i < domain->data->num_banks; i++) {
81 if (pin >= domain->data->banks[i].first &&
82 pin <= domain->data->banks[i].last) {
83 *bank = &domain->data->banks[i];
84 return 0;
85 }
86 }
87
88 return -EINVAL;
89}
90
91/**
92 * meson_get_domain_and_bank() - find domain and bank containing a given pin
93 *
94 * @pc: Meson pin controller device
95 * @pin: the pin number
96 * @domain: the found domain
97 * @bank: the found bank
98 *
99 * Return: 0 on success, a negative value on error
100 */
101static int meson_get_domain_and_bank(struct meson_pinctrl *pc, unsigned int pin,
102 struct meson_domain **domain,
103 struct meson_bank **bank)
104{
105 struct meson_domain *d;
106 int i;
107
108 for (i = 0; i < pc->data->num_domains; i++) {
109 d = &pc->domains[i];
110 if (pin >= d->data->pin_base &&
111 pin < d->data->pin_base + d->data->num_pins) {
112 *domain = d;
113 return meson_get_bank(d, pin, bank);
114 }
115 }
116
117 return -EINVAL;
118}
119
120/**
121 * meson_calc_reg_and_bit() - calculate register and bit for a pin
122 *
123 * @bank: the bank containing the pin
124 * @pin: the pin number
125 * @reg_type: the type of register needed (pull-enable, pull, etc...)
126 * @reg: the computed register offset
127 * @bit: the computed bit
128 */
129static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin,
130 enum meson_reg_type reg_type,
131 unsigned int *reg, unsigned int *bit)
132{
133 struct meson_reg_desc *desc = &bank->regs[reg_type];
134
135 *reg = desc->reg * 4;
136 *bit = desc->bit + pin - bank->first;
137}
138
139static int meson_get_groups_count(struct pinctrl_dev *pcdev)
140{
141 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
142
143 return pc->data->num_groups;
144}
145
146static const char *meson_get_group_name(struct pinctrl_dev *pcdev,
147 unsigned selector)
148{
149 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
150
151 return pc->data->groups[selector].name;
152}
153
154static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector,
155 const unsigned **pins, unsigned *num_pins)
156{
157 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
158
159 *pins = pc->data->groups[selector].pins;
160 *num_pins = pc->data->groups[selector].num_pins;
161
162 return 0;
163}
164
165static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s,
166 unsigned offset)
167{
168 seq_printf(s, " %s", dev_name(pcdev->dev));
169}
170
171static const struct pinctrl_ops meson_pctrl_ops = {
172 .get_groups_count = meson_get_groups_count,
173 .get_group_name = meson_get_group_name,
174 .get_group_pins = meson_get_group_pins,
175 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
176 .dt_free_map = pinctrl_utils_dt_free_map,
177 .pin_dbg_show = meson_pin_dbg_show,
178};
179
180/**
181 * meson_pmx_disable_other_groups() - disable other groups using a given pin
182 *
183 * @pc: meson pin controller device
184 * @pin: number of the pin
185 * @sel_group: index of the selected group, or -1 if none
186 *
187 * The function disables all pinmux groups using a pin except the
188 * selected one. If @sel_group is -1 all groups are disabled, leaving
189 * the pin in GPIO mode.
190 */
191static void meson_pmx_disable_other_groups(struct meson_pinctrl *pc,
192 unsigned int pin, int sel_group)
193{
194 struct meson_pmx_group *group;
195 struct meson_domain *domain;
196 int i, j;
197
198 for (i = 0; i < pc->data->num_groups; i++) {
199 group = &pc->data->groups[i];
200 if (group->is_gpio || i == sel_group)
201 continue;
202
203 for (j = 0; j < group->num_pins; j++) {
204 if (group->pins[j] == pin) {
205 /* We have found a group using the pin */
206 domain = &pc->domains[group->domain];
207 regmap_update_bits(domain->reg_mux,
208 group->reg * 4,
209 BIT(group->bit), 0);
210 }
211 }
212 }
213}
214
215static int meson_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num,
216 unsigned group_num)
217{
218 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
219 struct meson_pmx_func *func = &pc->data->funcs[func_num];
220 struct meson_pmx_group *group = &pc->data->groups[group_num];
221 struct meson_domain *domain = &pc->domains[group->domain];
222 int i, ret = 0;
223
224 dev_dbg(pc->dev, "enable function %s, group %s\n", func->name,
225 group->name);
226
227 /*
228 * Disable groups using the same pin.
229 * The selected group is not disabled to avoid glitches.
230 */
231 for (i = 0; i < group->num_pins; i++)
232 meson_pmx_disable_other_groups(pc, group->pins[i], group_num);
233
234 /* Function 0 (GPIO) doesn't need any additional setting */
235 if (func_num)
236 ret = regmap_update_bits(domain->reg_mux, group->reg * 4,
237 BIT(group->bit), BIT(group->bit));
238
239 return ret;
240}
241
242static int meson_pmx_request_gpio(struct pinctrl_dev *pcdev,
243 struct pinctrl_gpio_range *range,
244 unsigned offset)
245{
246 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
247
248 meson_pmx_disable_other_groups(pc, range->pin_base + offset, -1);
249
250 return 0;
251}
252
253static int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev)
254{
255 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
256
257 return pc->data->num_funcs;
258}
259
260static const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev,
261 unsigned selector)
262{
263 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
264
265 return pc->data->funcs[selector].name;
266}
267
268static int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector,
269 const char * const **groups,
270 unsigned * const num_groups)
271{
272 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
273
274 *groups = pc->data->funcs[selector].groups;
275 *num_groups = pc->data->funcs[selector].num_groups;
276
277 return 0;
278}
279
280static const struct pinmux_ops meson_pmx_ops = {
281 .set_mux = meson_pmx_set_mux,
282 .get_functions_count = meson_pmx_get_funcs_count,
283 .get_function_name = meson_pmx_get_func_name,
284 .get_function_groups = meson_pmx_get_groups,
285 .gpio_request_enable = meson_pmx_request_gpio,
286};
287
288static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
289 unsigned long *configs, unsigned num_configs)
290{
291 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
292 struct meson_domain *domain;
293 struct meson_bank *bank;
294 enum pin_config_param param;
295 unsigned int reg, bit;
296 int i, ret;
297 u16 arg;
298
299 ret = meson_get_domain_and_bank(pc, pin, &domain, &bank);
300 if (ret)
301 return ret;
302
303 for (i = 0; i < num_configs; i++) {
304 param = pinconf_to_config_param(configs[i]);
305 arg = pinconf_to_config_argument(configs[i]);
306
307 switch (param) {
308 case PIN_CONFIG_BIAS_DISABLE:
309 dev_dbg(pc->dev, "pin %u: disable bias\n", pin);
310
311 meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
312 ret = regmap_update_bits(domain->reg_pull, reg,
313 BIT(bit), 0);
314 if (ret)
315 return ret;
316 break;
317 case PIN_CONFIG_BIAS_PULL_UP:
318 dev_dbg(pc->dev, "pin %u: enable pull-up\n", pin);
319
320 meson_calc_reg_and_bit(bank, pin, REG_PULLEN,
321 &reg, &bit);
322 ret = regmap_update_bits(domain->reg_pullen, reg,
323 BIT(bit), BIT(bit));
324 if (ret)
325 return ret;
326
327 meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
328 ret = regmap_update_bits(domain->reg_pull, reg,
329 BIT(bit), BIT(bit));
330 if (ret)
331 return ret;
332 break;
333 case PIN_CONFIG_BIAS_PULL_DOWN:
334 dev_dbg(pc->dev, "pin %u: enable pull-down\n", pin);
335
336 meson_calc_reg_and_bit(bank, pin, REG_PULLEN,
337 &reg, &bit);
338 ret = regmap_update_bits(domain->reg_pullen, reg,
339 BIT(bit), BIT(bit));
340 if (ret)
341 return ret;
342
343 meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
344 ret = regmap_update_bits(domain->reg_pull, reg,
345 BIT(bit), 0);
346 if (ret)
347 return ret;
348 break;
349 default:
350 return -ENOTSUPP;
351 }
352 }
353
354 return 0;
355}
356
357static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin)
358{
359 struct meson_domain *domain;
360 struct meson_bank *bank;
361 unsigned int reg, bit, val;
362 int ret, conf;
363
364 ret = meson_get_domain_and_bank(pc, pin, &domain, &bank);
365 if (ret)
366 return ret;
367
368 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, &reg, &bit);
369
370 ret = regmap_read(domain->reg_pullen, reg, &val);
371 if (ret)
372 return ret;
373
374 if (!(val & BIT(bit))) {
375 conf = PIN_CONFIG_BIAS_DISABLE;
376 } else {
377 meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
378
379 ret = regmap_read(domain->reg_pull, reg, &val);
380 if (ret)
381 return ret;
382
383 if (val & BIT(bit))
384 conf = PIN_CONFIG_BIAS_PULL_UP;
385 else
386 conf = PIN_CONFIG_BIAS_PULL_DOWN;
387 }
388
389 return conf;
390}
391
392static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin,
393 unsigned long *config)
394{
395 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
396 enum pin_config_param param = pinconf_to_config_param(*config);
397 u16 arg;
398
399 switch (param) {
400 case PIN_CONFIG_BIAS_DISABLE:
401 case PIN_CONFIG_BIAS_PULL_DOWN:
402 case PIN_CONFIG_BIAS_PULL_UP:
403 if (meson_pinconf_get_pull(pc, pin) == param)
404 arg = 1;
405 else
406 return -EINVAL;
407 break;
408 default:
409 return -ENOTSUPP;
410 }
411
412 *config = pinconf_to_config_packed(param, arg);
413 dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config);
414
415 return 0;
416}
417
418static int meson_pinconf_group_set(struct pinctrl_dev *pcdev,
419 unsigned int num_group,
420 unsigned long *configs, unsigned num_configs)
421{
422 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
423 struct meson_pmx_group *group = &pc->data->groups[num_group];
424 int i;
425
426 dev_dbg(pc->dev, "set pinconf for group %s\n", group->name);
427
428 for (i = 0; i < group->num_pins; i++) {
429 meson_pinconf_set(pcdev, group->pins[i], configs,
430 num_configs);
431 }
432
433 return 0;
434}
435
436static int meson_pinconf_group_get(struct pinctrl_dev *pcdev,
437 unsigned int group, unsigned long *config)
438{
439 return -ENOSYS;
440}
441
442static const struct pinconf_ops meson_pinconf_ops = {
443 .pin_config_get = meson_pinconf_get,
444 .pin_config_set = meson_pinconf_set,
445 .pin_config_group_get = meson_pinconf_group_get,
446 .pin_config_group_set = meson_pinconf_group_set,
447 .is_generic = true,
448};
449
450static inline struct meson_domain *to_meson_domain(struct gpio_chip *chip)
451{
452 return container_of(chip, struct meson_domain, chip);
453}
454
455static int meson_gpio_request(struct gpio_chip *chip, unsigned gpio)
456{
457 return pinctrl_request_gpio(chip->base + gpio);
458}
459
460static void meson_gpio_free(struct gpio_chip *chip, unsigned gpio)
461{
462 struct meson_domain *domain = to_meson_domain(chip);
463
464 pinctrl_free_gpio(domain->data->pin_base + gpio);
465}
466
467static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
468{
469 struct meson_domain *domain = to_meson_domain(chip);
470 unsigned int reg, bit, pin;
471 struct meson_bank *bank;
472 int ret;
473
474 pin = domain->data->pin_base + gpio;
475 ret = meson_get_bank(domain, pin, &bank);
476 if (ret)
477 return ret;
478
479 meson_calc_reg_and_bit(bank, pin, REG_DIR, &reg, &bit);
480
481 return regmap_update_bits(domain->reg_gpio, reg, BIT(bit), BIT(bit));
482}
483
484static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
485 int value)
486{
487 struct meson_domain *domain = to_meson_domain(chip);
488 unsigned int reg, bit, pin;
489 struct meson_bank *bank;
490 int ret;
491
492 pin = domain->data->pin_base + gpio;
493 ret = meson_get_bank(domain, pin, &bank);
494 if (ret)
495 return ret;
496
497 meson_calc_reg_and_bit(bank, pin, REG_DIR, &reg, &bit);
498 ret = regmap_update_bits(domain->reg_gpio, reg, BIT(bit), 0);
499 if (ret)
500 return ret;
501
502 meson_calc_reg_and_bit(bank, pin, REG_OUT, &reg, &bit);
503 return regmap_update_bits(domain->reg_gpio, reg, BIT(bit),
504 value ? BIT(bit) : 0);
505}
506
507static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
508{
509 struct meson_domain *domain = to_meson_domain(chip);
510 unsigned int reg, bit, pin;
511 struct meson_bank *bank;
512 int ret;
513
514 pin = domain->data->pin_base + gpio;
515 ret = meson_get_bank(domain, pin, &bank);
516 if (ret)
517 return;
518
519 meson_calc_reg_and_bit(bank, pin, REG_OUT, &reg, &bit);
520 regmap_update_bits(domain->reg_gpio, reg, BIT(bit),
521 value ? BIT(bit) : 0);
522}
523
524static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio)
525{
526 struct meson_domain *domain = to_meson_domain(chip);
527 unsigned int reg, bit, val, pin;
528 struct meson_bank *bank;
529 int ret;
530
531 pin = domain->data->pin_base + gpio;
532 ret = meson_get_bank(domain, pin, &bank);
533 if (ret)
534 return ret;
535
536 meson_calc_reg_and_bit(bank, pin, REG_IN, &reg, &bit);
537 regmap_read(domain->reg_gpio, reg, &val);
538
539 return !!(val & BIT(bit));
540}
541
542static const struct of_device_id meson_pinctrl_dt_match[] = {
543 {
544 .compatible = "amlogic,meson8-pinctrl",
545 .data = &meson8_pinctrl_data,
546 },
547 { },
548};
549MODULE_DEVICE_TABLE(of, meson_pinctrl_dt_match);
550
551static int meson_gpiolib_register(struct meson_pinctrl *pc)
552{
553 struct meson_domain *domain;
554 int i, ret;
555
556 for (i = 0; i < pc->data->num_domains; i++) {
557 domain = &pc->domains[i];
558
559 domain->chip.label = domain->data->name;
560 domain->chip.dev = pc->dev;
561 domain->chip.request = meson_gpio_request;
562 domain->chip.free = meson_gpio_free;
563 domain->chip.direction_input = meson_gpio_direction_input;
564 domain->chip.direction_output = meson_gpio_direction_output;
565 domain->chip.get = meson_gpio_get;
566 domain->chip.set = meson_gpio_set;
567 domain->chip.base = -1;
568 domain->chip.ngpio = domain->data->num_pins;
569 domain->chip.can_sleep = false;
570 domain->chip.of_node = domain->of_node;
571 domain->chip.of_gpio_n_cells = 2;
572
573 ret = gpiochip_add(&domain->chip);
574 if (ret) {
575 dev_err(pc->dev, "can't add gpio chip %s\n",
576 domain->data->name);
577 goto fail;
578 }
579
580 ret = gpiochip_add_pin_range(&domain->chip, dev_name(pc->dev),
581 0, domain->data->pin_base,
582 domain->chip.ngpio);
583 if (ret) {
584 dev_err(pc->dev, "can't add pin range\n");
585 goto fail;
586 }
587 }
588
589 return 0;
590fail:
591 for (i--; i >= 0; i--)
592 gpiochip_remove(&pc->domains[i].chip);
593
594 return ret;
595}
596
597static struct meson_domain_data *meson_get_domain_data(struct meson_pinctrl *pc,
598 struct device_node *np)
599{
600 int i;
601
602 for (i = 0; i < pc->data->num_domains; i++) {
603 if (!strcmp(np->name, pc->data->domain_data[i].name))
604 return &pc->data->domain_data[i];
605 }
606
607 return NULL;
608}
609
610static struct regmap_config meson_regmap_config = {
611 .reg_bits = 32,
612 .val_bits = 32,
613 .reg_stride = 4,
614};
615
616static struct regmap *meson_map_resource(struct meson_pinctrl *pc,
617 struct device_node *node, char *name)
618{
619 struct resource res;
620 void __iomem *base;
621 int i;
622
623 i = of_property_match_string(node, "reg-names", name);
624 if (of_address_to_resource(node, i, &res))
625 return ERR_PTR(-ENOENT);
626
627 base = devm_ioremap_resource(pc->dev, &res);
628 if (IS_ERR(base))
629 return ERR_CAST(base);
630
631 meson_regmap_config.max_register = resource_size(&res) - 4;
632 meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL,
633 "%s-%s", node->name,
634 name);
635 if (!meson_regmap_config.name)
636 return ERR_PTR(-ENOMEM);
637
638 return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config);
639}
640
641static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
642 struct device_node *node)
643{
644 struct device_node *np;
645 struct meson_domain *domain;
646 int i = 0, num_domains = 0;
647
648 for_each_child_of_node(node, np) {
649 if (!of_find_property(np, "gpio-controller", NULL))
650 continue;
651 num_domains++;
652 }
653
654 if (num_domains != pc->data->num_domains) {
655 dev_err(pc->dev, "wrong number of subnodes\n");
656 return -EINVAL;
657 }
658
659 pc->domains = devm_kzalloc(pc->dev, num_domains *
660 sizeof(struct meson_domain), GFP_KERNEL);
661 if (!pc->domains)
662 return -ENOMEM;
663
664 for_each_child_of_node(node, np) {
665 if (!of_find_property(np, "gpio-controller", NULL))
666 continue;
667
668 domain = &pc->domains[i];
669
670 domain->data = meson_get_domain_data(pc, np);
671 if (!domain->data) {
672 dev_err(pc->dev, "domain data not found for node %s\n",
673 np->name);
674 return -ENODEV;
675 }
676
677 domain->of_node = np;
678
679 domain->reg_mux = meson_map_resource(pc, np, "mux");
680 if (IS_ERR(domain->reg_mux)) {
681 dev_err(pc->dev, "mux registers not found\n");
682 return PTR_ERR(domain->reg_mux);
683 }
684
685 domain->reg_pull = meson_map_resource(pc, np, "pull");
686 if (IS_ERR(domain->reg_pull)) {
687 dev_err(pc->dev, "pull registers not found\n");
688 return PTR_ERR(domain->reg_pull);
689 }
690
691 domain->reg_pullen = meson_map_resource(pc, np, "pull-enable");
692 /* Use pull region if pull-enable one is not present */
693 if (IS_ERR(domain->reg_pullen))
694 domain->reg_pullen = domain->reg_pull;
695
696 domain->reg_gpio = meson_map_resource(pc, np, "gpio");
697 if (IS_ERR(domain->reg_gpio)) {
698 dev_err(pc->dev, "gpio registers not found\n");
699 return PTR_ERR(domain->reg_gpio);
700 }
701
702 i++;
703 }
704
705 return 0;
706}
707
708static int meson_pinctrl_probe(struct platform_device *pdev)
709{
710 const struct of_device_id *match;
711 struct device *dev = &pdev->dev;
712 struct meson_pinctrl *pc;
713 int ret;
714
715 pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL);
716 if (!pc)
717 return -ENOMEM;
718
719 pc->dev = dev;
720 match = of_match_node(meson_pinctrl_dt_match, pdev->dev.of_node);
721 pc->data = (struct meson_pinctrl_data *)match->data;
722
723 ret = meson_pinctrl_parse_dt(pc, pdev->dev.of_node);
724 if (ret)
725 return ret;
726
727 pc->desc.name = "pinctrl-meson";
728 pc->desc.owner = THIS_MODULE;
729 pc->desc.pctlops = &meson_pctrl_ops;
730 pc->desc.pmxops = &meson_pmx_ops;
731 pc->desc.confops = &meson_pinconf_ops;
732 pc->desc.pins = pc->data->pins;
733 pc->desc.npins = pc->data->num_pins;
734
735 pc->pcdev = pinctrl_register(&pc->desc, pc->dev, pc);
736 if (!pc->pcdev) {
737 dev_err(pc->dev, "can't register pinctrl device");
738 return -EINVAL;
739 }
740
741 ret = meson_gpiolib_register(pc);
742 if (ret) {
743 pinctrl_unregister(pc->pcdev);
744 return ret;
745 }
746
747 return 0;
748}
749
750static struct platform_driver meson_pinctrl_driver = {
751 .probe = meson_pinctrl_probe,
752 .driver = {
753 .name = "meson-pinctrl",
754 .of_match_table = meson_pinctrl_dt_match,
755 },
756};
757module_platform_driver(meson_pinctrl_driver);
758
759MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
760MODULE_DESCRIPTION("Amlogic Meson pinctrl driver");
761MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h
new file mode 100644
index 000000000000..bfea8adc7953
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson.h
@@ -0,0 +1,209 @@
1/*
2 * Pin controller and GPIO driver for Amlogic Meson SoCs
3 *
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * You should have received a copy of the GNU General Public License
11 * along with this program. If not, see <http://www.gnu.org/licenses/>.
12 */
13
14#include <linux/gpio.h>
15#include <linux/pinctrl/pinctrl.h>
16#include <linux/regmap.h>
17#include <linux/types.h>
18
19/**
20 * struct meson_pmx_group - a pinmux group
21 *
22 * @name: group name
23 * @pins: pins in the group
24 * @num_pins: number of pins in the group
25 * @is_gpio: whether the group is a single GPIO group
26 * @reg: register offset for the group in the domain mux registers
27 * @bit bit index enabling the group
28 * @domain: index of the domain this group belongs to
29 */
30struct meson_pmx_group {
31 const char *name;
32 const unsigned int *pins;
33 unsigned int num_pins;
34 bool is_gpio;
35 unsigned int reg;
36 unsigned int bit;
37 unsigned int domain;
38};
39
40/**
41 * struct meson_pmx_func - a pinmux function
42 *
43 * @name: function name
44 * @groups: groups in the function
45 * @num_groups: number of groups in the function
46 */
47struct meson_pmx_func {
48 const char *name;
49 const char * const *groups;
50 unsigned int num_groups;
51};
52
53/**
54 * struct meson_reg_desc - a register descriptor
55 *
56 * @reg: register offset in the regmap
57 * @bit: bit index in register
58 *
59 * The structure describes the information needed to control pull,
60 * pull-enable, direction, etc. for a single pin
61 */
62struct meson_reg_desc {
63 unsigned int reg;
64 unsigned int bit;
65};
66
67/**
68 * enum meson_reg_type - type of registers encoded in @meson_reg_desc
69 */
70enum meson_reg_type {
71 REG_PULLEN,
72 REG_PULL,
73 REG_DIR,
74 REG_OUT,
75 REG_IN,
76 NUM_REG,
77};
78
79/**
80 * struct meson bank
81 *
82 * @name: bank name
83 * @first: first pin of the bank
84 * @last: last pin of the bank
85 * @regs: array of register descriptors
86 *
87 * A bank represents a set of pins controlled by a contiguous set of
88 * bits in the domain registers. The structure specifies which bits in
89 * the regmap control the different functionalities. Each member of
90 * the @regs array refers to the first pin of the bank.
91 */
92struct meson_bank {
93 const char *name;
94 unsigned int first;
95 unsigned int last;
96 struct meson_reg_desc regs[NUM_REG];
97};
98
99/**
100 * struct meson_domain_data - domain platform data
101 *
102 * @name: name of the domain
103 * @banks: set of banks belonging to the domain
104 * @num_banks: number of banks in the domain
105 */
106struct meson_domain_data {
107 const char *name;
108 struct meson_bank *banks;
109 unsigned int num_banks;
110 unsigned int pin_base;
111 unsigned int num_pins;
112};
113
114/**
115 * struct meson_domain
116 *
117 * @reg_mux: registers for mux settings
118 * @reg_pullen: registers for pull-enable settings
119 * @reg_pull: registers for pull settings
120 * @reg_gpio: registers for gpio settings
121 * @chip: gpio chip associated with the domain
122 * @data; platform data for the domain
123 * @node: device tree node for the domain
124 *
125 * A domain represents a set of banks controlled by the same set of
126 * registers.
127 */
128struct meson_domain {
129 struct regmap *reg_mux;
130 struct regmap *reg_pullen;
131 struct regmap *reg_pull;
132 struct regmap *reg_gpio;
133
134 struct gpio_chip chip;
135 struct meson_domain_data *data;
136 struct device_node *of_node;
137};
138
139struct meson_pinctrl_data {
140 const struct pinctrl_pin_desc *pins;
141 struct meson_pmx_group *groups;
142 struct meson_pmx_func *funcs;
143 struct meson_domain_data *domain_data;
144 unsigned int num_pins;
145 unsigned int num_groups;
146 unsigned int num_funcs;
147 unsigned int num_domains;
148};
149
150struct meson_pinctrl {
151 struct device *dev;
152 struct pinctrl_dev *pcdev;
153 struct pinctrl_desc desc;
154 struct meson_pinctrl_data *data;
155 struct meson_domain *domains;
156};
157
158#define GROUP(grp, r, b) \
159 { \
160 .name = #grp, \
161 .pins = grp ## _pins, \
162 .num_pins = ARRAY_SIZE(grp ## _pins), \
163 .reg = r, \
164 .bit = b, \
165 .domain = 0, \
166 }
167
168#define GPIO_GROUP(gpio) \
169 { \
170 .name = #gpio, \
171 .pins = (const unsigned int[]){ PIN_ ## gpio}, \
172 .num_pins = 1, \
173 .is_gpio = true, \
174 }
175
176#define GROUP_AO(grp, r, b) \
177 { \
178 .name = #grp, \
179 .pins = grp ## _pins, \
180 .num_pins = ARRAY_SIZE(grp ## _pins), \
181 .reg = r, \
182 .bit = b, \
183 .domain = 1, \
184 }
185
186#define FUNCTION(fn) \
187 { \
188 .name = #fn, \
189 .groups = fn ## _groups, \
190 .num_groups = ARRAY_SIZE(fn ## _groups), \
191 }
192
193#define BANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
194 { \
195 .name = n, \
196 .first = f, \
197 .last = l, \
198 .regs = { \
199 [REG_PULLEN] = { per, peb }, \
200 [REG_PULL] = { pr, pb }, \
201 [REG_DIR] = { dr, db }, \
202 [REG_OUT] = { or, ob }, \
203 [REG_IN] = { ir, ib }, \
204 }, \
205 }
206
207#define MESON_PIN(x) PINCTRL_PIN(PIN_ ## x, #x)
208
209extern struct meson_pinctrl_data meson8_pinctrl_data;
diff --git a/drivers/pinctrl/meson/pinctrl-meson8.c b/drivers/pinctrl/meson/pinctrl-meson8.c
new file mode 100644
index 000000000000..f8aa3a281767
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson8.c
@@ -0,0 +1,1089 @@
1/*
2 * Pin controller and GPIO driver for Amlogic Meson8.
3 *
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * You should have received a copy of the GNU General Public License
11 * along with this program. If not, see <http://www.gnu.org/licenses/>.
12 */
13
14#include <dt-bindings/gpio/meson8-gpio.h>
15#include "pinctrl-meson.h"
16
17#define AO_OFFSET 120
18
19#define PIN_GPIOX_0 GPIOX_0
20#define PIN_GPIOX_1 GPIOX_1
21#define PIN_GPIOX_2 GPIOX_2
22#define PIN_GPIOX_3 GPIOX_3
23#define PIN_GPIOX_4 GPIOX_4
24#define PIN_GPIOX_5 GPIOX_5
25#define PIN_GPIOX_6 GPIOX_6
26#define PIN_GPIOX_7 GPIOX_7
27#define PIN_GPIOX_8 GPIOX_8
28#define PIN_GPIOX_9 GPIOX_9
29#define PIN_GPIOX_10 GPIOX_10
30#define PIN_GPIOX_11 GPIOX_11
31#define PIN_GPIOX_12 GPIOX_12
32#define PIN_GPIOX_13 GPIOX_13
33#define PIN_GPIOX_14 GPIOX_14
34#define PIN_GPIOX_15 GPIOX_15
35#define PIN_GPIOX_16 GPIOX_16
36#define PIN_GPIOX_17 GPIOX_17
37#define PIN_GPIOX_18 GPIOX_18
38#define PIN_GPIOX_19 GPIOX_19
39#define PIN_GPIOX_20 GPIOX_20
40#define PIN_GPIOX_21 GPIOX_21
41#define PIN_GPIOY_0 GPIOY_0
42#define PIN_GPIOY_1 GPIOY_1
43#define PIN_GPIOY_2 GPIOY_2
44#define PIN_GPIOY_3 GPIOY_3
45#define PIN_GPIOY_4 GPIOY_4
46#define PIN_GPIOY_5 GPIOY_5
47#define PIN_GPIOY_6 GPIOY_6
48#define PIN_GPIOY_7 GPIOY_7
49#define PIN_GPIOY_8 GPIOY_8
50#define PIN_GPIOY_9 GPIOY_9
51#define PIN_GPIOY_10 GPIOY_10
52#define PIN_GPIOY_11 GPIOY_11
53#define PIN_GPIOY_12 GPIOY_12
54#define PIN_GPIOY_13 GPIOY_13
55#define PIN_GPIOY_14 GPIOY_14
56#define PIN_GPIOY_15 GPIOY_15
57#define PIN_GPIOY_16 GPIOY_16
58#define PIN_GPIODV_0 GPIODV_0
59#define PIN_GPIODV_1 GPIODV_1
60#define PIN_GPIODV_2 GPIODV_2
61#define PIN_GPIODV_3 GPIODV_3
62#define PIN_GPIODV_4 GPIODV_4
63#define PIN_GPIODV_5 GPIODV_5
64#define PIN_GPIODV_6 GPIODV_6
65#define PIN_GPIODV_7 GPIODV_7
66#define PIN_GPIODV_8 GPIODV_8
67#define PIN_GPIODV_9 GPIODV_9
68#define PIN_GPIODV_10 GPIODV_10
69#define PIN_GPIODV_11 GPIODV_11
70#define PIN_GPIODV_12 GPIODV_12
71#define PIN_GPIODV_13 GPIODV_13
72#define PIN_GPIODV_14 GPIODV_14
73#define PIN_GPIODV_15 GPIODV_15
74#define PIN_GPIODV_16 GPIODV_16
75#define PIN_GPIODV_17 GPIODV_17
76#define PIN_GPIODV_18 GPIODV_18
77#define PIN_GPIODV_19 GPIODV_19
78#define PIN_GPIODV_20 GPIODV_20
79#define PIN_GPIODV_21 GPIODV_21
80#define PIN_GPIODV_22 GPIODV_22
81#define PIN_GPIODV_23 GPIODV_23
82#define PIN_GPIODV_24 GPIODV_24
83#define PIN_GPIODV_25 GPIODV_25
84#define PIN_GPIODV_26 GPIODV_26
85#define PIN_GPIODV_27 GPIODV_27
86#define PIN_GPIODV_28 GPIODV_28
87#define PIN_GPIODV_29 GPIODV_29
88#define PIN_GPIOH_0 GPIOH_0
89#define PIN_GPIOH_1 GPIOH_1
90#define PIN_GPIOH_2 GPIOH_2
91#define PIN_GPIOH_3 GPIOH_3
92#define PIN_GPIOH_4 GPIOH_4
93#define PIN_GPIOH_5 GPIOH_5
94#define PIN_GPIOH_6 GPIOH_6
95#define PIN_GPIOH_7 GPIOH_7
96#define PIN_GPIOH_8 GPIOH_8
97#define PIN_GPIOH_9 GPIOH_9
98#define PIN_GPIOZ_0 GPIOZ_0
99#define PIN_GPIOZ_1 GPIOZ_1
100#define PIN_GPIOZ_2 GPIOZ_2
101#define PIN_GPIOZ_3 GPIOZ_3
102#define PIN_GPIOZ_4 GPIOZ_4
103#define PIN_GPIOZ_5 GPIOZ_5
104#define PIN_GPIOZ_6 GPIOZ_6
105#define PIN_GPIOZ_7 GPIOZ_7
106#define PIN_GPIOZ_8 GPIOZ_8
107#define PIN_GPIOZ_9 GPIOZ_9
108#define PIN_GPIOZ_10 GPIOZ_10
109#define PIN_GPIOZ_11 GPIOZ_11
110#define PIN_GPIOZ_12 GPIOZ_12
111#define PIN_GPIOZ_13 GPIOZ_13
112#define PIN_GPIOZ_14 GPIOZ_14
113#define PIN_CARD_0 CARD_0
114#define PIN_CARD_1 CARD_1
115#define PIN_CARD_2 CARD_2
116#define PIN_CARD_3 CARD_3
117#define PIN_CARD_4 CARD_4
118#define PIN_CARD_5 CARD_5
119#define PIN_CARD_6 CARD_6
120#define PIN_BOOT_0 BOOT_0
121#define PIN_BOOT_1 BOOT_1
122#define PIN_BOOT_2 BOOT_2
123#define PIN_BOOT_3 BOOT_3
124#define PIN_BOOT_4 BOOT_4
125#define PIN_BOOT_5 BOOT_5
126#define PIN_BOOT_6 BOOT_6
127#define PIN_BOOT_7 BOOT_7
128#define PIN_BOOT_8 BOOT_8
129#define PIN_BOOT_9 BOOT_9
130#define PIN_BOOT_10 BOOT_10
131#define PIN_BOOT_11 BOOT_11
132#define PIN_BOOT_12 BOOT_12
133#define PIN_BOOT_13 BOOT_13
134#define PIN_BOOT_14 BOOT_14
135#define PIN_BOOT_15 BOOT_15
136#define PIN_BOOT_16 BOOT_16
137#define PIN_BOOT_17 BOOT_17
138#define PIN_BOOT_18 BOOT_18
139
140#define PIN_GPIOAO_0 (AO_OFFSET + GPIOAO_0)
141#define PIN_GPIOAO_1 (AO_OFFSET + GPIOAO_1)
142#define PIN_GPIOAO_2 (AO_OFFSET + GPIOAO_2)
143#define PIN_GPIOAO_3 (AO_OFFSET + GPIOAO_3)
144#define PIN_GPIOAO_4 (AO_OFFSET + GPIOAO_4)
145#define PIN_GPIOAO_5 (AO_OFFSET + GPIOAO_5)
146#define PIN_GPIOAO_6 (AO_OFFSET + GPIOAO_6)
147#define PIN_GPIOAO_7 (AO_OFFSET + GPIOAO_7)
148#define PIN_GPIOAO_8 (AO_OFFSET + GPIOAO_8)
149#define PIN_GPIOAO_9 (AO_OFFSET + GPIOAO_9)
150#define PIN_GPIOAO_10 (AO_OFFSET + GPIOAO_10)
151#define PIN_GPIOAO_11 (AO_OFFSET + GPIOAO_11)
152#define PIN_GPIOAO_12 (AO_OFFSET + GPIOAO_12)
153#define PIN_GPIOAO_13 (AO_OFFSET + GPIOAO_13)
154#define PIN_GPIO_BSD_EN (AO_OFFSET + GPIO_BSD_EN)
155#define PIN_GPIO_TEST_N (AO_OFFSET + GPIO_TEST_N)
156
157static const struct pinctrl_pin_desc meson8_pins[] = {
158 MESON_PIN(GPIOX_0),
159 MESON_PIN(GPIOX_1),
160 MESON_PIN(GPIOX_2),
161 MESON_PIN(GPIOX_3),
162 MESON_PIN(GPIOX_4),
163 MESON_PIN(GPIOX_5),
164 MESON_PIN(GPIOX_6),
165 MESON_PIN(GPIOX_7),
166 MESON_PIN(GPIOX_8),
167 MESON_PIN(GPIOX_9),
168 MESON_PIN(GPIOX_10),
169 MESON_PIN(GPIOX_11),
170 MESON_PIN(GPIOX_12),
171 MESON_PIN(GPIOX_13),
172 MESON_PIN(GPIOX_14),
173 MESON_PIN(GPIOX_15),
174 MESON_PIN(GPIOX_16),
175 MESON_PIN(GPIOX_17),
176 MESON_PIN(GPIOX_18),
177 MESON_PIN(GPIOX_19),
178 MESON_PIN(GPIOX_20),
179 MESON_PIN(GPIOX_21),
180 MESON_PIN(GPIOY_0),
181 MESON_PIN(GPIOY_1),
182 MESON_PIN(GPIOY_2),
183 MESON_PIN(GPIOY_3),
184 MESON_PIN(GPIOY_4),
185 MESON_PIN(GPIOY_5),
186 MESON_PIN(GPIOY_6),
187 MESON_PIN(GPIOY_7),
188 MESON_PIN(GPIOY_8),
189 MESON_PIN(GPIOY_9),
190 MESON_PIN(GPIOY_10),
191 MESON_PIN(GPIOY_11),
192 MESON_PIN(GPIOY_12),
193 MESON_PIN(GPIOY_13),
194 MESON_PIN(GPIOY_14),
195 MESON_PIN(GPIOY_15),
196 MESON_PIN(GPIOY_16),
197 MESON_PIN(GPIODV_0),
198 MESON_PIN(GPIODV_1),
199 MESON_PIN(GPIODV_2),
200 MESON_PIN(GPIODV_3),
201 MESON_PIN(GPIODV_4),
202 MESON_PIN(GPIODV_5),
203 MESON_PIN(GPIODV_6),
204 MESON_PIN(GPIODV_7),
205 MESON_PIN(GPIODV_8),
206 MESON_PIN(GPIODV_9),
207 MESON_PIN(GPIODV_10),
208 MESON_PIN(GPIODV_11),
209 MESON_PIN(GPIODV_12),
210 MESON_PIN(GPIODV_13),
211 MESON_PIN(GPIODV_14),
212 MESON_PIN(GPIODV_15),
213 MESON_PIN(GPIODV_16),
214 MESON_PIN(GPIODV_17),
215 MESON_PIN(GPIODV_18),
216 MESON_PIN(GPIODV_19),
217 MESON_PIN(GPIODV_20),
218 MESON_PIN(GPIODV_21),
219 MESON_PIN(GPIODV_22),
220 MESON_PIN(GPIODV_23),
221 MESON_PIN(GPIODV_24),
222 MESON_PIN(GPIODV_25),
223 MESON_PIN(GPIODV_26),
224 MESON_PIN(GPIODV_27),
225 MESON_PIN(GPIODV_28),
226 MESON_PIN(GPIODV_29),
227 MESON_PIN(GPIOH_0),
228 MESON_PIN(GPIOH_1),
229 MESON_PIN(GPIOH_2),
230 MESON_PIN(GPIOH_3),
231 MESON_PIN(GPIOH_4),
232 MESON_PIN(GPIOH_5),
233 MESON_PIN(GPIOH_6),
234 MESON_PIN(GPIOH_7),
235 MESON_PIN(GPIOH_8),
236 MESON_PIN(GPIOH_9),
237 MESON_PIN(GPIOZ_0),
238 MESON_PIN(GPIOZ_1),
239 MESON_PIN(GPIOZ_2),
240 MESON_PIN(GPIOZ_3),
241 MESON_PIN(GPIOZ_4),
242 MESON_PIN(GPIOZ_5),
243 MESON_PIN(GPIOZ_6),
244 MESON_PIN(GPIOZ_7),
245 MESON_PIN(GPIOZ_8),
246 MESON_PIN(GPIOZ_9),
247 MESON_PIN(GPIOZ_10),
248 MESON_PIN(GPIOZ_11),
249 MESON_PIN(GPIOZ_12),
250 MESON_PIN(GPIOZ_13),
251 MESON_PIN(GPIOZ_14),
252 MESON_PIN(CARD_0),
253 MESON_PIN(CARD_1),
254 MESON_PIN(CARD_2),
255 MESON_PIN(CARD_3),
256 MESON_PIN(CARD_4),
257 MESON_PIN(CARD_5),
258 MESON_PIN(CARD_6),
259 MESON_PIN(BOOT_0),
260 MESON_PIN(BOOT_1),
261 MESON_PIN(BOOT_2),
262 MESON_PIN(BOOT_3),
263 MESON_PIN(BOOT_4),
264 MESON_PIN(BOOT_5),
265 MESON_PIN(BOOT_6),
266 MESON_PIN(BOOT_7),
267 MESON_PIN(BOOT_8),
268 MESON_PIN(BOOT_9),
269 MESON_PIN(BOOT_10),
270 MESON_PIN(BOOT_11),
271 MESON_PIN(BOOT_12),
272 MESON_PIN(BOOT_13),
273 MESON_PIN(BOOT_14),
274 MESON_PIN(BOOT_15),
275 MESON_PIN(BOOT_16),
276 MESON_PIN(BOOT_17),
277 MESON_PIN(BOOT_18),
278 MESON_PIN(GPIOAO_0),
279 MESON_PIN(GPIOAO_1),
280 MESON_PIN(GPIOAO_2),
281 MESON_PIN(GPIOAO_3),
282 MESON_PIN(GPIOAO_4),
283 MESON_PIN(GPIOAO_5),
284 MESON_PIN(GPIOAO_6),
285 MESON_PIN(GPIOAO_7),
286 MESON_PIN(GPIOAO_8),
287 MESON_PIN(GPIOAO_9),
288 MESON_PIN(GPIOAO_10),
289 MESON_PIN(GPIOAO_11),
290 MESON_PIN(GPIOAO_12),
291 MESON_PIN(GPIOAO_13),
292 MESON_PIN(GPIO_BSD_EN),
293 MESON_PIN(GPIO_TEST_N),
294};
295
296/* bank X */
297static const unsigned int sd_d0_a_pins[] = { PIN_GPIOX_0 };
298static const unsigned int sd_d1_a_pins[] = { PIN_GPIOX_1 };
299static const unsigned int sd_d2_a_pins[] = { PIN_GPIOX_2 };
300static const unsigned int sd_d3_a_pins[] = { PIN_GPIOX_3 };
301static const unsigned int sd_clk_a_pins[] = { PIN_GPIOX_8 };
302static const unsigned int sd_cmd_a_pins[] = { PIN_GPIOX_9 };
303
304static const unsigned int sdxc_d0_a_pins[] = { PIN_GPIOX_0 };
305static const unsigned int sdxc_d13_a_pins[] = { PIN_GPIOX_1, PIN_GPIOX_2,
306 PIN_GPIOX_3 };
307static const unsigned int sdxc_d47_a_pins[] = { PIN_GPIOX_4, PIN_GPIOX_5,
308 PIN_GPIOX_6, PIN_GPIOX_7 };
309static const unsigned int sdxc_clk_a_pins[] = { PIN_GPIOX_8 };
310static const unsigned int sdxc_cmd_a_pins[] = { PIN_GPIOX_9 };
311
312static const unsigned int pcm_out_a_pins[] = { PIN_GPIOX_4 };
313static const unsigned int pcm_in_a_pins[] = { PIN_GPIOX_5 };
314static const unsigned int pcm_fs_a_pins[] = { PIN_GPIOX_6 };
315static const unsigned int pcm_clk_a_pins[] = { PIN_GPIOX_7 };
316
317static const unsigned int uart_tx_a0_pins[] = { PIN_GPIOX_4 };
318static const unsigned int uart_rx_a0_pins[] = { PIN_GPIOX_5 };
319static const unsigned int uart_cts_a0_pins[] = { PIN_GPIOX_6 };
320static const unsigned int uart_rts_a0_pins[] = { PIN_GPIOX_7 };
321
322static const unsigned int uart_tx_a1_pins[] = { PIN_GPIOX_12 };
323static const unsigned int uart_rx_a1_pins[] = { PIN_GPIOX_13 };
324static const unsigned int uart_cts_a1_pins[] = { PIN_GPIOX_14 };
325static const unsigned int uart_rts_a1_pins[] = { PIN_GPIOX_15 };
326
327static const unsigned int uart_tx_b0_pins[] = { PIN_GPIOX_16 };
328static const unsigned int uart_rx_b0_pins[] = { PIN_GPIOX_17 };
329static const unsigned int uart_cts_b0_pins[] = { PIN_GPIOX_18 };
330static const unsigned int uart_rts_b0_pins[] = { PIN_GPIOX_19 };
331
332static const unsigned int iso7816_det_pins[] = { PIN_GPIOX_16 };
333static const unsigned int iso7816_reset_pins[] = { PIN_GPIOX_17 };
334static const unsigned int iso7816_clk_pins[] = { PIN_GPIOX_18 };
335static const unsigned int iso7816_data_pins[] = { PIN_GPIOX_19 };
336
337static const unsigned int i2c_sda_d0_pins[] = { PIN_GPIOX_16 };
338static const unsigned int i2c_sck_d0_pins[] = { PIN_GPIOX_17 };
339
340static const unsigned int xtal_32k_out_pins[] = { PIN_GPIOX_10 };
341static const unsigned int xtal_24m_out_pins[] = { PIN_GPIOX_11 };
342
343/* bank Y */
344static const unsigned int uart_tx_c_pins[] = { PIN_GPIOY_0 };
345static const unsigned int uart_rx_c_pins[] = { PIN_GPIOY_1 };
346static const unsigned int uart_cts_c_pins[] = { PIN_GPIOY_2 };
347static const unsigned int uart_rts_c_pins[] = { PIN_GPIOY_3 };
348
349static const unsigned int pcm_out_b_pins[] = { PIN_GPIOY_4 };
350static const unsigned int pcm_in_b_pins[] = { PIN_GPIOY_5 };
351static const unsigned int pcm_fs_b_pins[] = { PIN_GPIOY_6 };
352static const unsigned int pcm_clk_b_pins[] = { PIN_GPIOY_7 };
353
354static const unsigned int i2c_sda_c0_pins[] = { PIN_GPIOY_0 };
355static const unsigned int i2c_sck_c0_pins[] = { PIN_GPIOY_1 };
356
357/* bank DV */
358static const unsigned int dvin_rgb_pins[] = { PIN_GPIODV_0, PIN_GPIODV_1,
359 PIN_GPIODV_2, PIN_GPIODV_3,
360 PIN_GPIODV_4, PIN_GPIODV_5,
361 PIN_GPIODV_6, PIN_GPIODV_7,
362 PIN_GPIODV_8, PIN_GPIODV_9,
363 PIN_GPIODV_10, PIN_GPIODV_11,
364 PIN_GPIODV_12, PIN_GPIODV_13,
365 PIN_GPIODV_14, PIN_GPIODV_15,
366 PIN_GPIODV_16, PIN_GPIODV_17,
367 PIN_GPIODV_18, PIN_GPIODV_19,
368 PIN_GPIODV_20, PIN_GPIODV_21,
369 PIN_GPIODV_22, PIN_GPIODV_23 };
370static const unsigned int dvin_vs_pins[] = { PIN_GPIODV_24 };
371static const unsigned int dvin_hs_pins[] = { PIN_GPIODV_25 };
372static const unsigned int dvin_clk_pins[] = { PIN_GPIODV_26 };
373static const unsigned int dvin_de_pins[] = { PIN_GPIODV_27 };
374
375static const unsigned int enc_0_pins[] = { PIN_GPIODV_0 };
376static const unsigned int enc_1_pins[] = { PIN_GPIODV_1 };
377static const unsigned int enc_2_pins[] = { PIN_GPIODV_2 };
378static const unsigned int enc_3_pins[] = { PIN_GPIODV_3 };
379static const unsigned int enc_4_pins[] = { PIN_GPIODV_4 };
380static const unsigned int enc_5_pins[] = { PIN_GPIODV_5 };
381static const unsigned int enc_6_pins[] = { PIN_GPIODV_6 };
382static const unsigned int enc_7_pins[] = { PIN_GPIODV_7 };
383static const unsigned int enc_8_pins[] = { PIN_GPIODV_8 };
384static const unsigned int enc_9_pins[] = { PIN_GPIODV_9 };
385static const unsigned int enc_10_pins[] = { PIN_GPIODV_10 };
386static const unsigned int enc_11_pins[] = { PIN_GPIODV_11 };
387static const unsigned int enc_12_pins[] = { PIN_GPIODV_12 };
388static const unsigned int enc_13_pins[] = { PIN_GPIODV_13 };
389static const unsigned int enc_14_pins[] = { PIN_GPIODV_14 };
390static const unsigned int enc_15_pins[] = { PIN_GPIODV_15 };
391static const unsigned int enc_16_pins[] = { PIN_GPIODV_16 };
392static const unsigned int enc_17_pins[] = { PIN_GPIODV_17 };
393
394static const unsigned int uart_tx_b1_pins[] = { PIN_GPIODV_24 };
395static const unsigned int uart_rx_b1_pins[] = { PIN_GPIODV_25 };
396static const unsigned int uart_cts_b1_pins[] = { PIN_GPIODV_26 };
397static const unsigned int uart_rts_b1_pins[] = { PIN_GPIODV_27 };
398
399static const unsigned int vga_vs_pins[] = { PIN_GPIODV_24 };
400static const unsigned int vga_hs_pins[] = { PIN_GPIODV_25 };
401
402/* bank H */
403static const unsigned int hdmi_hpd_pins[] = { PIN_GPIOH_0 };
404static const unsigned int hdmi_sda_pins[] = { PIN_GPIOH_1 };
405static const unsigned int hdmi_scl_pins[] = { PIN_GPIOH_2 };
406static const unsigned int hdmi_cec_pins[] = { PIN_GPIOH_3 };
407
408static const unsigned int spi_ss0_0_pins[] = { PIN_GPIOH_3 };
409static const unsigned int spi_miso_0_pins[] = { PIN_GPIOH_4 };
410static const unsigned int spi_mosi_0_pins[] = { PIN_GPIOH_5 };
411static const unsigned int spi_sclk_0_pins[] = { PIN_GPIOH_6 };
412
413static const unsigned int i2c_sda_d1_pins[] = { PIN_GPIOH_7 };
414static const unsigned int i2c_sck_d1_pins[] = { PIN_GPIOH_8 };
415
416/* bank Z */
417static const unsigned int spi_ss0_1_pins[] = { PIN_GPIOZ_9 };
418static const unsigned int spi_ss1_1_pins[] = { PIN_GPIOZ_10 };
419static const unsigned int spi_sclk_1_pins[] = { PIN_GPIOZ_11 };
420static const unsigned int spi_mosi_1_pins[] = { PIN_GPIOZ_12 };
421static const unsigned int spi_miso_1_pins[] = { PIN_GPIOZ_13 };
422static const unsigned int spi_ss2_1_pins[] = { PIN_GPIOZ_14 };
423
424static const unsigned int eth_tx_clk_50m_pins[] = { PIN_GPIOZ_4 };
425static const unsigned int eth_tx_en_pins[] = { PIN_GPIOZ_5 };
426static const unsigned int eth_txd1_pins[] = { PIN_GPIOZ_6 };
427static const unsigned int eth_txd0_pins[] = { PIN_GPIOZ_7 };
428static const unsigned int eth_rx_clk_in_pins[] = { PIN_GPIOZ_8 };
429static const unsigned int eth_rx_dv_pins[] = { PIN_GPIOZ_9 };
430static const unsigned int eth_rxd1_pins[] = { PIN_GPIOZ_10 };
431static const unsigned int eth_rxd0_pins[] = { PIN_GPIOZ_11 };
432static const unsigned int eth_mdio_pins[] = { PIN_GPIOZ_12 };
433static const unsigned int eth_mdc_pins[] = { PIN_GPIOZ_13 };
434
435static const unsigned int i2c_sda_a0_pins[] = { PIN_GPIOZ_0 };
436static const unsigned int i2c_sck_a0_pins[] = { PIN_GPIOZ_1 };
437
438static const unsigned int i2c_sda_b_pins[] = { PIN_GPIOZ_2 };
439static const unsigned int i2c_sck_b_pins[] = { PIN_GPIOZ_3 };
440
441static const unsigned int i2c_sda_c1_pins[] = { PIN_GPIOZ_4 };
442static const unsigned int i2c_sck_c1_pins[] = { PIN_GPIOZ_5 };
443
444static const unsigned int i2c_sda_a1_pins[] = { PIN_GPIOZ_0 };
445static const unsigned int i2c_sck_a1_pins[] = { PIN_GPIOZ_1 };
446
447static const unsigned int i2c_sda_a2_pins[] = { PIN_GPIOZ_0 };
448static const unsigned int i2c_sck_a2_pins[] = { PIN_GPIOZ_1 };
449
450/* bank BOOT */
451static const unsigned int sd_d0_c_pins[] = { PIN_BOOT_0 };
452static const unsigned int sd_d1_c_pins[] = { PIN_BOOT_1 };
453static const unsigned int sd_d2_c_pins[] = { PIN_BOOT_2 };
454static const unsigned int sd_d3_c_pins[] = { PIN_BOOT_3 };
455static const unsigned int sd_cmd_c_pins[] = { PIN_BOOT_16 };
456static const unsigned int sd_clk_c_pins[] = { PIN_BOOT_17 };
457
458static const unsigned int sdxc_d0_c_pins[] = { PIN_BOOT_0};
459static const unsigned int sdxc_d13_c_pins[] = { PIN_BOOT_1, PIN_BOOT_2,
460 PIN_BOOT_3 };
461static const unsigned int sdxc_d47_c_pins[] = { PIN_BOOT_4, PIN_BOOT_5,
462 PIN_BOOT_6, PIN_BOOT_7 };
463static const unsigned int sdxc_cmd_c_pins[] = { PIN_BOOT_16 };
464static const unsigned int sdxc_clk_c_pins[] = { PIN_BOOT_17 };
465
466static const unsigned int nand_io_pins[] = { PIN_BOOT_0, PIN_BOOT_1,
467 PIN_BOOT_2, PIN_BOOT_3,
468 PIN_BOOT_4, PIN_BOOT_5,
469 PIN_BOOT_6, PIN_BOOT_7 };
470static const unsigned int nand_io_ce0_pins[] = { PIN_BOOT_8 };
471static const unsigned int nand_io_ce1_pins[] = { PIN_BOOT_9 };
472static const unsigned int nand_io_rb0_pins[] = { PIN_BOOT_10 };
473static const unsigned int nand_ale_pins[] = { PIN_BOOT_11 };
474static const unsigned int nand_cle_pins[] = { PIN_BOOT_12 };
475static const unsigned int nand_wen_clk_pins[] = { PIN_BOOT_13 };
476static const unsigned int nand_ren_clk_pins[] = { PIN_BOOT_14 };
477static const unsigned int nand_dqs_pins[] = { PIN_BOOT_15 };
478static const unsigned int nand_ce2_pins[] = { PIN_BOOT_16 };
479static const unsigned int nand_ce3_pins[] = { PIN_BOOT_17 };
480
481static const unsigned int nor_d_pins[] = { PIN_BOOT_11 };
482static const unsigned int nor_q_pins[] = { PIN_BOOT_12 };
483static const unsigned int nor_c_pins[] = { PIN_BOOT_13 };
484static const unsigned int nor_cs_pins[] = { PIN_BOOT_18 };
485
486/* bank CARD */
487static const unsigned int sd_d1_b_pins[] = { PIN_CARD_0 };
488static const unsigned int sd_d0_b_pins[] = { PIN_CARD_1 };
489static const unsigned int sd_clk_b_pins[] = { PIN_CARD_2 };
490static const unsigned int sd_cmd_b_pins[] = { PIN_CARD_3 };
491static const unsigned int sd_d3_b_pins[] = { PIN_CARD_4 };
492static const unsigned int sd_d2_b_pins[] = { PIN_CARD_5 };
493
494static const unsigned int sdxc_d13_b_pins[] = { PIN_CARD_0, PIN_CARD_4,
495 PIN_CARD_5 };
496static const unsigned int sdxc_d0_b_pins[] = { PIN_CARD_1 };
497static const unsigned int sdxc_clk_b_pins[] = { PIN_CARD_2 };
498static const unsigned int sdxc_cmd_b_pins[] = { PIN_CARD_3 };
499
500/* bank AO */
501static const unsigned int uart_tx_ao_a_pins[] = { PIN_GPIOAO_0 };
502static const unsigned int uart_rx_ao_a_pins[] = { PIN_GPIOAO_1 };
503static const unsigned int uart_cts_ao_a_pins[] = { PIN_GPIOAO_2 };
504static const unsigned int uart_rts_ao_a_pins[] = { PIN_GPIOAO_3 };
505
506static const unsigned int remote_input_pins[] = { PIN_GPIOAO_7 };
507
508static const unsigned int i2c_slave_sck_ao_pins[] = { PIN_GPIOAO_4 };
509static const unsigned int i2c_slave_sda_ao_pins[] = { PIN_GPIOAO_5 };
510
511static const unsigned int uart_tx_ao_b0_pins[] = { PIN_GPIOAO_0 };
512static const unsigned int uart_rx_ao_b0_pins[] = { PIN_GPIOAO_1 };
513
514static const unsigned int uart_tx_ao_b1_pins[] = { PIN_GPIOAO_4 };
515static const unsigned int uart_rx_ao_b1_pins[] = { PIN_GPIOAO_5 };
516
517static const unsigned int i2c_mst_sck_ao_pins[] = { PIN_GPIOAO_4 };
518static const unsigned int i2c_mst_sda_ao_pins[] = { PIN_GPIOAO_5 };
519
520static struct meson_pmx_group meson8_groups[] = {
521 GPIO_GROUP(GPIOX_0),
522 GPIO_GROUP(GPIOX_1),
523 GPIO_GROUP(GPIOX_2),
524 GPIO_GROUP(GPIOX_3),
525 GPIO_GROUP(GPIOX_4),
526 GPIO_GROUP(GPIOX_5),
527 GPIO_GROUP(GPIOX_6),
528 GPIO_GROUP(GPIOX_7),
529 GPIO_GROUP(GPIOX_8),
530 GPIO_GROUP(GPIOX_9),
531 GPIO_GROUP(GPIOX_10),
532 GPIO_GROUP(GPIOX_11),
533 GPIO_GROUP(GPIOX_12),
534 GPIO_GROUP(GPIOX_13),
535 GPIO_GROUP(GPIOX_14),
536 GPIO_GROUP(GPIOX_15),
537 GPIO_GROUP(GPIOX_16),
538 GPIO_GROUP(GPIOX_17),
539 GPIO_GROUP(GPIOX_18),
540 GPIO_GROUP(GPIOX_19),
541 GPIO_GROUP(GPIOX_20),
542 GPIO_GROUP(GPIOX_21),
543 GPIO_GROUP(GPIOY_0),
544 GPIO_GROUP(GPIOY_1),
545 GPIO_GROUP(GPIOY_2),
546 GPIO_GROUP(GPIOY_3),
547 GPIO_GROUP(GPIOY_4),
548 GPIO_GROUP(GPIOY_5),
549 GPIO_GROUP(GPIOY_6),
550 GPIO_GROUP(GPIOY_7),
551 GPIO_GROUP(GPIOY_8),
552 GPIO_GROUP(GPIOY_9),
553 GPIO_GROUP(GPIOY_10),
554 GPIO_GROUP(GPIOY_11),
555 GPIO_GROUP(GPIOY_12),
556 GPIO_GROUP(GPIOY_13),
557 GPIO_GROUP(GPIOY_14),
558 GPIO_GROUP(GPIOY_15),
559 GPIO_GROUP(GPIOY_16),
560 GPIO_GROUP(GPIODV_0),
561 GPIO_GROUP(GPIODV_1),
562 GPIO_GROUP(GPIODV_2),
563 GPIO_GROUP(GPIODV_3),
564 GPIO_GROUP(GPIODV_4),
565 GPIO_GROUP(GPIODV_5),
566 GPIO_GROUP(GPIODV_6),
567 GPIO_GROUP(GPIODV_7),
568 GPIO_GROUP(GPIODV_8),
569 GPIO_GROUP(GPIODV_9),
570 GPIO_GROUP(GPIODV_10),
571 GPIO_GROUP(GPIODV_11),
572 GPIO_GROUP(GPIODV_12),
573 GPIO_GROUP(GPIODV_13),
574 GPIO_GROUP(GPIODV_14),
575 GPIO_GROUP(GPIODV_15),
576 GPIO_GROUP(GPIODV_16),
577 GPIO_GROUP(GPIODV_17),
578 GPIO_GROUP(GPIODV_18),
579 GPIO_GROUP(GPIODV_19),
580 GPIO_GROUP(GPIODV_20),
581 GPIO_GROUP(GPIODV_21),
582 GPIO_GROUP(GPIODV_22),
583 GPIO_GROUP(GPIODV_23),
584 GPIO_GROUP(GPIODV_24),
585 GPIO_GROUP(GPIODV_25),
586 GPIO_GROUP(GPIODV_26),
587 GPIO_GROUP(GPIODV_27),
588 GPIO_GROUP(GPIODV_28),
589 GPIO_GROUP(GPIODV_29),
590 GPIO_GROUP(GPIOH_0),
591 GPIO_GROUP(GPIOH_1),
592 GPIO_GROUP(GPIOH_2),
593 GPIO_GROUP(GPIOH_3),
594 GPIO_GROUP(GPIOH_4),
595 GPIO_GROUP(GPIOH_5),
596 GPIO_GROUP(GPIOH_6),
597 GPIO_GROUP(GPIOH_7),
598 GPIO_GROUP(GPIOH_8),
599 GPIO_GROUP(GPIOH_9),
600 GPIO_GROUP(GPIOZ_0),
601 GPIO_GROUP(GPIOZ_1),
602 GPIO_GROUP(GPIOZ_2),
603 GPIO_GROUP(GPIOZ_3),
604 GPIO_GROUP(GPIOZ_4),
605 GPIO_GROUP(GPIOZ_5),
606 GPIO_GROUP(GPIOZ_6),
607 GPIO_GROUP(GPIOZ_7),
608 GPIO_GROUP(GPIOZ_8),
609 GPIO_GROUP(GPIOZ_9),
610 GPIO_GROUP(GPIOZ_10),
611 GPIO_GROUP(GPIOZ_11),
612 GPIO_GROUP(GPIOZ_12),
613 GPIO_GROUP(GPIOZ_13),
614 GPIO_GROUP(GPIOZ_14),
615 GPIO_GROUP(GPIOAO_0),
616 GPIO_GROUP(GPIOAO_1),
617 GPIO_GROUP(GPIOAO_2),
618 GPIO_GROUP(GPIOAO_3),
619 GPIO_GROUP(GPIOAO_4),
620 GPIO_GROUP(GPIOAO_5),
621 GPIO_GROUP(GPIOAO_6),
622 GPIO_GROUP(GPIOAO_7),
623 GPIO_GROUP(GPIOAO_8),
624 GPIO_GROUP(GPIOAO_9),
625 GPIO_GROUP(GPIOAO_10),
626 GPIO_GROUP(GPIOAO_11),
627 GPIO_GROUP(GPIOAO_12),
628 GPIO_GROUP(GPIOAO_13),
629 GPIO_GROUP(GPIO_BSD_EN),
630 GPIO_GROUP(GPIO_TEST_N),
631
632 /* bank X */
633 GROUP(sd_d0_a, 8, 5),
634 GROUP(sd_d1_a, 8, 4),
635 GROUP(sd_d2_a, 8, 3),
636 GROUP(sd_d3_a, 8, 2),
637 GROUP(sd_clk_a, 8, 1),
638 GROUP(sd_cmd_a, 8, 0),
639
640 GROUP(sdxc_d0_a, 5, 14),
641 GROUP(sdxc_d13_a, 5, 13),
642 GROUP(sdxc_d47_a, 5, 12),
643 GROUP(sdxc_clk_a, 5, 11),
644 GROUP(sdxc_cmd_a, 5, 10),
645
646 GROUP(pcm_out_a, 3, 30),
647 GROUP(pcm_in_a, 3, 29),
648 GROUP(pcm_fs_a, 3, 28),
649 GROUP(pcm_clk_a, 3, 27),
650
651 GROUP(uart_tx_a0, 4, 17),
652 GROUP(uart_rx_a0, 4, 16),
653 GROUP(uart_cts_a0, 4, 15),
654 GROUP(uart_rts_a0, 4, 14),
655
656 GROUP(uart_tx_a1, 4, 13),
657 GROUP(uart_rx_a1, 4, 12),
658 GROUP(uart_cts_a1, 4, 11),
659 GROUP(uart_rts_a1, 4, 10),
660
661 GROUP(uart_tx_b0, 4, 9),
662 GROUP(uart_rx_b0, 4, 8),
663 GROUP(uart_cts_b0, 4, 7),
664 GROUP(uart_rts_b0, 4, 6),
665
666 GROUP(iso7816_det, 4, 21),
667 GROUP(iso7816_reset, 4, 20),
668 GROUP(iso7816_clk, 4, 19),
669 GROUP(iso7816_data, 4, 18),
670
671 GROUP(i2c_sda_d0, 4, 5),
672 GROUP(i2c_sck_d0, 4, 4),
673
674 GROUP(xtal_32k_out, 3, 22),
675 GROUP(xtal_24m_out, 3, 23),
676
677 /* bank Y */
678 GROUP(uart_tx_c, 1, 19),
679 GROUP(uart_rx_c, 1, 18),
680 GROUP(uart_cts_c, 1, 17),
681 GROUP(uart_rts_c, 1, 16),
682
683 GROUP(pcm_out_b, 4, 25),
684 GROUP(pcm_in_b, 4, 24),
685 GROUP(pcm_fs_b, 4, 23),
686 GROUP(pcm_clk_b, 4, 22),
687
688 GROUP(i2c_sda_c0, 1, 15),
689 GROUP(i2c_sck_c0, 1, 14),
690
691 /* bank DV */
692 GROUP(dvin_rgb, 0, 6),
693 GROUP(dvin_vs, 0, 9),
694 GROUP(dvin_hs, 0, 8),
695 GROUP(dvin_clk, 0, 7),
696 GROUP(dvin_de, 0, 10),
697
698 GROUP(enc_0, 7, 0),
699 GROUP(enc_1, 7, 1),
700 GROUP(enc_2, 7, 2),
701 GROUP(enc_3, 7, 3),
702 GROUP(enc_4, 7, 4),
703 GROUP(enc_5, 7, 5),
704 GROUP(enc_6, 7, 6),
705 GROUP(enc_7, 7, 7),
706 GROUP(enc_8, 7, 8),
707 GROUP(enc_9, 7, 9),
708 GROUP(enc_10, 7, 10),
709 GROUP(enc_11, 7, 11),
710 GROUP(enc_12, 7, 12),
711 GROUP(enc_13, 7, 13),
712 GROUP(enc_14, 7, 14),
713 GROUP(enc_15, 7, 15),
714 GROUP(enc_16, 7, 16),
715 GROUP(enc_17, 7, 17),
716
717 GROUP(uart_tx_b1, 6, 23),
718 GROUP(uart_rx_b1, 6, 22),
719 GROUP(uart_cts_b1, 6, 21),
720 GROUP(uart_rts_b1, 6, 20),
721
722 GROUP(vga_vs, 0, 21),
723 GROUP(vga_hs, 0, 20),
724
725 /* bank H */
726 GROUP(hdmi_hpd, 1, 26),
727 GROUP(hdmi_sda, 1, 25),
728 GROUP(hdmi_scl, 1, 24),
729 GROUP(hdmi_cec, 1, 23),
730
731 GROUP(spi_ss0_0, 9, 13),
732 GROUP(spi_miso_0, 9, 12),
733 GROUP(spi_mosi_0, 9, 11),
734 GROUP(spi_sclk_0, 9, 10),
735
736 GROUP(i2c_sda_d1, 4, 3),
737 GROUP(i2c_sck_d1, 4, 2),
738
739 /* bank Z */
740 GROUP(spi_ss0_1, 8, 16),
741 GROUP(spi_ss1_1, 8, 12),
742 GROUP(spi_sclk_1, 8, 15),
743 GROUP(spi_mosi_1, 8, 14),
744 GROUP(spi_miso_1, 8, 13),
745 GROUP(spi_ss2_1, 8, 17),
746
747 GROUP(eth_tx_clk_50m, 6, 15),
748 GROUP(eth_tx_en, 6, 14),
749 GROUP(eth_txd1, 6, 13),
750 GROUP(eth_txd0, 6, 12),
751 GROUP(eth_rx_clk_in, 6, 10),
752 GROUP(eth_rx_dv, 6, 11),
753 GROUP(eth_rxd1, 6, 8),
754 GROUP(eth_rxd0, 6, 7),
755 GROUP(eth_mdio, 6, 6),
756 GROUP(eth_mdc, 6, 5),
757
758 GROUP(i2c_sda_a0, 5, 31),
759 GROUP(i2c_sck_a0, 5, 30),
760
761 GROUP(i2c_sda_b, 5, 27),
762 GROUP(i2c_sck_b, 5, 26),
763
764 GROUP(i2c_sda_c1, 5, 25),
765 GROUP(i2c_sck_c1, 5, 24),
766
767 GROUP(i2c_sda_a1, 5, 9),
768 GROUP(i2c_sck_a1, 5, 8),
769
770 GROUP(i2c_sda_a2, 5, 7),
771 GROUP(i2c_sck_a2, 5, 6),
772
773 /* bank BOOT */
774 GROUP(sd_d0_c, 6, 29),
775 GROUP(sd_d1_c, 6, 28),
776 GROUP(sd_d2_c, 6, 27),
777 GROUP(sd_d3_c, 6, 26),
778 GROUP(sd_cmd_c, 6, 25),
779 GROUP(sd_clk_c, 6, 24),
780
781 GROUP(sdxc_d0_c, 4, 30),
782 GROUP(sdxc_d13_c, 4, 29),
783 GROUP(sdxc_d47_c, 4, 28),
784 GROUP(sdxc_cmd_c, 4, 27),
785 GROUP(sdxc_clk_c, 4, 26),
786
787 GROUP(nand_io, 2, 26),
788 GROUP(nand_io_ce0, 2, 25),
789 GROUP(nand_io_ce1, 2, 24),
790 GROUP(nand_io_rb0, 2, 17),
791 GROUP(nand_ale, 2, 21),
792 GROUP(nand_cle, 2, 20),
793 GROUP(nand_wen_clk, 2, 19),
794 GROUP(nand_ren_clk, 2, 18),
795 GROUP(nand_dqs, 2, 27),
796 GROUP(nand_ce2, 2, 23),
797 GROUP(nand_ce3, 2, 22),
798
799 GROUP(nor_d, 5, 1),
800 GROUP(nor_q, 5, 3),
801 GROUP(nor_c, 5, 2),
802 GROUP(nor_cs, 5, 0),
803
804 /* bank CARD */
805 GROUP(sd_d1_b, 2, 14),
806 GROUP(sd_d0_b, 2, 15),
807 GROUP(sd_clk_b, 2, 11),
808 GROUP(sd_cmd_b, 2, 10),
809 GROUP(sd_d3_b, 2, 12),
810 GROUP(sd_d2_b, 2, 13),
811
812 GROUP(sdxc_d13_b, 2, 6),
813 GROUP(sdxc_d0_b, 2, 7),
814 GROUP(sdxc_clk_b, 2, 5),
815 GROUP(sdxc_cmd_b, 2, 4),
816
817 /* bank AO */
818 GROUP_AO(uart_tx_ao_a, 0, 12),
819 GROUP_AO(uart_rx_ao_a, 0, 11),
820 GROUP_AO(uart_cts_ao_a, 0, 10),
821 GROUP_AO(uart_rts_ao_a, 0, 9),
822
823 GROUP_AO(remote_input, 0, 0),
824
825 GROUP_AO(i2c_slave_sck_ao, 0, 2),
826 GROUP_AO(i2c_slave_sda_ao, 0, 1),
827
828 GROUP_AO(uart_tx_ao_b0, 0, 26),
829 GROUP_AO(uart_rx_ao_b0, 0, 25),
830
831 GROUP_AO(uart_tx_ao_b1, 0, 24),
832 GROUP_AO(uart_rx_ao_b1, 0, 23),
833
834 GROUP_AO(i2c_mst_sck_ao, 0, 6),
835 GROUP_AO(i2c_mst_sda_ao, 0, 5),
836};
837
838static const char * const gpio_groups[] = {
839 "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
840 "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
841 "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
842 "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19",
843 "GPIOX_20", "GPIOX_21",
844
845 "GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4",
846 "GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9",
847 "GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14",
848 "GPIOY_15", "GPIOY_16",
849
850 "GPIODV_0", "GPIODV_1", "GPIODV_2", "GPIODV_3", "GPIODV_4",
851 "GPIODV_5", "GPIODV_6", "GPIODV_7", "GPIODV_8", "GPIODV_9",
852 "GPIODV_10", "GPIODV_11", "GPIODV_12", "GPIODV_13", "GPIODV_14",
853 "GPIODV_15", "GPIODV_16", "GPIODV_17", "GPIODV_18", "GPIODV_19",
854 "GPIODV_20", "GPIODV_21", "GPIODV_22", "GPIODV_23", "GPIODV_24",
855 "GPIODV_25", "GPIODV_26", "GPIODV_27", "GPIODV_28", "GPIODV_29",
856
857 "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4",
858 "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9",
859
860 "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4",
861 "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9",
862 "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14",
863
864 "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4",
865 "CARD_5", "CARD_6",
866
867 "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
868 "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
869 "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
870 "BOOT_15", "BOOT_16", "BOOT_17", "BOOT_18",
871
872 "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3",
873 "GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7",
874 "GPIOAO_8", "GPIOAO_9", "GPIOAO_10", "GPIOAO_11",
875 "GPIOAO_12", "GPIOAO_13", "GPIO_BSD_EN", "GPIO_TEST_N"
876};
877
878static const char * const sd_a_groups[] = {
879 "sd_d0_a", "sd_d1_a", "sd_d2_a", "sd_d3_a", "sd_clk_a", "sd_cmd_a"
880};
881
882static const char * const sdxc_a_groups[] = {
883 "sdxc_d0_a", "sdxc_d13_a", "sdxc_d47_a", "sdxc_clk_a", "sdxc_cmd_a"
884};
885
886static const char * const pcm_a_groups[] = {
887 "pcm_out_a", "pcm_in_a", "pcm_fs_a", "pcm_clk_a"
888};
889
890static const char * const uart_a_groups[] = {
891 "uart_tx_a0", "uart_rx_a0", "uart_cts_a0", "uart_rts_a0",
892 "uart_tx_a1", "uart_rx_a1", "uart_cts_a1", "uart_rts_a1"
893};
894
895static const char * const uart_b_groups[] = {
896 "uart_tx_b0", "uart_rx_b0", "uart_cts_b0", "uart_rts_b0",
897 "uart_tx_b1", "uart_rx_b1", "uart_cts_b1", "uart_rts_b1"
898};
899
900static const char * const iso7816_groups[] = {
901 "iso7816_det", "iso7816_reset", "iso7816_clk", "iso7816_data"
902};
903
904static const char * const i2c_d_groups[] = {
905 "i2c_sda_d0", "i2c_sck_d0", "i2c_sda_d1", "i2c_sck_d1"
906};
907
908static const char * const xtal_groups[] = {
909 "xtal_32k_out", "xtal_24m_out"
910};
911
912static const char * const uart_c_groups[] = {
913 "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c"
914};
915
916static const char * const pcm_b_groups[] = {
917 "pcm_out_b", "pcm_in_b", "pcm_fs_b", "pcm_clk_b"
918};
919
920static const char * const i2c_c_groups[] = {
921 "i2c_sda_c0", "i2c_sck_c0", "i2c_sda_c1", "i2c_sck_c1"
922};
923
924static const char * const dvin_groups[] = {
925 "dvin_rgb", "dvin_vs", "dvin_hs", "dvin_clk", "dvin_de"
926};
927
928static const char * const enc_groups[] = {
929 "enc_0", "enc_1", "enc_2", "enc_3", "enc_4", "enc_5",
930 "enc_6", "enc_7", "enc_8", "enc_9", "enc_10", "enc_11",
931 "enc_12", "enc_13", "enc_14", "enc_15", "enc_16", "enc_17"
932};
933
934static const char * const vga_groups[] = {
935 "vga_vs", "vga_hs"
936};
937
938static const char * const hdmi_groups[] = {
939 "hdmi_hpd", "hdmi_sda", "hdmi_scl", "hdmi_cec"
940};
941
942static const char * const spi_groups[] = {
943 "spi_ss0_0", "spi_miso_0", "spi_mosi_0", "spi_sclk_0",
944 "spi_ss0_1", "spi_ss1_1", "spi_sclk_1", "spi_mosi_1",
945 "spi_miso_1", "spi_ss2_1"
946};
947
948static const char * const ethernet_groups[] = {
949 "eth_tx_clk_50m", "eth_tx_en", "eth_txd1",
950 "eth_txd0", "eth_rx_clk_in", "eth_rx_dv",
951 "eth_rxd1", "eth_rxd0", "eth_mdio", "eth_mdc"
952};
953
954static const char * const i2c_a_groups[] = {
955 "i2c_sda_a0", "i2c_sck_a0", "i2c_sda_a1", "i2c_sck_a1",
956 "i2c_sda_a2", "i2c_sck_a2"
957};
958
959static const char * const i2c_b_groups[] = {
960 "i2c_sda_b", "i2c_sck_b"
961};
962
963static const char * const sd_c_groups[] = {
964 "sd_d0_c", "sd_d1_c", "sd_d2_c", "sd_d3_c",
965 "sd_cmd_c", "sd_clk_c"
966};
967
968static const char * const sdxc_c_groups[] = {
969 "sdxc_d0_c", "sdxc_d13_c", "sdxc_d47_c", "sdxc_cmd_c",
970 "sdxc_clk_c"
971};
972
973static const char * const nand_groups[] = {
974 "nand_io", "nand_io_ce0", "nand_io_ce1",
975 "nand_io_rb0", "nand_ale", "nand_cle",
976 "nand_wen_clk", "nand_ren_clk", "nand_dqs",
977 "nand_ce2", "nand_ce3"
978};
979
980static const char * const nor_groups[] = {
981 "nor_d", "nor_q", "nor_c", "nor_cs"
982};
983
984static const char * const sd_b_groups[] = {
985 "sd_d1_b", "sd_d0_b", "sd_clk_b", "sd_cmd_b",
986 "sd_d3_b", "sd_d2_b"
987};
988
989static const char * const sdxc_b_groups[] = {
990 "sdxc_d13_b", "sdxc_d0_b", "sdxc_clk_b", "sdxc_cmd_b"
991};
992
993static const char * const uart_ao_groups[] = {
994 "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a"
995};
996
997static const char * const remote_groups[] = {
998 "remote_input"
999};
1000
1001static const char * const i2c_slave_ao_groups[] = {
1002 "i2c_slave_sck_ao", "i2c_slave_sda_ao"
1003};
1004
1005static const char * const uart_ao_b_groups[] = {
1006 "uart_tx_ao_b0", "uart_rx_ao_b0", "uart_tx_ao_b1", "uart_rx_ao_b1"
1007};
1008
1009static const char * const i2c_mst_ao_groups[] = {
1010 "i2c_mst_sck_ao", "i2c_mst_sda_ao"
1011};
1012
1013static struct meson_pmx_func meson8_functions[] = {
1014 FUNCTION(gpio),
1015 FUNCTION(sd_a),
1016 FUNCTION(sdxc_a),
1017 FUNCTION(pcm_a),
1018 FUNCTION(uart_a),
1019 FUNCTION(uart_b),
1020 FUNCTION(iso7816),
1021 FUNCTION(i2c_d),
1022 FUNCTION(xtal),
1023 FUNCTION(uart_c),
1024 FUNCTION(pcm_b),
1025 FUNCTION(i2c_c),
1026 FUNCTION(dvin),
1027 FUNCTION(enc),
1028 FUNCTION(vga),
1029 FUNCTION(hdmi),
1030 FUNCTION(spi),
1031 FUNCTION(ethernet),
1032 FUNCTION(i2c_a),
1033 FUNCTION(i2c_b),
1034 FUNCTION(sd_c),
1035 FUNCTION(sdxc_c),
1036 FUNCTION(nand),
1037 FUNCTION(nor),
1038 FUNCTION(sd_b),
1039 FUNCTION(sdxc_b),
1040 FUNCTION(uart_ao),
1041 FUNCTION(remote),
1042 FUNCTION(i2c_slave_ao),
1043 FUNCTION(uart_ao_b),
1044 FUNCTION(i2c_mst_ao),
1045};
1046
1047static struct meson_bank meson8_banks[] = {
1048 /* name first last pullen pull dir out in */
1049 BANK("X", PIN_GPIOX_0, PIN_GPIOX_21, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
1050 BANK("Y", PIN_GPIOY_0, PIN_GPIOY_16, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
1051 BANK("DV", PIN_GPIODV_0, PIN_GPIODV_29, 0, 0, 0, 0, 7, 0, 8, 0, 9, 0),
1052 BANK("H", PIN_GPIOH_0, PIN_GPIOH_9, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19),
1053 BANK("Z", PIN_GPIOZ_0, PIN_GPIOZ_14, 1, 0, 1, 0, 3, 17, 4, 17, 5, 17),
1054 BANK("CARD", PIN_CARD_0, PIN_CARD_6, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22),
1055 BANK("BOOT", PIN_BOOT_0, PIN_BOOT_18, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
1056};
1057
1058static struct meson_bank meson8_ao_banks[] = {
1059 /* name first last pullen pull dir out in */
1060 BANK("AO", PIN_GPIOAO_0, PIN_GPIO_TEST_N, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
1061};
1062
1063static struct meson_domain_data meson8_domain_data[] = {
1064 {
1065 .name = "banks",
1066 .banks = meson8_banks,
1067 .num_banks = ARRAY_SIZE(meson8_banks),
1068 .pin_base = 0,
1069 .num_pins = 120,
1070 },
1071 {
1072 .name = "ao-bank",
1073 .banks = meson8_ao_banks,
1074 .num_banks = ARRAY_SIZE(meson8_ao_banks),
1075 .pin_base = 120,
1076 .num_pins = 16,
1077 },
1078};
1079
1080struct meson_pinctrl_data meson8_pinctrl_data = {
1081 .pins = meson8_pins,
1082 .groups = meson8_groups,
1083 .funcs = meson8_functions,
1084 .domain_data = meson8_domain_data,
1085 .num_pins = ARRAY_SIZE(meson8_pins),
1086 .num_groups = ARRAY_SIZE(meson8_groups),
1087 .num_funcs = ARRAY_SIZE(meson8_functions),
1088 .num_domains = ARRAY_SIZE(meson8_domain_data),
1089};
diff --git a/include/dt-bindings/gpio/meson8-gpio.h b/include/dt-bindings/gpio/meson8-gpio.h
new file mode 100644
index 000000000000..fdaeb5cbf5e1
--- /dev/null
+++ b/include/dt-bindings/gpio/meson8-gpio.h
@@ -0,0 +1,157 @@
1/*
2 * GPIO definitions for Amlogic Meson8 SoCs
3 *
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * You should have received a copy of the GNU General Public License
11 * along with this program. If not, see <http://www.gnu.org/licenses/>.
12 */
13
14#ifndef _DT_BINDINGS_MESON8_GPIO_H
15#define _DT_BINDINGS_MESON8_GPIO_H
16
17/* First GPIO chip */
18#define GPIOX_0 0
19#define GPIOX_1 1
20#define GPIOX_2 2
21#define GPIOX_3 3
22#define GPIOX_4 4
23#define GPIOX_5 5
24#define GPIOX_6 6
25#define GPIOX_7 7
26#define GPIOX_8 8
27#define GPIOX_9 9
28#define GPIOX_10 10
29#define GPIOX_11 11
30#define GPIOX_12 12
31#define GPIOX_13 13
32#define GPIOX_14 14
33#define GPIOX_15 15
34#define GPIOX_16 16
35#define GPIOX_17 17
36#define GPIOX_18 18
37#define GPIOX_19 19
38#define GPIOX_20 20
39#define GPIOX_21 21
40#define GPIOY_0 22
41#define GPIOY_1 23
42#define GPIOY_2 24
43#define GPIOY_3 25
44#define GPIOY_4 26
45#define GPIOY_5 27
46#define GPIOY_6 28
47#define GPIOY_7 29
48#define GPIOY_8 30
49#define GPIOY_9 31
50#define GPIOY_10 32
51#define GPIOY_11 33
52#define GPIOY_12 34
53#define GPIOY_13 35
54#define GPIOY_14 36
55#define GPIOY_15 37
56#define GPIOY_16 38
57#define GPIODV_0 39
58#define GPIODV_1 40
59#define GPIODV_2 41
60#define GPIODV_3 42
61#define GPIODV_4 43
62#define GPIODV_5 44
63#define GPIODV_6 45
64#define GPIODV_7 46
65#define GPIODV_8 47
66#define GPIODV_9 48
67#define GPIODV_10 49
68#define GPIODV_11 50
69#define GPIODV_12 51
70#define GPIODV_13 52
71#define GPIODV_14 53
72#define GPIODV_15 54
73#define GPIODV_16 55
74#define GPIODV_17 56
75#define GPIODV_18 57
76#define GPIODV_19 58
77#define GPIODV_20 59
78#define GPIODV_21 60
79#define GPIODV_22 61
80#define GPIODV_23 62
81#define GPIODV_24 63
82#define GPIODV_25 64
83#define GPIODV_26 65
84#define GPIODV_27 66
85#define GPIODV_28 67
86#define GPIODV_29 68
87#define GPIOH_0 69
88#define GPIOH_1 70
89#define GPIOH_2 71
90#define GPIOH_3 72
91#define GPIOH_4 73
92#define GPIOH_5 74
93#define GPIOH_6 75
94#define GPIOH_7 76
95#define GPIOH_8 77
96#define GPIOH_9 78
97#define GPIOZ_0 79
98#define GPIOZ_1 80
99#define GPIOZ_2 81
100#define GPIOZ_3 82
101#define GPIOZ_4 83
102#define GPIOZ_5 84
103#define GPIOZ_6 85
104#define GPIOZ_7 86
105#define GPIOZ_8 87
106#define GPIOZ_9 88
107#define GPIOZ_10 89
108#define GPIOZ_11 90
109#define GPIOZ_12 91
110#define GPIOZ_13 92
111#define GPIOZ_14 93
112#define CARD_0 94
113#define CARD_1 95
114#define CARD_2 96
115#define CARD_3 97
116#define CARD_4 98
117#define CARD_5 99
118#define CARD_6 100
119#define BOOT_0 101
120#define BOOT_1 102
121#define BOOT_2 103
122#define BOOT_3 104
123#define BOOT_4 105
124#define BOOT_5 106
125#define BOOT_6 107
126#define BOOT_7 108
127#define BOOT_8 109
128#define BOOT_9 110
129#define BOOT_10 111
130#define BOOT_11 112
131#define BOOT_12 113
132#define BOOT_13 114
133#define BOOT_14 115
134#define BOOT_15 116
135#define BOOT_16 117
136#define BOOT_17 118
137#define BOOT_18 119
138
139/* Second GPIO chip */
140#define GPIOAO_0 0
141#define GPIOAO_1 1
142#define GPIOAO_2 2
143#define GPIOAO_3 3
144#define GPIOAO_4 4
145#define GPIOAO_5 5
146#define GPIOAO_6 6
147#define GPIOAO_7 7
148#define GPIOAO_8 8
149#define GPIOAO_9 9
150#define GPIOAO_10 10
151#define GPIOAO_11 11
152#define GPIOAO_12 12
153#define GPIOAO_13 13
154#define GPIO_BSD_EN 14
155#define GPIO_TEST_N 15
156
157#endif /* _DT_BINDINGS_MESON8_GPIO_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-11 06:24:05 -0400