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authorShirish S <s.shirish@samsung.com>2014-04-03 11:11:02 -0400
committerInki Dae <daeinki@gmail.com>2014-06-01 13:07:15 -0400
commit6a296e20499f8aa15d4939bf3d4c13dbf81c948c (patch)
tree403cb791a1f42c1d17b237e012e20ad537a70c2a
parent85a64f7cc95bef1941d923cf6263460638d6e2ab (diff)
drm/exynos: add hdmiphy power on/off sequence
This patch implements the power on/off sequence of HDMI PHY in exynos5420 and exynos5250 as provided by the hardware team. This has been verified for mulitple iterations of S2R. Signed-off-by: Shirish S <s.shirish@samsung.com> Signed-off-by: Rahul Sharma <Rahul.Sharma@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
-rw-r--r--drivers/gpu/drm/exynos/exynos_hdmi.c40
-rw-r--r--drivers/gpu/drm/exynos/regs-hdmi.h7
2 files changed, 40 insertions, 7 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
index e05c86af9c35..d0f4f5d5a9f9 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -1683,16 +1683,44 @@ static void hdmiphy_conf_reset(struct hdmi_context *hdata)
1683 1683
1684static void hdmiphy_poweron(struct hdmi_context *hdata) 1684static void hdmiphy_poweron(struct hdmi_context *hdata)
1685{ 1685{
1686 if (hdata->type == HDMI_TYPE14) 1686 if (hdata->type != HDMI_TYPE14)
1687 hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, 0, 1687 return;
1688 HDMI_PHY_POWER_OFF_EN); 1688
1689 DRM_DEBUG_KMS("\n");
1690
1691 /* For PHY Mode Setting */
1692 hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1693 HDMI_PHY_ENABLE_MODE_SET);
1694 /* Phy Power On */
1695 hdmiphy_reg_writeb(hdata, HDMIPHY_POWER,
1696 HDMI_PHY_POWER_ON);
1697 /* For PHY Mode Setting */
1698 hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1699 HDMI_PHY_DISABLE_MODE_SET);
1700 /* PHY SW Reset */
1701 hdmiphy_conf_reset(hdata);
1689} 1702}
1690 1703
1691static void hdmiphy_poweroff(struct hdmi_context *hdata) 1704static void hdmiphy_poweroff(struct hdmi_context *hdata)
1692{ 1705{
1693 if (hdata->type == HDMI_TYPE14) 1706 if (hdata->type != HDMI_TYPE14)
1694 hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, ~0, 1707 return;
1695 HDMI_PHY_POWER_OFF_EN); 1708
1709 DRM_DEBUG_KMS("\n");
1710
1711 /* PHY SW Reset */
1712 hdmiphy_conf_reset(hdata);
1713 /* For PHY Mode Setting */
1714 hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1715 HDMI_PHY_ENABLE_MODE_SET);
1716
1717 /* PHY Power Off */
1718 hdmiphy_reg_writeb(hdata, HDMIPHY_POWER,
1719 HDMI_PHY_POWER_OFF);
1720
1721 /* For PHY Mode Setting */
1722 hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1723 HDMI_PHY_DISABLE_MODE_SET);
1696} 1724}
1697 1725
1698static void hdmiphy_conf_apply(struct hdmi_context *hdata) 1726static void hdmiphy_conf_apply(struct hdmi_context *hdata)
diff --git a/drivers/gpu/drm/exynos/regs-hdmi.h b/drivers/gpu/drm/exynos/regs-hdmi.h
index 6d846b979045..3f35ac6d8a47 100644
--- a/drivers/gpu/drm/exynos/regs-hdmi.h
+++ b/drivers/gpu/drm/exynos/regs-hdmi.h
@@ -579,7 +579,12 @@
579#define HDMI_TG_3D HDMI_TG_BASE(0x00F0) 579#define HDMI_TG_3D HDMI_TG_BASE(0x00F0)
580 580
581/* HDMI PHY Registers Offsets*/ 581/* HDMI PHY Registers Offsets*/
582#define HDMIPHY_MODE_SET_DONE (0x7C >> 2) 582#define HDMIPHY_POWER (0x74 >> 2)
583#define HDMIPHY_MODE_SET_DONE (0x7c >> 2)
584
585/* HDMI PHY Values */
586#define HDMI_PHY_POWER_ON 0x80
587#define HDMI_PHY_POWER_OFF 0xff
583 588
584/* HDMI PHY Values */ 589/* HDMI PHY Values */
585#define HDMI_PHY_DISABLE_MODE_SET 0x80 590#define HDMI_PHY_DISABLE_MODE_SET 0x80