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authorAlex Deucher <alexander.deucher@amd.com>2016-09-13 00:06:07 -0400
committerAlex Deucher <alexander.deucher@amd.com>2016-09-14 15:10:40 -0400
commit6861c837e28e1b1300a1b24ddab748c8ee50da3b (patch)
tree2118a141ef6a7d31b8e3d65104aeedbd3b235138
parenta1047777323cc5da8f59d738708f554937be3193 (diff)
drm/amdgpu/si/dpm: fix symbol conflicts with radeon
Acked-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si_dpm.c287
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si_smc.c37
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sislands_smc.h30
3 files changed, 181 insertions, 173 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 374d92b96519..e2db4a734676 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -2274,12 +2274,12 @@ static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
2274 smc_table->dpm2Params.SafePowerLimit = 2274 smc_table->dpm2Params.SafePowerLimit =
2275 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2275 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2276 2276
2277 ret = si_copy_bytes_to_smc(adev, 2277 ret = amdgpu_si_copy_bytes_to_smc(adev,
2278 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2278 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2279 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2279 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2280 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2280 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2281 sizeof(u32) * 3, 2281 sizeof(u32) * 3,
2282 si_pi->sram_end); 2282 si_pi->sram_end);
2283 if (ret) 2283 if (ret)
2284 return ret; 2284 return ret;
2285 2285
@@ -2293,10 +2293,10 @@ static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
2293 papm_parm->PlatformPowerLimit = 0xffffffff; 2293 papm_parm->PlatformPowerLimit = 0xffffffff;
2294 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2294 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2295 2295
2296 ret = si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start, 2296 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
2297 (u8 *)papm_parm, 2297 (u8 *)papm_parm,
2298 sizeof(PP_SIslands_PAPMParameters), 2298 sizeof(PP_SIslands_PAPMParameters),
2299 si_pi->sram_end); 2299 si_pi->sram_end);
2300 if (ret) 2300 if (ret)
2301 return ret; 2301 return ret;
2302 } 2302 }
@@ -2322,13 +2322,13 @@ static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev,
2322 smc_table->dpm2Params.SafePowerLimit = 2322 smc_table->dpm2Params.SafePowerLimit =
2323 cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2323 cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2324 2324
2325 ret = si_copy_bytes_to_smc(adev, 2325 ret = amdgpu_si_copy_bytes_to_smc(adev,
2326 (si_pi->state_table_start + 2326 (si_pi->state_table_start +
2327 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2327 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2328 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2328 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2329 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2329 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2330 sizeof(u32) * 2, 2330 sizeof(u32) * 2,
2331 si_pi->sram_end); 2331 si_pi->sram_end);
2332 if (ret) 2332 if (ret)
2333 return ret; 2333 return ret;
2334 } 2334 }
@@ -2538,7 +2538,7 @@ static int si_enable_power_containment(struct amdgpu_device *adev,
2538 if (ni_pi->enable_power_containment) { 2538 if (ni_pi->enable_power_containment) {
2539 if (enable) { 2539 if (enable) {
2540 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) { 2540 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2541 smc_result = si_send_msg_to_smc(adev, PPSMC_TDPClampingActive); 2541 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
2542 if (smc_result != PPSMC_Result_OK) { 2542 if (smc_result != PPSMC_Result_OK) {
2543 ret = -EINVAL; 2543 ret = -EINVAL;
2544 ni_pi->pc_enabled = false; 2544 ni_pi->pc_enabled = false;
@@ -2547,7 +2547,7 @@ static int si_enable_power_containment(struct amdgpu_device *adev,
2547 } 2547 }
2548 } 2548 }
2549 } else { 2549 } else {
2550 smc_result = si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive); 2550 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
2551 if (smc_result != PPSMC_Result_OK) 2551 if (smc_result != PPSMC_Result_OK)
2552 ret = -EINVAL; 2552 ret = -EINVAL;
2553 ni_pi->pc_enabled = false; 2553 ni_pi->pc_enabled = false;
@@ -2615,8 +2615,10 @@ static int si_initialize_smc_dte_tables(struct amdgpu_device *adev)
2615 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2615 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2616 } 2616 }
2617 2617
2618 ret = si_copy_bytes_to_smc(adev, si_pi->dte_table_start, (u8 *)dte_tables, 2618 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start,
2619 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2619 (u8 *)dte_tables,
2620 sizeof(Smc_SIslands_DTE_Configuration),
2621 si_pi->sram_end);
2620 kfree(dte_tables); 2622 kfree(dte_tables);
2621 2623
2622 return ret; 2624 return ret;
@@ -2806,8 +2808,10 @@ static int si_initialize_smc_cac_tables(struct amdgpu_device *adev)
2806 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2808 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2807 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2809 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2808 2810
2809 ret = si_copy_bytes_to_smc(adev, si_pi->cac_table_start, (u8 *)cac_tables, 2811 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start,
2810 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2812 (u8 *)cac_tables,
2813 sizeof(PP_SIslands_CacConfig),
2814 si_pi->sram_end);
2811 2815
2812 if (ret) 2816 if (ret)
2813 goto done_free; 2817 goto done_free;
@@ -2900,12 +2904,12 @@ static int si_enable_smc_cac(struct amdgpu_device *adev,
2900 if (enable) { 2904 if (enable) {
2901 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) { 2905 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2902 if (ni_pi->support_cac_long_term_average) { 2906 if (ni_pi->support_cac_long_term_average) {
2903 smc_result = si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable); 2907 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
2904 if (smc_result != PPSMC_Result_OK) 2908 if (smc_result != PPSMC_Result_OK)
2905 ni_pi->support_cac_long_term_average = false; 2909 ni_pi->support_cac_long_term_average = false;
2906 } 2910 }
2907 2911
2908 smc_result = si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac); 2912 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
2909 if (smc_result != PPSMC_Result_OK) { 2913 if (smc_result != PPSMC_Result_OK) {
2910 ret = -EINVAL; 2914 ret = -EINVAL;
2911 ni_pi->cac_enabled = false; 2915 ni_pi->cac_enabled = false;
@@ -2914,21 +2918,21 @@ static int si_enable_smc_cac(struct amdgpu_device *adev,
2914 } 2918 }
2915 2919
2916 if (si_pi->enable_dte) { 2920 if (si_pi->enable_dte) {
2917 smc_result = si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE); 2921 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
2918 if (smc_result != PPSMC_Result_OK) 2922 if (smc_result != PPSMC_Result_OK)
2919 ret = -EINVAL; 2923 ret = -EINVAL;
2920 } 2924 }
2921 } 2925 }
2922 } else if (ni_pi->cac_enabled) { 2926 } else if (ni_pi->cac_enabled) {
2923 if (si_pi->enable_dte) 2927 if (si_pi->enable_dte)
2924 smc_result = si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE); 2928 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
2925 2929
2926 smc_result = si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac); 2930 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
2927 2931
2928 ni_pi->cac_enabled = false; 2932 ni_pi->cac_enabled = false;
2929 2933
2930 if (ni_pi->support_cac_long_term_average) 2934 if (ni_pi->support_cac_long_term_average)
2931 smc_result = si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable); 2935 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
2932 } 2936 }
2933 } 2937 }
2934 return ret; 2938 return ret;
@@ -2992,9 +2996,10 @@ static int si_init_smc_spll_table(struct amdgpu_device *adev)
2992 2996
2993 2997
2994 if (!ret) 2998 if (!ret)
2995 ret = si_copy_bytes_to_smc(adev, si_pi->spll_table_start, 2999 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start,
2996 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 3000 (u8 *)spll_table,
2997 si_pi->sram_end); 3001 sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
3002 si_pi->sram_end);
2998 3003
2999 if (ret) 3004 if (ret)
3000 ni_pi->enable_power_containment = false; 3005 ni_pi->enable_power_containment = false;
@@ -3664,9 +3669,9 @@ static int si_read_smc_soft_register(struct amdgpu_device *adev,
3664{ 3669{
3665 struct si_power_info *si_pi = si_get_pi(adev); 3670 struct si_power_info *si_pi = si_get_pi(adev);
3666 3671
3667 return si_read_smc_sram_dword(adev, 3672 return amdgpu_si_read_smc_sram_dword(adev,
3668 si_pi->soft_regs_start + reg_offset, value, 3673 si_pi->soft_regs_start + reg_offset, value,
3669 si_pi->sram_end); 3674 si_pi->sram_end);
3670} 3675}
3671#endif 3676#endif
3672 3677
@@ -3675,9 +3680,9 @@ static int si_write_smc_soft_register(struct amdgpu_device *adev,
3675{ 3680{
3676 struct si_power_info *si_pi = si_get_pi(adev); 3681 struct si_power_info *si_pi = si_get_pi(adev);
3677 3682
3678 return si_write_smc_sram_dword(adev, 3683 return amdgpu_si_write_smc_sram_dword(adev,
3679 si_pi->soft_regs_start + reg_offset, 3684 si_pi->soft_regs_start + reg_offset,
3680 value, si_pi->sram_end); 3685 value, si_pi->sram_end);
3681} 3686}
3682 3687
3683static bool si_is_special_1gb_platform(struct amdgpu_device *adev) 3688static bool si_is_special_1gb_platform(struct amdgpu_device *adev)
@@ -3834,7 +3839,7 @@ static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev,
3834 PPSMC_Result ret; 3839 PPSMC_Result ret;
3835 3840
3836 if (thermal_level == 0) { 3841 if (thermal_level == 0) {
3837 ret = si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt); 3842 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
3838 if (ret == PPSMC_Result_OK) 3843 if (ret == PPSMC_Result_OK)
3839 return 0; 3844 return 0;
3840 else 3845 else
@@ -3853,7 +3858,7 @@ static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev)
3853static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power) 3858static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)
3854{ 3859{
3855 if (ac_power) 3860 if (ac_power)
3856 return (si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3861 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3857 0 : -EINVAL; 3862 0 : -EINVAL;
3858 3863
3859 return 0; 3864 return 0;
@@ -3864,12 +3869,12 @@ static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev
3864 PPSMC_Msg msg, u32 parameter) 3869 PPSMC_Msg msg, u32 parameter)
3865{ 3870{
3866 WREG32(SMC_SCRATCH0, parameter); 3871 WREG32(SMC_SCRATCH0, parameter);
3867 return si_send_msg_to_smc(adev, msg); 3872 return amdgpu_si_send_msg_to_smc(adev, msg);
3868} 3873}
3869 3874
3870static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev) 3875static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev)
3871{ 3876{
3872 if (si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3877 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3873 return -EINVAL; 3878 return -EINVAL;
3874 3879
3875 return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3880 return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
@@ -3911,46 +3916,46 @@ static int si_dpm_force_performance_level(struct amdgpu_device *adev,
3911#if 0 3916#if 0
3912static int si_set_boot_state(struct amdgpu_device *adev) 3917static int si_set_boot_state(struct amdgpu_device *adev)
3913{ 3918{
3914 return (si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3919 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3915 0 : -EINVAL; 3920 0 : -EINVAL;
3916} 3921}
3917#endif 3922#endif
3918 3923
3919static int si_set_sw_state(struct amdgpu_device *adev) 3924static int si_set_sw_state(struct amdgpu_device *adev)
3920{ 3925{
3921 return (si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3926 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3922 0 : -EINVAL; 3927 0 : -EINVAL;
3923} 3928}
3924 3929
3925static int si_halt_smc(struct amdgpu_device *adev) 3930static int si_halt_smc(struct amdgpu_device *adev)
3926{ 3931{
3927 if (si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3932 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3928 return -EINVAL; 3933 return -EINVAL;
3929 3934
3930 return (si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ? 3935 return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?
3931 0 : -EINVAL; 3936 0 : -EINVAL;
3932} 3937}
3933 3938
3934static int si_resume_smc(struct amdgpu_device *adev) 3939static int si_resume_smc(struct amdgpu_device *adev)
3935{ 3940{
3936 if (si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3941 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3937 return -EINVAL; 3942 return -EINVAL;
3938 3943
3939 return (si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3944 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3940 0 : -EINVAL; 3945 0 : -EINVAL;
3941} 3946}
3942 3947
3943static void si_dpm_start_smc(struct amdgpu_device *adev) 3948static void si_dpm_start_smc(struct amdgpu_device *adev)
3944{ 3949{
3945 si_program_jump_on_start(adev); 3950 amdgpu_si_program_jump_on_start(adev);
3946 si_start_smc(adev); 3951 amdgpu_si_start_smc(adev);
3947 si_smc_clock(adev, true); 3952 amdgpu_si_smc_clock(adev, true);
3948} 3953}
3949 3954
3950static void si_dpm_stop_smc(struct amdgpu_device *adev) 3955static void si_dpm_stop_smc(struct amdgpu_device *adev)
3951{ 3956{
3952 si_reset_smc(adev); 3957 amdgpu_si_reset_smc(adev);
3953 si_smc_clock(adev, false); 3958 amdgpu_si_smc_clock(adev, false);
3954} 3959}
3955 3960
3956static int si_process_firmware_header(struct amdgpu_device *adev) 3961static int si_process_firmware_header(struct amdgpu_device *adev)
@@ -3959,82 +3964,82 @@ static int si_process_firmware_header(struct amdgpu_device *adev)
3959 u32 tmp; 3964 u32 tmp;
3960 int ret; 3965 int ret;
3961 3966
3962 ret = si_read_smc_sram_dword(adev, 3967 ret = amdgpu_si_read_smc_sram_dword(adev,
3963 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3968 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3964 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3969 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3965 &tmp, si_pi->sram_end); 3970 &tmp, si_pi->sram_end);
3966 if (ret) 3971 if (ret)
3967 return ret; 3972 return ret;
3968 3973
3969 si_pi->state_table_start = tmp; 3974 si_pi->state_table_start = tmp;
3970 3975
3971 ret = si_read_smc_sram_dword(adev, 3976 ret = amdgpu_si_read_smc_sram_dword(adev,
3972 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3977 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3973 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3978 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3974 &tmp, si_pi->sram_end); 3979 &tmp, si_pi->sram_end);
3975 if (ret) 3980 if (ret)
3976 return ret; 3981 return ret;
3977 3982
3978 si_pi->soft_regs_start = tmp; 3983 si_pi->soft_regs_start = tmp;
3979 3984
3980 ret = si_read_smc_sram_dword(adev, 3985 ret = amdgpu_si_read_smc_sram_dword(adev,
3981 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3986 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3982 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3987 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3983 &tmp, si_pi->sram_end); 3988 &tmp, si_pi->sram_end);
3984 if (ret) 3989 if (ret)
3985 return ret; 3990 return ret;
3986 3991
3987 si_pi->mc_reg_table_start = tmp; 3992 si_pi->mc_reg_table_start = tmp;
3988 3993
3989 ret = si_read_smc_sram_dword(adev, 3994 ret = amdgpu_si_read_smc_sram_dword(adev,
3990 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3995 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3991 SISLANDS_SMC_FIRMWARE_HEADER_fanTable, 3996 SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3992 &tmp, si_pi->sram_end); 3997 &tmp, si_pi->sram_end);
3993 if (ret) 3998 if (ret)
3994 return ret; 3999 return ret;
3995 4000
3996 si_pi->fan_table_start = tmp; 4001 si_pi->fan_table_start = tmp;
3997 4002
3998 ret = si_read_smc_sram_dword(adev, 4003 ret = amdgpu_si_read_smc_sram_dword(adev,
3999 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4004 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4000 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 4005 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
4001 &tmp, si_pi->sram_end); 4006 &tmp, si_pi->sram_end);
4002 if (ret) 4007 if (ret)
4003 return ret; 4008 return ret;
4004 4009
4005 si_pi->arb_table_start = tmp; 4010 si_pi->arb_table_start = tmp;
4006 4011
4007 ret = si_read_smc_sram_dword(adev, 4012 ret = amdgpu_si_read_smc_sram_dword(adev,
4008 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4013 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4009 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 4014 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
4010 &tmp, si_pi->sram_end); 4015 &tmp, si_pi->sram_end);
4011 if (ret) 4016 if (ret)
4012 return ret; 4017 return ret;
4013 4018
4014 si_pi->cac_table_start = tmp; 4019 si_pi->cac_table_start = tmp;
4015 4020
4016 ret = si_read_smc_sram_dword(adev, 4021 ret = amdgpu_si_read_smc_sram_dword(adev,
4017 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4022 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4018 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 4023 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
4019 &tmp, si_pi->sram_end); 4024 &tmp, si_pi->sram_end);
4020 if (ret) 4025 if (ret)
4021 return ret; 4026 return ret;
4022 4027
4023 si_pi->dte_table_start = tmp; 4028 si_pi->dte_table_start = tmp;
4024 4029
4025 ret = si_read_smc_sram_dword(adev, 4030 ret = amdgpu_si_read_smc_sram_dword(adev,
4026 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4031 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4027 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 4032 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
4028 &tmp, si_pi->sram_end); 4033 &tmp, si_pi->sram_end);
4029 if (ret) 4034 if (ret)
4030 return ret; 4035 return ret;
4031 4036
4032 si_pi->spll_table_start = tmp; 4037 si_pi->spll_table_start = tmp;
4033 4038
4034 ret = si_read_smc_sram_dword(adev, 4039 ret = amdgpu_si_read_smc_sram_dword(adev,
4035 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4040 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4036 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 4041 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
4037 &tmp, si_pi->sram_end); 4042 &tmp, si_pi->sram_end);
4038 if (ret) 4043 if (ret)
4039 return ret; 4044 return ret;
4040 4045
@@ -4112,7 +4117,7 @@ static int si_notify_smc_display_change(struct amdgpu_device *adev,
4112 PPSMC_Msg msg = has_display ? 4117 PPSMC_Msg msg = has_display ?
4113 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 4118 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
4114 4119
4115 return (si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ? 4120 return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?
4116 0 : -EINVAL; 4121 0 : -EINVAL;
4117} 4122}
4118 4123
@@ -4365,10 +4370,10 @@ static int si_upload_firmware(struct amdgpu_device *adev)
4365{ 4370{
4366 struct si_power_info *si_pi = si_get_pi(adev); 4371 struct si_power_info *si_pi = si_get_pi(adev);
4367 4372
4368 si_reset_smc(adev); 4373 amdgpu_si_reset_smc(adev);
4369 si_smc_clock(adev, false); 4374 amdgpu_si_smc_clock(adev, false);
4370 4375
4371 return si_load_smc_ucode(adev, si_pi->sram_end); 4376 return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end);
4372} 4377}
4373 4378
4374static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev, 4379static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
@@ -4712,14 +4717,16 @@ static int si_init_arb_table_index(struct amdgpu_device *adev)
4712 u32 tmp; 4717 u32 tmp;
4713 int ret; 4718 int ret;
4714 4719
4715 ret = si_read_smc_sram_dword(adev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 4720 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4721 &tmp, si_pi->sram_end);
4716 if (ret) 4722 if (ret)
4717 return ret; 4723 return ret;
4718 4724
4719 tmp &= 0x00FFFFFF; 4725 tmp &= 0x00FFFFFF;
4720 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4726 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4721 4727
4722 return si_write_smc_sram_dword(adev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4728 return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start,
4729 tmp, si_pi->sram_end);
4723} 4730}
4724 4731
4725static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev) 4732static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
@@ -4729,7 +4736,7 @@ static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
4729 4736
4730static int si_reset_to_default(struct amdgpu_device *adev) 4737static int si_reset_to_default(struct amdgpu_device *adev)
4731{ 4738{
4732 return (si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4739 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4733 0 : -EINVAL; 4740 0 : -EINVAL;
4734} 4741}
4735 4742
@@ -4739,8 +4746,8 @@ static int si_force_switch_to_arb_f0(struct amdgpu_device *adev)
4739 u32 tmp; 4746 u32 tmp;
4740 int ret; 4747 int ret;
4741 4748
4742 ret = si_read_smc_sram_dword(adev, si_pi->arb_table_start, 4749 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4743 &tmp, si_pi->sram_end); 4750 &tmp, si_pi->sram_end);
4744 if (ret) 4751 if (ret)
4745 return ret; 4752 return ret;
4746 4753
@@ -4810,13 +4817,13 @@ static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev,
4810 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs); 4817 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);
4811 if (ret) 4818 if (ret)
4812 break; 4819 break;
4813 ret = si_copy_bytes_to_smc(adev, 4820 ret = amdgpu_si_copy_bytes_to_smc(adev,
4814 si_pi->arb_table_start + 4821 si_pi->arb_table_start +
4815 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4822 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4816 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4823 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4817 (u8 *)&arb_regs, 4824 (u8 *)&arb_regs,
4818 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4825 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4819 si_pi->sram_end); 4826 si_pi->sram_end);
4820 if (ret) 4827 if (ret)
4821 break; 4828 break;
4822 } 4829 }
@@ -5152,13 +5159,13 @@ static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev)
5152 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 5159 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
5153 ulv->volt_change_delay); 5160 ulv->volt_change_delay);
5154 5161
5155 ret = si_copy_bytes_to_smc(adev, 5162 ret = amdgpu_si_copy_bytes_to_smc(adev,
5156 si_pi->arb_table_start + 5163 si_pi->arb_table_start +
5157 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 5164 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
5158 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 5165 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
5159 (u8 *)&arb_regs, 5166 (u8 *)&arb_regs,
5160 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 5167 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
5161 si_pi->sram_end); 5168 si_pi->sram_end);
5162 5169
5163 return ret; 5170 return ret;
5164} 5171}
@@ -5252,9 +5259,9 @@ static int si_init_smc_table(struct amdgpu_device *adev)
5252 table->ULVState = table->initialState; 5259 table->ULVState = table->initialState;
5253 } 5260 }
5254 5261
5255 return si_copy_bytes_to_smc(adev, si_pi->state_table_start, 5262 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start,
5256 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 5263 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
5257 si_pi->sram_end); 5264 si_pi->sram_end);
5258} 5265}
5259 5266
5260static int si_calculate_sclk_params(struct amdgpu_device *adev, 5267static int si_calculate_sclk_params(struct amdgpu_device *adev,
@@ -5616,7 +5623,7 @@ static int si_disable_ulv(struct amdgpu_device *adev)
5616 struct si_ulv_param *ulv = &si_pi->ulv; 5623 struct si_ulv_param *ulv = &si_pi->ulv;
5617 5624
5618 if (ulv->supported) 5625 if (ulv->supported)
5619 return (si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 5626 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5620 0 : -EINVAL; 5627 0 : -EINVAL;
5621 5628
5622 return 0; 5629 return 0;
@@ -5658,7 +5665,7 @@ static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *ade
5658 5665
5659 if (ulv->supported) { 5666 if (ulv->supported) {
5660 if (si_is_state_ulv_compatible(adev, amdgpu_new_state)) 5667 if (si_is_state_ulv_compatible(adev, amdgpu_new_state))
5661 return (si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5668 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5662 0 : -EINVAL; 5669 0 : -EINVAL;
5663 } 5670 }
5664 return 0; 5671 return 0;
@@ -5763,8 +5770,8 @@ static int si_upload_sw_state(struct amdgpu_device *adev,
5763 if (ret) 5770 if (ret)
5764 return ret; 5771 return ret;
5765 5772
5766 return si_copy_bytes_to_smc(adev, address, (u8 *)smc_state, 5773 return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5767 state_size, si_pi->sram_end); 5774 state_size, si_pi->sram_end);
5768} 5775}
5769 5776
5770static int si_upload_ulv_state(struct amdgpu_device *adev) 5777static int si_upload_ulv_state(struct amdgpu_device *adev)
@@ -5783,8 +5790,8 @@ static int si_upload_ulv_state(struct amdgpu_device *adev)
5783 5790
5784 ret = si_populate_ulv_state(adev, smc_state); 5791 ret = si_populate_ulv_state(adev, smc_state);
5785 if (!ret) 5792 if (!ret)
5786 ret = si_copy_bytes_to_smc(adev, address, (u8 *)smc_state, 5793 ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5787 state_size, si_pi->sram_end); 5794 state_size, si_pi->sram_end);
5788 } 5795 }
5789 5796
5790 return ret; 5797 return ret;
@@ -6155,9 +6162,9 @@ static int si_populate_mc_reg_table(struct amdgpu_device *adev,
6155 6162
6156 si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table); 6163 si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table);
6157 6164
6158 return si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start, 6165 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,
6159 (u8 *)smc_mc_reg_table, 6166 (u8 *)smc_mc_reg_table,
6160 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 6167 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
6161} 6168}
6162 6169
6163static int si_upload_mc_reg_table(struct amdgpu_device *adev, 6170static int si_upload_mc_reg_table(struct amdgpu_device *adev,
@@ -6174,10 +6181,10 @@ static int si_upload_mc_reg_table(struct amdgpu_device *adev,
6174 6181
6175 si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table); 6182 si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);
6176 6183
6177 return si_copy_bytes_to_smc(adev, address, 6184 return amdgpu_si_copy_bytes_to_smc(adev, address,
6178 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 6185 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
6179 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 6186 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
6180 si_pi->sram_end); 6187 si_pi->sram_end);
6181} 6188}
6182 6189
6183static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable) 6190static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
@@ -6285,11 +6292,11 @@ static int si_ds_request(struct amdgpu_device *adev,
6285 6292
6286 if (eg_pi->sclk_deep_sleep) { 6293 if (eg_pi->sclk_deep_sleep) {
6287 if (ds_status_on) 6294 if (ds_status_on)
6288 return (si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 6295 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
6289 PPSMC_Result_OK) ? 6296 PPSMC_Result_OK) ?
6290 0 : -EINVAL; 6297 0 : -EINVAL;
6291 else 6298 else
6292 return (si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 6299 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
6293 PPSMC_Result_OK) ? 0 : -EINVAL; 6300 PPSMC_Result_OK) ? 0 : -EINVAL;
6294 } 6301 }
6295 return 0; 6302 return 0;
@@ -6420,7 +6427,7 @@ static int si_thermal_enable_alert(struct amdgpu_device *adev,
6420 6427
6421 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 6428 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6422 WREG32(CG_THERMAL_INT, thermal_int); 6429 WREG32(CG_THERMAL_INT, thermal_int);
6423 result = si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt); 6430 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
6424 if (result != PPSMC_Result_OK) { 6431 if (result != PPSMC_Result_OK) {
6425 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 6432 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6426 return -EINVAL; 6433 return -EINVAL;
@@ -6535,11 +6542,11 @@ static int si_thermal_setup_fan_table(struct amdgpu_device *adev)
6535 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; 6542 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6536 fan_table.temp_src = (uint8_t)tmp; 6543 fan_table.temp_src = (uint8_t)tmp;
6537 6544
6538 ret = si_copy_bytes_to_smc(adev, 6545 ret = amdgpu_si_copy_bytes_to_smc(adev,
6539 si_pi->fan_table_start, 6546 si_pi->fan_table_start,
6540 (u8 *)(&fan_table), 6547 (u8 *)(&fan_table),
6541 sizeof(fan_table), 6548 sizeof(fan_table),
6542 si_pi->sram_end); 6549 si_pi->sram_end);
6543 6550
6544 if (ret) { 6551 if (ret) {
6545 DRM_ERROR("Failed to load fan table to the SMC."); 6552 DRM_ERROR("Failed to load fan table to the SMC.");
@@ -6554,7 +6561,7 @@ static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
6554 struct si_power_info *si_pi = si_get_pi(adev); 6561 struct si_power_info *si_pi = si_get_pi(adev);
6555 PPSMC_Result ret; 6562 PPSMC_Result ret;
6556 6563
6557 ret = si_send_msg_to_smc(adev, PPSMC_StartFanControl); 6564 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl);
6558 if (ret == PPSMC_Result_OK) { 6565 if (ret == PPSMC_Result_OK) {
6559 si_pi->fan_is_controlled_by_smc = true; 6566 si_pi->fan_is_controlled_by_smc = true;
6560 return 0; 6567 return 0;
@@ -6568,7 +6575,7 @@ static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
6568 struct si_power_info *si_pi = si_get_pi(adev); 6575 struct si_power_info *si_pi = si_get_pi(adev);
6569 PPSMC_Result ret; 6576 PPSMC_Result ret;
6570 6577
6571 ret = si_send_msg_to_smc(adev, PPSMC_StopFanControl); 6578 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl);
6572 6579
6573 if (ret == PPSMC_Result_OK) { 6580 if (ret == PPSMC_Result_OK) {
6574 si_pi->fan_is_controlled_by_smc = false; 6581 si_pi->fan_is_controlled_by_smc = false;
@@ -6799,7 +6806,7 @@ static int si_dpm_enable(struct amdgpu_device *adev)
6799 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; 6806 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6800 int ret; 6807 int ret;
6801 6808
6802 if (si_is_smc_running(adev)) 6809 if (amdgpu_si_is_smc_running(adev))
6803 return -EINVAL; 6810 return -EINVAL;
6804 if (pi->voltage_control || si_pi->voltage_control_svi2) 6811 if (pi->voltage_control || si_pi->voltage_control_svi2)
6805 si_enable_voltage_control(adev, true); 6812 si_enable_voltage_control(adev, true);
@@ -6930,7 +6937,7 @@ static void si_dpm_disable(struct amdgpu_device *adev)
6930 struct rv7xx_power_info *pi = rv770_get_pi(adev); 6937 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6931 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; 6938 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6932 6939
6933 if (!si_is_smc_running(adev)) 6940 if (!amdgpu_si_is_smc_running(adev))
6934 return; 6941 return;
6935 si_thermal_stop_thermal_controller(adev); 6942 si_thermal_stop_thermal_controller(adev);
6936 si_disable_ulv(adev); 6943 si_disable_ulv(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/si_smc.c b/drivers/gpu/drm/amd/amdgpu/si_smc.c
index 47bbb40e7014..668ba99d6c05 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_smc.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_smc.c
@@ -44,9 +44,9 @@ static int si_set_smc_sram_address(struct amdgpu_device *adev,
44 return 0; 44 return 0;
45} 45}
46 46
47int si_copy_bytes_to_smc(struct amdgpu_device *adev, 47int amdgpu_si_copy_bytes_to_smc(struct amdgpu_device *adev,
48 u32 smc_start_address, 48 u32 smc_start_address,
49 const u8 *src, u32 byte_count, u32 limit) 49 const u8 *src, u32 byte_count, u32 limit)
50{ 50{
51 unsigned long flags; 51 unsigned long flags;
52 int ret = 0; 52 int ret = 0;
@@ -108,7 +108,7 @@ done:
108 return ret; 108 return ret;
109} 109}
110 110
111void si_start_smc(struct amdgpu_device *adev) 111void amdgpu_si_start_smc(struct amdgpu_device *adev)
112{ 112{
113 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); 113 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
114 114
@@ -117,7 +117,7 @@ void si_start_smc(struct amdgpu_device *adev)
117 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); 117 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
118} 118}
119 119
120void si_reset_smc(struct amdgpu_device *adev) 120void amdgpu_si_reset_smc(struct amdgpu_device *adev)
121{ 121{
122 u32 tmp; 122 u32 tmp;
123 123
@@ -131,14 +131,14 @@ void si_reset_smc(struct amdgpu_device *adev)
131 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); 131 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
132} 132}
133 133
134int si_program_jump_on_start(struct amdgpu_device *adev) 134int amdgpu_si_program_jump_on_start(struct amdgpu_device *adev)
135{ 135{
136 static const u8 data[] = { 0x0E, 0x00, 0x40, 0x40 }; 136 static const u8 data[] = { 0x0E, 0x00, 0x40, 0x40 };
137 137
138 return si_copy_bytes_to_smc(adev, 0x0, data, 4, sizeof(data)+1); 138 return amdgpu_si_copy_bytes_to_smc(adev, 0x0, data, 4, sizeof(data)+1);
139} 139}
140 140
141void si_smc_clock(struct amdgpu_device *adev, bool enable) 141void amdgpu_si_smc_clock(struct amdgpu_device *adev, bool enable)
142{ 142{
143 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); 143 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
144 144
@@ -150,7 +150,7 @@ void si_smc_clock(struct amdgpu_device *adev, bool enable)
150 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); 150 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
151} 151}
152 152
153bool si_is_smc_running(struct amdgpu_device *adev) 153bool amdgpu_si_is_smc_running(struct amdgpu_device *adev)
154{ 154{
155 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL); 155 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
156 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); 156 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
@@ -161,12 +161,13 @@ bool si_is_smc_running(struct amdgpu_device *adev)
161 return false; 161 return false;
162} 162}
163 163
164PPSMC_Result si_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg) 164PPSMC_Result amdgpu_si_send_msg_to_smc(struct amdgpu_device *adev,
165 PPSMC_Msg msg)
165{ 166{
166 u32 tmp; 167 u32 tmp;
167 int i; 168 int i;
168 169
169 if (!si_is_smc_running(adev)) 170 if (!amdgpu_si_is_smc_running(adev))
170 return PPSMC_Result_Failed; 171 return PPSMC_Result_Failed;
171 172
172 WREG32(SMC_MESSAGE_0, msg); 173 WREG32(SMC_MESSAGE_0, msg);
@@ -181,12 +182,12 @@ PPSMC_Result si_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg)
181 return (PPSMC_Result)RREG32(SMC_RESP_0); 182 return (PPSMC_Result)RREG32(SMC_RESP_0);
182} 183}
183 184
184PPSMC_Result si_wait_for_smc_inactive(struct amdgpu_device *adev) 185PPSMC_Result amdgpu_si_wait_for_smc_inactive(struct amdgpu_device *adev)
185{ 186{
186 u32 tmp; 187 u32 tmp;
187 int i; 188 int i;
188 189
189 if (!si_is_smc_running(adev)) 190 if (!amdgpu_si_is_smc_running(adev))
190 return PPSMC_Result_OK; 191 return PPSMC_Result_OK;
191 192
192 for (i = 0; i < adev->usec_timeout; i++) { 193 for (i = 0; i < adev->usec_timeout; i++) {
@@ -199,7 +200,7 @@ PPSMC_Result si_wait_for_smc_inactive(struct amdgpu_device *adev)
199 return PPSMC_Result_OK; 200 return PPSMC_Result_OK;
200} 201}
201 202
202int si_load_smc_ucode(struct amdgpu_device *adev, u32 limit) 203int amdgpu_si_load_smc_ucode(struct amdgpu_device *adev, u32 limit)
203{ 204{
204 const struct smc_firmware_header_v1_0 *hdr; 205 const struct smc_firmware_header_v1_0 *hdr;
205 unsigned long flags; 206 unsigned long flags;
@@ -241,8 +242,8 @@ int si_load_smc_ucode(struct amdgpu_device *adev, u32 limit)
241 return 0; 242 return 0;
242} 243}
243 244
244int si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, 245int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
245 u32 *value, u32 limit) 246 u32 *value, u32 limit)
246{ 247{
247 unsigned long flags; 248 unsigned long flags;
248 int ret; 249 int ret;
@@ -256,8 +257,8 @@ int si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
256 return ret; 257 return ret;
257} 258}
258 259
259int si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, 260int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
260 u32 value, u32 limit) 261 u32 value, u32 limit)
261{ 262{
262 unsigned long flags; 263 unsigned long flags;
263 int ret; 264 int ret;
diff --git a/drivers/gpu/drm/amd/amdgpu/sislands_smc.h b/drivers/gpu/drm/amd/amdgpu/sislands_smc.h
index c5b3377df2da..ee4b846e58fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/sislands_smc.h
+++ b/drivers/gpu/drm/amd/amdgpu/sislands_smc.h
@@ -402,21 +402,21 @@ typedef struct Smc_SIslands_DTE_Configuration Smc_SIslands_DTE_Configuration;
402 402
403#pragma pack(pop) 403#pragma pack(pop)
404 404
405int si_copy_bytes_to_smc(struct amdgpu_device *adev, 405int amdgpu_si_copy_bytes_to_smc(struct amdgpu_device *adev,
406 u32 smc_start_address, 406 u32 smc_start_address,
407 const u8 *src, u32 byte_count, u32 limit); 407 const u8 *src, u32 byte_count, u32 limit);
408void si_start_smc(struct amdgpu_device *adev); 408void amdgpu_si_start_smc(struct amdgpu_device *adev);
409void si_reset_smc(struct amdgpu_device *adev); 409void amdgpu_si_reset_smc(struct amdgpu_device *adev);
410int si_program_jump_on_start(struct amdgpu_device *adev); 410int amdgpu_si_program_jump_on_start(struct amdgpu_device *adev);
411void si_smc_clock(struct amdgpu_device *adev, bool enable); 411void amdgpu_si_smc_clock(struct amdgpu_device *adev, bool enable);
412bool si_is_smc_running(struct amdgpu_device *adev); 412bool amdgpu_si_is_smc_running(struct amdgpu_device *adev);
413PPSMC_Result si_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg); 413PPSMC_Result amdgpu_si_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg);
414PPSMC_Result si_wait_for_smc_inactive(struct amdgpu_device *adev); 414PPSMC_Result amdgpu_si_wait_for_smc_inactive(struct amdgpu_device *adev);
415int si_load_smc_ucode(struct amdgpu_device *adev, u32 limit); 415int amdgpu_si_load_smc_ucode(struct amdgpu_device *adev, u32 limit);
416int si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, 416int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
417 u32 *value, u32 limit); 417 u32 *value, u32 limit);
418int si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, 418int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
419 u32 value, u32 limit); 419 u32 value, u32 limit);
420 420
421#endif 421#endif
422 422
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-14 08:19:34 -0400