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authorThomas Abraham <thomas.ab@samsung.com>2015-12-15 12:33:17 -0500
committerKrzysztof Kozlowski <k.kozlowski@samsung.com>2016-01-28 05:30:26 -0500
commit66a4a1fb2398cc03637394a6ddfd077a5ee2acf4 (patch)
tree3a8f42d721c2eaab3269904f06cd423de37bf9da
parent8b51c5e730fb66048f48437b17a024d2107347c3 (diff)
ARM: dts: Add CPU OPP properties for exynos542x/5800
For Exynos542x/5800 platforms, add CPU operating points for migrating from Exynos specific cpufreq driver to using generic cpufreq driver. Changes by Bartlomiej: - split Exynos5420 support from the original patch - merged Exynos5422 fixes from Ben Changes by Ben Gamari: - Port to operating-points-v2 Cc: Doug Anderson <dianders@chromium.org> Cc: Javier Martinez Canillas <javier@osg.samsung.com> Cc: Andreas Faerber <afaerber@suse.de> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Ben Gamari <ben@smart-cactus.org> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Diffstat
-rw-r--r--arch/arm/boot/dts/exynos5420-cpus.dtsi10
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi110
-rw-r--r--arch/arm/boot/dts/exynos5422-cpus.dtsi10
3 files changed, 130 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi
index 7aaf0313274f..261d25173f61 100644
--- a/arch/arm/boot/dts/exynos5420-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi
@@ -29,8 +29,10 @@
29 device_type = "cpu"; 29 device_type = "cpu";
30 compatible = "arm,cortex-a15"; 30 compatible = "arm,cortex-a15";
31 reg = <0x0>; 31 reg = <0x0>;
32 clocks = <&clock CLK_ARM_CLK>;
32 clock-frequency = <1800000000>; 33 clock-frequency = <1800000000>;
33 cci-control-port = <&cci_control1>; 34 cci-control-port = <&cci_control1>;
35 operating-points-v2 = <&cluster_a15_opp_table>;
34 }; 36 };
35 37
36 cpu1: cpu@1 { 38 cpu1: cpu@1 {
@@ -39,6 +41,7 @@
39 reg = <0x1>; 41 reg = <0x1>;
40 clock-frequency = <1800000000>; 42 clock-frequency = <1800000000>;
41 cci-control-port = <&cci_control1>; 43 cci-control-port = <&cci_control1>;
44 operating-points-v2 = <&cluster_a15_opp_table>;
42 }; 45 };
43 46
44 cpu2: cpu@2 { 47 cpu2: cpu@2 {
@@ -47,6 +50,7 @@
47 reg = <0x2>; 50 reg = <0x2>;
48 clock-frequency = <1800000000>; 51 clock-frequency = <1800000000>;
49 cci-control-port = <&cci_control1>; 52 cci-control-port = <&cci_control1>;
53 operating-points-v2 = <&cluster_a15_opp_table>;
50 }; 54 };
51 55
52 cpu3: cpu@3 { 56 cpu3: cpu@3 {
@@ -55,14 +59,17 @@
55 reg = <0x3>; 59 reg = <0x3>;
56 clock-frequency = <1800000000>; 60 clock-frequency = <1800000000>;
57 cci-control-port = <&cci_control1>; 61 cci-control-port = <&cci_control1>;
62 operating-points-v2 = <&cluster_a15_opp_table>;
58 }; 63 };
59 64
60 cpu4: cpu@100 { 65 cpu4: cpu@100 {
61 device_type = "cpu"; 66 device_type = "cpu";
62 compatible = "arm,cortex-a7"; 67 compatible = "arm,cortex-a7";
63 reg = <0x100>; 68 reg = <0x100>;
69 clocks = <&clock CLK_KFC_CLK>;
64 clock-frequency = <1000000000>; 70 clock-frequency = <1000000000>;
65 cci-control-port = <&cci_control0>; 71 cci-control-port = <&cci_control0>;
72 operating-points-v2 = <&cluster_a7_opp_table>;
66 }; 73 };
67 74
68 cpu5: cpu@101 { 75 cpu5: cpu@101 {
@@ -71,6 +78,7 @@
71 reg = <0x101>; 78 reg = <0x101>;
72 clock-frequency = <1000000000>; 79 clock-frequency = <1000000000>;
73 cci-control-port = <&cci_control0>; 80 cci-control-port = <&cci_control0>;
81 operating-points-v2 = <&cluster_a7_opp_table>;
74 }; 82 };
75 83
76 cpu6: cpu@102 { 84 cpu6: cpu@102 {
@@ -79,6 +87,7 @@
79 reg = <0x102>; 87 reg = <0x102>;
80 clock-frequency = <1000000000>; 88 clock-frequency = <1000000000>;
81 cci-control-port = <&cci_control0>; 89 cci-control-port = <&cci_control0>;
90 operating-points-v2 = <&cluster_a7_opp_table>;
82 }; 91 };
83 92
84 cpu7: cpu@103 { 93 cpu7: cpu@103 {
@@ -87,6 +96,7 @@
87 reg = <0x103>; 96 reg = <0x103>;
88 clock-frequency = <1000000000>; 97 clock-frequency = <1000000000>;
89 cci-control-port = <&cci_control0>; 98 cci-control-port = <&cci_control0>;
99 operating-points-v2 = <&cluster_a7_opp_table>;
90 }; 100 };
91 }; 101 };
92}; 102};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 6c102c46af73..2a405544ea46 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -50,6 +50,116 @@
50 usbdrdphy1 = &usbdrd_phy1; 50 usbdrdphy1 = &usbdrd_phy1;
51 }; 51 };
52 52
53 cluster_a15_opp_table: opp_table0 {
54 compatible = "operating-points-v2";
55 opp-shared;
56 opp@1800000000 {
57 opp-hz = /bits/ 64 <1800000000>;
58 opp-microvolt = <1250000>;
59 clock-latency-ns = <140000>;
60 };
61 opp@1700000000 {
62 opp-hz = /bits/ 64 <1700000000>;
63 opp-microvolt = <1212500>;
64 clock-latency-ns = <140000>;
65 };
66 opp@1600000000 {
67 opp-hz = /bits/ 64 <1600000000>;
68 opp-microvolt = <1175000>;
69 clock-latency-ns = <140000>;
70 };
71 opp@1500000000 {
72 opp-hz = /bits/ 64 <1500000000>;
73 opp-microvolt = <1137500>;
74 clock-latency-ns = <140000>;
75 };
76 opp@1400000000 {
77 opp-hz = /bits/ 64 <1400000000>;
78 opp-microvolt = <1112500>;
79 clock-latency-ns = <140000>;
80 };
81 opp@1300000000 {
82 opp-hz = /bits/ 64 <1300000000>;
83 opp-microvolt = <1062500>;
84 clock-latency-ns = <140000>;
85 };
86 opp@1200000000 {
87 opp-hz = /bits/ 64 <1200000000>;
88 opp-microvolt = <1037500>;
89 clock-latency-ns = <140000>;
90 };
91 opp@1100000000 {
92 opp-hz = /bits/ 64 <1100000000>;
93 opp-microvolt = <1012500>;
94 clock-latency-ns = <140000>;
95 };
96 opp@1000000000 {
97 opp-hz = /bits/ 64 <1000000000>;
98 opp-microvolt = < 987500>;
99 clock-latency-ns = <140000>;
100 };
101 opp@900000000 {
102 opp-hz = /bits/ 64 <900000000>;
103 opp-microvolt = < 962500>;
104 clock-latency-ns = <140000>;
105 };
106 opp@800000000 {
107 opp-hz = /bits/ 64 <800000000>;
108 opp-microvolt = < 937500>;
109 clock-latency-ns = <140000>;
110 };
111 opp@700000000 {
112 opp-hz = /bits/ 64 <700000000>;
113 opp-microvolt = < 912500>;
114 clock-latency-ns = <140000>;
115 };
116 };
117
118 cluster_a7_opp_table: opp_table1 {
119 compatible = "operating-points-v2";
120 opp-shared;
121 opp@1300000000 {
122 opp-hz = /bits/ 64 <1300000000>;
123 opp-microvolt = <1275000>;
124 clock-latency-ns = <140000>;
125 };
126 opp@1200000000 {
127 opp-hz = /bits/ 64 <1200000000>;
128 opp-microvolt = <1212500>;
129 clock-latency-ns = <140000>;
130 };
131 opp@1100000000 {
132 opp-hz = /bits/ 64 <1100000000>;
133 opp-microvolt = <1162500>;
134 clock-latency-ns = <140000>;
135 };
136 opp@1000000000 {
137 opp-hz = /bits/ 64 <1000000000>;
138 opp-microvolt = <1112500>;
139 clock-latency-ns = <140000>;
140 };
141 opp@900000000 {
142 opp-hz = /bits/ 64 <900000000>;
143 opp-microvolt = <1062500>;
144 clock-latency-ns = <140000>;
145 };
146 opp@800000000 {
147 opp-hz = /bits/ 64 <800000000>;
148 opp-microvolt = <1025000>;
149 clock-latency-ns = <140000>;
150 };
151 opp@700000000 {
152 opp-hz = /bits/ 64 <700000000>;
153 opp-microvolt = <975000>;
154 clock-latency-ns = <140000>;
155 };
156 opp@600000000 {
157 opp-hz = /bits/ 64 <600000000>;
158 opp-microvolt = <937500>;
159 clock-latency-ns = <140000>;
160 };
161 };
162
53 /* 163 /*
54 * The 'cpus' node is not present here but instead it is provided 164 * The 'cpus' node is not present here but instead it is provided
55 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi. 165 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
index 33028ac76a33..9b46b9fbac4e 100644
--- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
@@ -28,8 +28,10 @@
28 device_type = "cpu"; 28 device_type = "cpu";
29 compatible = "arm,cortex-a7"; 29 compatible = "arm,cortex-a7";
30 reg = <0x100>; 30 reg = <0x100>;
31 clocks = <&clock CLK_KFC_CLK>;
31 clock-frequency = <1000000000>; 32 clock-frequency = <1000000000>;
32 cci-control-port = <&cci_control0>; 33 cci-control-port = <&cci_control0>;
34 operating-points-v2 = <&cluster_a7_opp_table>;
33 }; 35 };
34 36
35 cpu1: cpu@101 { 37 cpu1: cpu@101 {
@@ -38,6 +40,7 @@
38 reg = <0x101>; 40 reg = <0x101>;
39 clock-frequency = <1000000000>; 41 clock-frequency = <1000000000>;
40 cci-control-port = <&cci_control0>; 42 cci-control-port = <&cci_control0>;
43 operating-points-v2 = <&cluster_a7_opp_table>;
41 }; 44 };
42 45
43 cpu2: cpu@102 { 46 cpu2: cpu@102 {
@@ -46,6 +49,7 @@
46 reg = <0x102>; 49 reg = <0x102>;
47 clock-frequency = <1000000000>; 50 clock-frequency = <1000000000>;
48 cci-control-port = <&cci_control0>; 51 cci-control-port = <&cci_control0>;
52 operating-points-v2 = <&cluster_a7_opp_table>;
49 }; 53 };
50 54
51 cpu3: cpu@103 { 55 cpu3: cpu@103 {
@@ -54,14 +58,17 @@
54 reg = <0x103>; 58 reg = <0x103>;
55 clock-frequency = <1000000000>; 59 clock-frequency = <1000000000>;
56 cci-control-port = <&cci_control0>; 60 cci-control-port = <&cci_control0>;
61 operating-points-v2 = <&cluster_a7_opp_table>;
57 }; 62 };
58 63
59 cpu4: cpu@0 { 64 cpu4: cpu@0 {
60 device_type = "cpu"; 65 device_type = "cpu";
61 compatible = "arm,cortex-a15"; 66 compatible = "arm,cortex-a15";
67 clocks = <&clock CLK_ARM_CLK>;
62 reg = <0x0>; 68 reg = <0x0>;
63 clock-frequency = <1800000000>; 69 clock-frequency = <1800000000>;
64 cci-control-port = <&cci_control1>; 70 cci-control-port = <&cci_control1>;
71 operating-points-v2 = <&cluster_a15_opp_table>;
65 }; 72 };
66 73
67 cpu5: cpu@1 { 74 cpu5: cpu@1 {
@@ -70,6 +77,7 @@
70 reg = <0x1>; 77 reg = <0x1>;
71 clock-frequency = <1800000000>; 78 clock-frequency = <1800000000>;
72 cci-control-port = <&cci_control1>; 79 cci-control-port = <&cci_control1>;
80 operating-points-v2 = <&cluster_a15_opp_table>;
73 }; 81 };
74 82
75 cpu6: cpu@2 { 83 cpu6: cpu@2 {
@@ -78,6 +86,7 @@
78 reg = <0x2>; 86 reg = <0x2>;
79 clock-frequency = <1800000000>; 87 clock-frequency = <1800000000>;
80 cci-control-port = <&cci_control1>; 88 cci-control-port = <&cci_control1>;
89 operating-points-v2 = <&cluster_a15_opp_table>;
81 }; 90 };
82 91
83 cpu7: cpu@3 { 92 cpu7: cpu@3 {
@@ -86,6 +95,7 @@
86 reg = <0x3>; 95 reg = <0x3>;
87 clock-frequency = <1800000000>; 96 clock-frequency = <1800000000>;
88 cci-control-port = <&cci_control1>; 97 cci-control-port = <&cci_control1>;
98 operating-points-v2 = <&cluster_a15_opp_table>;
89 }; 99 };
90 }; 100 };
91}; 101};
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-14 19:36:11 -0400