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authoryanyang1 <young.yang@amd.com>2015-05-22 14:39:35 -0400
committerAlex Deucher <alexander.deucher@amd.com>2015-06-03 21:03:51 -0400
commit5fc3aeeb9e553a20ce62544f7176c6c4aca52d71 (patch)
tree3b05b96a184970166b8e9c61465b47734e65141c
parentdcc357e63727b63995dd869f015a748c9235eb42 (diff)
drm/amdgpu: rename amdgpu_ip_funcs to amd_ip_funcs (v2)
The structure is renamed and moved to amd_shared.h to make the component independent. This makes it easier to add new components in the future. v2: fix include path Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: yanyang1 <young.yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/amd/amdgpu/Makefile3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h75
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c50
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c24
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/ci_dpm.c57
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik.c130
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik_dpm.h4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik_ih.c54
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik_ih.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik_sdma.c53
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik_sdma.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cz_dpm.c53
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cz_ih.c53
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cz_ih.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v10_0.c50
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v10_0.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v11_0.c50
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v11_0.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v8_0.c50
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v8_0.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c57
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c51
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c52
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c51
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/iceland_dpm.c34
-rw-r--r--drivers/gpu/drm/amd/amdgpu/iceland_ih.c55
-rw-r--r--drivers/gpu/drm/amd/amdgpu/iceland_ih.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/kv_dpm.c89
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c51
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c52
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/tonga_dpm.c35
-rw-r--r--drivers/gpu/drm/amd/amdgpu/tonga_ih.c51
-rw-r--r--drivers/gpu/drm/amd/amdgpu/tonga_ih.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c53
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c52
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c52
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v2_0.c54
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v2_0.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v3_0.c52
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v3_0.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.c96
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi_dpm.h6
-rw-r--r--drivers/gpu/drm/amd/include/amd_shared.h81
55 files changed, 1067 insertions, 707 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 9a573e87cdd3..616dfd4a1398 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -2,7 +2,8 @@
2# Makefile for the drm device driver. This driver provides support for the 2# Makefile for the drm device driver. This driver provides support for the
3# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. 3# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
4 4
5ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/amd/include/asic_reg 5ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/amd/include/asic_reg \
6 -Idrivers/gpu/drm/amd/include
6 7
7amdgpu-y := amdgpu_drv.o 8amdgpu-y := amdgpu_drv.o
8 9
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 411cfb91170f..80f0bea52e33 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -44,6 +44,7 @@
44 44
45#include <drm/drm_gem.h> 45#include <drm/drm_gem.h>
46 46
47#include "amd_shared.h"
47#include "amdgpu_family.h" 48#include "amdgpu_family.h"
48#include "amdgpu_mode.h" 49#include "amdgpu_mode.h"
49#include "amdgpu_ih.h" 50#include "amdgpu_ih.h"
@@ -205,86 +206,28 @@ enum amdgpu_thermal_irq {
205 AMDGPU_THERMAL_IRQ_LAST 206 AMDGPU_THERMAL_IRQ_LAST
206}; 207};
207 208
208/*
209 * IP block functions
210 */
211enum amdgpu_ip_block_type {
212 AMDGPU_IP_BLOCK_TYPE_COMMON,
213 AMDGPU_IP_BLOCK_TYPE_GMC,
214 AMDGPU_IP_BLOCK_TYPE_IH,
215 AMDGPU_IP_BLOCK_TYPE_SMC,
216 AMDGPU_IP_BLOCK_TYPE_DCE,
217 AMDGPU_IP_BLOCK_TYPE_GFX,
218 AMDGPU_IP_BLOCK_TYPE_SDMA,
219 AMDGPU_IP_BLOCK_TYPE_UVD,
220 AMDGPU_IP_BLOCK_TYPE_VCE,
221};
222
223enum amdgpu_clockgating_state {
224 AMDGPU_CG_STATE_GATE = 0,
225 AMDGPU_CG_STATE_UNGATE,
226};
227
228enum amdgpu_powergating_state {
229 AMDGPU_PG_STATE_GATE = 0,
230 AMDGPU_PG_STATE_UNGATE,
231};
232
233struct amdgpu_ip_funcs {
234 /* sets up early driver state (pre sw_init), does not configure hw - Optional */
235 int (*early_init)(struct amdgpu_device *adev);
236 /* sets up late driver/hw state (post hw_init) - Optional */
237 int (*late_init)(struct amdgpu_device *adev);
238 /* sets up driver state, does not configure hw */
239 int (*sw_init)(struct amdgpu_device *adev);
240 /* tears down driver state, does not configure hw */
241 int (*sw_fini)(struct amdgpu_device *adev);
242 /* sets up the hw state */
243 int (*hw_init)(struct amdgpu_device *adev);
244 /* tears down the hw state */
245 int (*hw_fini)(struct amdgpu_device *adev);
246 /* handles IP specific hw/sw changes for suspend */
247 int (*suspend)(struct amdgpu_device *adev);
248 /* handles IP specific hw/sw changes for resume */
249 int (*resume)(struct amdgpu_device *adev);
250 /* returns current IP block idle status */
251 bool (*is_idle)(struct amdgpu_device *adev);
252 /* poll for idle */
253 int (*wait_for_idle)(struct amdgpu_device *adev);
254 /* soft reset the IP block */
255 int (*soft_reset)(struct amdgpu_device *adev);
256 /* dump the IP block status registers */
257 void (*print_status)(struct amdgpu_device *adev);
258 /* enable/disable cg for the IP block */
259 int (*set_clockgating_state)(struct amdgpu_device *adev,
260 enum amdgpu_clockgating_state state);
261 /* enable/disable pg for the IP block */
262 int (*set_powergating_state)(struct amdgpu_device *adev,
263 enum amdgpu_powergating_state state);
264};
265
266int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 209int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
267 enum amdgpu_ip_block_type block_type, 210 enum amd_ip_block_type block_type,
268 enum amdgpu_clockgating_state state); 211 enum amd_clockgating_state state);
269int amdgpu_set_powergating_state(struct amdgpu_device *adev, 212int amdgpu_set_powergating_state(struct amdgpu_device *adev,
270 enum amdgpu_ip_block_type block_type, 213 enum amd_ip_block_type block_type,
271 enum amdgpu_powergating_state state); 214 enum amd_powergating_state state);
272 215
273struct amdgpu_ip_block_version { 216struct amdgpu_ip_block_version {
274 enum amdgpu_ip_block_type type; 217 enum amd_ip_block_type type;
275 u32 major; 218 u32 major;
276 u32 minor; 219 u32 minor;
277 u32 rev; 220 u32 rev;
278 const struct amdgpu_ip_funcs *funcs; 221 const struct amd_ip_funcs *funcs;
279}; 222};
280 223
281int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 224int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
282 enum amdgpu_ip_block_type type, 225 enum amd_ip_block_type type,
283 u32 major, u32 minor); 226 u32 major, u32 minor);
284 227
285const struct amdgpu_ip_block_version * amdgpu_get_ip_block( 228const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
286 struct amdgpu_device *adev, 229 struct amdgpu_device *adev,
287 enum amdgpu_ip_block_type type); 230 enum amd_ip_block_type type);
288 231
289/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 232/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
290struct amdgpu_buffer_funcs { 233struct amdgpu_buffer_funcs {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 3448d9fe88cd..d9d26f2e7bd7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1081,14 +1081,14 @@ static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1081}; 1081};
1082 1082
1083int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 1083int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1084 enum amdgpu_ip_block_type block_type, 1084 enum amd_ip_block_type block_type,
1085 enum amdgpu_clockgating_state state) 1085 enum amd_clockgating_state state)
1086{ 1086{
1087 int i, r = 0; 1087 int i, r = 0;
1088 1088
1089 for (i = 0; i < adev->num_ip_blocks; i++) { 1089 for (i = 0; i < adev->num_ip_blocks; i++) {
1090 if (adev->ip_blocks[i].type == block_type) { 1090 if (adev->ip_blocks[i].type == block_type) {
1091 r = adev->ip_blocks[i].funcs->set_clockgating_state(adev, 1091 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1092 state); 1092 state);
1093 if (r) 1093 if (r)
1094 return r; 1094 return r;
@@ -1098,14 +1098,14 @@ int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1098} 1098}
1099 1099
1100int amdgpu_set_powergating_state(struct amdgpu_device *adev, 1100int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1101 enum amdgpu_ip_block_type block_type, 1101 enum amd_ip_block_type block_type,
1102 enum amdgpu_powergating_state state) 1102 enum amd_powergating_state state)
1103{ 1103{
1104 int i, r = 0; 1104 int i, r = 0;
1105 1105
1106 for (i = 0; i < adev->num_ip_blocks; i++) { 1106 for (i = 0; i < adev->num_ip_blocks; i++) {
1107 if (adev->ip_blocks[i].type == block_type) { 1107 if (adev->ip_blocks[i].type == block_type) {
1108 r = adev->ip_blocks[i].funcs->set_powergating_state(adev, 1108 r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev,
1109 state); 1109 state);
1110 if (r) 1110 if (r)
1111 return r; 1111 return r;
@@ -1116,7 +1116,7 @@ int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1116 1116
1117const struct amdgpu_ip_block_version * amdgpu_get_ip_block( 1117const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
1118 struct amdgpu_device *adev, 1118 struct amdgpu_device *adev,
1119 enum amdgpu_ip_block_type type) 1119 enum amd_ip_block_type type)
1120{ 1120{
1121 int i; 1121 int i;
1122 1122
@@ -1131,7 +1131,7 @@ const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
1131 * amdgpu_ip_block_version_cmp 1131 * amdgpu_ip_block_version_cmp
1132 * 1132 *
1133 * @adev: amdgpu_device pointer 1133 * @adev: amdgpu_device pointer
1134 * @type: enum amdgpu_ip_block_type 1134 * @type: enum amd_ip_block_type
1135 * @major: major version 1135 * @major: major version
1136 * @minor: minor version 1136 * @minor: minor version
1137 * 1137 *
@@ -1139,7 +1139,7 @@ const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
1139 * return 1 if smaller or the ip_block doesn't exist 1139 * return 1 if smaller or the ip_block doesn't exist
1140 */ 1140 */
1141int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 1141int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1142 enum amdgpu_ip_block_type type, 1142 enum amd_ip_block_type type,
1143 u32 major, u32 minor) 1143 u32 major, u32 minor)
1144{ 1144{
1145 const struct amdgpu_ip_block_version *ip_block; 1145 const struct amdgpu_ip_block_version *ip_block;
@@ -1204,7 +1204,7 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
1204 adev->ip_block_enabled[i] = false; 1204 adev->ip_block_enabled[i] = false;
1205 } else { 1205 } else {
1206 if (adev->ip_blocks[i].funcs->early_init) { 1206 if (adev->ip_blocks[i].funcs->early_init) {
1207 r = adev->ip_blocks[i].funcs->early_init(adev); 1207 r = adev->ip_blocks[i].funcs->early_init((void *)adev);
1208 if (r) 1208 if (r)
1209 return r; 1209 return r;
1210 } 1210 }
@@ -1222,15 +1222,15 @@ static int amdgpu_init(struct amdgpu_device *adev)
1222 for (i = 0; i < adev->num_ip_blocks; i++) { 1222 for (i = 0; i < adev->num_ip_blocks; i++) {
1223 if (!adev->ip_block_enabled[i]) 1223 if (!adev->ip_block_enabled[i])
1224 continue; 1224 continue;
1225 r = adev->ip_blocks[i].funcs->sw_init(adev); 1225 r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
1226 if (r) 1226 if (r)
1227 return r; 1227 return r;
1228 /* need to do gmc hw init early so we can allocate gpu mem */ 1228 /* need to do gmc hw init early so we can allocate gpu mem */
1229 if (adev->ip_blocks[i].type == AMDGPU_IP_BLOCK_TYPE_GMC) { 1229 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1230 r = amdgpu_vram_scratch_init(adev); 1230 r = amdgpu_vram_scratch_init(adev);
1231 if (r) 1231 if (r)
1232 return r; 1232 return r;
1233 r = adev->ip_blocks[i].funcs->hw_init(adev); 1233 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1234 if (r) 1234 if (r)
1235 return r; 1235 return r;
1236 r = amdgpu_wb_init(adev); 1236 r = amdgpu_wb_init(adev);
@@ -1243,9 +1243,9 @@ static int amdgpu_init(struct amdgpu_device *adev)
1243 if (!adev->ip_block_enabled[i]) 1243 if (!adev->ip_block_enabled[i])
1244 continue; 1244 continue;
1245 /* gmc hw init is done early */ 1245 /* gmc hw init is done early */
1246 if (adev->ip_blocks[i].type == AMDGPU_IP_BLOCK_TYPE_GMC) 1246 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
1247 continue; 1247 continue;
1248 r = adev->ip_blocks[i].funcs->hw_init(adev); 1248 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1249 if (r) 1249 if (r)
1250 return r; 1250 return r;
1251 } 1251 }
@@ -1261,12 +1261,12 @@ static int amdgpu_late_init(struct amdgpu_device *adev)
1261 if (!adev->ip_block_enabled[i]) 1261 if (!adev->ip_block_enabled[i])
1262 continue; 1262 continue;
1263 /* enable clockgating to save power */ 1263 /* enable clockgating to save power */
1264 r = adev->ip_blocks[i].funcs->set_clockgating_state(adev, 1264 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1265 AMDGPU_CG_STATE_GATE); 1265 AMD_CG_STATE_GATE);
1266 if (r) 1266 if (r)
1267 return r; 1267 return r;
1268 if (adev->ip_blocks[i].funcs->late_init) { 1268 if (adev->ip_blocks[i].funcs->late_init) {
1269 r = adev->ip_blocks[i].funcs->late_init(adev); 1269 r = adev->ip_blocks[i].funcs->late_init((void *)adev);
1270 if (r) 1270 if (r)
1271 return r; 1271 return r;
1272 } 1272 }
@@ -1282,23 +1282,23 @@ static int amdgpu_fini(struct amdgpu_device *adev)
1282 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { 1282 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1283 if (!adev->ip_block_enabled[i]) 1283 if (!adev->ip_block_enabled[i])
1284 continue; 1284 continue;
1285 if (adev->ip_blocks[i].type == AMDGPU_IP_BLOCK_TYPE_GMC) { 1285 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1286 amdgpu_wb_fini(adev); 1286 amdgpu_wb_fini(adev);
1287 amdgpu_vram_scratch_fini(adev); 1287 amdgpu_vram_scratch_fini(adev);
1288 } 1288 }
1289 /* ungate blocks before hw fini so that we can shutdown the blocks safely */ 1289 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1290 r = adev->ip_blocks[i].funcs->set_clockgating_state(adev, 1290 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1291 AMDGPU_CG_STATE_UNGATE); 1291 AMD_CG_STATE_UNGATE);
1292 if (r) 1292 if (r)
1293 return r; 1293 return r;
1294 r = adev->ip_blocks[i].funcs->hw_fini(adev); 1294 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
1295 /* XXX handle errors */ 1295 /* XXX handle errors */
1296 } 1296 }
1297 1297
1298 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { 1298 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1299 if (!adev->ip_block_enabled[i]) 1299 if (!adev->ip_block_enabled[i])
1300 continue; 1300 continue;
1301 r = adev->ip_blocks[i].funcs->sw_fini(adev); 1301 r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
1302 /* XXX handle errors */ 1302 /* XXX handle errors */
1303 adev->ip_block_enabled[i] = false; 1303 adev->ip_block_enabled[i] = false;
1304 } 1304 }
@@ -1314,8 +1314,8 @@ static int amdgpu_suspend(struct amdgpu_device *adev)
1314 if (!adev->ip_block_enabled[i]) 1314 if (!adev->ip_block_enabled[i])
1315 continue; 1315 continue;
1316 /* ungate blocks so that suspend can properly shut them down */ 1316 /* ungate blocks so that suspend can properly shut them down */
1317 r = adev->ip_blocks[i].funcs->set_clockgating_state(adev, 1317 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1318 AMDGPU_CG_STATE_UNGATE); 1318 AMD_CG_STATE_UNGATE);
1319 /* XXX handle errors */ 1319 /* XXX handle errors */
1320 r = adev->ip_blocks[i].funcs->suspend(adev); 1320 r = adev->ip_blocks[i].funcs->suspend(adev);
1321 /* XXX handle errors */ 1321 /* XXX handle errors */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 35185d6b7d46..b6dd3751d9a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -186,7 +186,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
186 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 186 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
187 case AMDGPU_INFO_HW_IP_INFO: { 187 case AMDGPU_INFO_HW_IP_INFO: {
188 struct drm_amdgpu_info_hw_ip ip = {}; 188 struct drm_amdgpu_info_hw_ip ip = {};
189 enum amdgpu_ip_block_type type; 189 enum amd_ip_block_type type;
190 uint32_t ring_mask = 0; 190 uint32_t ring_mask = 0;
191 191
192 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 192 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
@@ -194,26 +194,26 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
194 194
195 switch (info->query_hw_ip.type) { 195 switch (info->query_hw_ip.type) {
196 case AMDGPU_HW_IP_GFX: 196 case AMDGPU_HW_IP_GFX:
197 type = AMDGPU_IP_BLOCK_TYPE_GFX; 197 type = AMD_IP_BLOCK_TYPE_GFX;
198 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 198 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
199 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i); 199 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i);
200 break; 200 break;
201 case AMDGPU_HW_IP_COMPUTE: 201 case AMDGPU_HW_IP_COMPUTE:
202 type = AMDGPU_IP_BLOCK_TYPE_GFX; 202 type = AMD_IP_BLOCK_TYPE_GFX;
203 for (i = 0; i < adev->gfx.num_compute_rings; i++) 203 for (i = 0; i < adev->gfx.num_compute_rings; i++)
204 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i); 204 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i);
205 break; 205 break;
206 case AMDGPU_HW_IP_DMA: 206 case AMDGPU_HW_IP_DMA:
207 type = AMDGPU_IP_BLOCK_TYPE_SDMA; 207 type = AMD_IP_BLOCK_TYPE_SDMA;
208 ring_mask = adev->sdma[0].ring.ready ? 1 : 0; 208 ring_mask = adev->sdma[0].ring.ready ? 1 : 0;
209 ring_mask |= ((adev->sdma[1].ring.ready ? 1 : 0) << 1); 209 ring_mask |= ((adev->sdma[1].ring.ready ? 1 : 0) << 1);
210 break; 210 break;
211 case AMDGPU_HW_IP_UVD: 211 case AMDGPU_HW_IP_UVD:
212 type = AMDGPU_IP_BLOCK_TYPE_UVD; 212 type = AMD_IP_BLOCK_TYPE_UVD;
213 ring_mask = adev->uvd.ring.ready ? 1 : 0; 213 ring_mask = adev->uvd.ring.ready ? 1 : 0;
214 break; 214 break;
215 case AMDGPU_HW_IP_VCE: 215 case AMDGPU_HW_IP_VCE:
216 type = AMDGPU_IP_BLOCK_TYPE_VCE; 216 type = AMD_IP_BLOCK_TYPE_VCE;
217 for (i = 0; i < AMDGPU_MAX_VCE_RINGS; i++) 217 for (i = 0; i < AMDGPU_MAX_VCE_RINGS; i++)
218 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i); 218 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i);
219 break; 219 break;
@@ -235,24 +235,24 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
235 min((size_t)size, sizeof(ip))) ? -EFAULT : 0; 235 min((size_t)size, sizeof(ip))) ? -EFAULT : 0;
236 } 236 }
237 case AMDGPU_INFO_HW_IP_COUNT: { 237 case AMDGPU_INFO_HW_IP_COUNT: {
238 enum amdgpu_ip_block_type type; 238 enum amd_ip_block_type type;
239 uint32_t count = 0; 239 uint32_t count = 0;
240 240
241 switch (info->query_hw_ip.type) { 241 switch (info->query_hw_ip.type) {
242 case AMDGPU_HW_IP_GFX: 242 case AMDGPU_HW_IP_GFX:
243 type = AMDGPU_IP_BLOCK_TYPE_GFX; 243 type = AMD_IP_BLOCK_TYPE_GFX;
244 break; 244 break;
245 case AMDGPU_HW_IP_COMPUTE: 245 case AMDGPU_HW_IP_COMPUTE:
246 type = AMDGPU_IP_BLOCK_TYPE_GFX; 246 type = AMD_IP_BLOCK_TYPE_GFX;
247 break; 247 break;
248 case AMDGPU_HW_IP_DMA: 248 case AMDGPU_HW_IP_DMA:
249 type = AMDGPU_IP_BLOCK_TYPE_SDMA; 249 type = AMD_IP_BLOCK_TYPE_SDMA;
250 break; 250 break;
251 case AMDGPU_HW_IP_UVD: 251 case AMDGPU_HW_IP_UVD:
252 type = AMDGPU_IP_BLOCK_TYPE_UVD; 252 type = AMD_IP_BLOCK_TYPE_UVD;
253 break; 253 break;
254 case AMDGPU_HW_IP_VCE: 254 case AMDGPU_HW_IP_VCE:
255 type = AMDGPU_IP_BLOCK_TYPE_VCE; 255 type = AMD_IP_BLOCK_TYPE_VCE;
256 break; 256 break;
257 default: 257 default:
258 return -EINVAL; 258 return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 4b0be906d235..375759c8639c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -185,7 +185,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
185 } 185 }
186 186
187 /* from uvd v5.0 HW addressing capacity increased to 64 bits */ 187 /* from uvd v5.0 HW addressing capacity increased to 64 bits */
188 if (!amdgpu_ip_block_version_cmp(adev, AMDGPU_IP_BLOCK_TYPE_UVD, 5, 0)) 188 if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
189 adev->uvd.address_64_bit = true; 189 adev->uvd.address_64_bit = true;
190 190
191 return 0; 191 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 5a9dad8e55c9..03809f1bcfd5 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -4227,8 +4227,8 @@ static int ci_update_vce_dpm(struct amdgpu_device *adev,
4227 if (amdgpu_current_state->evclk != amdgpu_new_state->evclk) { 4227 if (amdgpu_current_state->evclk != amdgpu_new_state->evclk) {
4228 if (amdgpu_new_state->evclk) { 4228 if (amdgpu_new_state->evclk) {
4229 /* turn the clocks on when encoding */ 4229 /* turn the clocks on when encoding */
4230 ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE, 4230 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
4231 AMDGPU_CG_STATE_UNGATE); 4231 AMD_CG_STATE_UNGATE);
4232 if (ret) 4232 if (ret)
4233 return ret; 4233 return ret;
4234 4234
@@ -4241,8 +4241,8 @@ static int ci_update_vce_dpm(struct amdgpu_device *adev,
4241 ret = ci_enable_vce_dpm(adev, true); 4241 ret = ci_enable_vce_dpm(adev, true);
4242 } else { 4242 } else {
4243 /* turn the clocks off when not encoding */ 4243 /* turn the clocks off when not encoding */
4244 ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE, 4244 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
4245 AMDGPU_CG_STATE_GATE); 4245 AMD_CG_STATE_GATE);
4246 if (ret) 4246 if (ret)
4247 return ret; 4247 return ret;
4248 4248
@@ -6171,17 +6171,20 @@ static int ci_set_temperature_range(struct amdgpu_device *adev)
6171 return ret; 6171 return ret;
6172} 6172}
6173 6173
6174static int ci_dpm_early_init(struct amdgpu_device *adev) 6174static int ci_dpm_early_init(void *handle)
6175{ 6175{
6176 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6177
6176 ci_dpm_set_dpm_funcs(adev); 6178 ci_dpm_set_dpm_funcs(adev);
6177 ci_dpm_set_irq_funcs(adev); 6179 ci_dpm_set_irq_funcs(adev);
6178 6180
6179 return 0; 6181 return 0;
6180} 6182}
6181 6183
6182static int ci_dpm_late_init(struct amdgpu_device *adev) 6184static int ci_dpm_late_init(void *handle)
6183{ 6185{
6184 int ret; 6186 int ret;
6187 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6185 6188
6186 if (!amdgpu_dpm) 6189 if (!amdgpu_dpm)
6187 return 0; 6190 return 0;
@@ -6195,9 +6198,10 @@ static int ci_dpm_late_init(struct amdgpu_device *adev)
6195 return 0; 6198 return 0;
6196} 6199}
6197 6200
6198static int ci_dpm_sw_init(struct amdgpu_device *adev) 6201static int ci_dpm_sw_init(void *handle)
6199{ 6202{
6200 int ret; 6203 int ret;
6204 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6201 6205
6202 ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq); 6206 ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
6203 if (ret) 6207 if (ret)
@@ -6243,8 +6247,10 @@ dpm_failed:
6243 return ret; 6247 return ret;
6244} 6248}
6245 6249
6246static int ci_dpm_sw_fini(struct amdgpu_device *adev) 6250static int ci_dpm_sw_fini(void *handle)
6247{ 6251{
6252 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6253
6248 mutex_lock(&adev->pm.mutex); 6254 mutex_lock(&adev->pm.mutex);
6249 amdgpu_pm_sysfs_fini(adev); 6255 amdgpu_pm_sysfs_fini(adev);
6250 ci_dpm_fini(adev); 6256 ci_dpm_fini(adev);
@@ -6253,10 +6259,12 @@ static int ci_dpm_sw_fini(struct amdgpu_device *adev)
6253 return 0; 6259 return 0;
6254} 6260}
6255 6261
6256static int ci_dpm_hw_init(struct amdgpu_device *adev) 6262static int ci_dpm_hw_init(void *handle)
6257{ 6263{
6258 int ret; 6264 int ret;
6259 6265
6266 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6267
6260 if (!amdgpu_dpm) 6268 if (!amdgpu_dpm)
6261 return 0; 6269 return 0;
6262 6270
@@ -6272,8 +6280,10 @@ static int ci_dpm_hw_init(struct amdgpu_device *adev)
6272 return ret; 6280 return ret;
6273} 6281}
6274 6282
6275static int ci_dpm_hw_fini(struct amdgpu_device *adev) 6283static int ci_dpm_hw_fini(void *handle)
6276{ 6284{
6285 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6286
6277 if (adev->pm.dpm_enabled) { 6287 if (adev->pm.dpm_enabled) {
6278 mutex_lock(&adev->pm.mutex); 6288 mutex_lock(&adev->pm.mutex);
6279 ci_dpm_disable(adev); 6289 ci_dpm_disable(adev);
@@ -6283,8 +6293,10 @@ static int ci_dpm_hw_fini(struct amdgpu_device *adev)
6283 return 0; 6293 return 0;
6284} 6294}
6285 6295
6286static int ci_dpm_suspend(struct amdgpu_device *adev) 6296static int ci_dpm_suspend(void *handle)
6287{ 6297{
6298 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6299
6288 if (adev->pm.dpm_enabled) { 6300 if (adev->pm.dpm_enabled) {
6289 mutex_lock(&adev->pm.mutex); 6301 mutex_lock(&adev->pm.mutex);
6290 /* disable dpm */ 6302 /* disable dpm */
@@ -6296,9 +6308,10 @@ static int ci_dpm_suspend(struct amdgpu_device *adev)
6296 return 0; 6308 return 0;
6297} 6309}
6298 6310
6299static int ci_dpm_resume(struct amdgpu_device *adev) 6311static int ci_dpm_resume(void *handle)
6300{ 6312{
6301 int ret; 6313 int ret;
6314 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6302 6315
6303 if (adev->pm.dpm_enabled) { 6316 if (adev->pm.dpm_enabled) {
6304 /* asic init will reset to the boot state */ 6317 /* asic init will reset to the boot state */
@@ -6316,20 +6329,22 @@ static int ci_dpm_resume(struct amdgpu_device *adev)
6316 return 0; 6329 return 0;
6317} 6330}
6318 6331
6319static bool ci_dpm_is_idle(struct amdgpu_device *adev) 6332static bool ci_dpm_is_idle(void *handle)
6320{ 6333{
6321 /* XXX */ 6334 /* XXX */
6322 return true; 6335 return true;
6323} 6336}
6324 6337
6325static int ci_dpm_wait_for_idle(struct amdgpu_device *adev) 6338static int ci_dpm_wait_for_idle(void *handle)
6326{ 6339{
6327 /* XXX */ 6340 /* XXX */
6328 return 0; 6341 return 0;
6329} 6342}
6330 6343
6331static void ci_dpm_print_status(struct amdgpu_device *adev) 6344static void ci_dpm_print_status(void *handle)
6332{ 6345{
6346 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6347
6333 dev_info(adev->dev, "CIK DPM registers\n"); 6348 dev_info(adev->dev, "CIK DPM registers\n");
6334 dev_info(adev->dev, " BIOS_SCRATCH_4=0x%08X\n", 6349 dev_info(adev->dev, " BIOS_SCRATCH_4=0x%08X\n",
6335 RREG32(mmBIOS_SCRATCH_4)); 6350 RREG32(mmBIOS_SCRATCH_4));
@@ -6535,7 +6550,7 @@ static void ci_dpm_print_status(struct amdgpu_device *adev)
6535 RREG32_SMC(ixSMC_PC_C)); 6550 RREG32_SMC(ixSMC_PC_C));
6536} 6551}
6537 6552
6538static int ci_dpm_soft_reset(struct amdgpu_device *adev) 6553static int ci_dpm_soft_reset(void *handle)
6539{ 6554{
6540 return 0; 6555 return 0;
6541} 6556}
@@ -6618,19 +6633,19 @@ static int ci_dpm_process_interrupt(struct amdgpu_device *adev,
6618 return 0; 6633 return 0;
6619} 6634}
6620 6635
6621static int ci_dpm_set_clockgating_state(struct amdgpu_device *adev, 6636static int ci_dpm_set_clockgating_state(void *handle,
6622 enum amdgpu_clockgating_state state) 6637 enum amd_clockgating_state state)
6623{ 6638{
6624 return 0; 6639 return 0;
6625} 6640}
6626 6641
6627static int ci_dpm_set_powergating_state(struct amdgpu_device *adev, 6642static int ci_dpm_set_powergating_state(void *handle,
6628 enum amdgpu_powergating_state state) 6643 enum amd_powergating_state state)
6629{ 6644{
6630 return 0; 6645 return 0;
6631} 6646}
6632 6647
6633const struct amdgpu_ip_funcs ci_dpm_ip_funcs = { 6648const struct amd_ip_funcs ci_dpm_ip_funcs = {
6634 .early_init = ci_dpm_early_init, 6649 .early_init = ci_dpm_early_init,
6635 .late_init = ci_dpm_late_init, 6650 .late_init = ci_dpm_late_init,
6636 .sw_init = ci_dpm_sw_init, 6651 .sw_init = ci_dpm_sw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 74ce0be2fbb7..5dab578d6462 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1892,63 +1892,63 @@ static const struct amdgpu_ip_block_version bonaire_ip_blocks[] =
1892{ 1892{
1893 /* ORDER MATTERS! */ 1893 /* ORDER MATTERS! */
1894 { 1894 {
1895 .type = AMDGPU_IP_BLOCK_TYPE_COMMON, 1895 .type = AMD_IP_BLOCK_TYPE_COMMON,
1896 .major = 1, 1896 .major = 1,
1897 .minor = 0, 1897 .minor = 0,
1898 .rev = 0, 1898 .rev = 0,
1899 .funcs = &cik_common_ip_funcs, 1899 .funcs = &cik_common_ip_funcs,
1900 }, 1900 },
1901 { 1901 {
1902 .type = AMDGPU_IP_BLOCK_TYPE_GMC, 1902 .type = AMD_IP_BLOCK_TYPE_GMC,
1903 .major = 7, 1903 .major = 7,
1904 .minor = 0, 1904 .minor = 0,
1905 .rev = 0, 1905 .rev = 0,
1906 .funcs = &gmc_v7_0_ip_funcs, 1906 .funcs = &gmc_v7_0_ip_funcs,
1907 }, 1907 },
1908 { 1908 {
1909 .type = AMDGPU_IP_BLOCK_TYPE_IH, 1909 .type = AMD_IP_BLOCK_TYPE_IH,
1910 .major = 2, 1910 .major = 2,
1911 .minor = 0, 1911 .minor = 0,
1912 .rev = 0, 1912 .rev = 0,
1913 .funcs = &cik_ih_ip_funcs, 1913 .funcs = &cik_ih_ip_funcs,
1914 }, 1914 },
1915 { 1915 {
1916 .type = AMDGPU_IP_BLOCK_TYPE_SMC, 1916 .type = AMD_IP_BLOCK_TYPE_SMC,
1917 .major = 7, 1917 .major = 7,
1918 .minor = 0, 1918 .minor = 0,
1919 .rev = 0, 1919 .rev = 0,
1920 .funcs = &ci_dpm_ip_funcs, 1920 .funcs = &ci_dpm_ip_funcs,
1921 }, 1921 },
1922 { 1922 {
1923 .type = AMDGPU_IP_BLOCK_TYPE_DCE, 1923 .type = AMD_IP_BLOCK_TYPE_DCE,
1924 .major = 8, 1924 .major = 8,
1925 .minor = 2, 1925 .minor = 2,
1926 .rev = 0, 1926 .rev = 0,
1927 .funcs = &dce_v8_0_ip_funcs, 1927 .funcs = &dce_v8_0_ip_funcs,
1928 }, 1928 },
1929 { 1929 {
1930 .type = AMDGPU_IP_BLOCK_TYPE_GFX, 1930 .type = AMD_IP_BLOCK_TYPE_GFX,
1931 .major = 7, 1931 .major = 7,
1932 .minor = 2, 1932 .minor = 2,
1933 .rev = 0, 1933 .rev = 0,
1934 .funcs = &gfx_v7_0_ip_funcs, 1934 .funcs = &gfx_v7_0_ip_funcs,
1935 }, 1935 },
1936 { 1936 {
1937 .type = AMDGPU_IP_BLOCK_TYPE_SDMA, 1937 .type = AMD_IP_BLOCK_TYPE_SDMA,
1938 .major = 2, 1938 .major = 2,
1939 .minor = 0, 1939 .minor = 0,
1940 .rev = 0, 1940 .rev = 0,
1941 .funcs = &cik_sdma_ip_funcs, 1941 .funcs = &cik_sdma_ip_funcs,
1942 }, 1942 },
1943 { 1943 {
1944 .type = AMDGPU_IP_BLOCK_TYPE_UVD, 1944 .type = AMD_IP_BLOCK_TYPE_UVD,
1945 .major = 4, 1945 .major = 4,
1946 .minor = 2, 1946 .minor = 2,
1947 .rev = 0, 1947 .rev = 0,
1948 .funcs = &uvd_v4_2_ip_funcs, 1948 .funcs = &uvd_v4_2_ip_funcs,
1949 }, 1949 },
1950 { 1950 {
1951 .type = AMDGPU_IP_BLOCK_TYPE_VCE, 1951 .type = AMD_IP_BLOCK_TYPE_VCE,
1952 .major = 2, 1952 .major = 2,
1953 .minor = 0, 1953 .minor = 0,
1954 .rev = 0, 1954 .rev = 0,
@@ -1960,63 +1960,63 @@ static const struct amdgpu_ip_block_version hawaii_ip_blocks[] =
1960{ 1960{
1961 /* ORDER MATTERS! */ 1961 /* ORDER MATTERS! */
1962 { 1962 {
1963 .type = AMDGPU_IP_BLOCK_TYPE_COMMON, 1963 .type = AMD_IP_BLOCK_TYPE_COMMON,
1964 .major = 1, 1964 .major = 1,
1965 .minor = 0, 1965 .minor = 0,
1966 .rev = 0, 1966 .rev = 0,
1967 .funcs = &cik_common_ip_funcs, 1967 .funcs = &cik_common_ip_funcs,
1968 }, 1968 },
1969 { 1969 {
1970 .type = AMDGPU_IP_BLOCK_TYPE_GMC, 1970 .type = AMD_IP_BLOCK_TYPE_GMC,
1971 .major = 7, 1971 .major = 7,
1972 .minor = 0, 1972 .minor = 0,
1973 .rev = 0, 1973 .rev = 0,
1974 .funcs = &gmc_v7_0_ip_funcs, 1974 .funcs = &gmc_v7_0_ip_funcs,
1975 }, 1975 },
1976 { 1976 {
1977 .type = AMDGPU_IP_BLOCK_TYPE_IH, 1977 .type = AMD_IP_BLOCK_TYPE_IH,
1978 .major = 2, 1978 .major = 2,
1979 .minor = 0, 1979 .minor = 0,
1980 .rev = 0, 1980 .rev = 0,
1981 .funcs = &cik_ih_ip_funcs, 1981 .funcs = &cik_ih_ip_funcs,
1982 }, 1982 },
1983 { 1983 {
1984 .type = AMDGPU_IP_BLOCK_TYPE_SMC, 1984 .type = AMD_IP_BLOCK_TYPE_SMC,
1985 .major = 7, 1985 .major = 7,
1986 .minor = 0, 1986 .minor = 0,
1987 .rev = 0, 1987 .rev = 0,
1988 .funcs = &ci_dpm_ip_funcs, 1988 .funcs = &ci_dpm_ip_funcs,
1989 }, 1989 },
1990 { 1990 {
1991 .type = AMDGPU_IP_BLOCK_TYPE_DCE, 1991 .type = AMD_IP_BLOCK_TYPE_DCE,
1992 .major = 8, 1992 .major = 8,
1993 .minor = 5, 1993 .minor = 5,
1994 .rev = 0, 1994 .rev = 0,
1995 .funcs = &dce_v8_0_ip_funcs, 1995 .funcs = &dce_v8_0_ip_funcs,
1996 }, 1996 },
1997 { 1997 {
1998 .type = AMDGPU_IP_BLOCK_TYPE_GFX, 1998 .type = AMD_IP_BLOCK_TYPE_GFX,
1999 .major = 7, 1999 .major = 7,
2000 .minor = 3, 2000 .minor = 3,
2001 .rev = 0, 2001 .rev = 0,
2002 .funcs = &gfx_v7_0_ip_funcs, 2002 .funcs = &gfx_v7_0_ip_funcs,
2003 }, 2003 },
2004 { 2004 {
2005 .type = AMDGPU_IP_BLOCK_TYPE_SDMA, 2005 .type = AMD_IP_BLOCK_TYPE_SDMA,
2006 .major = 2, 2006 .major = 2,
2007 .minor = 0, 2007 .minor = 0,
2008 .rev = 0, 2008 .rev = 0,
2009 .funcs = &cik_sdma_ip_funcs, 2009 .funcs = &cik_sdma_ip_funcs,
2010 }, 2010 },
2011 { 2011 {
2012 .type = AMDGPU_IP_BLOCK_TYPE_UVD, 2012 .type = AMD_IP_BLOCK_TYPE_UVD,
2013 .major = 4, 2013 .major = 4,
2014 .minor = 2, 2014 .minor = 2,
2015 .rev = 0, 2015 .rev = 0,
2016 .funcs = &uvd_v4_2_ip_funcs, 2016 .funcs = &uvd_v4_2_ip_funcs,
2017 }, 2017 },
2018 { 2018 {
2019 .type = AMDGPU_IP_BLOCK_TYPE_VCE, 2019 .type = AMD_IP_BLOCK_TYPE_VCE,
2020 .major = 2, 2020 .major = 2,
2021 .minor = 0, 2021 .minor = 0,
2022 .rev = 0, 2022 .rev = 0,
@@ -2028,63 +2028,63 @@ static const struct amdgpu_ip_block_version kabini_ip_blocks[] =
2028{ 2028{
2029 /* ORDER MATTERS! */ 2029 /* ORDER MATTERS! */
2030 { 2030 {
2031 .type = AMDGPU_IP_BLOCK_TYPE_COMMON, 2031 .type = AMD_IP_BLOCK_TYPE_COMMON,
2032 .major = 1, 2032 .major = 1,
2033 .minor = 0, 2033 .minor = 0,
2034 .rev = 0, 2034 .rev = 0,
2035 .funcs = &cik_common_ip_funcs, 2035 .funcs = &cik_common_ip_funcs,
2036 }, 2036 },
2037 { 2037 {
2038 .type = AMDGPU_IP_BLOCK_TYPE_GMC, 2038 .type = AMD_IP_BLOCK_TYPE_GMC,
2039 .major = 7, 2039 .major = 7,
2040 .minor = 0, 2040 .minor = 0,
2041 .rev = 0, 2041 .rev = 0,
2042 .funcs = &gmc_v7_0_ip_funcs, 2042 .funcs = &gmc_v7_0_ip_funcs,
2043 }, 2043 },
2044 { 2044 {
2045 .type = AMDGPU_IP_BLOCK_TYPE_IH, 2045 .type = AMD_IP_BLOCK_TYPE_IH,
2046 .major = 2, 2046 .major = 2,
2047 .minor = 0, 2047 .minor = 0,
2048 .rev = 0, 2048 .rev = 0,
2049 .funcs = &cik_ih_ip_funcs, 2049 .funcs = &cik_ih_ip_funcs,
2050 }, 2050 },
2051 { 2051 {
2052 .type = AMDGPU_IP_BLOCK_TYPE_SMC, 2052 .type = AMD_IP_BLOCK_TYPE_SMC,
2053 .major = 7, 2053 .major = 7,
2054 .minor = 0, 2054 .minor = 0,
2055 .rev = 0, 2055 .rev = 0,
2056 .funcs = &kv_dpm_ip_funcs, 2056 .funcs = &kv_dpm_ip_funcs,
2057 }, 2057 },
2058 { 2058 {
2059 .type = AMDGPU_IP_BLOCK_TYPE_DCE, 2059 .type = AMD_IP_BLOCK_TYPE_DCE,
2060 .major = 8, 2060 .major = 8,
2061 .minor = 3, 2061 .minor = 3,
2062 .rev = 0, 2062 .rev = 0,
2063 .funcs = &dce_v8_0_ip_funcs, 2063 .funcs = &dce_v8_0_ip_funcs,
2064 }, 2064 },
2065 { 2065 {
2066 .type = AMDGPU_IP_BLOCK_TYPE_GFX, 2066 .type = AMD_IP_BLOCK_TYPE_GFX,
2067 .major = 7, 2067 .major = 7,
2068 .minor = 2, 2068 .minor = 2,
2069 .rev = 0, 2069 .rev = 0,
2070 .funcs = &gfx_v7_0_ip_funcs, 2070 .funcs = &gfx_v7_0_ip_funcs,
2071 }, 2071 },
2072 { 2072 {
2073 .type = AMDGPU_IP_BLOCK_TYPE_SDMA, 2073 .type = AMD_IP_BLOCK_TYPE_SDMA,
2074 .major = 2, 2074 .major = 2,
2075 .minor = 0, 2075 .minor = 0,
2076 .rev = 0, 2076 .rev = 0,
2077 .funcs = &cik_sdma_ip_funcs, 2077 .funcs = &cik_sdma_ip_funcs,
2078 }, 2078 },
2079 { 2079 {
2080 .type = AMDGPU_IP_BLOCK_TYPE_UVD, 2080 .type = AMD_IP_BLOCK_TYPE_UVD,
2081 .major = 4, 2081 .major = 4,
2082 .minor = 2, 2082 .minor = 2,
2083 .rev = 0, 2083 .rev = 0,
2084 .funcs = &uvd_v4_2_ip_funcs, 2084 .funcs = &uvd_v4_2_ip_funcs,
2085 }, 2085 },
2086 { 2086 {
2087 .type = AMDGPU_IP_BLOCK_TYPE_VCE, 2087 .type = AMD_IP_BLOCK_TYPE_VCE,
2088 .major = 2, 2088 .major = 2,
2089 .minor = 0, 2089 .minor = 0,
2090 .rev = 0, 2090 .rev = 0,
@@ -2096,63 +2096,63 @@ static const struct amdgpu_ip_block_version mullins_ip_blocks[] =
2096{ 2096{
2097 /* ORDER MATTERS! */ 2097 /* ORDER MATTERS! */
2098 { 2098 {
2099 .type = AMDGPU_IP_BLOCK_TYPE_COMMON, 2099 .type = AMD_IP_BLOCK_TYPE_COMMON,
2100 .major = 1, 2100 .major = 1,
2101 .minor = 0, 2101 .minor = 0,
2102 .rev = 0, 2102 .rev = 0,
2103 .funcs = &cik_common_ip_funcs, 2103 .funcs = &cik_common_ip_funcs,
2104 }, 2104 },
2105 { 2105 {
2106 .type = AMDGPU_IP_BLOCK_TYPE_GMC, 2106 .type = AMD_IP_BLOCK_TYPE_GMC,
2107 .major = 7, 2107 .major = 7,
2108 .minor = 0, 2108 .minor = 0,
2109 .rev = 0, 2109 .rev = 0,
2110 .funcs = &gmc_v7_0_ip_funcs, 2110 .funcs = &gmc_v7_0_ip_funcs,
2111 }, 2111 },
2112 { 2112 {
2113 .type = AMDGPU_IP_BLOCK_TYPE_IH, 2113 .type = AMD_IP_BLOCK_TYPE_IH,
2114 .major = 2, 2114 .major = 2,
2115 .minor = 0, 2115 .minor = 0,
2116 .rev = 0, 2116 .rev = 0,
2117 .funcs = &cik_ih_ip_funcs, 2117 .funcs = &cik_ih_ip_funcs,
2118 }, 2118 },
2119 { 2119 {
2120 .type = AMDGPU_IP_BLOCK_TYPE_SMC, 2120 .type = AMD_IP_BLOCK_TYPE_SMC,
2121 .major = 7, 2121 .major = 7,
2122 .minor = 0, 2122 .minor = 0,
2123 .rev = 0, 2123 .rev = 0,
2124 .funcs = &kv_dpm_ip_funcs, 2124 .funcs = &kv_dpm_ip_funcs,
2125 }, 2125 },
2126 { 2126 {
2127 .type = AMDGPU_IP_BLOCK_TYPE_DCE, 2127 .type = AMD_IP_BLOCK_TYPE_DCE,
2128 .major = 8, 2128 .major = 8,
2129 .minor = 3, 2129 .minor = 3,
2130 .rev = 0, 2130 .rev = 0,
2131 .funcs = &dce_v8_0_ip_funcs, 2131 .funcs = &dce_v8_0_ip_funcs,
2132 }, 2132 },
2133 { 2133 {
2134 .type = AMDGPU_IP_BLOCK_TYPE_GFX, 2134 .type = AMD_IP_BLOCK_TYPE_GFX,
2135 .major = 7, 2135 .major = 7,
2136 .minor = 2, 2136 .minor = 2,
2137 .rev = 0, 2137 .rev = 0,
2138 .funcs = &gfx_v7_0_ip_funcs, 2138 .funcs = &gfx_v7_0_ip_funcs,
2139 }, 2139 },
2140 { 2140 {
2141 .type = AMDGPU_IP_BLOCK_TYPE_SDMA, 2141 .type = AMD_IP_BLOCK_TYPE_SDMA,
2142 .major = 2, 2142 .major = 2,
2143 .minor = 0, 2143 .minor = 0,
2144 .rev = 0, 2144 .rev = 0,
2145 .funcs = &cik_sdma_ip_funcs, 2145 .funcs = &cik_sdma_ip_funcs,
2146 }, 2146 },
2147 { 2147 {
2148 .type = AMDGPU_IP_BLOCK_TYPE_UVD, 2148 .type = AMD_IP_BLOCK_TYPE_UVD,
2149 .major = 4, 2149 .major = 4,
2150 .minor = 2, 2150 .minor = 2,
2151 .rev = 0, 2151 .rev = 0,
2152 .funcs = &uvd_v4_2_ip_funcs, 2152 .funcs = &uvd_v4_2_ip_funcs,
2153 }, 2153 },
2154 { 2154 {
2155 .type = AMDGPU_IP_BLOCK_TYPE_VCE, 2155 .type = AMD_IP_BLOCK_TYPE_VCE,
2156 .major = 2, 2156 .major = 2,
2157 .minor = 0, 2157 .minor = 0,
2158 .rev = 0, 2158 .rev = 0,
@@ -2164,63 +2164,63 @@ static const struct amdgpu_ip_block_version kaveri_ip_blocks[] =
2164{ 2164{
2165 /* ORDER MATTERS! */ 2165 /* ORDER MATTERS! */
2166 { 2166 {
2167 .type = AMDGPU_IP_BLOCK_TYPE_COMMON, 2167 .type = AMD_IP_BLOCK_TYPE_COMMON,
2168 .major = 1, 2168 .major = 1,
2169 .minor = 0, 2169 .minor = 0,
2170 .rev = 0, 2170 .rev = 0,
2171 .funcs = &cik_common_ip_funcs, 2171 .funcs = &cik_common_ip_funcs,
2172 }, 2172 },
2173 { 2173 {
2174 .type = AMDGPU_IP_BLOCK_TYPE_GMC, 2174 .type = AMD_IP_BLOCK_TYPE_GMC,
2175 .major = 7, 2175 .major = 7,
2176 .minor = 0, 2176 .minor = 0,
2177 .rev = 0, 2177 .rev = 0,
2178 .funcs = &gmc_v7_0_ip_funcs, 2178 .funcs = &gmc_v7_0_ip_funcs,
2179 }, 2179 },
2180 { 2180 {
2181 .type = AMDGPU_IP_BLOCK_TYPE_IH, 2181 .type = AMD_IP_BLOCK_TYPE_IH,
2182 .major = 2, 2182 .major = 2,
2183 .minor = 0, 2183 .minor = 0,
2184 .rev = 0, 2184 .rev = 0,
2185 .funcs = &cik_ih_ip_funcs, 2185 .funcs = &cik_ih_ip_funcs,
2186 }, 2186 },
2187 { 2187 {
2188 .type = AMDGPU_IP_BLOCK_TYPE_SMC, 2188 .type = AMD_IP_BLOCK_TYPE_SMC,
2189 .major = 7, 2189 .major = 7,
2190 .minor = 0, 2190 .minor = 0,
2191 .rev = 0, 2191 .rev = 0,
2192 .funcs = &kv_dpm_ip_funcs, 2192 .funcs = &kv_dpm_ip_funcs,
2193 }, 2193 },
2194 { 2194 {
2195 .type = AMDGPU_IP_BLOCK_TYPE_DCE, 2195 .type = AMD_IP_BLOCK_TYPE_DCE,
2196 .major = 8, 2196 .major = 8,
2197 .minor = 1, 2197 .minor = 1,
2198 .rev = 0, 2198 .rev = 0,
2199 .funcs = &dce_v8_0_ip_funcs, 2199 .funcs = &dce_v8_0_ip_funcs,
2200 }, 2200 },
2201 { 2201 {
2202 .type = AMDGPU_IP_BLOCK_TYPE_GFX, 2202 .type = AMD_IP_BLOCK_TYPE_GFX,
2203 .major = 7, 2203 .major = 7,
2204 .minor = 1, 2204 .minor = 1,
2205 .rev = 0, 2205 .rev = 0,
2206 .funcs = &gfx_v7_0_ip_funcs, 2206 .funcs = &gfx_v7_0_ip_funcs,
2207 }, 2207 },
2208 { 2208 {
2209 .type = AMDGPU_IP_BLOCK_TYPE_SDMA, 2209 .type = AMD_IP_BLOCK_TYPE_SDMA,
2210 .major = 2, 2210 .major = 2,
2211 .minor = 0, 2211 .minor = 0,
2212 .rev = 0, 2212 .rev = 0,
2213 .funcs = &cik_sdma_ip_funcs, 2213 .funcs = &cik_sdma_ip_funcs,
2214 }, 2214 },
2215 { 2215 {
2216 .type = AMDGPU_IP_BLOCK_TYPE_UVD, 2216 .type = AMD_IP_BLOCK_TYPE_UVD,
2217 .major = 4, 2217 .major = 4,
2218 .minor = 2, 2218 .minor = 2,
2219 .rev = 0, 2219 .rev = 0,
2220 .funcs = &uvd_v4_2_ip_funcs, 2220 .funcs = &uvd_v4_2_ip_funcs,
2221 }, 2221 },
2222 { 2222 {
2223 .type = AMDGPU_IP_BLOCK_TYPE_VCE, 2223 .type = AMD_IP_BLOCK_TYPE_VCE,
2224 .major = 2, 2224 .major = 2,
2225 .minor = 0, 2225 .minor = 0,
2226 .rev = 0, 2226 .rev = 0,
@@ -2278,8 +2278,10 @@ static const struct amdgpu_asic_funcs cik_asic_funcs =
2278 .wait_for_mc_idle = &gmc_v7_0_mc_wait_for_idle, 2278 .wait_for_mc_idle = &gmc_v7_0_mc_wait_for_idle,
2279}; 2279};
2280 2280
2281static int cik_common_early_init(struct amdgpu_device *adev) 2281static int cik_common_early_init(void *handle)
2282{ 2282{
2283 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2284
2283 adev->smc_rreg = &cik_smc_rreg; 2285 adev->smc_rreg = &cik_smc_rreg;
2284 adev->smc_wreg = &cik_smc_wreg; 2286 adev->smc_wreg = &cik_smc_wreg;
2285 adev->pcie_rreg = &cik_pcie_rreg; 2287 adev->pcie_rreg = &cik_pcie_rreg;
@@ -2417,18 +2419,20 @@ static int cik_common_early_init(struct amdgpu_device *adev)
2417 return 0; 2419 return 0;
2418} 2420}
2419 2421
2420static int cik_common_sw_init(struct amdgpu_device *adev) 2422static int cik_common_sw_init(void *handle)
2421{ 2423{
2422 return 0; 2424 return 0;
2423} 2425}
2424 2426
2425static int cik_common_sw_fini(struct amdgpu_device *adev) 2427static int cik_common_sw_fini(void *handle)
2426{ 2428{
2427 return 0; 2429 return 0;
2428} 2430}
2429 2431
2430static int cik_common_hw_init(struct amdgpu_device *adev) 2432static int cik_common_hw_init(void *handle)
2431{ 2433{
2434 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2435
2432 /* move the golden regs per IP block */ 2436 /* move the golden regs per IP block */
2433 cik_init_golden_registers(adev); 2437 cik_init_golden_registers(adev);
2434 /* enable pcie gen2/3 link */ 2438 /* enable pcie gen2/3 link */
@@ -2439,55 +2443,59 @@ static int cik_common_hw_init(struct amdgpu_device *adev)
2439 return 0; 2443 return 0;
2440} 2444}
2441 2445
2442static int cik_common_hw_fini(struct amdgpu_device *adev) 2446static int cik_common_hw_fini(void *handle)
2443{ 2447{
2444 return 0; 2448 return 0;
2445} 2449}
2446 2450
2447static int cik_common_suspend(struct amdgpu_device *adev) 2451static int cik_common_suspend(void *handle)
2448{ 2452{
2453 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2454
2449 return cik_common_hw_fini(adev); 2455 return cik_common_hw_fini(adev);
2450} 2456}
2451 2457
2452static int cik_common_resume(struct amdgpu_device *adev) 2458static int cik_common_resume(void *handle)
2453{ 2459{
2460 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2461
2454 return cik_common_hw_init(adev); 2462 return cik_common_hw_init(adev);
2455} 2463}
2456 2464
2457static bool cik_common_is_idle(struct amdgpu_device *adev) 2465static bool cik_common_is_idle(void *handle)
2458{ 2466{
2459 return true; 2467 return true;
2460} 2468}
2461 2469
2462static int cik_common_wait_for_idle(struct amdgpu_device *adev) 2470static int cik_common_wait_for_idle(void *handle)
2463{ 2471{
2464 return 0; 2472 return 0;
2465} 2473}
2466 2474
2467static void cik_common_print_status(struct amdgpu_device *adev) 2475static void cik_common_print_status(void *handle)
2468{ 2476{
2469 2477
2470} 2478}
2471 2479
2472static int cik_common_soft_reset(struct amdgpu_device *adev) 2480static int cik_common_soft_reset(void *handle)
2473{ 2481{
2474 /* XXX hard reset?? */ 2482 /* XXX hard reset?? */
2475 return 0; 2483 return 0;
2476} 2484}
2477 2485
2478static int cik_common_set_clockgating_state(struct amdgpu_device *adev, 2486static int cik_common_set_clockgating_state(void *handle,
2479 enum amdgpu_clockgating_state state) 2487 enum amd_clockgating_state state)
2480{ 2488{
2481 return 0; 2489 return 0;
2482} 2490}
2483 2491
2484static int cik_common_set_powergating_state(struct amdgpu_device *adev, 2492static int cik_common_set_powergating_state(void *handle,
2485 enum amdgpu_powergating_state state) 2493 enum amd_powergating_state state)
2486{ 2494{
2487 return 0; 2495 return 0;
2488} 2496}
2489 2497
2490const struct amdgpu_ip_funcs cik_common_ip_funcs = { 2498const struct amd_ip_funcs cik_common_ip_funcs = {
2491 .early_init = cik_common_early_init, 2499 .early_init = cik_common_early_init,
2492 .late_init = NULL, 2500 .late_init = NULL,
2493 .sw_init = cik_common_sw_init, 2501 .sw_init = cik_common_sw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.h b/drivers/gpu/drm/amd/amdgpu/cik.h
index 967d630a4dcb..5ebd2d7a0327 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.h
+++ b/drivers/gpu/drm/amd/amdgpu/cik.h
@@ -24,7 +24,7 @@
24#ifndef __CIK_H__ 24#ifndef __CIK_H__
25#define __CIK_H__ 25#define __CIK_H__
26 26
27extern const struct amdgpu_ip_funcs cik_common_ip_funcs; 27extern const struct amd_ip_funcs cik_common_ip_funcs;
28 28
29void cik_srbm_select(struct amdgpu_device *adev, 29void cik_srbm_select(struct amdgpu_device *adev,
30 u32 me, u32 pipe, u32 queue, u32 vmid); 30 u32 me, u32 pipe, u32 queue, u32 vmid);
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_dpm.h b/drivers/gpu/drm/amd/amdgpu/cik_dpm.h
index 35d8efdcde7e..b1c8e7b446ea 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/cik_dpm.h
@@ -24,7 +24,7 @@
24#ifndef __CIK_DPM_H__ 24#ifndef __CIK_DPM_H__
25#define __CIK_DPM_H__ 25#define __CIK_DPM_H__
26 26
27extern const struct amdgpu_ip_funcs ci_dpm_ip_funcs; 27extern const struct amd_ip_funcs ci_dpm_ip_funcs;
28extern const struct amdgpu_ip_funcs kv_dpm_ip_funcs; 28extern const struct amd_ip_funcs kv_dpm_ip_funcs;
29 29
30#endif 30#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index 81e8bbaba3e8..8993c50cb89f 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -271,16 +271,19 @@ static void cik_ih_set_rptr(struct amdgpu_device *adev)
271 WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr); 271 WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
272} 272}
273 273
274static int cik_ih_early_init(struct amdgpu_device *adev) 274static int cik_ih_early_init(void *handle)
275{ 275{
276 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
277
276 cik_ih_set_interrupt_funcs(adev); 278 cik_ih_set_interrupt_funcs(adev);
277 279
278 return 0; 280 return 0;
279} 281}
280 282
281static int cik_ih_sw_init(struct amdgpu_device *adev) 283static int cik_ih_sw_init(void *handle)
282{ 284{
283 int r; 285 int r;
286 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
284 287
285 r = amdgpu_ih_ring_init(adev, 64 * 1024, false); 288 r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
286 if (r) 289 if (r)
@@ -291,17 +294,20 @@ static int cik_ih_sw_init(struct amdgpu_device *adev)
291 return r; 294 return r;
292} 295}
293 296
294static int cik_ih_sw_fini(struct amdgpu_device *adev) 297static int cik_ih_sw_fini(void *handle)
295{ 298{
299 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
300
296 amdgpu_irq_fini(adev); 301 amdgpu_irq_fini(adev);
297 amdgpu_ih_ring_fini(adev); 302 amdgpu_ih_ring_fini(adev);
298 303
299 return 0; 304 return 0;
300} 305}
301 306
302static int cik_ih_hw_init(struct amdgpu_device *adev) 307static int cik_ih_hw_init(void *handle)
303{ 308{
304 int r; 309 int r;
310 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
305 311
306 r = cik_ih_irq_init(adev); 312 r = cik_ih_irq_init(adev);
307 if (r) 313 if (r)
@@ -310,25 +316,32 @@ static int cik_ih_hw_init(struct amdgpu_device *adev)
310 return 0; 316 return 0;
311} 317}
312 318
313static int cik_ih_hw_fini(struct amdgpu_device *adev) 319static int cik_ih_hw_fini(void *handle)
314{ 320{
321 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
322
315 cik_ih_irq_disable(adev); 323 cik_ih_irq_disable(adev);
316 324
317 return 0; 325 return 0;
318} 326}
319 327
320static int cik_ih_suspend(struct amdgpu_device *adev) 328static int cik_ih_suspend(void *handle)
321{ 329{
330 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
331
322 return cik_ih_hw_fini(adev); 332 return cik_ih_hw_fini(adev);
323} 333}
324 334
325static int cik_ih_resume(struct amdgpu_device *adev) 335static int cik_ih_resume(void *handle)
326{ 336{
337 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
338
327 return cik_ih_hw_init(adev); 339 return cik_ih_hw_init(adev);
328} 340}
329 341
330static bool cik_ih_is_idle(struct amdgpu_device *adev) 342static bool cik_ih_is_idle(void *handle)
331{ 343{
344 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
332 u32 tmp = RREG32(mmSRBM_STATUS); 345 u32 tmp = RREG32(mmSRBM_STATUS);
333 346
334 if (tmp & SRBM_STATUS__IH_BUSY_MASK) 347 if (tmp & SRBM_STATUS__IH_BUSY_MASK)
@@ -337,10 +350,11 @@ static bool cik_ih_is_idle(struct amdgpu_device *adev)
337 return true; 350 return true;
338} 351}
339 352
340static int cik_ih_wait_for_idle(struct amdgpu_device *adev) 353static int cik_ih_wait_for_idle(void *handle)
341{ 354{
342 unsigned i; 355 unsigned i;
343 u32 tmp; 356 u32 tmp;
357 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
344 358
345 for (i = 0; i < adev->usec_timeout; i++) { 359 for (i = 0; i < adev->usec_timeout; i++) {
346 /* read MC_STATUS */ 360 /* read MC_STATUS */
@@ -352,8 +366,10 @@ static int cik_ih_wait_for_idle(struct amdgpu_device *adev)
352 return -ETIMEDOUT; 366 return -ETIMEDOUT;
353} 367}
354 368
355static void cik_ih_print_status(struct amdgpu_device *adev) 369static void cik_ih_print_status(void *handle)
356{ 370{
371 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
372
357 dev_info(adev->dev, "CIK IH registers\n"); 373 dev_info(adev->dev, "CIK IH registers\n");
358 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", 374 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
359 RREG32(mmSRBM_STATUS)); 375 RREG32(mmSRBM_STATUS));
@@ -379,8 +395,10 @@ static void cik_ih_print_status(struct amdgpu_device *adev)
379 RREG32(mmIH_RB_WPTR)); 395 RREG32(mmIH_RB_WPTR));
380} 396}
381 397
382static int cik_ih_soft_reset(struct amdgpu_device *adev) 398static int cik_ih_soft_reset(void *handle)
383{ 399{
400 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
401
384 u32 srbm_soft_reset = 0; 402 u32 srbm_soft_reset = 0;
385 u32 tmp = RREG32(mmSRBM_STATUS); 403 u32 tmp = RREG32(mmSRBM_STATUS);
386 404
@@ -388,7 +406,7 @@ static int cik_ih_soft_reset(struct amdgpu_device *adev)
388 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK; 406 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK;
389 407
390 if (srbm_soft_reset) { 408 if (srbm_soft_reset) {
391 cik_ih_print_status(adev); 409 cik_ih_print_status((void *)adev);
392 410
393 tmp = RREG32(mmSRBM_SOFT_RESET); 411 tmp = RREG32(mmSRBM_SOFT_RESET);
394 tmp |= srbm_soft_reset; 412 tmp |= srbm_soft_reset;
@@ -405,25 +423,25 @@ static int cik_ih_soft_reset(struct amdgpu_device *adev)
405 /* Wait a little for things to settle down */ 423 /* Wait a little for things to settle down */
406 udelay(50); 424 udelay(50);
407 425
408 cik_ih_print_status(adev); 426 cik_ih_print_status((void *)adev);
409 } 427 }
410 428
411 return 0; 429 return 0;
412} 430}
413 431
414static int cik_ih_set_clockgating_state(struct amdgpu_device *adev, 432static int cik_ih_set_clockgating_state(void *handle,
415 enum amdgpu_clockgating_state state) 433 enum amd_clockgating_state state)
416{ 434{
417 return 0; 435 return 0;
418} 436}
419 437
420static int cik_ih_set_powergating_state(struct amdgpu_device *adev, 438static int cik_ih_set_powergating_state(void *handle,
421 enum amdgpu_powergating_state state) 439 enum amd_powergating_state state)
422{ 440{
423 return 0; 441 return 0;
424} 442}
425 443
426const struct amdgpu_ip_funcs cik_ih_ip_funcs = { 444const struct amd_ip_funcs cik_ih_ip_funcs = {
427 .early_init = cik_ih_early_init, 445 .early_init = cik_ih_early_init,
428 .late_init = NULL, 446 .late_init = NULL,
429 .sw_init = cik_ih_sw_init, 447 .sw_init = cik_ih_sw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.h b/drivers/gpu/drm/amd/amdgpu/cik_ih.h
index f70162525034..6b0f375ec244 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.h
@@ -24,6 +24,6 @@
24#ifndef __CIK_IH_H__ 24#ifndef __CIK_IH_H__
25#define __CIK_IH_H__ 25#define __CIK_IH_H__
26 26
27extern const struct amdgpu_ip_funcs cik_ih_ip_funcs; 27extern const struct amd_ip_funcs cik_ih_ip_funcs;
28 28
29#endif 29#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index d5055ea4d112..7c816b5cf17a 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -927,8 +927,10 @@ static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
927 } 927 }
928} 928}
929 929
930static int cik_sdma_early_init(struct amdgpu_device *adev) 930static int cik_sdma_early_init(void *handle)
931{ 931{
932 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
933
932 cik_sdma_set_ring_funcs(adev); 934 cik_sdma_set_ring_funcs(adev);
933 cik_sdma_set_irq_funcs(adev); 935 cik_sdma_set_irq_funcs(adev);
934 cik_sdma_set_buffer_funcs(adev); 936 cik_sdma_set_buffer_funcs(adev);
@@ -937,9 +939,10 @@ static int cik_sdma_early_init(struct amdgpu_device *adev)
937 return 0; 939 return 0;
938} 940}
939 941
940static int cik_sdma_sw_init(struct amdgpu_device *adev) 942static int cik_sdma_sw_init(void *handle)
941{ 943{
942 struct amdgpu_ring *ring; 944 struct amdgpu_ring *ring;
945 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
943 int r; 946 int r;
944 947
945 r = cik_sdma_init_microcode(adev); 948 r = cik_sdma_init_microcode(adev);
@@ -990,17 +993,20 @@ static int cik_sdma_sw_init(struct amdgpu_device *adev)
990 return r; 993 return r;
991} 994}
992 995
993static int cik_sdma_sw_fini(struct amdgpu_device *adev) 996static int cik_sdma_sw_fini(void *handle)
994{ 997{
998 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
999
995 amdgpu_ring_fini(&adev->sdma[0].ring); 1000 amdgpu_ring_fini(&adev->sdma[0].ring);
996 amdgpu_ring_fini(&adev->sdma[1].ring); 1001 amdgpu_ring_fini(&adev->sdma[1].ring);
997 1002
998 return 0; 1003 return 0;
999} 1004}
1000 1005
1001static int cik_sdma_hw_init(struct amdgpu_device *adev) 1006static int cik_sdma_hw_init(void *handle)
1002{ 1007{
1003 int r; 1008 int r;
1009 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1004 1010
1005 r = cik_sdma_start(adev); 1011 r = cik_sdma_start(adev);
1006 if (r) 1012 if (r)
@@ -1009,27 +1015,32 @@ static int cik_sdma_hw_init(struct amdgpu_device *adev)
1009 return r; 1015 return r;
1010} 1016}
1011 1017
1012static int cik_sdma_hw_fini(struct amdgpu_device *adev) 1018static int cik_sdma_hw_fini(void *handle)
1013{ 1019{
1020 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1021
1014 cik_sdma_enable(adev, false); 1022 cik_sdma_enable(adev, false);
1015 1023
1016 return 0; 1024 return 0;
1017} 1025}
1018 1026
1019static int cik_sdma_suspend(struct amdgpu_device *adev) 1027static int cik_sdma_suspend(void *handle)
1020{ 1028{
1029 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1021 1030
1022 return cik_sdma_hw_fini(adev); 1031 return cik_sdma_hw_fini(adev);
1023} 1032}
1024 1033
1025static int cik_sdma_resume(struct amdgpu_device *adev) 1034static int cik_sdma_resume(void *handle)
1026{ 1035{
1036 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1027 1037
1028 return cik_sdma_hw_init(adev); 1038 return cik_sdma_hw_init(adev);
1029} 1039}
1030 1040
1031static bool cik_sdma_is_idle(struct amdgpu_device *adev) 1041static bool cik_sdma_is_idle(void *handle)
1032{ 1042{
1043 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1033 u32 tmp = RREG32(mmSRBM_STATUS2); 1044 u32 tmp = RREG32(mmSRBM_STATUS2);
1034 1045
1035 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1046 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
@@ -1039,10 +1050,11 @@ static bool cik_sdma_is_idle(struct amdgpu_device *adev)
1039 return true; 1050 return true;
1040} 1051}
1041 1052
1042static int cik_sdma_wait_for_idle(struct amdgpu_device *adev) 1053static int cik_sdma_wait_for_idle(void *handle)
1043{ 1054{
1044 unsigned i; 1055 unsigned i;
1045 u32 tmp; 1056 u32 tmp;
1057 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1046 1058
1047 for (i = 0; i < adev->usec_timeout; i++) { 1059 for (i = 0; i < adev->usec_timeout; i++) {
1048 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1060 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
@@ -1055,9 +1067,10 @@ static int cik_sdma_wait_for_idle(struct amdgpu_device *adev)
1055 return -ETIMEDOUT; 1067 return -ETIMEDOUT;
1056} 1068}
1057 1069
1058static void cik_sdma_print_status(struct amdgpu_device *adev) 1070static void cik_sdma_print_status(void *handle)
1059{ 1071{
1060 int i, j; 1072 int i, j;
1073 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1061 1074
1062 dev_info(adev->dev, "CIK SDMA registers\n"); 1075 dev_info(adev->dev, "CIK SDMA registers\n");
1063 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", 1076 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
@@ -1103,9 +1116,10 @@ static void cik_sdma_print_status(struct amdgpu_device *adev)
1103 } 1116 }
1104} 1117}
1105 1118
1106static int cik_sdma_soft_reset(struct amdgpu_device *adev) 1119static int cik_sdma_soft_reset(void *handle)
1107{ 1120{
1108 u32 srbm_soft_reset = 0; 1121 u32 srbm_soft_reset = 0;
1122 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1109 u32 tmp = RREG32(mmSRBM_STATUS2); 1123 u32 tmp = RREG32(mmSRBM_STATUS2);
1110 1124
1111 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { 1125 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
@@ -1124,7 +1138,7 @@ static int cik_sdma_soft_reset(struct amdgpu_device *adev)
1124 } 1138 }
1125 1139
1126 if (srbm_soft_reset) { 1140 if (srbm_soft_reset) {
1127 cik_sdma_print_status(adev); 1141 cik_sdma_print_status((void *)adev);
1128 1142
1129 tmp = RREG32(mmSRBM_SOFT_RESET); 1143 tmp = RREG32(mmSRBM_SOFT_RESET);
1130 tmp |= srbm_soft_reset; 1144 tmp |= srbm_soft_reset;
@@ -1141,7 +1155,7 @@ static int cik_sdma_soft_reset(struct amdgpu_device *adev)
1141 /* Wait a little for things to settle down */ 1155 /* Wait a little for things to settle down */
1142 udelay(50); 1156 udelay(50);
1143 1157
1144 cik_sdma_print_status(adev); 1158 cik_sdma_print_status((void *)adev);
1145 } 1159 }
1146 1160
1147 return 0; 1161 return 0;
@@ -1243,12 +1257,13 @@ static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1243 return 0; 1257 return 0;
1244} 1258}
1245 1259
1246static int cik_sdma_set_clockgating_state(struct amdgpu_device *adev, 1260static int cik_sdma_set_clockgating_state(void *handle,
1247 enum amdgpu_clockgating_state state) 1261 enum amd_clockgating_state state)
1248{ 1262{
1249 bool gate = false; 1263 bool gate = false;
1264 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1250 1265
1251 if (state == AMDGPU_CG_STATE_GATE) 1266 if (state == AMD_CG_STATE_GATE)
1252 gate = true; 1267 gate = true;
1253 1268
1254 cik_enable_sdma_mgcg(adev, gate); 1269 cik_enable_sdma_mgcg(adev, gate);
@@ -1257,13 +1272,13 @@ static int cik_sdma_set_clockgating_state(struct amdgpu_device *adev,
1257 return 0; 1272 return 0;
1258} 1273}
1259 1274
1260static int cik_sdma_set_powergating_state(struct amdgpu_device *adev, 1275static int cik_sdma_set_powergating_state(void *handle,
1261 enum amdgpu_powergating_state state) 1276 enum amd_powergating_state state)
1262{ 1277{
1263 return 0; 1278 return 0;
1264} 1279}
1265 1280
1266const struct amdgpu_ip_funcs cik_sdma_ip_funcs = { 1281const struct amd_ip_funcs cik_sdma_ip_funcs = {
1267 .early_init = cik_sdma_early_init, 1282 .early_init = cik_sdma_early_init,
1268 .late_init = NULL, 1283 .late_init = NULL,
1269 .sw_init = cik_sdma_sw_init, 1284 .sw_init = cik_sdma_sw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.h b/drivers/gpu/drm/amd/amdgpu/cik_sdma.h
index 42b59960bc53..027727c677b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.h
@@ -24,6 +24,6 @@
24#ifndef __CIK_SDMA_H__ 24#ifndef __CIK_SDMA_H__
25#define __CIK_SDMA_H__ 25#define __CIK_SDMA_H__
26 26
27extern const struct amdgpu_ip_funcs cik_sdma_ip_funcs; 27extern const struct amd_ip_funcs cik_sdma_ip_funcs;
28 28
29#endif 29#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
index 2649b505d2d0..f275b5d2d060 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
@@ -542,24 +542,29 @@ static void cz_dpm_print_power_state(struct amdgpu_device *adev,
542 542
543static void cz_dpm_set_funcs(struct amdgpu_device *adev); 543static void cz_dpm_set_funcs(struct amdgpu_device *adev);
544 544
545static int cz_dpm_early_init(struct amdgpu_device *adev) 545static int cz_dpm_early_init(void *handle)
546{ 546{
547 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
548
547 cz_dpm_set_funcs(adev); 549 cz_dpm_set_funcs(adev);
548 550
549 return 0; 551 return 0;
550} 552}
551 553
552 554
553static int cz_dpm_late_init(struct amdgpu_device *adev) 555static int cz_dpm_late_init(void *handle)
554{ 556{
557 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
558
555 /* powerdown unused blocks for now */ 559 /* powerdown unused blocks for now */
556 cz_dpm_powergate_uvd(adev, true); 560 cz_dpm_powergate_uvd(adev, true);
557 561
558 return 0; 562 return 0;
559} 563}
560 564
561static int cz_dpm_sw_init(struct amdgpu_device *adev) 565static int cz_dpm_sw_init(void *handle)
562{ 566{
567 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
563 int ret = 0; 568 int ret = 0;
564 /* fix me to add thermal support TODO */ 569 /* fix me to add thermal support TODO */
565 570
@@ -602,8 +607,10 @@ dpm_init_failed:
602 return ret; 607 return ret;
603} 608}
604 609
605static int cz_dpm_sw_fini(struct amdgpu_device *adev) 610static int cz_dpm_sw_fini(void *handle)
606{ 611{
612 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
613
607 mutex_lock(&adev->pm.mutex); 614 mutex_lock(&adev->pm.mutex);
608 amdgpu_pm_sysfs_fini(adev); 615 amdgpu_pm_sysfs_fini(adev);
609 cz_dpm_fini(adev); 616 cz_dpm_fini(adev);
@@ -1216,8 +1223,9 @@ static int cz_dpm_enable(struct amdgpu_device *adev)
1216 return 0; 1223 return 0;
1217} 1224}
1218 1225
1219static int cz_dpm_hw_init(struct amdgpu_device *adev) 1226static int cz_dpm_hw_init(void *handle)
1220{ 1227{
1228 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1221 int ret = 0; 1229 int ret = 0;
1222 1230
1223 mutex_lock(&adev->pm.mutex); 1231 mutex_lock(&adev->pm.mutex);
@@ -1282,9 +1290,10 @@ static int cz_dpm_disable(struct amdgpu_device *adev)
1282 return 0; 1290 return 0;
1283} 1291}
1284 1292
1285static int cz_dpm_hw_fini(struct amdgpu_device *adev) 1293static int cz_dpm_hw_fini(void *handle)
1286{ 1294{
1287 int ret = 0; 1295 int ret = 0;
1296 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1288 1297
1289 mutex_lock(&adev->pm.mutex); 1298 mutex_lock(&adev->pm.mutex);
1290 1299
@@ -1305,9 +1314,10 @@ static int cz_dpm_hw_fini(struct amdgpu_device *adev)
1305 return ret; 1314 return ret;
1306} 1315}
1307 1316
1308static int cz_dpm_suspend(struct amdgpu_device *adev) 1317static int cz_dpm_suspend(void *handle)
1309{ 1318{
1310 int ret = 0; 1319 int ret = 0;
1320 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1311 1321
1312 if (adev->pm.dpm_enabled) { 1322 if (adev->pm.dpm_enabled) {
1313 mutex_lock(&adev->pm.mutex); 1323 mutex_lock(&adev->pm.mutex);
@@ -1324,9 +1334,10 @@ static int cz_dpm_suspend(struct amdgpu_device *adev)
1324 return ret; 1334 return ret;
1325} 1335}
1326 1336
1327static int cz_dpm_resume(struct amdgpu_device *adev) 1337static int cz_dpm_resume(void *handle)
1328{ 1338{
1329 int ret = 0; 1339 int ret = 0;
1340 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1330 1341
1331 mutex_lock(&adev->pm.mutex); 1342 mutex_lock(&adev->pm.mutex);
1332 ret = cz_smu_init(adev); 1343 ret = cz_smu_init(adev);
@@ -1368,14 +1379,14 @@ static int cz_dpm_resume(struct amdgpu_device *adev)
1368 return 0; 1379 return 0;
1369} 1380}
1370 1381
1371static int cz_dpm_set_clockgating_state(struct amdgpu_device *adev, 1382static int cz_dpm_set_clockgating_state(void *handle,
1372 enum amdgpu_clockgating_state state) 1383 enum amd_clockgating_state state)
1373{ 1384{
1374 return 0; 1385 return 0;
1375} 1386}
1376 1387
1377static int cz_dpm_set_powergating_state(struct amdgpu_device *adev, 1388static int cz_dpm_set_powergating_state(void *handle,
1378 enum amdgpu_powergating_state state) 1389 enum amd_powergating_state state)
1379{ 1390{
1380 return 0; 1391 return 0;
1381} 1392}
@@ -1733,11 +1744,11 @@ static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
1733 if (gate) { 1744 if (gate) {
1734 if (pi->caps_uvd_pg) { 1745 if (pi->caps_uvd_pg) {
1735 /* disable clockgating so we can properly shut down the block */ 1746 /* disable clockgating so we can properly shut down the block */
1736 ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD, 1747 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1737 AMDGPU_CG_STATE_UNGATE); 1748 AMD_CG_STATE_UNGATE);
1738 /* shutdown the UVD block */ 1749 /* shutdown the UVD block */
1739 ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD, 1750 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1740 AMDGPU_PG_STATE_GATE); 1751 AMD_PG_STATE_GATE);
1741 /* XXX: check for errors */ 1752 /* XXX: check for errors */
1742 } 1753 }
1743 cz_update_uvd_dpm(adev, gate); 1754 cz_update_uvd_dpm(adev, gate);
@@ -1752,18 +1763,18 @@ static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
1752 else 1763 else
1753 cz_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_UVDPowerON, 0); 1764 cz_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_UVDPowerON, 0);
1754 /* re-init the UVD block */ 1765 /* re-init the UVD block */
1755 ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD, 1766 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1756 AMDGPU_PG_STATE_UNGATE); 1767 AMD_PG_STATE_UNGATE);
1757 /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */ 1768 /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
1758 ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD, 1769 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1759 AMDGPU_CG_STATE_GATE); 1770 AMD_CG_STATE_GATE);
1760 /* XXX: check for errors */ 1771 /* XXX: check for errors */
1761 } 1772 }
1762 cz_update_uvd_dpm(adev, gate); 1773 cz_update_uvd_dpm(adev, gate);
1763 } 1774 }
1764} 1775}
1765 1776
1766const struct amdgpu_ip_funcs cz_dpm_ip_funcs = { 1777const struct amd_ip_funcs cz_dpm_ip_funcs = {
1767 .early_init = cz_dpm_early_init, 1778 .early_init = cz_dpm_early_init,
1768 .late_init = cz_dpm_late_init, 1779 .late_init = cz_dpm_late_init,
1769 .sw_init = cz_dpm_sw_init, 1780 .sw_init = cz_dpm_sw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index 80d508e64a86..bc751bfbcae2 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -250,15 +250,18 @@ static void cz_ih_set_rptr(struct amdgpu_device *adev)
250 WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr); 250 WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
251} 251}
252 252
253static int cz_ih_early_init(struct amdgpu_device *adev) 253static int cz_ih_early_init(void *handle)
254{ 254{
255 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
256
255 cz_ih_set_interrupt_funcs(adev); 257 cz_ih_set_interrupt_funcs(adev);
256 return 0; 258 return 0;
257} 259}
258 260
259static int cz_ih_sw_init(struct amdgpu_device *adev) 261static int cz_ih_sw_init(void *handle)
260{ 262{
261 int r; 263 int r;
264 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
262 265
263 r = amdgpu_ih_ring_init(adev, 64 * 1024, false); 266 r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
264 if (r) 267 if (r)
@@ -269,17 +272,20 @@ static int cz_ih_sw_init(struct amdgpu_device *adev)
269 return r; 272 return r;
270} 273}
271 274
272static int cz_ih_sw_fini(struct amdgpu_device *adev) 275static int cz_ih_sw_fini(void *handle)
273{ 276{
277 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
278
274 amdgpu_irq_fini(adev); 279 amdgpu_irq_fini(adev);
275 amdgpu_ih_ring_fini(adev); 280 amdgpu_ih_ring_fini(adev);
276 281
277 return 0; 282 return 0;
278} 283}
279 284
280static int cz_ih_hw_init(struct amdgpu_device *adev) 285static int cz_ih_hw_init(void *handle)
281{ 286{
282 int r; 287 int r;
288 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
283 289
284 r = cz_ih_irq_init(adev); 290 r = cz_ih_irq_init(adev);
285 if (r) 291 if (r)
@@ -288,25 +294,32 @@ static int cz_ih_hw_init(struct amdgpu_device *adev)
288 return 0; 294 return 0;
289} 295}
290 296
291static int cz_ih_hw_fini(struct amdgpu_device *adev) 297static int cz_ih_hw_fini(void *handle)
292{ 298{
299 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
300
293 cz_ih_irq_disable(adev); 301 cz_ih_irq_disable(adev);
294 302
295 return 0; 303 return 0;
296} 304}
297 305
298static int cz_ih_suspend(struct amdgpu_device *adev) 306static int cz_ih_suspend(void *handle)
299{ 307{
308 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
309
300 return cz_ih_hw_fini(adev); 310 return cz_ih_hw_fini(adev);
301} 311}
302 312
303static int cz_ih_resume(struct amdgpu_device *adev) 313static int cz_ih_resume(void *handle)
304{ 314{
315 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
316
305 return cz_ih_hw_init(adev); 317 return cz_ih_hw_init(adev);
306} 318}
307 319
308static bool cz_ih_is_idle(struct amdgpu_device *adev) 320static bool cz_ih_is_idle(void *handle)
309{ 321{
322 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
310 u32 tmp = RREG32(mmSRBM_STATUS); 323 u32 tmp = RREG32(mmSRBM_STATUS);
311 324
312 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) 325 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
@@ -315,10 +328,11 @@ static bool cz_ih_is_idle(struct amdgpu_device *adev)
315 return true; 328 return true;
316} 329}
317 330
318static int cz_ih_wait_for_idle(struct amdgpu_device *adev) 331static int cz_ih_wait_for_idle(void *handle)
319{ 332{
320 unsigned i; 333 unsigned i;
321 u32 tmp; 334 u32 tmp;
335 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
322 336
323 for (i = 0; i < adev->usec_timeout; i++) { 337 for (i = 0; i < adev->usec_timeout; i++) {
324 /* read MC_STATUS */ 338 /* read MC_STATUS */
@@ -330,8 +344,10 @@ static int cz_ih_wait_for_idle(struct amdgpu_device *adev)
330 return -ETIMEDOUT; 344 return -ETIMEDOUT;
331} 345}
332 346
333static void cz_ih_print_status(struct amdgpu_device *adev) 347static void cz_ih_print_status(void *handle)
334{ 348{
349 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
350
335 dev_info(adev->dev, "CZ IH registers\n"); 351 dev_info(adev->dev, "CZ IH registers\n");
336 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", 352 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
337 RREG32(mmSRBM_STATUS)); 353 RREG32(mmSRBM_STATUS));
@@ -357,9 +373,10 @@ static void cz_ih_print_status(struct amdgpu_device *adev)
357 RREG32(mmIH_RB_WPTR)); 373 RREG32(mmIH_RB_WPTR));
358} 374}
359 375
360static int cz_ih_soft_reset(struct amdgpu_device *adev) 376static int cz_ih_soft_reset(void *handle)
361{ 377{
362 u32 srbm_soft_reset = 0; 378 u32 srbm_soft_reset = 0;
379 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
363 u32 tmp = RREG32(mmSRBM_STATUS); 380 u32 tmp = RREG32(mmSRBM_STATUS);
364 381
365 if (tmp & SRBM_STATUS__IH_BUSY_MASK) 382 if (tmp & SRBM_STATUS__IH_BUSY_MASK)
@@ -367,7 +384,7 @@ static int cz_ih_soft_reset(struct amdgpu_device *adev)
367 SOFT_RESET_IH, 1); 384 SOFT_RESET_IH, 1);
368 385
369 if (srbm_soft_reset) { 386 if (srbm_soft_reset) {
370 cz_ih_print_status(adev); 387 cz_ih_print_status((void *)adev);
371 388
372 tmp = RREG32(mmSRBM_SOFT_RESET); 389 tmp = RREG32(mmSRBM_SOFT_RESET);
373 tmp |= srbm_soft_reset; 390 tmp |= srbm_soft_reset;
@@ -384,27 +401,27 @@ static int cz_ih_soft_reset(struct amdgpu_device *adev)
384 /* Wait a little for things to settle down */ 401 /* Wait a little for things to settle down */
385 udelay(50); 402 udelay(50);
386 403
387 cz_ih_print_status(adev); 404 cz_ih_print_status((void *)adev);
388 } 405 }
389 406
390 return 0; 407 return 0;
391} 408}
392 409
393static int cz_ih_set_clockgating_state(struct amdgpu_device *adev, 410static int cz_ih_set_clockgating_state(void *handle,
394 enum amdgpu_clockgating_state state) 411 enum amd_clockgating_state state)
395{ 412{
396 // TODO 413 // TODO
397 return 0; 414 return 0;
398} 415}
399 416
400static int cz_ih_set_powergating_state(struct amdgpu_device *adev, 417static int cz_ih_set_powergating_state(void *handle,
401 enum amdgpu_powergating_state state) 418 enum amd_powergating_state state)
402{ 419{
403 // TODO 420 // TODO
404 return 0; 421 return 0;
405} 422}
406 423
407const struct amdgpu_ip_funcs cz_ih_ip_funcs = { 424const struct amd_ip_funcs cz_ih_ip_funcs = {
408 .early_init = cz_ih_early_init, 425 .early_init = cz_ih_early_init,
409 .late_init = NULL, 426 .late_init = NULL,
410 .sw_init = cz_ih_sw_init, 427 .sw_init = cz_ih_sw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.h b/drivers/gpu/drm/amd/amdgpu/cz_ih.h
index 1bce136876ff..fc4057a2ecb9 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.h
@@ -24,6 +24,6 @@
24#ifndef __CZ_IH_H__ 24#ifndef __CZ_IH_H__
25#define __CZ_IH_H__ 25#define __CZ_IH_H__
26 26
27extern const struct amdgpu_ip_funcs cz_ih_ip_funcs; 27extern const struct amd_ip_funcs cz_ih_ip_funcs;
28 28
29#endif /* __CZ_IH_H__ */ 29#endif /* __CZ_IH_H__ */
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 37b96236fe2c..da9a4b9a1f6c 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -2864,8 +2864,10 @@ static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
2864 return 0; 2864 return 0;
2865} 2865}
2866 2866
2867static int dce_v10_0_early_init(struct amdgpu_device *adev) 2867static int dce_v10_0_early_init(void *handle)
2868{ 2868{
2869 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2870
2869 adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg; 2871 adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
2870 adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg; 2872 adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
2871 2873
@@ -2886,9 +2888,10 @@ static int dce_v10_0_early_init(struct amdgpu_device *adev)
2886 return 0; 2888 return 0;
2887} 2889}
2888 2890
2889static int dce_v10_0_sw_init(struct amdgpu_device *adev) 2891static int dce_v10_0_sw_init(void *handle)
2890{ 2892{
2891 int r, i; 2893 int r, i;
2894 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2892 2895
2893 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2896 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2894 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); 2897 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
@@ -2950,8 +2953,10 @@ static int dce_v10_0_sw_init(struct amdgpu_device *adev)
2950 return r; 2953 return r;
2951} 2954}
2952 2955
2953static int dce_v10_0_sw_fini(struct amdgpu_device *adev) 2956static int dce_v10_0_sw_fini(void *handle)
2954{ 2957{
2958 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2959
2955 kfree(adev->mode_info.bios_hardcoded_edid); 2960 kfree(adev->mode_info.bios_hardcoded_edid);
2956 2961
2957 drm_kms_helper_poll_fini(adev->ddev); 2962 drm_kms_helper_poll_fini(adev->ddev);
@@ -2966,9 +2971,10 @@ static int dce_v10_0_sw_fini(struct amdgpu_device *adev)
2966 return 0; 2971 return 0;
2967} 2972}
2968 2973
2969static int dce_v10_0_hw_init(struct amdgpu_device *adev) 2974static int dce_v10_0_hw_init(void *handle)
2970{ 2975{
2971 int i; 2976 int i;
2977 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2972 2978
2973 dce_v10_0_init_golden_registers(adev); 2979 dce_v10_0_init_golden_registers(adev);
2974 2980
@@ -2986,9 +2992,10 @@ static int dce_v10_0_hw_init(struct amdgpu_device *adev)
2986 return 0; 2992 return 0;
2987} 2993}
2988 2994
2989static int dce_v10_0_hw_fini(struct amdgpu_device *adev) 2995static int dce_v10_0_hw_fini(void *handle)
2990{ 2996{
2991 int i; 2997 int i;
2998 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2992 2999
2993 dce_v10_0_hpd_fini(adev); 3000 dce_v10_0_hpd_fini(adev);
2994 3001
@@ -2999,9 +3006,10 @@ static int dce_v10_0_hw_fini(struct amdgpu_device *adev)
2999 return 0; 3006 return 0;
3000} 3007}
3001 3008
3002static int dce_v10_0_suspend(struct amdgpu_device *adev) 3009static int dce_v10_0_suspend(void *handle)
3003{ 3010{
3004 struct drm_connector *connector; 3011 struct drm_connector *connector;
3012 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3005 3013
3006 drm_kms_helper_poll_disable(adev->ddev); 3014 drm_kms_helper_poll_disable(adev->ddev);
3007 3015
@@ -3017,9 +3025,10 @@ static int dce_v10_0_suspend(struct amdgpu_device *adev)
3017 return 0; 3025 return 0;
3018} 3026}
3019 3027
3020static int dce_v10_0_resume(struct amdgpu_device *adev) 3028static int dce_v10_0_resume(void *handle)
3021{ 3029{
3022 struct drm_connector *connector; 3030 struct drm_connector *connector;
3031 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3023 3032
3024 dce_v10_0_init_golden_registers(adev); 3033 dce_v10_0_init_golden_registers(adev);
3025 3034
@@ -3051,33 +3060,34 @@ static int dce_v10_0_resume(struct amdgpu_device *adev)
3051 return 0; 3060 return 0;
3052} 3061}
3053 3062
3054static bool dce_v10_0_is_idle(struct amdgpu_device *adev) 3063static bool dce_v10_0_is_idle(void *handle)
3055{ 3064{
3056 /* XXX todo */
3057 return true; 3065 return true;
3058} 3066}
3059 3067
3060static int dce_v10_0_wait_for_idle(struct amdgpu_device *adev) 3068static int dce_v10_0_wait_for_idle(void *handle)
3061{ 3069{
3062 /* XXX todo */
3063 return 0; 3070 return 0;
3064} 3071}
3065 3072
3066static void dce_v10_0_print_status(struct amdgpu_device *adev) 3073static void dce_v10_0_print_status(void *handle)
3067{ 3074{
3075 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3076
3068 dev_info(adev->dev, "DCE 10.x registers\n"); 3077 dev_info(adev->dev, "DCE 10.x registers\n");
3069 /* XXX todo */ 3078 /* XXX todo */
3070} 3079}
3071 3080
3072static int dce_v10_0_soft_reset(struct amdgpu_device *adev) 3081static int dce_v10_0_soft_reset(void *handle)
3073{ 3082{
3074 u32 srbm_soft_reset = 0, tmp; 3083 u32 srbm_soft_reset = 0, tmp;
3084 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3075 3085
3076 if (dce_v10_0_is_display_hung(adev)) 3086 if (dce_v10_0_is_display_hung(adev))
3077 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 3087 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3078 3088
3079 if (srbm_soft_reset) { 3089 if (srbm_soft_reset) {
3080 dce_v10_0_print_status(adev); 3090 dce_v10_0_print_status((void *)adev);
3081 3091
3082 tmp = RREG32(mmSRBM_SOFT_RESET); 3092 tmp = RREG32(mmSRBM_SOFT_RESET);
3083 tmp |= srbm_soft_reset; 3093 tmp |= srbm_soft_reset;
@@ -3093,7 +3103,7 @@ static int dce_v10_0_soft_reset(struct amdgpu_device *adev)
3093 3103
3094 /* Wait a little for things to settle down */ 3104 /* Wait a little for things to settle down */
3095 udelay(50); 3105 udelay(50);
3096 dce_v10_0_print_status(adev); 3106 dce_v10_0_print_status((void *)adev);
3097 } 3107 }
3098 return 0; 3108 return 0;
3099} 3109}
@@ -3449,19 +3459,19 @@ static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
3449 return 0; 3459 return 0;
3450} 3460}
3451 3461
3452static int dce_v10_0_set_clockgating_state(struct amdgpu_device *adev, 3462static int dce_v10_0_set_clockgating_state(void *handle,
3453 enum amdgpu_clockgating_state state) 3463 enum amd_clockgating_state state)
3454{ 3464{
3455 return 0; 3465 return 0;
3456} 3466}
3457 3467
3458static int dce_v10_0_set_powergating_state(struct amdgpu_device *adev, 3468static int dce_v10_0_set_powergating_state(void *handle,
3459 enum amdgpu_powergating_state state) 3469 enum amd_powergating_state state)
3460{ 3470{
3461 return 0; 3471 return 0;
3462} 3472}
3463 3473
3464const struct amdgpu_ip_funcs dce_v10_0_ip_funcs = { 3474const struct amd_ip_funcs dce_v10_0_ip_funcs = {
3465 .early_init = dce_v10_0_early_init, 3475 .early_init = dce_v10_0_early_init,
3466 .late_init = NULL, 3476 .late_init = NULL,
3467 .sw_init = dce_v10_0_sw_init, 3477 .sw_init = dce_v10_0_sw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h
index 72ca20d1793c..1bfa48ddd8a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h
@@ -24,6 +24,6 @@
24#ifndef __DCE_V10_0_H__ 24#ifndef __DCE_V10_0_H__
25#define __DCE_V10_0_H__ 25#define __DCE_V10_0_H__
26 26
27extern const struct amdgpu_ip_funcs dce_v10_0_ip_funcs; 27extern const struct amd_ip_funcs dce_v10_0_ip_funcs;
28 28
29#endif 29#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 04a5d4cd75b6..edd9d17ba82a 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -2863,8 +2863,10 @@ static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2863 return 0; 2863 return 0;
2864} 2864}
2865 2865
2866static int dce_v11_0_early_init(struct amdgpu_device *adev) 2866static int dce_v11_0_early_init(void *handle)
2867{ 2867{
2868 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2869
2868 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg; 2870 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2869 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg; 2871 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2870 2872
@@ -2885,9 +2887,10 @@ static int dce_v11_0_early_init(struct amdgpu_device *adev)
2885 return 0; 2887 return 0;
2886} 2888}
2887 2889
2888static int dce_v11_0_sw_init(struct amdgpu_device *adev) 2890static int dce_v11_0_sw_init(void *handle)
2889{ 2891{
2890 int r, i; 2892 int r, i;
2893 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2891 2894
2892 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2895 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2893 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); 2896 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
@@ -2949,8 +2952,10 @@ static int dce_v11_0_sw_init(struct amdgpu_device *adev)
2949 return r; 2952 return r;
2950} 2953}
2951 2954
2952static int dce_v11_0_sw_fini(struct amdgpu_device *adev) 2955static int dce_v11_0_sw_fini(void *handle)
2953{ 2956{
2957 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2958
2954 kfree(adev->mode_info.bios_hardcoded_edid); 2959 kfree(adev->mode_info.bios_hardcoded_edid);
2955 2960
2956 drm_kms_helper_poll_fini(adev->ddev); 2961 drm_kms_helper_poll_fini(adev->ddev);
@@ -2964,9 +2969,10 @@ static int dce_v11_0_sw_fini(struct amdgpu_device *adev)
2964 return 0; 2969 return 0;
2965} 2970}
2966 2971
2967static int dce_v11_0_hw_init(struct amdgpu_device *adev) 2972static int dce_v11_0_hw_init(void *handle)
2968{ 2973{
2969 int i; 2974 int i;
2975 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2970 2976
2971 dce_v11_0_init_golden_registers(adev); 2977 dce_v11_0_init_golden_registers(adev);
2972 2978
@@ -2984,9 +2990,10 @@ static int dce_v11_0_hw_init(struct amdgpu_device *adev)
2984 return 0; 2990 return 0;
2985} 2991}
2986 2992
2987static int dce_v11_0_hw_fini(struct amdgpu_device *adev) 2993static int dce_v11_0_hw_fini(void *handle)
2988{ 2994{
2989 int i; 2995 int i;
2996 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2990 2997
2991 dce_v11_0_hpd_fini(adev); 2998 dce_v11_0_hpd_fini(adev);
2992 2999
@@ -2997,9 +3004,10 @@ static int dce_v11_0_hw_fini(struct amdgpu_device *adev)
2997 return 0; 3004 return 0;
2998} 3005}
2999 3006
3000static int dce_v11_0_suspend(struct amdgpu_device *adev) 3007static int dce_v11_0_suspend(void *handle)
3001{ 3008{
3002 struct drm_connector *connector; 3009 struct drm_connector *connector;
3010 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3003 3011
3004 drm_kms_helper_poll_disable(adev->ddev); 3012 drm_kms_helper_poll_disable(adev->ddev);
3005 3013
@@ -3015,9 +3023,10 @@ static int dce_v11_0_suspend(struct amdgpu_device *adev)
3015 return 0; 3023 return 0;
3016} 3024}
3017 3025
3018static int dce_v11_0_resume(struct amdgpu_device *adev) 3026static int dce_v11_0_resume(void *handle)
3019{ 3027{
3020 struct drm_connector *connector; 3028 struct drm_connector *connector;
3029 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3021 3030
3022 dce_v11_0_init_golden_registers(adev); 3031 dce_v11_0_init_golden_registers(adev);
3023 3032
@@ -3050,33 +3059,34 @@ static int dce_v11_0_resume(struct amdgpu_device *adev)
3050 return 0; 3059 return 0;
3051} 3060}
3052 3061
3053static bool dce_v11_0_is_idle(struct amdgpu_device *adev) 3062static bool dce_v11_0_is_idle(void *handle)
3054{ 3063{
3055 /* XXX todo */
3056 return true; 3064 return true;
3057} 3065}
3058 3066
3059static int dce_v11_0_wait_for_idle(struct amdgpu_device *adev) 3067static int dce_v11_0_wait_for_idle(void *handle)
3060{ 3068{
3061 /* XXX todo */
3062 return 0; 3069 return 0;
3063} 3070}
3064 3071
3065static void dce_v11_0_print_status(struct amdgpu_device *adev) 3072static void dce_v11_0_print_status(void *handle)
3066{ 3073{
3074 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3075
3067 dev_info(adev->dev, "DCE 10.x registers\n"); 3076 dev_info(adev->dev, "DCE 10.x registers\n");
3068 /* XXX todo */ 3077 /* XXX todo */
3069} 3078}
3070 3079
3071static int dce_v11_0_soft_reset(struct amdgpu_device *adev) 3080static int dce_v11_0_soft_reset(void *handle)
3072{ 3081{
3073 u32 srbm_soft_reset = 0, tmp; 3082 u32 srbm_soft_reset = 0, tmp;
3083 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3074 3084
3075 if (dce_v11_0_is_display_hung(adev)) 3085 if (dce_v11_0_is_display_hung(adev))
3076 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 3086 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3077 3087
3078 if (srbm_soft_reset) { 3088 if (srbm_soft_reset) {
3079 dce_v11_0_print_status(adev); 3089 dce_v11_0_print_status((void *)adev);
3080 3090
3081 tmp = RREG32(mmSRBM_SOFT_RESET); 3091 tmp = RREG32(mmSRBM_SOFT_RESET);
3082 tmp |= srbm_soft_reset; 3092 tmp |= srbm_soft_reset;
@@ -3092,7 +3102,7 @@ static int dce_v11_0_soft_reset(struct amdgpu_device *adev)
3092 3102
3093 /* Wait a little for things to settle down */ 3103 /* Wait a little for things to settle down */
3094 udelay(50); 3104 udelay(50);
3095 dce_v11_0_print_status(adev); 3105 dce_v11_0_print_status((void *)adev);
3096 } 3106 }
3097 return 0; 3107 return 0;
3098} 3108}
@@ -3448,19 +3458,19 @@ static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3448 return 0; 3458 return 0;
3449} 3459}
3450 3460
3451static int dce_v11_0_set_clockgating_state(struct amdgpu_device *adev, 3461static int dce_v11_0_set_clockgating_state(void *handle,
3452 enum amdgpu_clockgating_state state) 3462 enum amd_clockgating_state state)
3453{ 3463{
3454 return 0; 3464 return 0;
3455} 3465}
3456 3466
3457static int dce_v11_0_set_powergating_state(struct amdgpu_device *adev, 3467static int dce_v11_0_set_powergating_state(void *handle,
3458 enum amdgpu_powergating_state state) 3468 enum amd_powergating_state state)
3459{ 3469{
3460 return 0; 3470 return 0;
3461} 3471}
3462 3472
3463const struct amdgpu_ip_funcs dce_v11_0_ip_funcs = { 3473const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3464 .early_init = dce_v11_0_early_init, 3474 .early_init = dce_v11_0_early_init,
3465 .late_init = NULL, 3475 .late_init = NULL,
3466 .sw_init = dce_v11_0_sw_init, 3476 .sw_init = dce_v11_0_sw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h
index eeb9a56b514a..84e4618f5253 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h
@@ -24,6 +24,6 @@
24#ifndef __DCE_V11_0_H__ 24#ifndef __DCE_V11_0_H__
25#define __DCE_V11_0_H__ 25#define __DCE_V11_0_H__
26 26
27extern const struct amdgpu_ip_funcs dce_v11_0_ip_funcs; 27extern const struct amd_ip_funcs dce_v11_0_ip_funcs;
28 28
29#endif 29#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 9f2ff8d374f3..1d291f1d5b79 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -2794,8 +2794,10 @@ static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
2794 return 0; 2794 return 0;
2795} 2795}
2796 2796
2797static int dce_v8_0_early_init(struct amdgpu_device *adev) 2797static int dce_v8_0_early_init(void *handle)
2798{ 2798{
2799 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2800
2799 adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg; 2801 adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg;
2800 adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg; 2802 adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg;
2801 2803
@@ -2828,9 +2830,10 @@ static int dce_v8_0_early_init(struct amdgpu_device *adev)
2828 return 0; 2830 return 0;
2829} 2831}
2830 2832
2831static int dce_v8_0_sw_init(struct amdgpu_device *adev) 2833static int dce_v8_0_sw_init(void *handle)
2832{ 2834{
2833 int r, i; 2835 int r, i;
2836 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2834 2837
2835 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2838 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2836 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); 2839 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
@@ -2892,8 +2895,10 @@ static int dce_v8_0_sw_init(struct amdgpu_device *adev)
2892 return r; 2895 return r;
2893} 2896}
2894 2897
2895static int dce_v8_0_sw_fini(struct amdgpu_device *adev) 2898static int dce_v8_0_sw_fini(void *handle)
2896{ 2899{
2900 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2901
2897 kfree(adev->mode_info.bios_hardcoded_edid); 2902 kfree(adev->mode_info.bios_hardcoded_edid);
2898 2903
2899 drm_kms_helper_poll_fini(adev->ddev); 2904 drm_kms_helper_poll_fini(adev->ddev);
@@ -2908,9 +2913,10 @@ static int dce_v8_0_sw_fini(struct amdgpu_device *adev)
2908 return 0; 2913 return 0;
2909} 2914}
2910 2915
2911static int dce_v8_0_hw_init(struct amdgpu_device *adev) 2916static int dce_v8_0_hw_init(void *handle)
2912{ 2917{
2913 int i; 2918 int i;
2919 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2914 2920
2915 /* init dig PHYs, disp eng pll */ 2921 /* init dig PHYs, disp eng pll */
2916 amdgpu_atombios_encoder_init_dig(adev); 2922 amdgpu_atombios_encoder_init_dig(adev);
@@ -2926,9 +2932,10 @@ static int dce_v8_0_hw_init(struct amdgpu_device *adev)
2926 return 0; 2932 return 0;
2927} 2933}
2928 2934
2929static int dce_v8_0_hw_fini(struct amdgpu_device *adev) 2935static int dce_v8_0_hw_fini(void *handle)
2930{ 2936{
2931 int i; 2937 int i;
2938 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2932 2939
2933 dce_v8_0_hpd_fini(adev); 2940 dce_v8_0_hpd_fini(adev);
2934 2941
@@ -2939,9 +2946,10 @@ static int dce_v8_0_hw_fini(struct amdgpu_device *adev)
2939 return 0; 2946 return 0;
2940} 2947}
2941 2948
2942static int dce_v8_0_suspend(struct amdgpu_device *adev) 2949static int dce_v8_0_suspend(void *handle)
2943{ 2950{
2944 struct drm_connector *connector; 2951 struct drm_connector *connector;
2952 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2945 2953
2946 drm_kms_helper_poll_disable(adev->ddev); 2954 drm_kms_helper_poll_disable(adev->ddev);
2947 2955
@@ -2957,9 +2965,10 @@ static int dce_v8_0_suspend(struct amdgpu_device *adev)
2957 return 0; 2965 return 0;
2958} 2966}
2959 2967
2960static int dce_v8_0_resume(struct amdgpu_device *adev) 2968static int dce_v8_0_resume(void *handle)
2961{ 2969{
2962 struct drm_connector *connector; 2970 struct drm_connector *connector;
2971 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2963 2972
2964 amdgpu_atombios_scratch_regs_restore(adev); 2973 amdgpu_atombios_scratch_regs_restore(adev);
2965 2974
@@ -2989,33 +2998,34 @@ static int dce_v8_0_resume(struct amdgpu_device *adev)
2989 return 0; 2998 return 0;
2990} 2999}
2991 3000
2992static bool dce_v8_0_is_idle(struct amdgpu_device *adev) 3001static bool dce_v8_0_is_idle(void *handle)
2993{ 3002{
2994 /* XXX todo */
2995 return true; 3003 return true;
2996} 3004}
2997 3005
2998static int dce_v8_0_wait_for_idle(struct amdgpu_device *adev) 3006static int dce_v8_0_wait_for_idle(void *handle)
2999{ 3007{
3000 /* XXX todo */
3001 return 0; 3008 return 0;
3002} 3009}
3003 3010
3004static void dce_v8_0_print_status(struct amdgpu_device *adev) 3011static void dce_v8_0_print_status(void *handle)
3005{ 3012{
3013 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3014
3006 dev_info(adev->dev, "DCE 8.x registers\n"); 3015 dev_info(adev->dev, "DCE 8.x registers\n");
3007 /* XXX todo */ 3016 /* XXX todo */
3008} 3017}
3009 3018
3010static int dce_v8_0_soft_reset(struct amdgpu_device *adev) 3019static int dce_v8_0_soft_reset(void *handle)
3011{ 3020{
3012 u32 srbm_soft_reset = 0, tmp; 3021 u32 srbm_soft_reset = 0, tmp;
3022 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3013 3023
3014 if (dce_v8_0_is_display_hung(adev)) 3024 if (dce_v8_0_is_display_hung(adev))
3015 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 3025 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3016 3026
3017 if (srbm_soft_reset) { 3027 if (srbm_soft_reset) {
3018 dce_v8_0_print_status(adev); 3028 dce_v8_0_print_status((void *)adev);
3019 3029
3020 tmp = RREG32(mmSRBM_SOFT_RESET); 3030 tmp = RREG32(mmSRBM_SOFT_RESET);
3021 tmp |= srbm_soft_reset; 3031 tmp |= srbm_soft_reset;
@@ -3031,7 +3041,7 @@ static int dce_v8_0_soft_reset(struct amdgpu_device *adev)
3031 3041
3032 /* Wait a little for things to settle down */ 3042 /* Wait a little for things to settle down */
3033 udelay(50); 3043 udelay(50);
3034 dce_v8_0_print_status(adev); 3044 dce_v8_0_print_status((void *)adev);
3035 } 3045 }
3036 return 0; 3046 return 0;
3037} 3047}
@@ -3409,19 +3419,19 @@ static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,
3409 3419
3410} 3420}
3411 3421
3412static int dce_v8_0_set_clockgating_state(struct amdgpu_device *adev, 3422static int dce_v8_0_set_clockgating_state(void *handle,
3413 enum amdgpu_clockgating_state state) 3423 enum amd_clockgating_state state)
3414{ 3424{
3415 return 0; 3425 return 0;
3416} 3426}
3417 3427
3418static int dce_v8_0_set_powergating_state(struct amdgpu_device *adev, 3428static int dce_v8_0_set_powergating_state(void *handle,
3419 enum amdgpu_powergating_state state) 3429 enum amd_powergating_state state)
3420{ 3430{
3421 return 0; 3431 return 0;
3422} 3432}
3423 3433
3424const struct amdgpu_ip_funcs dce_v8_0_ip_funcs = { 3434const struct amd_ip_funcs dce_v8_0_ip_funcs = {
3425 .early_init = dce_v8_0_early_init, 3435 .early_init = dce_v8_0_early_init,
3426 .late_init = NULL, 3436 .late_init = NULL,
3427 .sw_init = dce_v8_0_sw_init, 3437 .sw_init = dce_v8_0_sw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h
index 3a0a73b41041..77016852b252 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h
@@ -24,6 +24,6 @@
24#ifndef __DCE_V8_0_H__ 24#ifndef __DCE_V8_0_H__
25#define __DCE_V8_0_H__ 25#define __DCE_V8_0_H__
26 26
27extern const struct amdgpu_ip_funcs dce_v8_0_ip_funcs; 27extern const struct amd_ip_funcs dce_v8_0_ip_funcs;
28 28
29#endif 29#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 5315c13a8921..0057699cb8fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4682,8 +4682,9 @@ static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4682 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); 4682 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4683} 4683}
4684 4684
4685static int gfx_v7_0_early_init(struct amdgpu_device *adev) 4685static int gfx_v7_0_early_init(void *handle)
4686{ 4686{
4687 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4687 4688
4688 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS; 4689 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
4689 adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS; 4690 adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS;
@@ -4694,9 +4695,10 @@ static int gfx_v7_0_early_init(struct amdgpu_device *adev)
4694 return 0; 4695 return 0;
4695} 4696}
4696 4697
4697static int gfx_v7_0_sw_init(struct amdgpu_device *adev) 4698static int gfx_v7_0_sw_init(void *handle)
4698{ 4699{
4699 struct amdgpu_ring *ring; 4700 struct amdgpu_ring *ring;
4701 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4700 int i, r; 4702 int i, r;
4701 4703
4702 /* EOP Event */ 4704 /* EOP Event */
@@ -4805,9 +4807,10 @@ static int gfx_v7_0_sw_init(struct amdgpu_device *adev)
4805 return r; 4807 return r;
4806} 4808}
4807 4809
4808static int gfx_v7_0_sw_fini(struct amdgpu_device *adev) 4810static int gfx_v7_0_sw_fini(void *handle)
4809{ 4811{
4810 int i; 4812 int i;
4813 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4811 4814
4812 amdgpu_bo_unref(&adev->gds.oa_gfx_bo); 4815 amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
4813 amdgpu_bo_unref(&adev->gds.gws_gfx_bo); 4816 amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
@@ -4827,9 +4830,10 @@ static int gfx_v7_0_sw_fini(struct amdgpu_device *adev)
4827 return 0; 4830 return 0;
4828} 4831}
4829 4832
4830static int gfx_v7_0_hw_init(struct amdgpu_device *adev) 4833static int gfx_v7_0_hw_init(void *handle)
4831{ 4834{
4832 int r; 4835 int r;
4836 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4833 4837
4834 gfx_v7_0_gpu_init(adev); 4838 gfx_v7_0_gpu_init(adev);
4835 4839
@@ -4845,8 +4849,10 @@ static int gfx_v7_0_hw_init(struct amdgpu_device *adev)
4845 return r; 4849 return r;
4846} 4850}
4847 4851
4848static int gfx_v7_0_hw_fini(struct amdgpu_device *adev) 4852static int gfx_v7_0_hw_fini(void *handle)
4849{ 4853{
4854 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4855
4850 gfx_v7_0_cp_enable(adev, false); 4856 gfx_v7_0_cp_enable(adev, false);
4851 gfx_v7_0_rlc_stop(adev); 4857 gfx_v7_0_rlc_stop(adev);
4852 gfx_v7_0_fini_pg(adev); 4858 gfx_v7_0_fini_pg(adev);
@@ -4854,28 +4860,35 @@ static int gfx_v7_0_hw_fini(struct amdgpu_device *adev)
4854 return 0; 4860 return 0;
4855} 4861}
4856 4862
4857static int gfx_v7_0_suspend(struct amdgpu_device *adev) 4863static int gfx_v7_0_suspend(void *handle)
4858{ 4864{
4865 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4866
4859 return gfx_v7_0_hw_fini(adev); 4867 return gfx_v7_0_hw_fini(adev);
4860} 4868}
4861 4869
4862static int gfx_v7_0_resume(struct amdgpu_device *adev) 4870static int gfx_v7_0_resume(void *handle)
4863{ 4871{
4872 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4873
4864 return gfx_v7_0_hw_init(adev); 4874 return gfx_v7_0_hw_init(adev);
4865} 4875}
4866 4876
4867static bool gfx_v7_0_is_idle(struct amdgpu_device *adev) 4877static bool gfx_v7_0_is_idle(void *handle)
4868{ 4878{
4879 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4880
4869 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) 4881 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
4870 return false; 4882 return false;
4871 else 4883 else
4872 return true; 4884 return true;
4873} 4885}
4874 4886
4875static int gfx_v7_0_wait_for_idle(struct amdgpu_device *adev) 4887static int gfx_v7_0_wait_for_idle(void *handle)
4876{ 4888{
4877 unsigned i; 4889 unsigned i;
4878 u32 tmp; 4890 u32 tmp;
4891 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4879 4892
4880 for (i = 0; i < adev->usec_timeout; i++) { 4893 for (i = 0; i < adev->usec_timeout; i++) {
4881 /* read MC_STATUS */ 4894 /* read MC_STATUS */
@@ -4888,9 +4901,10 @@ static int gfx_v7_0_wait_for_idle(struct amdgpu_device *adev)
4888 return -ETIMEDOUT; 4901 return -ETIMEDOUT;
4889} 4902}
4890 4903
4891static void gfx_v7_0_print_status(struct amdgpu_device *adev) 4904static void gfx_v7_0_print_status(void *handle)
4892{ 4905{
4893 int i; 4906 int i;
4907 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4894 4908
4895 dev_info(adev->dev, "GFX 7.x registers\n"); 4909 dev_info(adev->dev, "GFX 7.x registers\n");
4896 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n", 4910 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
@@ -5147,10 +5161,11 @@ static void gfx_v7_0_print_status(struct amdgpu_device *adev)
5147 mutex_unlock(&adev->srbm_mutex); 5161 mutex_unlock(&adev->srbm_mutex);
5148} 5162}
5149 5163
5150static int gfx_v7_0_soft_reset(struct amdgpu_device *adev) 5164static int gfx_v7_0_soft_reset(void *handle)
5151{ 5165{
5152 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 5166 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
5153 u32 tmp; 5167 u32 tmp;
5168 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5154 5169
5155 /* GRBM_STATUS */ 5170 /* GRBM_STATUS */
5156 tmp = RREG32(mmGRBM_STATUS); 5171 tmp = RREG32(mmGRBM_STATUS);
@@ -5179,7 +5194,7 @@ static int gfx_v7_0_soft_reset(struct amdgpu_device *adev)
5179 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; 5194 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
5180 5195
5181 if (grbm_soft_reset || srbm_soft_reset) { 5196 if (grbm_soft_reset || srbm_soft_reset) {
5182 gfx_v7_0_print_status(adev); 5197 gfx_v7_0_print_status((void *)adev);
5183 /* disable CG/PG */ 5198 /* disable CG/PG */
5184 gfx_v7_0_fini_pg(adev); 5199 gfx_v7_0_fini_pg(adev);
5185 gfx_v7_0_update_cg(adev, false); 5200 gfx_v7_0_update_cg(adev, false);
@@ -5222,7 +5237,7 @@ static int gfx_v7_0_soft_reset(struct amdgpu_device *adev)
5222 } 5237 }
5223 /* Wait a little for things to settle down */ 5238 /* Wait a little for things to settle down */
5224 udelay(50); 5239 udelay(50);
5225 gfx_v7_0_print_status(adev); 5240 gfx_v7_0_print_status((void *)adev);
5226 } 5241 }
5227 return 0; 5242 return 0;
5228} 5243}
@@ -5425,12 +5440,13 @@ static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
5425 return 0; 5440 return 0;
5426} 5441}
5427 5442
5428static int gfx_v7_0_set_clockgating_state(struct amdgpu_device *adev, 5443static int gfx_v7_0_set_clockgating_state(void *handle,
5429 enum amdgpu_clockgating_state state) 5444 enum amd_clockgating_state state)
5430{ 5445{
5431 bool gate = false; 5446 bool gate = false;
5447 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5432 5448
5433 if (state == AMDGPU_CG_STATE_GATE) 5449 if (state == AMD_CG_STATE_GATE)
5434 gate = true; 5450 gate = true;
5435 5451
5436 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 5452 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
@@ -5447,12 +5463,13 @@ static int gfx_v7_0_set_clockgating_state(struct amdgpu_device *adev,
5447 return 0; 5463 return 0;
5448} 5464}
5449 5465
5450static int gfx_v7_0_set_powergating_state(struct amdgpu_device *adev, 5466static int gfx_v7_0_set_powergating_state(void *handle,
5451 enum amdgpu_powergating_state state) 5467 enum amd_powergating_state state)
5452{ 5468{
5453 bool gate = false; 5469 bool gate = false;
5470 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5454 5471
5455 if (state == AMDGPU_PG_STATE_GATE) 5472 if (state == AMD_PG_STATE_GATE)
5456 gate = true; 5473 gate = true;
5457 5474
5458 if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG | 5475 if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
@@ -5471,7 +5488,7 @@ static int gfx_v7_0_set_powergating_state(struct amdgpu_device *adev,
5471 return 0; 5488 return 0;
5472} 5489}
5473 5490
5474const struct amdgpu_ip_funcs gfx_v7_0_ip_funcs = { 5491const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
5475 .early_init = gfx_v7_0_early_init, 5492 .early_init = gfx_v7_0_early_init,
5476 .late_init = NULL, 5493 .late_init = NULL,
5477 .sw_init = gfx_v7_0_sw_init, 5494 .sw_init = gfx_v7_0_sw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h
index 668b91a89e1e..c04bfbabfc88 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h
@@ -24,7 +24,7 @@
24#ifndef __GFX_V7_0_H__ 24#ifndef __GFX_V7_0_H__
25#define __GFX_V7_0_H__ 25#define __GFX_V7_0_H__
26 26
27extern const struct amdgpu_ip_funcs gfx_v7_0_ip_funcs; 27extern const struct amd_ip_funcs gfx_v7_0_ip_funcs;
28 28
29/* XXX these shouldn't be exported */ 29/* XXX these shouldn't be exported */
30void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev); 30void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 4597256cc6e2..a7d687da10d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -784,10 +784,11 @@ static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
784 return 0; 784 return 0;
785} 785}
786 786
787static int gfx_v8_0_sw_init(struct amdgpu_device *adev) 787static int gfx_v8_0_sw_init(void *handle)
788{ 788{
789 int i, r; 789 int i, r;
790 struct amdgpu_ring *ring; 790 struct amdgpu_ring *ring;
791 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
791 792
792 /* EOP Event */ 793 /* EOP Event */
793 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq); 794 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
@@ -897,9 +898,10 @@ static int gfx_v8_0_sw_init(struct amdgpu_device *adev)
897 return 0; 898 return 0;
898} 899}
899 900
900static int gfx_v8_0_sw_fini(struct amdgpu_device *adev) 901static int gfx_v8_0_sw_fini(void *handle)
901{ 902{
902 int i; 903 int i;
904 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
903 905
904 amdgpu_bo_unref(&adev->gds.oa_gfx_bo); 906 amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
905 amdgpu_bo_unref(&adev->gds.gws_gfx_bo); 907 amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
@@ -3148,9 +3150,10 @@ static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
3148 gfx_v8_0_cp_compute_enable(adev, enable); 3150 gfx_v8_0_cp_compute_enable(adev, enable);
3149} 3151}
3150 3152
3151static int gfx_v8_0_hw_init(struct amdgpu_device *adev) 3153static int gfx_v8_0_hw_init(void *handle)
3152{ 3154{
3153 int r; 3155 int r;
3156 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3154 3157
3155 gfx_v8_0_init_golden_registers(adev); 3158 gfx_v8_0_init_golden_registers(adev);
3156 3159
@@ -3167,8 +3170,10 @@ static int gfx_v8_0_hw_init(struct amdgpu_device *adev)
3167 return r; 3170 return r;
3168} 3171}
3169 3172
3170static int gfx_v8_0_hw_fini(struct amdgpu_device *adev) 3173static int gfx_v8_0_hw_fini(void *handle)
3171{ 3174{
3175 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3176
3172 gfx_v8_0_cp_enable(adev, false); 3177 gfx_v8_0_cp_enable(adev, false);
3173 gfx_v8_0_rlc_stop(adev); 3178 gfx_v8_0_rlc_stop(adev);
3174 gfx_v8_0_cp_compute_fini(adev); 3179 gfx_v8_0_cp_compute_fini(adev);
@@ -3176,28 +3181,35 @@ static int gfx_v8_0_hw_fini(struct amdgpu_device *adev)
3176 return 0; 3181 return 0;
3177} 3182}
3178 3183
3179static int gfx_v8_0_suspend(struct amdgpu_device *adev) 3184static int gfx_v8_0_suspend(void *handle)
3180{ 3185{
3186 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3187
3181 return gfx_v8_0_hw_fini(adev); 3188 return gfx_v8_0_hw_fini(adev);
3182} 3189}
3183 3190
3184static int gfx_v8_0_resume(struct amdgpu_device *adev) 3191static int gfx_v8_0_resume(void *handle)
3185{ 3192{
3193 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3194
3186 return gfx_v8_0_hw_init(adev); 3195 return gfx_v8_0_hw_init(adev);
3187} 3196}
3188 3197
3189static bool gfx_v8_0_is_idle(struct amdgpu_device *adev) 3198static bool gfx_v8_0_is_idle(void *handle)
3190{ 3199{
3200 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3201
3191 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)) 3202 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
3192 return false; 3203 return false;
3193 else 3204 else
3194 return true; 3205 return true;
3195} 3206}
3196 3207
3197static int gfx_v8_0_wait_for_idle(struct amdgpu_device *adev) 3208static int gfx_v8_0_wait_for_idle(void *handle)
3198{ 3209{
3199 unsigned i; 3210 unsigned i;
3200 u32 tmp; 3211 u32 tmp;
3212 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3201 3213
3202 for (i = 0; i < adev->usec_timeout; i++) { 3214 for (i = 0; i < adev->usec_timeout; i++) {
3203 /* read MC_STATUS */ 3215 /* read MC_STATUS */
@@ -3210,9 +3222,10 @@ static int gfx_v8_0_wait_for_idle(struct amdgpu_device *adev)
3210 return -ETIMEDOUT; 3222 return -ETIMEDOUT;
3211} 3223}
3212 3224
3213static void gfx_v8_0_print_status(struct amdgpu_device *adev) 3225static void gfx_v8_0_print_status(void *handle)
3214{ 3226{
3215 int i; 3227 int i;
3228 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3216 3229
3217 dev_info(adev->dev, "GFX 8.x registers\n"); 3230 dev_info(adev->dev, "GFX 8.x registers\n");
3218 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n", 3231 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
@@ -3398,10 +3411,11 @@ static void gfx_v8_0_print_status(struct amdgpu_device *adev)
3398 mutex_unlock(&adev->srbm_mutex); 3411 mutex_unlock(&adev->srbm_mutex);
3399} 3412}
3400 3413
3401static int gfx_v8_0_soft_reset(struct amdgpu_device *adev) 3414static int gfx_v8_0_soft_reset(void *handle)
3402{ 3415{
3403 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 3416 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
3404 u32 tmp; 3417 u32 tmp;
3418 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3405 3419
3406 /* GRBM_STATUS */ 3420 /* GRBM_STATUS */
3407 tmp = RREG32(mmGRBM_STATUS); 3421 tmp = RREG32(mmGRBM_STATUS);
@@ -3437,7 +3451,7 @@ static int gfx_v8_0_soft_reset(struct amdgpu_device *adev)
3437 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1); 3451 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
3438 3452
3439 if (grbm_soft_reset || srbm_soft_reset) { 3453 if (grbm_soft_reset || srbm_soft_reset) {
3440 gfx_v8_0_print_status(adev); 3454 gfx_v8_0_print_status((void *)adev);
3441 /* stop the rlc */ 3455 /* stop the rlc */
3442 gfx_v8_0_rlc_stop(adev); 3456 gfx_v8_0_rlc_stop(adev);
3443 3457
@@ -3476,7 +3490,7 @@ static int gfx_v8_0_soft_reset(struct amdgpu_device *adev)
3476 } 3490 }
3477 /* Wait a little for things to settle down */ 3491 /* Wait a little for things to settle down */
3478 udelay(50); 3492 udelay(50);
3479 gfx_v8_0_print_status(adev); 3493 gfx_v8_0_print_status((void *)adev);
3480 } 3494 }
3481 return 0; 3495 return 0;
3482} 3496}
@@ -3549,8 +3563,9 @@ static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3549 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); 3563 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
3550} 3564}
3551 3565
3552static int gfx_v8_0_early_init(struct amdgpu_device *adev) 3566static int gfx_v8_0_early_init(void *handle)
3553{ 3567{
3568 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3554 3569
3555 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS; 3570 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
3556 adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS; 3571 adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS;
@@ -3561,14 +3576,14 @@ static int gfx_v8_0_early_init(struct amdgpu_device *adev)
3561 return 0; 3576 return 0;
3562} 3577}
3563 3578
3564static int gfx_v8_0_set_powergating_state(struct amdgpu_device *adev, 3579static int gfx_v8_0_set_powergating_state(void *handle,
3565 enum amdgpu_powergating_state state) 3580 enum amd_powergating_state state)
3566{ 3581{
3567 return 0; 3582 return 0;
3568} 3583}
3569 3584
3570static int gfx_v8_0_set_clockgating_state(struct amdgpu_device *adev, 3585static int gfx_v8_0_set_clockgating_state(void *handle,
3571 enum amdgpu_clockgating_state state) 3586 enum amd_clockgating_state state)
3572{ 3587{
3573 return 0; 3588 return 0;
3574} 3589}
@@ -4116,7 +4131,7 @@ static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
4116 return 0; 4131 return 0;
4117} 4132}
4118 4133
4119const struct amdgpu_ip_funcs gfx_v8_0_ip_funcs = { 4134const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
4120 .early_init = gfx_v8_0_early_init, 4135 .early_init = gfx_v8_0_early_init,
4121 .late_init = NULL, 4136 .late_init = NULL,
4122 .sw_init = gfx_v8_0_sw_init, 4137 .sw_init = gfx_v8_0_sw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h
index be8a5f8e176e..021e05193cb9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h
@@ -24,7 +24,7 @@
24#ifndef __GFX_V8_0_H__ 24#ifndef __GFX_V8_0_H__
25#define __GFX_V8_0_H__ 25#define __GFX_V8_0_H__
26 26
27extern const struct amdgpu_ip_funcs gfx_v8_0_ip_funcs; 27extern const struct amd_ip_funcs gfx_v8_0_ip_funcs;
28 28
29uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev); 29uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev);
30void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num); 30void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index ab096723a588..01cd6b207d26 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -812,8 +812,10 @@ static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
812 WREG32(mmHDP_MEM_POWER_LS, data); 812 WREG32(mmHDP_MEM_POWER_LS, data);
813} 813}
814 814
815static int gmc_v7_0_early_init(struct amdgpu_device *adev) 815static int gmc_v7_0_early_init(void *handle)
816{ 816{
817 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
818
817 gmc_v7_0_set_gart_funcs(adev); 819 gmc_v7_0_set_gart_funcs(adev);
818 gmc_v7_0_set_irq_funcs(adev); 820 gmc_v7_0_set_irq_funcs(adev);
819 821
@@ -832,10 +834,11 @@ static int gmc_v7_0_early_init(struct amdgpu_device *adev)
832 return 0; 834 return 0;
833} 835}
834 836
835static int gmc_v7_0_sw_init(struct amdgpu_device *adev) 837static int gmc_v7_0_sw_init(void *handle)
836{ 838{
837 int r; 839 int r;
838 int dma_bits; 840 int dma_bits;
841 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
839 842
840 r = amdgpu_gem_init(adev); 843 r = amdgpu_gem_init(adev);
841 if (r) 844 if (r)
@@ -911,9 +914,10 @@ static int gmc_v7_0_sw_init(struct amdgpu_device *adev)
911 return r; 914 return r;
912} 915}
913 916
914static int gmc_v7_0_sw_fini(struct amdgpu_device *adev) 917static int gmc_v7_0_sw_fini(void *handle)
915{ 918{
916 int i; 919 int i;
920 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
917 921
918 if (adev->vm_manager.enabled) { 922 if (adev->vm_manager.enabled) {
919 for (i = 0; i < AMDGPU_NUM_VM; ++i) 923 for (i = 0; i < AMDGPU_NUM_VM; ++i)
@@ -928,9 +932,10 @@ static int gmc_v7_0_sw_fini(struct amdgpu_device *adev)
928 return 0; 932 return 0;
929} 933}
930 934
931static int gmc_v7_0_hw_init(struct amdgpu_device *adev) 935static int gmc_v7_0_hw_init(void *handle)
932{ 936{
933 int r; 937 int r;
938 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
934 939
935 gmc_v7_0_mc_program(adev); 940 gmc_v7_0_mc_program(adev);
936 941
@@ -949,16 +954,19 @@ static int gmc_v7_0_hw_init(struct amdgpu_device *adev)
949 return r; 954 return r;
950} 955}
951 956
952static int gmc_v7_0_hw_fini(struct amdgpu_device *adev) 957static int gmc_v7_0_hw_fini(void *handle)
953{ 958{
959 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
960
954 gmc_v7_0_gart_disable(adev); 961 gmc_v7_0_gart_disable(adev);
955 962
956 return 0; 963 return 0;
957} 964}
958 965
959static int gmc_v7_0_suspend(struct amdgpu_device *adev) 966static int gmc_v7_0_suspend(void *handle)
960{ 967{
961 int i; 968 int i;
969 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
962 970
963 if (adev->vm_manager.enabled) { 971 if (adev->vm_manager.enabled) {
964 for (i = 0; i < AMDGPU_NUM_VM; ++i) 972 for (i = 0; i < AMDGPU_NUM_VM; ++i)
@@ -971,9 +979,10 @@ static int gmc_v7_0_suspend(struct amdgpu_device *adev)
971 return 0; 979 return 0;
972} 980}
973 981
974static int gmc_v7_0_resume(struct amdgpu_device *adev) 982static int gmc_v7_0_resume(void *handle)
975{ 983{
976 int r; 984 int r;
985 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
977 986
978 r = gmc_v7_0_hw_init(adev); 987 r = gmc_v7_0_hw_init(adev);
979 if (r) 988 if (r)
@@ -991,8 +1000,9 @@ static int gmc_v7_0_resume(struct amdgpu_device *adev)
991 return r; 1000 return r;
992} 1001}
993 1002
994static bool gmc_v7_0_is_idle(struct amdgpu_device *adev) 1003static bool gmc_v7_0_is_idle(void *handle)
995{ 1004{
1005 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
996 u32 tmp = RREG32(mmSRBM_STATUS); 1006 u32 tmp = RREG32(mmSRBM_STATUS);
997 1007
998 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1008 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
@@ -1002,10 +1012,11 @@ static bool gmc_v7_0_is_idle(struct amdgpu_device *adev)
1002 return true; 1012 return true;
1003} 1013}
1004 1014
1005static int gmc_v7_0_wait_for_idle(struct amdgpu_device *adev) 1015static int gmc_v7_0_wait_for_idle(void *handle)
1006{ 1016{
1007 unsigned i; 1017 unsigned i;
1008 u32 tmp; 1018 u32 tmp;
1019 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1009 1020
1010 for (i = 0; i < adev->usec_timeout; i++) { 1021 for (i = 0; i < adev->usec_timeout; i++) {
1011 /* read MC_STATUS */ 1022 /* read MC_STATUS */
@@ -1022,9 +1033,10 @@ static int gmc_v7_0_wait_for_idle(struct amdgpu_device *adev)
1022 1033
1023} 1034}
1024 1035
1025static void gmc_v7_0_print_status(struct amdgpu_device *adev) 1036static void gmc_v7_0_print_status(void *handle)
1026{ 1037{
1027 int i, j; 1038 int i, j;
1039 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1028 1040
1029 dev_info(adev->dev, "GMC 8.x registers\n"); 1041 dev_info(adev->dev, "GMC 8.x registers\n");
1030 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", 1042 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
@@ -1129,8 +1141,9 @@ static void gmc_v7_0_print_status(struct amdgpu_device *adev)
1129 RREG32(mmBIF_FB_EN)); 1141 RREG32(mmBIF_FB_EN));
1130} 1142}
1131 1143
1132static int gmc_v7_0_soft_reset(struct amdgpu_device *adev) 1144static int gmc_v7_0_soft_reset(void *handle)
1133{ 1145{
1146 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1134 struct amdgpu_mode_mc_save save; 1147 struct amdgpu_mode_mc_save save;
1135 u32 srbm_soft_reset = 0; 1148 u32 srbm_soft_reset = 0;
1136 u32 tmp = RREG32(mmSRBM_STATUS); 1149 u32 tmp = RREG32(mmSRBM_STATUS);
@@ -1147,7 +1160,7 @@ static int gmc_v7_0_soft_reset(struct amdgpu_device *adev)
1147 } 1160 }
1148 1161
1149 if (srbm_soft_reset) { 1162 if (srbm_soft_reset) {
1150 gmc_v7_0_print_status(adev); 1163 gmc_v7_0_print_status((void *)adev);
1151 1164
1152 gmc_v7_0_mc_stop(adev, &save); 1165 gmc_v7_0_mc_stop(adev, &save);
1153 if (gmc_v7_0_wait_for_idle(adev)) { 1166 if (gmc_v7_0_wait_for_idle(adev)) {
@@ -1173,7 +1186,7 @@ static int gmc_v7_0_soft_reset(struct amdgpu_device *adev)
1173 gmc_v7_0_mc_resume(adev, &save); 1186 gmc_v7_0_mc_resume(adev, &save);
1174 udelay(50); 1187 udelay(50);
1175 1188
1176 gmc_v7_0_print_status(adev); 1189 gmc_v7_0_print_status((void *)adev);
1177 } 1190 }
1178 1191
1179 return 0; 1192 return 0;
@@ -1242,12 +1255,13 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1242 return 0; 1255 return 0;
1243} 1256}
1244 1257
1245static int gmc_v7_0_set_clockgating_state(struct amdgpu_device *adev, 1258static int gmc_v7_0_set_clockgating_state(void *handle,
1246 enum amdgpu_clockgating_state state) 1259 enum amd_clockgating_state state)
1247{ 1260{
1248 bool gate = false; 1261 bool gate = false;
1262 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1249 1263
1250 if (state == AMDGPU_CG_STATE_GATE) 1264 if (state == AMD_CG_STATE_GATE)
1251 gate = true; 1265 gate = true;
1252 1266
1253 if (!(adev->flags & AMDGPU_IS_APU)) { 1267 if (!(adev->flags & AMDGPU_IS_APU)) {
@@ -1261,13 +1275,13 @@ static int gmc_v7_0_set_clockgating_state(struct amdgpu_device *adev,
1261 return 0; 1275 return 0;
1262} 1276}
1263 1277
1264static int gmc_v7_0_set_powergating_state(struct amdgpu_device *adev, 1278static int gmc_v7_0_set_powergating_state(void *handle,
1265 enum amdgpu_powergating_state state) 1279 enum amd_powergating_state state)
1266{ 1280{
1267 return 0; 1281 return 0;
1268} 1282}
1269 1283
1270const struct amdgpu_ip_funcs gmc_v7_0_ip_funcs = { 1284const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1271 .early_init = gmc_v7_0_early_init, 1285 .early_init = gmc_v7_0_early_init,
1272 .late_init = NULL, 1286 .late_init = NULL,
1273 .sw_init = gmc_v7_0_sw_init, 1287 .sw_init = gmc_v7_0_sw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h
index ab1a2fa1afcd..36fcbbc46ada 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h
@@ -24,7 +24,7 @@
24#ifndef __GMC_V7_0_H__ 24#ifndef __GMC_V7_0_H__
25#define __GMC_V7_0_H__ 25#define __GMC_V7_0_H__
26 26
27extern const struct amdgpu_ip_funcs gmc_v7_0_ip_funcs; 27extern const struct amd_ip_funcs gmc_v7_0_ip_funcs;
28 28
29/* XXX these shouldn't be exported */ 29/* XXX these shouldn't be exported */
30void gmc_v7_0_mc_stop(struct amdgpu_device *adev, 30void gmc_v7_0_mc_stop(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index f816165acd70..675483a612c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -786,8 +786,10 @@ static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
786 "write" : "read", block, mc_client, mc_id); 786 "write" : "read", block, mc_client, mc_id);
787} 787}
788 788
789static int gmc_v8_0_early_init(struct amdgpu_device *adev) 789static int gmc_v8_0_early_init(void *handle)
790{ 790{
791 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
792
791 gmc_v8_0_set_gart_funcs(adev); 793 gmc_v8_0_set_gart_funcs(adev);
792 gmc_v8_0_set_irq_funcs(adev); 794 gmc_v8_0_set_irq_funcs(adev);
793 795
@@ -806,10 +808,11 @@ static int gmc_v8_0_early_init(struct amdgpu_device *adev)
806 return 0; 808 return 0;
807} 809}
808 810
809static int gmc_v8_0_sw_init(struct amdgpu_device *adev) 811static int gmc_v8_0_sw_init(void *handle)
810{ 812{
811 int r; 813 int r;
812 int dma_bits; 814 int dma_bits;
815 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
813 816
814 r = amdgpu_gem_init(adev); 817 r = amdgpu_gem_init(adev);
815 if (r) 818 if (r)
@@ -885,9 +888,10 @@ static int gmc_v8_0_sw_init(struct amdgpu_device *adev)
885 return r; 888 return r;
886} 889}
887 890
888static int gmc_v8_0_sw_fini(struct amdgpu_device *adev) 891static int gmc_v8_0_sw_fini(void *handle)
889{ 892{
890 int i; 893 int i;
894 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
891 895
892 if (adev->vm_manager.enabled) { 896 if (adev->vm_manager.enabled) {
893 for (i = 0; i < AMDGPU_NUM_VM; ++i) 897 for (i = 0; i < AMDGPU_NUM_VM; ++i)
@@ -902,9 +906,10 @@ static int gmc_v8_0_sw_fini(struct amdgpu_device *adev)
902 return 0; 906 return 0;
903} 907}
904 908
905static int gmc_v8_0_hw_init(struct amdgpu_device *adev) 909static int gmc_v8_0_hw_init(void *handle)
906{ 910{
907 int r; 911 int r;
912 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
908 913
909 gmc_v8_0_init_golden_registers(adev); 914 gmc_v8_0_init_golden_registers(adev);
910 915
@@ -925,16 +930,19 @@ static int gmc_v8_0_hw_init(struct amdgpu_device *adev)
925 return r; 930 return r;
926} 931}
927 932
928static int gmc_v8_0_hw_fini(struct amdgpu_device *adev) 933static int gmc_v8_0_hw_fini(void *handle)
929{ 934{
935 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
936
930 gmc_v8_0_gart_disable(adev); 937 gmc_v8_0_gart_disable(adev);
931 938
932 return 0; 939 return 0;
933} 940}
934 941
935static int gmc_v8_0_suspend(struct amdgpu_device *adev) 942static int gmc_v8_0_suspend(void *handle)
936{ 943{
937 int i; 944 int i;
945 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
938 946
939 if (adev->vm_manager.enabled) { 947 if (adev->vm_manager.enabled) {
940 for (i = 0; i < AMDGPU_NUM_VM; ++i) 948 for (i = 0; i < AMDGPU_NUM_VM; ++i)
@@ -947,9 +955,10 @@ static int gmc_v8_0_suspend(struct amdgpu_device *adev)
947 return 0; 955 return 0;
948} 956}
949 957
950static int gmc_v8_0_resume(struct amdgpu_device *adev) 958static int gmc_v8_0_resume(void *handle)
951{ 959{
952 int r; 960 int r;
961 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
953 962
954 r = gmc_v8_0_hw_init(adev); 963 r = gmc_v8_0_hw_init(adev);
955 if (r) 964 if (r)
@@ -967,8 +976,9 @@ static int gmc_v8_0_resume(struct amdgpu_device *adev)
967 return r; 976 return r;
968} 977}
969 978
970static bool gmc_v8_0_is_idle(struct amdgpu_device *adev) 979static bool gmc_v8_0_is_idle(void *handle)
971{ 980{
981 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
972 u32 tmp = RREG32(mmSRBM_STATUS); 982 u32 tmp = RREG32(mmSRBM_STATUS);
973 983
974 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 984 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
@@ -978,10 +988,11 @@ static bool gmc_v8_0_is_idle(struct amdgpu_device *adev)
978 return true; 988 return true;
979} 989}
980 990
981static int gmc_v8_0_wait_for_idle(struct amdgpu_device *adev) 991static int gmc_v8_0_wait_for_idle(void *handle)
982{ 992{
983 unsigned i; 993 unsigned i;
984 u32 tmp; 994 u32 tmp;
995 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
985 996
986 for (i = 0; i < adev->usec_timeout; i++) { 997 for (i = 0; i < adev->usec_timeout; i++) {
987 /* read MC_STATUS */ 998 /* read MC_STATUS */
@@ -999,9 +1010,10 @@ static int gmc_v8_0_wait_for_idle(struct amdgpu_device *adev)
999 1010
1000} 1011}
1001 1012
1002static void gmc_v8_0_print_status(struct amdgpu_device *adev) 1013static void gmc_v8_0_print_status(void *handle)
1003{ 1014{
1004 int i, j; 1015 int i, j;
1016 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1005 1017
1006 dev_info(adev->dev, "GMC 8.x registers\n"); 1018 dev_info(adev->dev, "GMC 8.x registers\n");
1007 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", 1019 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
@@ -1103,10 +1115,11 @@ static void gmc_v8_0_print_status(struct amdgpu_device *adev)
1103 RREG32(mmBIF_FB_EN)); 1115 RREG32(mmBIF_FB_EN));
1104} 1116}
1105 1117
1106static int gmc_v8_0_soft_reset(struct amdgpu_device *adev) 1118static int gmc_v8_0_soft_reset(void *handle)
1107{ 1119{
1108 struct amdgpu_mode_mc_save save; 1120 struct amdgpu_mode_mc_save save;
1109 u32 srbm_soft_reset = 0; 1121 u32 srbm_soft_reset = 0;
1122 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1110 u32 tmp = RREG32(mmSRBM_STATUS); 1123 u32 tmp = RREG32(mmSRBM_STATUS);
1111 1124
1112 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1125 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
@@ -1121,7 +1134,7 @@ static int gmc_v8_0_soft_reset(struct amdgpu_device *adev)
1121 } 1134 }
1122 1135
1123 if (srbm_soft_reset) { 1136 if (srbm_soft_reset) {
1124 gmc_v8_0_print_status(adev); 1137 gmc_v8_0_print_status((void *)adev);
1125 1138
1126 gmc_v8_0_mc_stop(adev, &save); 1139 gmc_v8_0_mc_stop(adev, &save);
1127 if (gmc_v8_0_wait_for_idle(adev)) { 1140 if (gmc_v8_0_wait_for_idle(adev)) {
@@ -1147,7 +1160,7 @@ static int gmc_v8_0_soft_reset(struct amdgpu_device *adev)
1147 gmc_v8_0_mc_resume(adev, &save); 1160 gmc_v8_0_mc_resume(adev, &save);
1148 udelay(50); 1161 udelay(50);
1149 1162
1150 gmc_v8_0_print_status(adev); 1163 gmc_v8_0_print_status((void *)adev);
1151 } 1164 }
1152 1165
1153 return 0; 1166 return 0;
@@ -1217,21 +1230,19 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1217 return 0; 1230 return 0;
1218} 1231}
1219 1232
1220static int gmc_v8_0_set_clockgating_state(struct amdgpu_device *adev, 1233static int gmc_v8_0_set_clockgating_state(void *handle,
1221 enum amdgpu_clockgating_state state) 1234 enum amd_clockgating_state state)
1222{ 1235{
1223 /* XXX handled via the smc on VI */
1224
1225 return 0; 1236 return 0;
1226} 1237}
1227 1238
1228static int gmc_v8_0_set_powergating_state(struct amdgpu_device *adev, 1239static int gmc_v8_0_set_powergating_state(void *handle,
1229 enum amdgpu_powergating_state state) 1240 enum amd_powergating_state state)
1230{ 1241{
1231 return 0; 1242 return 0;
1232} 1243}
1233 1244
1234const struct amdgpu_ip_funcs gmc_v8_0_ip_funcs = { 1245const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1235 .early_init = gmc_v8_0_early_init, 1246 .early_init = gmc_v8_0_early_init,
1236 .late_init = NULL, 1247 .late_init = NULL,
1237 .sw_init = gmc_v8_0_sw_init, 1248 .sw_init = gmc_v8_0_sw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h
index 2dd7f809d4e1..973436086b38 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h
@@ -24,7 +24,7 @@
24#ifndef __GMC_V8_0_H__ 24#ifndef __GMC_V8_0_H__
25#define __GMC_V8_0_H__ 25#define __GMC_V8_0_H__
26 26
27extern const struct amdgpu_ip_funcs gmc_v8_0_ip_funcs; 27extern const struct amd_ip_funcs gmc_v8_0_ip_funcs;
28 28
29/* XXX these shouldn't be exported */ 29/* XXX these shouldn't be exported */
30void gmc_v8_0_mc_stop(struct amdgpu_device *adev, 30void gmc_v8_0_mc_stop(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
index 0688b88cb170..4b773f29167a 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
@@ -30,8 +30,10 @@ MODULE_FIRMWARE("amdgpu/topaz_smc.bin");
30 30
31static void iceland_dpm_set_funcs(struct amdgpu_device *adev); 31static void iceland_dpm_set_funcs(struct amdgpu_device *adev);
32 32
33static int iceland_dpm_early_init(struct amdgpu_device *adev) 33static int iceland_dpm_early_init(void *handle)
34{ 34{
35 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
36
35 iceland_dpm_set_funcs(adev); 37 iceland_dpm_set_funcs(adev);
36 38
37 return 0; 39 return 0;
@@ -56,9 +58,10 @@ out:
56 return err; 58 return err;
57} 59}
58 60
59static int iceland_dpm_sw_init(struct amdgpu_device *adev) 61static int iceland_dpm_sw_init(void *handle)
60{ 62{
61 int ret; 63 int ret;
64 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
62 65
63 ret = iceland_dpm_init_microcode(adev); 66 ret = iceland_dpm_init_microcode(adev);
64 if (ret) 67 if (ret)
@@ -67,14 +70,15 @@ static int iceland_dpm_sw_init(struct amdgpu_device *adev)
67 return 0; 70 return 0;
68} 71}
69 72
70static int iceland_dpm_sw_fini(struct amdgpu_device *adev) 73static int iceland_dpm_sw_fini(void *handle)
71{ 74{
72 return 0; 75 return 0;
73} 76}
74 77
75static int iceland_dpm_hw_init(struct amdgpu_device *adev) 78static int iceland_dpm_hw_init(void *handle)
76{ 79{
77 int ret; 80 int ret;
81 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
78 82
79 mutex_lock(&adev->pm.mutex); 83 mutex_lock(&adev->pm.mutex);
80 84
@@ -99,41 +103,47 @@ fail:
99 return -EINVAL; 103 return -EINVAL;
100} 104}
101 105
102static int iceland_dpm_hw_fini(struct amdgpu_device *adev) 106static int iceland_dpm_hw_fini(void *handle)
103{ 107{
108 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
109
104 mutex_lock(&adev->pm.mutex); 110 mutex_lock(&adev->pm.mutex);
105 iceland_smu_fini(adev); 111 iceland_smu_fini(adev);
106 mutex_unlock(&adev->pm.mutex); 112 mutex_unlock(&adev->pm.mutex);
107 return 0; 113 return 0;
108} 114}
109 115
110static int iceland_dpm_suspend(struct amdgpu_device *adev) 116static int iceland_dpm_suspend(void *handle)
111{ 117{
118 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
119
112 iceland_dpm_hw_fini(adev); 120 iceland_dpm_hw_fini(adev);
113 121
114 return 0; 122 return 0;
115} 123}
116 124
117static int iceland_dpm_resume(struct amdgpu_device *adev) 125static int iceland_dpm_resume(void *handle)
118{ 126{
127 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
128
119 iceland_dpm_hw_init(adev); 129 iceland_dpm_hw_init(adev);
120 130
121 return 0; 131 return 0;
122} 132}
123 133
124static int iceland_dpm_set_clockgating_state(struct amdgpu_device *adev, 134static int iceland_dpm_set_clockgating_state(void *handle,
125 enum amdgpu_clockgating_state state) 135 enum amd_clockgating_state state)
126{ 136{
127 return 0; 137 return 0;
128} 138}
129 139
130static int iceland_dpm_set_powergating_state(struct amdgpu_device *adev, 140static int iceland_dpm_set_powergating_state(void *handle,
131 enum amdgpu_powergating_state state) 141 enum amd_powergating_state state)
132{ 142{
133 return 0; 143 return 0;
134} 144}
135 145
136const struct amdgpu_ip_funcs iceland_dpm_ip_funcs = { 146const struct amd_ip_funcs iceland_dpm_ip_funcs = {
137 .early_init = iceland_dpm_early_init, 147 .early_init = iceland_dpm_early_init,
138 .late_init = NULL, 148 .late_init = NULL,
139 .sw_init = iceland_dpm_sw_init, 149 .sw_init = iceland_dpm_sw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
index 2de8adfac471..779532d350ff 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
@@ -250,15 +250,18 @@ static void iceland_ih_set_rptr(struct amdgpu_device *adev)
250 WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr); 250 WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
251} 251}
252 252
253static int iceland_ih_early_init(struct amdgpu_device *adev) 253static int iceland_ih_early_init(void *handle)
254{ 254{
255 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
256
255 iceland_ih_set_interrupt_funcs(adev); 257 iceland_ih_set_interrupt_funcs(adev);
256 return 0; 258 return 0;
257} 259}
258 260
259static int iceland_ih_sw_init(struct amdgpu_device *adev) 261static int iceland_ih_sw_init(void *handle)
260{ 262{
261 int r; 263 int r;
264 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
262 265
263 r = amdgpu_ih_ring_init(adev, 64 * 1024, false); 266 r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
264 if (r) 267 if (r)
@@ -269,17 +272,20 @@ static int iceland_ih_sw_init(struct amdgpu_device *adev)
269 return r; 272 return r;
270} 273}
271 274
272static int iceland_ih_sw_fini(struct amdgpu_device *adev) 275static int iceland_ih_sw_fini(void *handle)
273{ 276{
277 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
278
274 amdgpu_irq_fini(adev); 279 amdgpu_irq_fini(adev);
275 amdgpu_ih_ring_fini(adev); 280 amdgpu_ih_ring_fini(adev);
276 281
277 return 0; 282 return 0;
278} 283}
279 284
280static int iceland_ih_hw_init(struct amdgpu_device *adev) 285static int iceland_ih_hw_init(void *handle)
281{ 286{
282 int r; 287 int r;
288 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
283 289
284 r = iceland_ih_irq_init(adev); 290 r = iceland_ih_irq_init(adev);
285 if (r) 291 if (r)
@@ -288,25 +294,32 @@ static int iceland_ih_hw_init(struct amdgpu_device *adev)
288 return 0; 294 return 0;
289} 295}
290 296
291static int iceland_ih_hw_fini(struct amdgpu_device *adev) 297static int iceland_ih_hw_fini(void *handle)
292{ 298{
299 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
300
293 iceland_ih_irq_disable(adev); 301 iceland_ih_irq_disable(adev);
294 302
295 return 0; 303 return 0;
296} 304}
297 305
298static int iceland_ih_suspend(struct amdgpu_device *adev) 306static int iceland_ih_suspend(void *handle)
299{ 307{
308 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
309
300 return iceland_ih_hw_fini(adev); 310 return iceland_ih_hw_fini(adev);
301} 311}
302 312
303static int iceland_ih_resume(struct amdgpu_device *adev) 313static int iceland_ih_resume(void *handle)
304{ 314{
315 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
316
305 return iceland_ih_hw_init(adev); 317 return iceland_ih_hw_init(adev);
306} 318}
307 319
308static bool iceland_ih_is_idle(struct amdgpu_device *adev) 320static bool iceland_ih_is_idle(void *handle)
309{ 321{
322 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
310 u32 tmp = RREG32(mmSRBM_STATUS); 323 u32 tmp = RREG32(mmSRBM_STATUS);
311 324
312 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) 325 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
@@ -315,10 +328,11 @@ static bool iceland_ih_is_idle(struct amdgpu_device *adev)
315 return true; 328 return true;
316} 329}
317 330
318static int iceland_ih_wait_for_idle(struct amdgpu_device *adev) 331static int iceland_ih_wait_for_idle(void *handle)
319{ 332{
320 unsigned i; 333 unsigned i;
321 u32 tmp; 334 u32 tmp;
335 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
322 336
323 for (i = 0; i < adev->usec_timeout; i++) { 337 for (i = 0; i < adev->usec_timeout; i++) {
324 /* read MC_STATUS */ 338 /* read MC_STATUS */
@@ -330,8 +344,10 @@ static int iceland_ih_wait_for_idle(struct amdgpu_device *adev)
330 return -ETIMEDOUT; 344 return -ETIMEDOUT;
331} 345}
332 346
333static void iceland_ih_print_status(struct amdgpu_device *adev) 347static void iceland_ih_print_status(void *handle)
334{ 348{
349 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
350
335 dev_info(adev->dev, "ICELAND IH registers\n"); 351 dev_info(adev->dev, "ICELAND IH registers\n");
336 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", 352 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
337 RREG32(mmSRBM_STATUS)); 353 RREG32(mmSRBM_STATUS));
@@ -357,9 +373,10 @@ static void iceland_ih_print_status(struct amdgpu_device *adev)
357 RREG32(mmIH_RB_WPTR)); 373 RREG32(mmIH_RB_WPTR));
358} 374}
359 375
360static int iceland_ih_soft_reset(struct amdgpu_device *adev) 376static int iceland_ih_soft_reset(void *handle)
361{ 377{
362 u32 srbm_soft_reset = 0; 378 u32 srbm_soft_reset = 0;
379 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
363 u32 tmp = RREG32(mmSRBM_STATUS); 380 u32 tmp = RREG32(mmSRBM_STATUS);
364 381
365 if (tmp & SRBM_STATUS__IH_BUSY_MASK) 382 if (tmp & SRBM_STATUS__IH_BUSY_MASK)
@@ -367,7 +384,7 @@ static int iceland_ih_soft_reset(struct amdgpu_device *adev)
367 SOFT_RESET_IH, 1); 384 SOFT_RESET_IH, 1);
368 385
369 if (srbm_soft_reset) { 386 if (srbm_soft_reset) {
370 iceland_ih_print_status(adev); 387 iceland_ih_print_status((void *)adev);
371 388
372 tmp = RREG32(mmSRBM_SOFT_RESET); 389 tmp = RREG32(mmSRBM_SOFT_RESET);
373 tmp |= srbm_soft_reset; 390 tmp |= srbm_soft_reset;
@@ -384,27 +401,25 @@ static int iceland_ih_soft_reset(struct amdgpu_device *adev)
384 /* Wait a little for things to settle down */ 401 /* Wait a little for things to settle down */
385 udelay(50); 402 udelay(50);
386 403
387 iceland_ih_print_status(adev); 404 iceland_ih_print_status((void *)adev);
388 } 405 }
389 406
390 return 0; 407 return 0;
391} 408}
392 409
393static int iceland_ih_set_clockgating_state(struct amdgpu_device *adev, 410static int iceland_ih_set_clockgating_state(void *handle,
394 enum amdgpu_clockgating_state state) 411 enum amd_clockgating_state state)
395{ 412{
396 // TODO
397 return 0; 413 return 0;
398} 414}
399 415
400static int iceland_ih_set_powergating_state(struct amdgpu_device *adev, 416static int iceland_ih_set_powergating_state(void *handle,
401 enum amdgpu_powergating_state state) 417 enum amd_powergating_state state)
402{ 418{
403 // TODO
404 return 0; 419 return 0;
405} 420}
406 421
407const struct amdgpu_ip_funcs iceland_ih_ip_funcs = { 422const struct amd_ip_funcs iceland_ih_ip_funcs = {
408 .early_init = iceland_ih_early_init, 423 .early_init = iceland_ih_early_init,
409 .late_init = NULL, 424 .late_init = NULL,
410 .sw_init = iceland_ih_sw_init, 425 .sw_init = iceland_ih_sw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.h b/drivers/gpu/drm/amd/amdgpu/iceland_ih.h
index d001895eb93b..57558cddfbcb 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.h
@@ -24,6 +24,6 @@
24#ifndef __ICELAND_IH_H__ 24#ifndef __ICELAND_IH_H__
25#define __ICELAND_IH_H__ 25#define __ICELAND_IH_H__
26 26
27extern const struct amdgpu_ip_funcs iceland_ih_ip_funcs; 27extern const struct amd_ip_funcs iceland_ih_ip_funcs;
28 28
29#endif /* __ICELAND_IH_H__ */ 29#endif /* __ICELAND_IH_H__ */
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index cd902419e6a1..94ec04a9c4d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -1552,8 +1552,8 @@ static int kv_update_vce_dpm(struct amdgpu_device *adev,
1552 if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) { 1552 if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) {
1553 kv_dpm_powergate_vce(adev, false); 1553 kv_dpm_powergate_vce(adev, false);
1554 /* turn the clocks on when encoding */ 1554 /* turn the clocks on when encoding */
1555 ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE, 1555 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1556 AMDGPU_CG_STATE_UNGATE); 1556 AMD_CG_STATE_UNGATE);
1557 if (ret) 1557 if (ret)
1558 return ret; 1558 return ret;
1559 if (pi->caps_stable_p_state) 1559 if (pi->caps_stable_p_state)
@@ -1579,8 +1579,8 @@ static int kv_update_vce_dpm(struct amdgpu_device *adev,
1579 } else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk > 0) { 1579 } else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk > 0) {
1580 kv_enable_vce_dpm(adev, false); 1580 kv_enable_vce_dpm(adev, false);
1581 /* turn the clocks off when not encoding */ 1581 /* turn the clocks off when not encoding */
1582 ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE, 1582 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1583 AMDGPU_CG_STATE_GATE); 1583 AMD_CG_STATE_GATE);
1584 if (ret) 1584 if (ret)
1585 return ret; 1585 return ret;
1586 kv_dpm_powergate_vce(adev, true); 1586 kv_dpm_powergate_vce(adev, true);
@@ -1697,11 +1697,11 @@ static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
1697 if (gate) { 1697 if (gate) {
1698 if (pi->caps_uvd_pg) { 1698 if (pi->caps_uvd_pg) {
1699 /* disable clockgating so we can properly shut down the block */ 1699 /* disable clockgating so we can properly shut down the block */
1700 ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD, 1700 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1701 AMDGPU_CG_STATE_UNGATE); 1701 AMD_CG_STATE_UNGATE);
1702 /* shutdown the UVD block */ 1702 /* shutdown the UVD block */
1703 ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD, 1703 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1704 AMDGPU_PG_STATE_GATE); 1704 AMD_PG_STATE_GATE);
1705 /* XXX: check for errors */ 1705 /* XXX: check for errors */
1706 } 1706 }
1707 kv_update_uvd_dpm(adev, gate); 1707 kv_update_uvd_dpm(adev, gate);
@@ -1713,11 +1713,11 @@ static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
1713 /* power on the UVD block */ 1713 /* power on the UVD block */
1714 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON); 1714 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON);
1715 /* re-init the UVD block */ 1715 /* re-init the UVD block */
1716 ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD, 1716 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1717 AMDGPU_PG_STATE_UNGATE); 1717 AMD_PG_STATE_UNGATE);
1718 /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */ 1718 /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
1719 ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD, 1719 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1720 AMDGPU_CG_STATE_GATE); 1720 AMD_CG_STATE_GATE);
1721 /* XXX: check for errors */ 1721 /* XXX: check for errors */
1722 } 1722 }
1723 kv_update_uvd_dpm(adev, gate); 1723 kv_update_uvd_dpm(adev, gate);
@@ -1737,8 +1737,8 @@ static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
1737 if (gate) { 1737 if (gate) {
1738 if (pi->caps_vce_pg) { 1738 if (pi->caps_vce_pg) {
1739 /* shutdown the VCE block */ 1739 /* shutdown the VCE block */
1740 ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE, 1740 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1741 AMDGPU_PG_STATE_GATE); 1741 AMD_PG_STATE_GATE);
1742 /* XXX: check for errors */ 1742 /* XXX: check for errors */
1743 /* power off the VCE block */ 1743 /* power off the VCE block */
1744 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF); 1744 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF);
@@ -1748,8 +1748,8 @@ static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
1748 /* power on the VCE block */ 1748 /* power on the VCE block */
1749 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON); 1749 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON);
1750 /* re-init the VCE block */ 1750 /* re-init the VCE block */
1751 ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE, 1751 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1752 AMDGPU_PG_STATE_UNGATE); 1752 AMD_PG_STATE_UNGATE);
1753 /* XXX: check for errors */ 1753 /* XXX: check for errors */
1754 } 1754 }
1755 } 1755 }
@@ -2981,20 +2981,21 @@ static int kv_dpm_get_temp(struct amdgpu_device *adev)
2981 return actual_temp; 2981 return actual_temp;
2982} 2982}
2983 2983
2984static int kv_dpm_early_init(struct amdgpu_device *adev) 2984static int kv_dpm_early_init(void *handle)
2985{ 2985{
2986 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2987
2986 kv_dpm_set_dpm_funcs(adev); 2988 kv_dpm_set_dpm_funcs(adev);
2987 kv_dpm_set_irq_funcs(adev); 2989 kv_dpm_set_irq_funcs(adev);
2988 2990
2989 return 0; 2991 return 0;
2990} 2992}
2991 2993
2992static int kv_dpm_late_init(struct amdgpu_device *adev) 2994static int kv_dpm_late_init(void *handle)
2993{ 2995{
2994 if (!amdgpu_dpm)
2995 return 0;
2996
2997 /* powerdown unused blocks for now */ 2996 /* powerdown unused blocks for now */
2997 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2998
2998 kv_dpm_powergate_acp(adev, true); 2999 kv_dpm_powergate_acp(adev, true);
2999 kv_dpm_powergate_samu(adev, true); 3000 kv_dpm_powergate_samu(adev, true);
3000 kv_dpm_powergate_vce(adev, true); 3001 kv_dpm_powergate_vce(adev, true);
@@ -3003,9 +3004,10 @@ static int kv_dpm_late_init(struct amdgpu_device *adev)
3003 return 0; 3004 return 0;
3004} 3005}
3005 3006
3006static int kv_dpm_sw_init(struct amdgpu_device *adev) 3007static int kv_dpm_sw_init(void *handle)
3007{ 3008{
3008 int ret; 3009 int ret;
3010 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3009 3011
3010 ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq); 3012 ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
3011 if (ret) 3013 if (ret)
@@ -3051,8 +3053,10 @@ dpm_failed:
3051 return ret; 3053 return ret;
3052} 3054}
3053 3055
3054static int kv_dpm_sw_fini(struct amdgpu_device *adev) 3056static int kv_dpm_sw_fini(void *handle)
3055{ 3057{
3058 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3059
3056 mutex_lock(&adev->pm.mutex); 3060 mutex_lock(&adev->pm.mutex);
3057 amdgpu_pm_sysfs_fini(adev); 3061 amdgpu_pm_sysfs_fini(adev);
3058 kv_dpm_fini(adev); 3062 kv_dpm_fini(adev);
@@ -3061,12 +3065,10 @@ static int kv_dpm_sw_fini(struct amdgpu_device *adev)
3061 return 0; 3065 return 0;
3062} 3066}
3063 3067
3064static int kv_dpm_hw_init(struct amdgpu_device *adev) 3068static int kv_dpm_hw_init(void *handle)
3065{ 3069{
3066 int ret; 3070 int ret;
3067 3071 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3068 if (!amdgpu_dpm)
3069 return 0;
3070 3072
3071 mutex_lock(&adev->pm.mutex); 3073 mutex_lock(&adev->pm.mutex);
3072 kv_dpm_setup_asic(adev); 3074 kv_dpm_setup_asic(adev);
@@ -3080,8 +3082,10 @@ static int kv_dpm_hw_init(struct amdgpu_device *adev)
3080 return ret; 3082 return ret;
3081} 3083}
3082 3084
3083static int kv_dpm_hw_fini(struct amdgpu_device *adev) 3085static int kv_dpm_hw_fini(void *handle)
3084{ 3086{
3087 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3088
3085 if (adev->pm.dpm_enabled) { 3089 if (adev->pm.dpm_enabled) {
3086 mutex_lock(&adev->pm.mutex); 3090 mutex_lock(&adev->pm.mutex);
3087 kv_dpm_disable(adev); 3091 kv_dpm_disable(adev);
@@ -3091,8 +3095,10 @@ static int kv_dpm_hw_fini(struct amdgpu_device *adev)
3091 return 0; 3095 return 0;
3092} 3096}
3093 3097
3094static int kv_dpm_suspend(struct amdgpu_device *adev) 3098static int kv_dpm_suspend(void *handle)
3095{ 3099{
3100 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3101
3096 if (adev->pm.dpm_enabled) { 3102 if (adev->pm.dpm_enabled) {
3097 mutex_lock(&adev->pm.mutex); 3103 mutex_lock(&adev->pm.mutex);
3098 /* disable dpm */ 3104 /* disable dpm */
@@ -3104,9 +3110,10 @@ static int kv_dpm_suspend(struct amdgpu_device *adev)
3104 return 0; 3110 return 0;
3105} 3111}
3106 3112
3107static int kv_dpm_resume(struct amdgpu_device *adev) 3113static int kv_dpm_resume(void *handle)
3108{ 3114{
3109 int ret; 3115 int ret;
3116 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3110 3117
3111 if (adev->pm.dpm_enabled) { 3118 if (adev->pm.dpm_enabled) {
3112 /* asic init will reset to the boot state */ 3119 /* asic init will reset to the boot state */
@@ -3124,20 +3131,20 @@ static int kv_dpm_resume(struct amdgpu_device *adev)
3124 return 0; 3131 return 0;
3125} 3132}
3126 3133
3127static bool kv_dpm_is_idle(struct amdgpu_device *adev) 3134static bool kv_dpm_is_idle(void *handle)
3128{ 3135{
3129 /* XXX */
3130 return true; 3136 return true;
3131} 3137}
3132 3138
3133static int kv_dpm_wait_for_idle(struct amdgpu_device *adev) 3139static int kv_dpm_wait_for_idle(void *handle)
3134{ 3140{
3135 /* XXX */
3136 return 0; 3141 return 0;
3137} 3142}
3138 3143
3139static void kv_dpm_print_status(struct amdgpu_device *adev) 3144static void kv_dpm_print_status(void *handle)
3140{ 3145{
3146 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3147
3141 dev_info(adev->dev, "KV/KB DPM registers\n"); 3148 dev_info(adev->dev, "KV/KB DPM registers\n");
3142 dev_info(adev->dev, " DIDT_SQ_CTRL0=0x%08X\n", 3149 dev_info(adev->dev, " DIDT_SQ_CTRL0=0x%08X\n",
3143 RREG32_DIDT(ixDIDT_SQ_CTRL0)); 3150 RREG32_DIDT(ixDIDT_SQ_CTRL0));
@@ -3191,7 +3198,7 @@ static void kv_dpm_print_status(struct amdgpu_device *adev)
3191 RREG32(mmSMC_IND_ACCESS_CNTL)); 3198 RREG32(mmSMC_IND_ACCESS_CNTL));
3192} 3199}
3193 3200
3194static int kv_dpm_soft_reset(struct amdgpu_device *adev) 3201static int kv_dpm_soft_reset(void *handle)
3195{ 3202{
3196 return 0; 3203 return 0;
3197} 3204}
@@ -3274,19 +3281,19 @@ static int kv_dpm_process_interrupt(struct amdgpu_device *adev,
3274 return 0; 3281 return 0;
3275} 3282}
3276 3283
3277static int kv_dpm_set_clockgating_state(struct amdgpu_device *adev, 3284static int kv_dpm_set_clockgating_state(void *handle,
3278 enum amdgpu_clockgating_state state) 3285 enum amd_clockgating_state state)
3279{ 3286{
3280 return 0; 3287 return 0;
3281} 3288}
3282 3289
3283static int kv_dpm_set_powergating_state(struct amdgpu_device *adev, 3290static int kv_dpm_set_powergating_state(void *handle,
3284 enum amdgpu_powergating_state state) 3291 enum amd_powergating_state state)
3285{ 3292{
3286 return 0; 3293 return 0;
3287} 3294}
3288 3295
3289const struct amdgpu_ip_funcs kv_dpm_ip_funcs = { 3296const struct amd_ip_funcs kv_dpm_ip_funcs = {
3290 .early_init = kv_dpm_early_init, 3297 .early_init = kv_dpm_early_init,
3291 .late_init = kv_dpm_late_init, 3298 .late_init = kv_dpm_late_init,
3292 .sw_init = kv_dpm_sw_init, 3299 .sw_init = kv_dpm_sw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 99b8b326e999..64de8f60e3a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -955,8 +955,10 @@ static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
955 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 955 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
956} 956}
957 957
958static int sdma_v2_4_early_init(struct amdgpu_device *adev) 958static int sdma_v2_4_early_init(void *handle)
959{ 959{
960 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
961
960 sdma_v2_4_set_ring_funcs(adev); 962 sdma_v2_4_set_ring_funcs(adev);
961 sdma_v2_4_set_buffer_funcs(adev); 963 sdma_v2_4_set_buffer_funcs(adev);
962 sdma_v2_4_set_vm_pte_funcs(adev); 964 sdma_v2_4_set_vm_pte_funcs(adev);
@@ -965,10 +967,11 @@ static int sdma_v2_4_early_init(struct amdgpu_device *adev)
965 return 0; 967 return 0;
966} 968}
967 969
968static int sdma_v2_4_sw_init(struct amdgpu_device *adev) 970static int sdma_v2_4_sw_init(void *handle)
969{ 971{
970 struct amdgpu_ring *ring; 972 struct amdgpu_ring *ring;
971 int r; 973 int r;
974 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
972 975
973 /* SDMA trap event */ 976 /* SDMA trap event */
974 r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq); 977 r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq);
@@ -1020,17 +1023,20 @@ static int sdma_v2_4_sw_init(struct amdgpu_device *adev)
1020 return r; 1023 return r;
1021} 1024}
1022 1025
1023static int sdma_v2_4_sw_fini(struct amdgpu_device *adev) 1026static int sdma_v2_4_sw_fini(void *handle)
1024{ 1027{
1028 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1029
1025 amdgpu_ring_fini(&adev->sdma[0].ring); 1030 amdgpu_ring_fini(&adev->sdma[0].ring);
1026 amdgpu_ring_fini(&adev->sdma[1].ring); 1031 amdgpu_ring_fini(&adev->sdma[1].ring);
1027 1032
1028 return 0; 1033 return 0;
1029} 1034}
1030 1035
1031static int sdma_v2_4_hw_init(struct amdgpu_device *adev) 1036static int sdma_v2_4_hw_init(void *handle)
1032{ 1037{
1033 int r; 1038 int r;
1039 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1034 1040
1035 sdma_v2_4_init_golden_registers(adev); 1041 sdma_v2_4_init_golden_registers(adev);
1036 1042
@@ -1041,27 +1047,32 @@ static int sdma_v2_4_hw_init(struct amdgpu_device *adev)
1041 return r; 1047 return r;
1042} 1048}
1043 1049
1044static int sdma_v2_4_hw_fini(struct amdgpu_device *adev) 1050static int sdma_v2_4_hw_fini(void *handle)
1045{ 1051{
1052 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1053
1046 sdma_v2_4_enable(adev, false); 1054 sdma_v2_4_enable(adev, false);
1047 1055
1048 return 0; 1056 return 0;
1049} 1057}
1050 1058
1051static int sdma_v2_4_suspend(struct amdgpu_device *adev) 1059static int sdma_v2_4_suspend(void *handle)
1052{ 1060{
1061 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1053 1062
1054 return sdma_v2_4_hw_fini(adev); 1063 return sdma_v2_4_hw_fini(adev);
1055} 1064}
1056 1065
1057static int sdma_v2_4_resume(struct amdgpu_device *adev) 1066static int sdma_v2_4_resume(void *handle)
1058{ 1067{
1068 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1059 1069
1060 return sdma_v2_4_hw_init(adev); 1070 return sdma_v2_4_hw_init(adev);
1061} 1071}
1062 1072
1063static bool sdma_v2_4_is_idle(struct amdgpu_device *adev) 1073static bool sdma_v2_4_is_idle(void *handle)
1064{ 1074{
1075 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1065 u32 tmp = RREG32(mmSRBM_STATUS2); 1076 u32 tmp = RREG32(mmSRBM_STATUS2);
1066 1077
1067 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1078 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
@@ -1071,10 +1082,11 @@ static bool sdma_v2_4_is_idle(struct amdgpu_device *adev)
1071 return true; 1082 return true;
1072} 1083}
1073 1084
1074static int sdma_v2_4_wait_for_idle(struct amdgpu_device *adev) 1085static int sdma_v2_4_wait_for_idle(void *handle)
1075{ 1086{
1076 unsigned i; 1087 unsigned i;
1077 u32 tmp; 1088 u32 tmp;
1089 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1078 1090
1079 for (i = 0; i < adev->usec_timeout; i++) { 1091 for (i = 0; i < adev->usec_timeout; i++) {
1080 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1092 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
@@ -1087,9 +1099,10 @@ static int sdma_v2_4_wait_for_idle(struct amdgpu_device *adev)
1087 return -ETIMEDOUT; 1099 return -ETIMEDOUT;
1088} 1100}
1089 1101
1090static void sdma_v2_4_print_status(struct amdgpu_device *adev) 1102static void sdma_v2_4_print_status(void *handle)
1091{ 1103{
1092 int i, j; 1104 int i, j;
1105 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1093 1106
1094 dev_info(adev->dev, "VI SDMA registers\n"); 1107 dev_info(adev->dev, "VI SDMA registers\n");
1095 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", 1108 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
@@ -1133,9 +1146,10 @@ static void sdma_v2_4_print_status(struct amdgpu_device *adev)
1133 } 1146 }
1134} 1147}
1135 1148
1136static int sdma_v2_4_soft_reset(struct amdgpu_device *adev) 1149static int sdma_v2_4_soft_reset(void *handle)
1137{ 1150{
1138 u32 srbm_soft_reset = 0; 1151 u32 srbm_soft_reset = 0;
1152 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1139 u32 tmp = RREG32(mmSRBM_STATUS2); 1153 u32 tmp = RREG32(mmSRBM_STATUS2);
1140 1154
1141 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { 1155 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
@@ -1154,7 +1168,7 @@ static int sdma_v2_4_soft_reset(struct amdgpu_device *adev)
1154 } 1168 }
1155 1169
1156 if (srbm_soft_reset) { 1170 if (srbm_soft_reset) {
1157 sdma_v2_4_print_status(adev); 1171 sdma_v2_4_print_status((void *)adev);
1158 1172
1159 tmp = RREG32(mmSRBM_SOFT_RESET); 1173 tmp = RREG32(mmSRBM_SOFT_RESET);
1160 tmp |= srbm_soft_reset; 1174 tmp |= srbm_soft_reset;
@@ -1171,7 +1185,7 @@ static int sdma_v2_4_soft_reset(struct amdgpu_device *adev)
1171 /* Wait a little for things to settle down */ 1185 /* Wait a little for things to settle down */
1172 udelay(50); 1186 udelay(50);
1173 1187
1174 sdma_v2_4_print_status(adev); 1188 sdma_v2_4_print_status((void *)adev);
1175 } 1189 }
1176 1190
1177 return 0; 1191 return 0;
@@ -1272,21 +1286,20 @@ static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
1272 return 0; 1286 return 0;
1273} 1287}
1274 1288
1275static int sdma_v2_4_set_clockgating_state(struct amdgpu_device *adev, 1289static int sdma_v2_4_set_clockgating_state(void *handle,
1276 enum amdgpu_clockgating_state state) 1290 enum amd_clockgating_state state)
1277{ 1291{
1278 /* XXX handled via the smc on VI */ 1292 /* XXX handled via the smc on VI */
1279
1280 return 0; 1293 return 0;
1281} 1294}
1282 1295
1283static int sdma_v2_4_set_powergating_state(struct amdgpu_device *adev, 1296static int sdma_v2_4_set_powergating_state(void *handle,
1284 enum amdgpu_powergating_state state) 1297 enum amd_powergating_state state)
1285{ 1298{
1286 return 0; 1299 return 0;
1287} 1300}
1288 1301
1289const struct amdgpu_ip_funcs sdma_v2_4_ip_funcs = { 1302const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1290 .early_init = sdma_v2_4_early_init, 1303 .early_init = sdma_v2_4_early_init,
1291 .late_init = NULL, 1304 .late_init = NULL,
1292 .sw_init = sdma_v2_4_sw_init, 1305 .sw_init = sdma_v2_4_sw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h
index 6cdf8941c577..07349f5ee10f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h
@@ -24,6 +24,6 @@
24#ifndef __SDMA_V2_4_H__ 24#ifndef __SDMA_V2_4_H__
25#define __SDMA_V2_4_H__ 25#define __SDMA_V2_4_H__
26 26
27extern const struct amdgpu_ip_funcs sdma_v2_4_ip_funcs; 27extern const struct amd_ip_funcs sdma_v2_4_ip_funcs;
28 28
29#endif 29#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 86a5278b65f6..bf3cefc447ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1018,8 +1018,10 @@ static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1018 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 1018 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1019} 1019}
1020 1020
1021static int sdma_v3_0_early_init(struct amdgpu_device *adev) 1021static int sdma_v3_0_early_init(void *handle)
1022{ 1022{
1023 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1024
1023 sdma_v3_0_set_ring_funcs(adev); 1025 sdma_v3_0_set_ring_funcs(adev);
1024 sdma_v3_0_set_buffer_funcs(adev); 1026 sdma_v3_0_set_buffer_funcs(adev);
1025 sdma_v3_0_set_vm_pte_funcs(adev); 1027 sdma_v3_0_set_vm_pte_funcs(adev);
@@ -1028,10 +1030,11 @@ static int sdma_v3_0_early_init(struct amdgpu_device *adev)
1028 return 0; 1030 return 0;
1029} 1031}
1030 1032
1031static int sdma_v3_0_sw_init(struct amdgpu_device *adev) 1033static int sdma_v3_0_sw_init(void *handle)
1032{ 1034{
1033 struct amdgpu_ring *ring; 1035 struct amdgpu_ring *ring;
1034 int r; 1036 int r;
1037 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1035 1038
1036 /* SDMA trap event */ 1039 /* SDMA trap event */
1037 r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq); 1040 r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq);
@@ -1085,17 +1088,20 @@ static int sdma_v3_0_sw_init(struct amdgpu_device *adev)
1085 return r; 1088 return r;
1086} 1089}
1087 1090
1088static int sdma_v3_0_sw_fini(struct amdgpu_device *adev) 1091static int sdma_v3_0_sw_fini(void *handle)
1089{ 1092{
1093 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1094
1090 amdgpu_ring_fini(&adev->sdma[0].ring); 1095 amdgpu_ring_fini(&adev->sdma[0].ring);
1091 amdgpu_ring_fini(&adev->sdma[1].ring); 1096 amdgpu_ring_fini(&adev->sdma[1].ring);
1092 1097
1093 return 0; 1098 return 0;
1094} 1099}
1095 1100
1096static int sdma_v3_0_hw_init(struct amdgpu_device *adev) 1101static int sdma_v3_0_hw_init(void *handle)
1097{ 1102{
1098 int r; 1103 int r;
1104 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1099 1105
1100 sdma_v3_0_init_golden_registers(adev); 1106 sdma_v3_0_init_golden_registers(adev);
1101 1107
@@ -1106,27 +1112,32 @@ static int sdma_v3_0_hw_init(struct amdgpu_device *adev)
1106 return r; 1112 return r;
1107} 1113}
1108 1114
1109static int sdma_v3_0_hw_fini(struct amdgpu_device *adev) 1115static int sdma_v3_0_hw_fini(void *handle)
1110{ 1116{
1117 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1118
1111 sdma_v3_0_enable(adev, false); 1119 sdma_v3_0_enable(adev, false);
1112 1120
1113 return 0; 1121 return 0;
1114} 1122}
1115 1123
1116static int sdma_v3_0_suspend(struct amdgpu_device *adev) 1124static int sdma_v3_0_suspend(void *handle)
1117{ 1125{
1126 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1118 1127
1119 return sdma_v3_0_hw_fini(adev); 1128 return sdma_v3_0_hw_fini(adev);
1120} 1129}
1121 1130
1122static int sdma_v3_0_resume(struct amdgpu_device *adev) 1131static int sdma_v3_0_resume(void *handle)
1123{ 1132{
1133 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1124 1134
1125 return sdma_v3_0_hw_init(adev); 1135 return sdma_v3_0_hw_init(adev);
1126} 1136}
1127 1137
1128static bool sdma_v3_0_is_idle(struct amdgpu_device *adev) 1138static bool sdma_v3_0_is_idle(void *handle)
1129{ 1139{
1140 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1130 u32 tmp = RREG32(mmSRBM_STATUS2); 1141 u32 tmp = RREG32(mmSRBM_STATUS2);
1131 1142
1132 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1143 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
@@ -1136,10 +1147,11 @@ static bool sdma_v3_0_is_idle(struct amdgpu_device *adev)
1136 return true; 1147 return true;
1137} 1148}
1138 1149
1139static int sdma_v3_0_wait_for_idle(struct amdgpu_device *adev) 1150static int sdma_v3_0_wait_for_idle(void *handle)
1140{ 1151{
1141 unsigned i; 1152 unsigned i;
1142 u32 tmp; 1153 u32 tmp;
1154 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1143 1155
1144 for (i = 0; i < adev->usec_timeout; i++) { 1156 for (i = 0; i < adev->usec_timeout; i++) {
1145 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1157 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
@@ -1152,9 +1164,10 @@ static int sdma_v3_0_wait_for_idle(struct amdgpu_device *adev)
1152 return -ETIMEDOUT; 1164 return -ETIMEDOUT;
1153} 1165}
1154 1166
1155static void sdma_v3_0_print_status(struct amdgpu_device *adev) 1167static void sdma_v3_0_print_status(void *handle)
1156{ 1168{
1157 int i, j; 1169 int i, j;
1170 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1158 1171
1159 dev_info(adev->dev, "VI SDMA registers\n"); 1172 dev_info(adev->dev, "VI SDMA registers\n");
1160 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", 1173 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
@@ -1200,9 +1213,10 @@ static void sdma_v3_0_print_status(struct amdgpu_device *adev)
1200 } 1213 }
1201} 1214}
1202 1215
1203static int sdma_v3_0_soft_reset(struct amdgpu_device *adev) 1216static int sdma_v3_0_soft_reset(void *handle)
1204{ 1217{
1205 u32 srbm_soft_reset = 0; 1218 u32 srbm_soft_reset = 0;
1219 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1206 u32 tmp = RREG32(mmSRBM_STATUS2); 1220 u32 tmp = RREG32(mmSRBM_STATUS2);
1207 1221
1208 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { 1222 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
@@ -1221,7 +1235,7 @@ static int sdma_v3_0_soft_reset(struct amdgpu_device *adev)
1221 } 1235 }
1222 1236
1223 if (srbm_soft_reset) { 1237 if (srbm_soft_reset) {
1224 sdma_v3_0_print_status(adev); 1238 sdma_v3_0_print_status((void *)adev);
1225 1239
1226 tmp = RREG32(mmSRBM_SOFT_RESET); 1240 tmp = RREG32(mmSRBM_SOFT_RESET);
1227 tmp |= srbm_soft_reset; 1241 tmp |= srbm_soft_reset;
@@ -1238,7 +1252,7 @@ static int sdma_v3_0_soft_reset(struct amdgpu_device *adev)
1238 /* Wait a little for things to settle down */ 1252 /* Wait a little for things to settle down */
1239 udelay(50); 1253 udelay(50);
1240 1254
1241 sdma_v3_0_print_status(adev); 1255 sdma_v3_0_print_status((void *)adev);
1242 } 1256 }
1243 1257
1244 return 0; 1258 return 0;
@@ -1339,21 +1353,19 @@ static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1339 return 0; 1353 return 0;
1340} 1354}
1341 1355
1342static int sdma_v3_0_set_clockgating_state(struct amdgpu_device *adev, 1356static int sdma_v3_0_set_clockgating_state(void *handle,
1343 enum amdgpu_clockgating_state state) 1357 enum amd_clockgating_state state)
1344{ 1358{
1345 /* XXX handled via the smc on VI */
1346
1347 return 0; 1359 return 0;
1348} 1360}
1349 1361
1350static int sdma_v3_0_set_powergating_state(struct amdgpu_device *adev, 1362static int sdma_v3_0_set_powergating_state(void *handle,
1351 enum amdgpu_powergating_state state) 1363 enum amd_powergating_state state)
1352{ 1364{
1353 return 0; 1365 return 0;
1354} 1366}
1355 1367
1356const struct amdgpu_ip_funcs sdma_v3_0_ip_funcs = { 1368const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1357 .early_init = sdma_v3_0_early_init, 1369 .early_init = sdma_v3_0_early_init,
1358 .late_init = NULL, 1370 .late_init = NULL,
1359 .sw_init = sdma_v3_0_sw_init, 1371 .sw_init = sdma_v3_0_sw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h
index 85bf2ac59252..0cb9698a3054 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h
@@ -24,6 +24,6 @@
24#ifndef __SDMA_V3_0_H__ 24#ifndef __SDMA_V3_0_H__
25#define __SDMA_V3_0_H__ 25#define __SDMA_V3_0_H__
26 26
27extern const struct amdgpu_ip_funcs sdma_v3_0_ip_funcs; 27extern const struct amd_ip_funcs sdma_v3_0_ip_funcs;
28 28
29#endif 29#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
index cf97d496a7a4..2d5b1bd52afa 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
@@ -30,8 +30,10 @@ MODULE_FIRMWARE("amdgpu/tonga_smc.bin");
30 30
31static void tonga_dpm_set_funcs(struct amdgpu_device *adev); 31static void tonga_dpm_set_funcs(struct amdgpu_device *adev);
32 32
33static int tonga_dpm_early_init(struct amdgpu_device *adev) 33static int tonga_dpm_early_init(void *handle)
34{ 34{
35 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
36
35 tonga_dpm_set_funcs(adev); 37 tonga_dpm_set_funcs(adev);
36 38
37 return 0; 39 return 0;
@@ -41,7 +43,6 @@ static int tonga_dpm_init_microcode(struct amdgpu_device *adev)
41{ 43{
42 char fw_name[30] = "amdgpu/tonga_smc.bin"; 44 char fw_name[30] = "amdgpu/tonga_smc.bin";
43 int err; 45 int err;
44
45 err = request_firmware(&adev->pm.fw, fw_name, adev->dev); 46 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
46 if (err) 47 if (err)
47 goto out; 48 goto out;
@@ -56,9 +57,10 @@ out:
56 return err; 57 return err;
57} 58}
58 59
59static int tonga_dpm_sw_init(struct amdgpu_device *adev) 60static int tonga_dpm_sw_init(void *handle)
60{ 61{
61 int ret; 62 int ret;
63 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
62 64
63 ret = tonga_dpm_init_microcode(adev); 65 ret = tonga_dpm_init_microcode(adev);
64 if (ret) 66 if (ret)
@@ -67,14 +69,15 @@ static int tonga_dpm_sw_init(struct amdgpu_device *adev)
67 return 0; 69 return 0;
68} 70}
69 71
70static int tonga_dpm_sw_fini(struct amdgpu_device *adev) 72static int tonga_dpm_sw_fini(void *handle)
71{ 73{
72 return 0; 74 return 0;
73} 75}
74 76
75static int tonga_dpm_hw_init(struct amdgpu_device *adev) 77static int tonga_dpm_hw_init(void *handle)
76{ 78{
77 int ret; 79 int ret;
80 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
78 81
79 mutex_lock(&adev->pm.mutex); 82 mutex_lock(&adev->pm.mutex);
80 83
@@ -99,41 +102,47 @@ fail:
99 return -EINVAL; 102 return -EINVAL;
100} 103}
101 104
102static int tonga_dpm_hw_fini(struct amdgpu_device *adev) 105static int tonga_dpm_hw_fini(void *handle)
103{ 106{
107 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
108
104 mutex_lock(&adev->pm.mutex); 109 mutex_lock(&adev->pm.mutex);
105 tonga_smu_fini(adev); 110 tonga_smu_fini(adev);
106 mutex_unlock(&adev->pm.mutex); 111 mutex_unlock(&adev->pm.mutex);
107 return 0; 112 return 0;
108} 113}
109 114
110static int tonga_dpm_suspend(struct amdgpu_device *adev) 115static int tonga_dpm_suspend(void *handle)
111{ 116{
117 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
118
112 tonga_dpm_hw_fini(adev); 119 tonga_dpm_hw_fini(adev);
113 120
114 return 0; 121 return 0;
115} 122}
116 123
117static int tonga_dpm_resume(struct amdgpu_device *adev) 124static int tonga_dpm_resume(void *handle)
118{ 125{
126 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
127
119 tonga_dpm_hw_init(adev); 128 tonga_dpm_hw_init(adev);
120 129
121 return 0; 130 return 0;
122} 131}
123 132
124static int tonga_dpm_set_clockgating_state(struct amdgpu_device *adev, 133static int tonga_dpm_set_clockgating_state(void *handle,
125 enum amdgpu_clockgating_state state) 134 enum amd_clockgating_state state)
126{ 135{
127 return 0; 136 return 0;
128} 137}
129 138
130static int tonga_dpm_set_powergating_state(struct amdgpu_device *adev, 139static int tonga_dpm_set_powergating_state(void *handle,
131 enum amdgpu_powergating_state state) 140 enum amd_powergating_state state)
132{ 141{
133 return 0; 142 return 0;
134} 143}
135 144
136const struct amdgpu_ip_funcs tonga_dpm_ip_funcs = { 145const struct amd_ip_funcs tonga_dpm_ip_funcs = {
137 .early_init = tonga_dpm_early_init, 146 .early_init = tonga_dpm_early_init,
138 .late_init = NULL, 147 .late_init = NULL,
139 .sw_init = tonga_dpm_sw_init, 148 .sw_init = tonga_dpm_sw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index cff1b8bce6a4..743c372837aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -270,15 +270,18 @@ static void tonga_ih_set_rptr(struct amdgpu_device *adev)
270 } 270 }
271} 271}
272 272
273static int tonga_ih_early_init(struct amdgpu_device *adev) 273static int tonga_ih_early_init(void *handle)
274{ 274{
275 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
276
275 tonga_ih_set_interrupt_funcs(adev); 277 tonga_ih_set_interrupt_funcs(adev);
276 return 0; 278 return 0;
277} 279}
278 280
279static int tonga_ih_sw_init(struct amdgpu_device *adev) 281static int tonga_ih_sw_init(void *handle)
280{ 282{
281 int r; 283 int r;
284 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
282 285
283 r = amdgpu_ih_ring_init(adev, 4 * 1024, true); 286 r = amdgpu_ih_ring_init(adev, 4 * 1024, true);
284 if (r) 287 if (r)
@@ -292,17 +295,20 @@ static int tonga_ih_sw_init(struct amdgpu_device *adev)
292 return r; 295 return r;
293} 296}
294 297
295static int tonga_ih_sw_fini(struct amdgpu_device *adev) 298static int tonga_ih_sw_fini(void *handle)
296{ 299{
300 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
301
297 amdgpu_irq_fini(adev); 302 amdgpu_irq_fini(adev);
298 amdgpu_ih_ring_fini(adev); 303 amdgpu_ih_ring_fini(adev);
299 304
300 return 0; 305 return 0;
301} 306}
302 307
303static int tonga_ih_hw_init(struct amdgpu_device *adev) 308static int tonga_ih_hw_init(void *handle)
304{ 309{
305 int r; 310 int r;
311 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
306 312
307 r = tonga_ih_irq_init(adev); 313 r = tonga_ih_irq_init(adev);
308 if (r) 314 if (r)
@@ -311,25 +317,32 @@ static int tonga_ih_hw_init(struct amdgpu_device *adev)
311 return 0; 317 return 0;
312} 318}
313 319
314static int tonga_ih_hw_fini(struct amdgpu_device *adev) 320static int tonga_ih_hw_fini(void *handle)
315{ 321{
322 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
323
316 tonga_ih_irq_disable(adev); 324 tonga_ih_irq_disable(adev);
317 325
318 return 0; 326 return 0;
319} 327}
320 328
321static int tonga_ih_suspend(struct amdgpu_device *adev) 329static int tonga_ih_suspend(void *handle)
322{ 330{
331 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
332
323 return tonga_ih_hw_fini(adev); 333 return tonga_ih_hw_fini(adev);
324} 334}
325 335
326static int tonga_ih_resume(struct amdgpu_device *adev) 336static int tonga_ih_resume(void *handle)
327{ 337{
338 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
339
328 return tonga_ih_hw_init(adev); 340 return tonga_ih_hw_init(adev);
329} 341}
330 342
331static bool tonga_ih_is_idle(struct amdgpu_device *adev) 343static bool tonga_ih_is_idle(void *handle)
332{ 344{
345 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
333 u32 tmp = RREG32(mmSRBM_STATUS); 346 u32 tmp = RREG32(mmSRBM_STATUS);
334 347
335 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) 348 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
@@ -338,10 +351,11 @@ static bool tonga_ih_is_idle(struct amdgpu_device *adev)
338 return true; 351 return true;
339} 352}
340 353
341static int tonga_ih_wait_for_idle(struct amdgpu_device *adev) 354static int tonga_ih_wait_for_idle(void *handle)
342{ 355{
343 unsigned i; 356 unsigned i;
344 u32 tmp; 357 u32 tmp;
358 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
345 359
346 for (i = 0; i < adev->usec_timeout; i++) { 360 for (i = 0; i < adev->usec_timeout; i++) {
347 /* read MC_STATUS */ 361 /* read MC_STATUS */
@@ -353,8 +367,10 @@ static int tonga_ih_wait_for_idle(struct amdgpu_device *adev)
353 return -ETIMEDOUT; 367 return -ETIMEDOUT;
354} 368}
355 369
356static void tonga_ih_print_status(struct amdgpu_device *adev) 370static void tonga_ih_print_status(void *handle)
357{ 371{
372 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
373
358 dev_info(adev->dev, "TONGA IH registers\n"); 374 dev_info(adev->dev, "TONGA IH registers\n");
359 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", 375 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
360 RREG32(mmSRBM_STATUS)); 376 RREG32(mmSRBM_STATUS));
@@ -380,9 +396,10 @@ static void tonga_ih_print_status(struct amdgpu_device *adev)
380 RREG32(mmIH_RB_WPTR)); 396 RREG32(mmIH_RB_WPTR));
381} 397}
382 398
383static int tonga_ih_soft_reset(struct amdgpu_device *adev) 399static int tonga_ih_soft_reset(void *handle)
384{ 400{
385 u32 srbm_soft_reset = 0; 401 u32 srbm_soft_reset = 0;
402 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
386 u32 tmp = RREG32(mmSRBM_STATUS); 403 u32 tmp = RREG32(mmSRBM_STATUS);
387 404
388 if (tmp & SRBM_STATUS__IH_BUSY_MASK) 405 if (tmp & SRBM_STATUS__IH_BUSY_MASK)
@@ -413,21 +430,19 @@ static int tonga_ih_soft_reset(struct amdgpu_device *adev)
413 return 0; 430 return 0;
414} 431}
415 432
416static int tonga_ih_set_clockgating_state(struct amdgpu_device *adev, 433static int tonga_ih_set_clockgating_state(void *handle,
417 enum amdgpu_clockgating_state state) 434 enum amd_clockgating_state state)
418{ 435{
419 // TODO
420 return 0; 436 return 0;
421} 437}
422 438
423static int tonga_ih_set_powergating_state(struct amdgpu_device *adev, 439static int tonga_ih_set_powergating_state(void *handle,
424 enum amdgpu_powergating_state state) 440 enum amd_powergating_state state)
425{ 441{
426 // TODO
427 return 0; 442 return 0;
428} 443}
429 444
430const struct amdgpu_ip_funcs tonga_ih_ip_funcs = { 445const struct amd_ip_funcs tonga_ih_ip_funcs = {
431 .early_init = tonga_ih_early_init, 446 .early_init = tonga_ih_early_init,
432 .late_init = NULL, 447 .late_init = NULL,
433 .sw_init = tonga_ih_sw_init, 448 .sw_init = tonga_ih_sw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.h b/drivers/gpu/drm/amd/amdgpu/tonga_ih.h
index 7c9bae87124e..7392d70fa4a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.h
@@ -24,6 +24,6 @@
24#ifndef __TONGA_IH_H__ 24#ifndef __TONGA_IH_H__
25#define __TONGA_IH_H__ 25#define __TONGA_IH_H__
26 26
27extern const struct amdgpu_ip_funcs tonga_ih_ip_funcs; 27extern const struct amd_ip_funcs tonga_ih_ip_funcs;
28 28
29#endif /* __CZ_IH_H__ */ 29#endif /* __CZ_IH_H__ */
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index 6e4cb604f928..292932a73c81 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -83,17 +83,20 @@ static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring)
83 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 83 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
84} 84}
85 85
86static int uvd_v4_2_early_init(struct amdgpu_device *adev) 86static int uvd_v4_2_early_init(void *handle)
87{ 87{
88 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
89
88 uvd_v4_2_set_ring_funcs(adev); 90 uvd_v4_2_set_ring_funcs(adev);
89 uvd_v4_2_set_irq_funcs(adev); 91 uvd_v4_2_set_irq_funcs(adev);
90 92
91 return 0; 93 return 0;
92} 94}
93 95
94static int uvd_v4_2_sw_init(struct amdgpu_device *adev) 96static int uvd_v4_2_sw_init(void *handle)
95{ 97{
96 struct amdgpu_ring *ring; 98 struct amdgpu_ring *ring;
99 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
97 int r; 100 int r;
98 101
99 /* UVD TRAP */ 102 /* UVD TRAP */
@@ -117,9 +120,10 @@ static int uvd_v4_2_sw_init(struct amdgpu_device *adev)
117 return r; 120 return r;
118} 121}
119 122
120static int uvd_v4_2_sw_fini(struct amdgpu_device *adev) 123static int uvd_v4_2_sw_fini(void *handle)
121{ 124{
122 int r; 125 int r;
126 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
123 127
124 r = amdgpu_uvd_suspend(adev); 128 r = amdgpu_uvd_suspend(adev);
125 if (r) 129 if (r)
@@ -139,8 +143,9 @@ static int uvd_v4_2_sw_fini(struct amdgpu_device *adev)
139 * 143 *
140 * Initialize the hardware, boot up the VCPU and do some testing 144 * Initialize the hardware, boot up the VCPU and do some testing
141 */ 145 */
142static int uvd_v4_2_hw_init(struct amdgpu_device *adev) 146static int uvd_v4_2_hw_init(void *handle)
143{ 147{
148 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
144 struct amdgpu_ring *ring = &adev->uvd.ring; 149 struct amdgpu_ring *ring = &adev->uvd.ring;
145 uint32_t tmp; 150 uint32_t tmp;
146 int r; 151 int r;
@@ -203,8 +208,9 @@ done:
203 * 208 *
204 * Stop the UVD block, mark ring as not ready any more 209 * Stop the UVD block, mark ring as not ready any more
205 */ 210 */
206static int uvd_v4_2_hw_fini(struct amdgpu_device *adev) 211static int uvd_v4_2_hw_fini(void *handle)
207{ 212{
213 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
208 struct amdgpu_ring *ring = &adev->uvd.ring; 214 struct amdgpu_ring *ring = &adev->uvd.ring;
209 215
210 uvd_v4_2_stop(adev); 216 uvd_v4_2_stop(adev);
@@ -213,9 +219,10 @@ static int uvd_v4_2_hw_fini(struct amdgpu_device *adev)
213 return 0; 219 return 0;
214} 220}
215 221
216static int uvd_v4_2_suspend(struct amdgpu_device *adev) 222static int uvd_v4_2_suspend(void *handle)
217{ 223{
218 int r; 224 int r;
225 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
219 226
220 r = uvd_v4_2_hw_fini(adev); 227 r = uvd_v4_2_hw_fini(adev);
221 if (r) 228 if (r)
@@ -228,9 +235,10 @@ static int uvd_v4_2_suspend(struct amdgpu_device *adev)
228 return r; 235 return r;
229} 236}
230 237
231static int uvd_v4_2_resume(struct amdgpu_device *adev) 238static int uvd_v4_2_resume(void *handle)
232{ 239{
233 int r; 240 int r;
241 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
234 242
235 r = amdgpu_uvd_resume(adev); 243 r = amdgpu_uvd_resume(adev);
236 if (r) 244 if (r)
@@ -662,14 +670,17 @@ static void uvd_v4_2_init_cg(struct amdgpu_device *adev)
662 } 670 }
663} 671}
664 672
665static bool uvd_v4_2_is_idle(struct amdgpu_device *adev) 673static bool uvd_v4_2_is_idle(void *handle)
666{ 674{
675 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
676
667 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 677 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
668} 678}
669 679
670static int uvd_v4_2_wait_for_idle(struct amdgpu_device *adev) 680static int uvd_v4_2_wait_for_idle(void *handle)
671{ 681{
672 unsigned i; 682 unsigned i;
683 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
673 684
674 for (i = 0; i < adev->usec_timeout; i++) { 685 for (i = 0; i < adev->usec_timeout; i++) {
675 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 686 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
@@ -678,8 +689,10 @@ static int uvd_v4_2_wait_for_idle(struct amdgpu_device *adev)
678 return -ETIMEDOUT; 689 return -ETIMEDOUT;
679} 690}
680 691
681static int uvd_v4_2_soft_reset(struct amdgpu_device *adev) 692static int uvd_v4_2_soft_reset(void *handle)
682{ 693{
694 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
695
683 uvd_v4_2_stop(adev); 696 uvd_v4_2_stop(adev);
684 697
685 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 698 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
@@ -689,8 +702,9 @@ static int uvd_v4_2_soft_reset(struct amdgpu_device *adev)
689 return uvd_v4_2_start(adev); 702 return uvd_v4_2_start(adev);
690} 703}
691 704
692static void uvd_v4_2_print_status(struct amdgpu_device *adev) 705static void uvd_v4_2_print_status(void *handle)
693{ 706{
707 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
694 dev_info(adev->dev, "UVD 4.2 registers\n"); 708 dev_info(adev->dev, "UVD 4.2 registers\n");
695 dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n", 709 dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n",
696 RREG32(mmUVD_SEMA_ADDR_LOW)); 710 RREG32(mmUVD_SEMA_ADDR_LOW));
@@ -810,12 +824,13 @@ static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev,
810 return 0; 824 return 0;
811} 825}
812 826
813static int uvd_v4_2_set_clockgating_state(struct amdgpu_device *adev, 827static int uvd_v4_2_set_clockgating_state(void *handle,
814 enum amdgpu_clockgating_state state) 828 enum amd_clockgating_state state)
815{ 829{
816 bool gate = false; 830 bool gate = false;
831 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
817 832
818 if (state == AMDGPU_CG_STATE_GATE) 833 if (state == AMD_CG_STATE_GATE)
819 gate = true; 834 gate = true;
820 835
821 uvd_v4_2_enable_mgcg(adev, gate); 836 uvd_v4_2_enable_mgcg(adev, gate);
@@ -823,8 +838,8 @@ static int uvd_v4_2_set_clockgating_state(struct amdgpu_device *adev,
823 return 0; 838 return 0;
824} 839}
825 840
826static int uvd_v4_2_set_powergating_state(struct amdgpu_device *adev, 841static int uvd_v4_2_set_powergating_state(void *handle,
827 enum amdgpu_powergating_state state) 842 enum amd_powergating_state state)
828{ 843{
829 /* This doesn't actually powergate the UVD block. 844 /* This doesn't actually powergate the UVD block.
830 * That's done in the dpm code via the SMC. This 845 * That's done in the dpm code via the SMC. This
@@ -833,7 +848,9 @@ static int uvd_v4_2_set_powergating_state(struct amdgpu_device *adev,
833 * revisit this when there is a cleaner line between 848 * revisit this when there is a cleaner line between
834 * the smc and the hw blocks 849 * the smc and the hw blocks
835 */ 850 */
836 if (state == AMDGPU_PG_STATE_GATE) { 851 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
852
853 if (state == AMD_PG_STATE_GATE) {
837 uvd_v4_2_stop(adev); 854 uvd_v4_2_stop(adev);
838 return 0; 855 return 0;
839 } else { 856 } else {
@@ -841,7 +858,7 @@ static int uvd_v4_2_set_powergating_state(struct amdgpu_device *adev,
841 } 858 }
842} 859}
843 860
844const struct amdgpu_ip_funcs uvd_v4_2_ip_funcs = { 861const struct amd_ip_funcs uvd_v4_2_ip_funcs = {
845 .early_init = uvd_v4_2_early_init, 862 .early_init = uvd_v4_2_early_init,
846 .late_init = NULL, 863 .late_init = NULL,
847 .sw_init = uvd_v4_2_sw_init, 864 .sw_init = uvd_v4_2_sw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h
index 323a6d828dfe..0a615dd50840 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h
@@ -24,6 +24,6 @@
24#ifndef __UVD_V4_2_H__ 24#ifndef __UVD_V4_2_H__
25#define __UVD_V4_2_H__ 25#define __UVD_V4_2_H__
26 26
27extern const struct amdgpu_ip_funcs uvd_v4_2_ip_funcs; 27extern const struct amd_ip_funcs uvd_v4_2_ip_funcs;
28 28
29#endif 29#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index f3b3026d5932..004c56496fc4 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -79,17 +79,20 @@ static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
79 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 79 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
80} 80}
81 81
82static int uvd_v5_0_early_init(struct amdgpu_device *adev) 82static int uvd_v5_0_early_init(void *handle)
83{ 83{
84 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
85
84 uvd_v5_0_set_ring_funcs(adev); 86 uvd_v5_0_set_ring_funcs(adev);
85 uvd_v5_0_set_irq_funcs(adev); 87 uvd_v5_0_set_irq_funcs(adev);
86 88
87 return 0; 89 return 0;
88} 90}
89 91
90static int uvd_v5_0_sw_init(struct amdgpu_device *adev) 92static int uvd_v5_0_sw_init(void *handle)
91{ 93{
92 struct amdgpu_ring *ring; 94 struct amdgpu_ring *ring;
95 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
93 int r; 96 int r;
94 97
95 /* UVD TRAP */ 98 /* UVD TRAP */
@@ -113,9 +116,10 @@ static int uvd_v5_0_sw_init(struct amdgpu_device *adev)
113 return r; 116 return r;
114} 117}
115 118
116static int uvd_v5_0_sw_fini(struct amdgpu_device *adev) 119static int uvd_v5_0_sw_fini(void *handle)
117{ 120{
118 int r; 121 int r;
122 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
119 123
120 r = amdgpu_uvd_suspend(adev); 124 r = amdgpu_uvd_suspend(adev);
121 if (r) 125 if (r)
@@ -135,8 +139,9 @@ static int uvd_v5_0_sw_fini(struct amdgpu_device *adev)
135 * 139 *
136 * Initialize the hardware, boot up the VCPU and do some testing 140 * Initialize the hardware, boot up the VCPU and do some testing
137 */ 141 */
138static int uvd_v5_0_hw_init(struct amdgpu_device *adev) 142static int uvd_v5_0_hw_init(void *handle)
139{ 143{
144 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
140 struct amdgpu_ring *ring = &adev->uvd.ring; 145 struct amdgpu_ring *ring = &adev->uvd.ring;
141 uint32_t tmp; 146 uint32_t tmp;
142 int r; 147 int r;
@@ -199,8 +204,9 @@ done:
199 * 204 *
200 * Stop the UVD block, mark ring as not ready any more 205 * Stop the UVD block, mark ring as not ready any more
201 */ 206 */
202static int uvd_v5_0_hw_fini(struct amdgpu_device *adev) 207static int uvd_v5_0_hw_fini(void *handle)
203{ 208{
209 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
204 struct amdgpu_ring *ring = &adev->uvd.ring; 210 struct amdgpu_ring *ring = &adev->uvd.ring;
205 211
206 uvd_v5_0_stop(adev); 212 uvd_v5_0_stop(adev);
@@ -209,9 +215,10 @@ static int uvd_v5_0_hw_fini(struct amdgpu_device *adev)
209 return 0; 215 return 0;
210} 216}
211 217
212static int uvd_v5_0_suspend(struct amdgpu_device *adev) 218static int uvd_v5_0_suspend(void *handle)
213{ 219{
214 int r; 220 int r;
221 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
215 222
216 r = uvd_v5_0_hw_fini(adev); 223 r = uvd_v5_0_hw_fini(adev);
217 if (r) 224 if (r)
@@ -224,9 +231,10 @@ static int uvd_v5_0_suspend(struct amdgpu_device *adev)
224 return r; 231 return r;
225} 232}
226 233
227static int uvd_v5_0_resume(struct amdgpu_device *adev) 234static int uvd_v5_0_resume(void *handle)
228{ 235{
229 int r; 236 int r;
237 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
230 238
231 r = amdgpu_uvd_resume(adev); 239 r = amdgpu_uvd_resume(adev);
232 if (r) 240 if (r)
@@ -605,14 +613,17 @@ error:
605 return r; 613 return r;
606} 614}
607 615
608static bool uvd_v5_0_is_idle(struct amdgpu_device *adev) 616static bool uvd_v5_0_is_idle(void *handle)
609{ 617{
618 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
619
610 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 620 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
611} 621}
612 622
613static int uvd_v5_0_wait_for_idle(struct amdgpu_device *adev) 623static int uvd_v5_0_wait_for_idle(void *handle)
614{ 624{
615 unsigned i; 625 unsigned i;
626 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
616 627
617 for (i = 0; i < adev->usec_timeout; i++) { 628 for (i = 0; i < adev->usec_timeout; i++) {
618 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 629 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
@@ -621,8 +632,10 @@ static int uvd_v5_0_wait_for_idle(struct amdgpu_device *adev)
621 return -ETIMEDOUT; 632 return -ETIMEDOUT;
622} 633}
623 634
624static int uvd_v5_0_soft_reset(struct amdgpu_device *adev) 635static int uvd_v5_0_soft_reset(void *handle)
625{ 636{
637 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
638
626 uvd_v5_0_stop(adev); 639 uvd_v5_0_stop(adev);
627 640
628 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 641 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
@@ -632,8 +645,9 @@ static int uvd_v5_0_soft_reset(struct amdgpu_device *adev)
632 return uvd_v5_0_start(adev); 645 return uvd_v5_0_start(adev);
633} 646}
634 647
635static void uvd_v5_0_print_status(struct amdgpu_device *adev) 648static void uvd_v5_0_print_status(void *handle)
636{ 649{
650 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
637 dev_info(adev->dev, "UVD 5.0 registers\n"); 651 dev_info(adev->dev, "UVD 5.0 registers\n");
638 dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n", 652 dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n",
639 RREG32(mmUVD_SEMA_ADDR_LOW)); 653 RREG32(mmUVD_SEMA_ADDR_LOW));
@@ -757,16 +771,14 @@ static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev,
757 return 0; 771 return 0;
758} 772}
759 773
760static int uvd_v5_0_set_clockgating_state(struct amdgpu_device *adev, 774static int uvd_v5_0_set_clockgating_state(void *handle,
761 enum amdgpu_clockgating_state state) 775 enum amd_clockgating_state state)
762{ 776{
763 //TODO
764
765 return 0; 777 return 0;
766} 778}
767 779
768static int uvd_v5_0_set_powergating_state(struct amdgpu_device *adev, 780static int uvd_v5_0_set_powergating_state(void *handle,
769 enum amdgpu_powergating_state state) 781 enum amd_powergating_state state)
770{ 782{
771 /* This doesn't actually powergate the UVD block. 783 /* This doesn't actually powergate the UVD block.
772 * That's done in the dpm code via the SMC. This 784 * That's done in the dpm code via the SMC. This
@@ -775,7 +787,9 @@ static int uvd_v5_0_set_powergating_state(struct amdgpu_device *adev,
775 * revisit this when there is a cleaner line between 787 * revisit this when there is a cleaner line between
776 * the smc and the hw blocks 788 * the smc and the hw blocks
777 */ 789 */
778 if (state == AMDGPU_PG_STATE_GATE) { 790 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
791
792 if (state == AMD_PG_STATE_GATE) {
779 uvd_v5_0_stop(adev); 793 uvd_v5_0_stop(adev);
780 return 0; 794 return 0;
781 } else { 795 } else {
@@ -783,7 +797,7 @@ static int uvd_v5_0_set_powergating_state(struct amdgpu_device *adev,
783 } 797 }
784} 798}
785 799
786const struct amdgpu_ip_funcs uvd_v5_0_ip_funcs = { 800const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
787 .early_init = uvd_v5_0_early_init, 801 .early_init = uvd_v5_0_early_init,
788 .late_init = NULL, 802 .late_init = NULL,
789 .sw_init = uvd_v5_0_sw_init, 803 .sw_init = uvd_v5_0_sw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h
index 7d7a15296383..e3b3c49fa5de 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h
@@ -24,6 +24,6 @@
24#ifndef __UVD_V5_0_H__ 24#ifndef __UVD_V5_0_H__
25#define __UVD_V5_0_H__ 25#define __UVD_V5_0_H__
26 26
27extern const struct amdgpu_ip_funcs uvd_v5_0_ip_funcs; 27extern const struct amd_ip_funcs uvd_v5_0_ip_funcs;
28 28
29#endif 29#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index f59942d5c50e..8c790fb31e2f 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -79,18 +79,21 @@ static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
79 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 79 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
80} 80}
81 81
82static int uvd_v6_0_early_init(struct amdgpu_device *adev) 82static int uvd_v6_0_early_init(void *handle)
83{ 83{
84 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
85
84 uvd_v6_0_set_ring_funcs(adev); 86 uvd_v6_0_set_ring_funcs(adev);
85 uvd_v6_0_set_irq_funcs(adev); 87 uvd_v6_0_set_irq_funcs(adev);
86 88
87 return 0; 89 return 0;
88} 90}
89 91
90static int uvd_v6_0_sw_init(struct amdgpu_device *adev) 92static int uvd_v6_0_sw_init(void *handle)
91{ 93{
92 struct amdgpu_ring *ring; 94 struct amdgpu_ring *ring;
93 int r; 95 int r;
96 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
94 97
95 /* UVD TRAP */ 98 /* UVD TRAP */
96 r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); 99 r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);
@@ -113,9 +116,10 @@ static int uvd_v6_0_sw_init(struct amdgpu_device *adev)
113 return r; 116 return r;
114} 117}
115 118
116static int uvd_v6_0_sw_fini(struct amdgpu_device *adev) 119static int uvd_v6_0_sw_fini(void *handle)
117{ 120{
118 int r; 121 int r;
122 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
119 123
120 r = amdgpu_uvd_suspend(adev); 124 r = amdgpu_uvd_suspend(adev);
121 if (r) 125 if (r)
@@ -135,8 +139,9 @@ static int uvd_v6_0_sw_fini(struct amdgpu_device *adev)
135 * 139 *
136 * Initialize the hardware, boot up the VCPU and do some testing 140 * Initialize the hardware, boot up the VCPU and do some testing
137 */ 141 */
138static int uvd_v6_0_hw_init(struct amdgpu_device *adev) 142static int uvd_v6_0_hw_init(void *handle)
139{ 143{
144 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
140 struct amdgpu_ring *ring = &adev->uvd.ring; 145 struct amdgpu_ring *ring = &adev->uvd.ring;
141 uint32_t tmp; 146 uint32_t tmp;
142 int r; 147 int r;
@@ -193,8 +198,9 @@ done:
193 * 198 *
194 * Stop the UVD block, mark ring as not ready any more 199 * Stop the UVD block, mark ring as not ready any more
195 */ 200 */
196static int uvd_v6_0_hw_fini(struct amdgpu_device *adev) 201static int uvd_v6_0_hw_fini(void *handle)
197{ 202{
203 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
198 struct amdgpu_ring *ring = &adev->uvd.ring; 204 struct amdgpu_ring *ring = &adev->uvd.ring;
199 205
200 uvd_v6_0_stop(adev); 206 uvd_v6_0_stop(adev);
@@ -203,9 +209,10 @@ static int uvd_v6_0_hw_fini(struct amdgpu_device *adev)
203 return 0; 209 return 0;
204} 210}
205 211
206static int uvd_v6_0_suspend(struct amdgpu_device *adev) 212static int uvd_v6_0_suspend(void *handle)
207{ 213{
208 int r; 214 int r;
215 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
209 216
210 r = uvd_v6_0_hw_fini(adev); 217 r = uvd_v6_0_hw_fini(adev);
211 if (r) 218 if (r)
@@ -218,9 +225,10 @@ static int uvd_v6_0_suspend(struct amdgpu_device *adev)
218 return r; 225 return r;
219} 226}
220 227
221static int uvd_v6_0_resume(struct amdgpu_device *adev) 228static int uvd_v6_0_resume(void *handle)
222{ 229{
223 int r; 230 int r;
231 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
224 232
225 r = amdgpu_uvd_resume(adev); 233 r = amdgpu_uvd_resume(adev);
226 if (r) 234 if (r)
@@ -593,14 +601,17 @@ error:
593 return r; 601 return r;
594} 602}
595 603
596static bool uvd_v6_0_is_idle(struct amdgpu_device *adev) 604static bool uvd_v6_0_is_idle(void *handle)
597{ 605{
606 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
607
598 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 608 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
599} 609}
600 610
601static int uvd_v6_0_wait_for_idle(struct amdgpu_device *adev) 611static int uvd_v6_0_wait_for_idle(void *handle)
602{ 612{
603 unsigned i; 613 unsigned i;
614 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
604 615
605 for (i = 0; i < adev->usec_timeout; i++) { 616 for (i = 0; i < adev->usec_timeout; i++) {
606 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 617 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
@@ -609,8 +620,10 @@ static int uvd_v6_0_wait_for_idle(struct amdgpu_device *adev)
609 return -ETIMEDOUT; 620 return -ETIMEDOUT;
610} 621}
611 622
612static int uvd_v6_0_soft_reset(struct amdgpu_device *adev) 623static int uvd_v6_0_soft_reset(void *handle)
613{ 624{
625 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
626
614 uvd_v6_0_stop(adev); 627 uvd_v6_0_stop(adev);
615 628
616 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 629 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
@@ -620,8 +633,9 @@ static int uvd_v6_0_soft_reset(struct amdgpu_device *adev)
620 return uvd_v6_0_start(adev); 633 return uvd_v6_0_start(adev);
621} 634}
622 635
623static void uvd_v6_0_print_status(struct amdgpu_device *adev) 636static void uvd_v6_0_print_status(void *handle)
624{ 637{
638 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
625 dev_info(adev->dev, "UVD 6.0 registers\n"); 639 dev_info(adev->dev, "UVD 6.0 registers\n");
626 dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n", 640 dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n",
627 RREG32(mmUVD_SEMA_ADDR_LOW)); 641 RREG32(mmUVD_SEMA_ADDR_LOW));
@@ -737,16 +751,14 @@ static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
737 return 0; 751 return 0;
738} 752}
739 753
740static int uvd_v6_0_set_clockgating_state(struct amdgpu_device *adev, 754static int uvd_v6_0_set_clockgating_state(void *handle,
741 enum amdgpu_clockgating_state state) 755 enum amd_clockgating_state state)
742{ 756{
743 //TODO
744
745 return 0; 757 return 0;
746} 758}
747 759
748static int uvd_v6_0_set_powergating_state(struct amdgpu_device *adev, 760static int uvd_v6_0_set_powergating_state(void *handle,
749 enum amdgpu_powergating_state state) 761 enum amd_powergating_state state)
750{ 762{
751 /* This doesn't actually powergate the UVD block. 763 /* This doesn't actually powergate the UVD block.
752 * That's done in the dpm code via the SMC. This 764 * That's done in the dpm code via the SMC. This
@@ -755,7 +767,9 @@ static int uvd_v6_0_set_powergating_state(struct amdgpu_device *adev,
755 * revisit this when there is a cleaner line between 767 * revisit this when there is a cleaner line between
756 * the smc and the hw blocks 768 * the smc and the hw blocks
757 */ 769 */
758 if (state == AMDGPU_PG_STATE_GATE) { 770 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
771
772 if (state == AMD_PG_STATE_GATE) {
759 uvd_v6_0_stop(adev); 773 uvd_v6_0_stop(adev);
760 return 0; 774 return 0;
761 } else { 775 } else {
@@ -763,7 +777,7 @@ static int uvd_v6_0_set_powergating_state(struct amdgpu_device *adev,
763 } 777 }
764} 778}
765 779
766const struct amdgpu_ip_funcs uvd_v6_0_ip_funcs = { 780const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
767 .early_init = uvd_v6_0_early_init, 781 .early_init = uvd_v6_0_early_init,
768 .late_init = NULL, 782 .late_init = NULL,
769 .sw_init = uvd_v6_0_sw_init, 783 .sw_init = uvd_v6_0_sw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h
index bc21afc8abac..6b92a2352986 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h
@@ -24,6 +24,6 @@
24#ifndef __UVD_V6_0_H__ 24#ifndef __UVD_V6_0_H__
25#define __UVD_V6_0_H__ 25#define __UVD_V6_0_H__
26 26
27extern const struct amdgpu_ip_funcs uvd_v6_0_ip_funcs; 27extern const struct amd_ip_funcs uvd_v6_0_ip_funcs;
28 28
29#endif 29#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
index f200df3cf97a..303d961d57bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
@@ -169,18 +169,21 @@ static int vce_v2_0_start(struct amdgpu_device *adev)
169 return 0; 169 return 0;
170} 170}
171 171
172static int vce_v2_0_early_init(struct amdgpu_device *adev) 172static int vce_v2_0_early_init(void *handle)
173{ 173{
174 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
175
174 vce_v2_0_set_ring_funcs(adev); 176 vce_v2_0_set_ring_funcs(adev);
175 vce_v2_0_set_irq_funcs(adev); 177 vce_v2_0_set_irq_funcs(adev);
176 178
177 return 0; 179 return 0;
178} 180}
179 181
180static int vce_v2_0_sw_init(struct amdgpu_device *adev) 182static int vce_v2_0_sw_init(void *handle)
181{ 183{
182 struct amdgpu_ring *ring; 184 struct amdgpu_ring *ring;
183 int r; 185 int r;
186 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
184 187
185 /* VCE */ 188 /* VCE */
186 r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq); 189 r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq);
@@ -213,9 +216,10 @@ static int vce_v2_0_sw_init(struct amdgpu_device *adev)
213 return r; 216 return r;
214} 217}
215 218
216static int vce_v2_0_sw_fini(struct amdgpu_device *adev) 219static int vce_v2_0_sw_fini(void *handle)
217{ 220{
218 int r; 221 int r;
222 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
219 223
220 r = amdgpu_vce_suspend(adev); 224 r = amdgpu_vce_suspend(adev);
221 if (r) 225 if (r)
@@ -228,10 +232,11 @@ static int vce_v2_0_sw_fini(struct amdgpu_device *adev)
228 return r; 232 return r;
229} 233}
230 234
231static int vce_v2_0_hw_init(struct amdgpu_device *adev) 235static int vce_v2_0_hw_init(void *handle)
232{ 236{
233 struct amdgpu_ring *ring; 237 struct amdgpu_ring *ring;
234 int r; 238 int r;
239 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
235 240
236 r = vce_v2_0_start(adev); 241 r = vce_v2_0_start(adev);
237 if (r) 242 if (r)
@@ -258,15 +263,15 @@ static int vce_v2_0_hw_init(struct amdgpu_device *adev)
258 return 0; 263 return 0;
259} 264}
260 265
261static int vce_v2_0_hw_fini(struct amdgpu_device *adev) 266static int vce_v2_0_hw_fini(void *handle)
262{ 267{
263 // TODO
264 return 0; 268 return 0;
265} 269}
266 270
267static int vce_v2_0_suspend(struct amdgpu_device *adev) 271static int vce_v2_0_suspend(void *handle)
268{ 272{
269 int r; 273 int r;
274 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
270 275
271 r = vce_v2_0_hw_fini(adev); 276 r = vce_v2_0_hw_fini(adev);
272 if (r) 277 if (r)
@@ -279,9 +284,10 @@ static int vce_v2_0_suspend(struct amdgpu_device *adev)
279 return r; 284 return r;
280} 285}
281 286
282static int vce_v2_0_resume(struct amdgpu_device *adev) 287static int vce_v2_0_resume(void *handle)
283{ 288{
284 int r; 289 int r;
290 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
285 291
286 r = amdgpu_vce_resume(adev); 292 r = amdgpu_vce_resume(adev);
287 if (r) 293 if (r)
@@ -442,14 +448,17 @@ static void vce_v2_0_mc_resume(struct amdgpu_device *adev)
442 vce_v2_0_init_cg(adev); 448 vce_v2_0_init_cg(adev);
443} 449}
444 450
445static bool vce_v2_0_is_idle(struct amdgpu_device *adev) 451static bool vce_v2_0_is_idle(void *handle)
446{ 452{
453 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
454
447 return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK); 455 return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
448} 456}
449 457
450static int vce_v2_0_wait_for_idle(struct amdgpu_device *adev) 458static int vce_v2_0_wait_for_idle(void *handle)
451{ 459{
452 unsigned i; 460 unsigned i;
461 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
453 462
454 for (i = 0; i < adev->usec_timeout; i++) { 463 for (i = 0; i < adev->usec_timeout; i++) {
455 if (!(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK)) 464 if (!(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK))
@@ -458,8 +467,10 @@ static int vce_v2_0_wait_for_idle(struct amdgpu_device *adev)
458 return -ETIMEDOUT; 467 return -ETIMEDOUT;
459} 468}
460 469
461static int vce_v2_0_soft_reset(struct amdgpu_device *adev) 470static int vce_v2_0_soft_reset(void *handle)
462{ 471{
472 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
473
463 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK, 474 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK,
464 ~SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK); 475 ~SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK);
465 mdelay(5); 476 mdelay(5);
@@ -467,8 +478,10 @@ static int vce_v2_0_soft_reset(struct amdgpu_device *adev)
467 return vce_v2_0_start(adev); 478 return vce_v2_0_start(adev);
468} 479}
469 480
470static void vce_v2_0_print_status(struct amdgpu_device *adev) 481static void vce_v2_0_print_status(void *handle)
471{ 482{
483 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
484
472 dev_info(adev->dev, "VCE 2.0 registers\n"); 485 dev_info(adev->dev, "VCE 2.0 registers\n");
473 dev_info(adev->dev, " VCE_STATUS=0x%08X\n", 486 dev_info(adev->dev, " VCE_STATUS=0x%08X\n",
474 RREG32(mmVCE_STATUS)); 487 RREG32(mmVCE_STATUS));
@@ -569,12 +582,13 @@ static int vce_v2_0_process_interrupt(struct amdgpu_device *adev,
569 return 0; 582 return 0;
570} 583}
571 584
572static int vce_v2_0_set_clockgating_state(struct amdgpu_device *adev, 585static int vce_v2_0_set_clockgating_state(void *handle,
573 enum amdgpu_clockgating_state state) 586 enum amd_clockgating_state state)
574{ 587{
575 bool gate = false; 588 bool gate = false;
589 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
576 590
577 if (state == AMDGPU_CG_STATE_GATE) 591 if (state == AMD_CG_STATE_GATE)
578 gate = true; 592 gate = true;
579 593
580 vce_v2_0_enable_mgcg(adev, gate); 594 vce_v2_0_enable_mgcg(adev, gate);
@@ -582,8 +596,8 @@ static int vce_v2_0_set_clockgating_state(struct amdgpu_device *adev,
582 return 0; 596 return 0;
583} 597}
584 598
585static int vce_v2_0_set_powergating_state(struct amdgpu_device *adev, 599static int vce_v2_0_set_powergating_state(void *handle,
586 enum amdgpu_powergating_state state) 600 enum amd_powergating_state state)
587{ 601{
588 /* This doesn't actually powergate the VCE block. 602 /* This doesn't actually powergate the VCE block.
589 * That's done in the dpm code via the SMC. This 603 * That's done in the dpm code via the SMC. This
@@ -592,14 +606,16 @@ static int vce_v2_0_set_powergating_state(struct amdgpu_device *adev,
592 * revisit this when there is a cleaner line between 606 * revisit this when there is a cleaner line between
593 * the smc and the hw blocks 607 * the smc and the hw blocks
594 */ 608 */
595 if (state == AMDGPU_PG_STATE_GATE) 609 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
610
611 if (state == AMD_PG_STATE_GATE)
596 /* XXX do we need a vce_v2_0_stop()? */ 612 /* XXX do we need a vce_v2_0_stop()? */
597 return 0; 613 return 0;
598 else 614 else
599 return vce_v2_0_start(adev); 615 return vce_v2_0_start(adev);
600} 616}
601 617
602const struct amdgpu_ip_funcs vce_v2_0_ip_funcs = { 618const struct amd_ip_funcs vce_v2_0_ip_funcs = {
603 .early_init = vce_v2_0_early_init, 619 .early_init = vce_v2_0_early_init,
604 .late_init = NULL, 620 .late_init = NULL,
605 .sw_init = vce_v2_0_sw_init, 621 .sw_init = vce_v2_0_sw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.h b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.h
index 8eb1cf227ea6..0d2ae8a01acd 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.h
@@ -24,6 +24,6 @@
24#ifndef __VCE_V2_0_H__ 24#ifndef __VCE_V2_0_H__
25#define __VCE_V2_0_H__ 25#define __VCE_V2_0_H__
26 26
27extern const struct amdgpu_ip_funcs vce_v2_0_ip_funcs; 27extern const struct amd_ip_funcs vce_v2_0_ip_funcs;
28 28
29#endif 29#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 57e0e167c83b..d62c4002e39c 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -190,16 +190,19 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
190 return 0; 190 return 0;
191} 191}
192 192
193static int vce_v3_0_early_init(struct amdgpu_device *adev) 193static int vce_v3_0_early_init(void *handle)
194{ 194{
195 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
196
195 vce_v3_0_set_ring_funcs(adev); 197 vce_v3_0_set_ring_funcs(adev);
196 vce_v3_0_set_irq_funcs(adev); 198 vce_v3_0_set_irq_funcs(adev);
197 199
198 return 0; 200 return 0;
199} 201}
200 202
201static int vce_v3_0_sw_init(struct amdgpu_device *adev) 203static int vce_v3_0_sw_init(void *handle)
202{ 204{
205 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
203 struct amdgpu_ring *ring; 206 struct amdgpu_ring *ring;
204 int r; 207 int r;
205 208
@@ -234,9 +237,10 @@ static int vce_v3_0_sw_init(struct amdgpu_device *adev)
234 return r; 237 return r;
235} 238}
236 239
237static int vce_v3_0_sw_fini(struct amdgpu_device *adev) 240static int vce_v3_0_sw_fini(void *handle)
238{ 241{
239 int r; 242 int r;
243 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
240 244
241 r = amdgpu_vce_suspend(adev); 245 r = amdgpu_vce_suspend(adev);
242 if (r) 246 if (r)
@@ -249,10 +253,11 @@ static int vce_v3_0_sw_fini(struct amdgpu_device *adev)
249 return r; 253 return r;
250} 254}
251 255
252static int vce_v3_0_hw_init(struct amdgpu_device *adev) 256static int vce_v3_0_hw_init(void *handle)
253{ 257{
254 struct amdgpu_ring *ring; 258 struct amdgpu_ring *ring;
255 int r; 259 int r;
260 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
256 261
257 r = vce_v3_0_start(adev); 262 r = vce_v3_0_start(adev);
258 if (r) 263 if (r)
@@ -279,15 +284,15 @@ static int vce_v3_0_hw_init(struct amdgpu_device *adev)
279 return 0; 284 return 0;
280} 285}
281 286
282static int vce_v3_0_hw_fini(struct amdgpu_device *adev) 287static int vce_v3_0_hw_fini(void *handle)
283{ 288{
284 // TODO
285 return 0; 289 return 0;
286} 290}
287 291
288static int vce_v3_0_suspend(struct amdgpu_device *adev) 292static int vce_v3_0_suspend(void *handle)
289{ 293{
290 int r; 294 int r;
295 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
291 296
292 r = vce_v3_0_hw_fini(adev); 297 r = vce_v3_0_hw_fini(adev);
293 if (r) 298 if (r)
@@ -300,9 +305,10 @@ static int vce_v3_0_suspend(struct amdgpu_device *adev)
300 return r; 305 return r;
301} 306}
302 307
303static int vce_v3_0_resume(struct amdgpu_device *adev) 308static int vce_v3_0_resume(void *handle)
304{ 309{
305 int r; 310 int r;
311 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
306 312
307 r = amdgpu_vce_resume(adev); 313 r = amdgpu_vce_resume(adev);
308 if (r) 314 if (r)
@@ -362,14 +368,17 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx)
362 ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); 368 ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
363} 369}
364 370
365static bool vce_v3_0_is_idle(struct amdgpu_device *adev) 371static bool vce_v3_0_is_idle(void *handle)
366{ 372{
373 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
374
367 return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK); 375 return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
368} 376}
369 377
370static int vce_v3_0_wait_for_idle(struct amdgpu_device *adev) 378static int vce_v3_0_wait_for_idle(void *handle)
371{ 379{
372 unsigned i; 380 unsigned i;
381 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
373 382
374 for (i = 0; i < adev->usec_timeout; i++) { 383 for (i = 0; i < adev->usec_timeout; i++) {
375 if (!(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK)) 384 if (!(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK))
@@ -378,8 +387,10 @@ static int vce_v3_0_wait_for_idle(struct amdgpu_device *adev)
378 return -ETIMEDOUT; 387 return -ETIMEDOUT;
379} 388}
380 389
381static int vce_v3_0_soft_reset(struct amdgpu_device *adev) 390static int vce_v3_0_soft_reset(void *handle)
382{ 391{
392 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
393
383 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK, 394 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK,
384 ~SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK); 395 ~SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK);
385 mdelay(5); 396 mdelay(5);
@@ -387,8 +398,10 @@ static int vce_v3_0_soft_reset(struct amdgpu_device *adev)
387 return vce_v3_0_start(adev); 398 return vce_v3_0_start(adev);
388} 399}
389 400
390static void vce_v3_0_print_status(struct amdgpu_device *adev) 401static void vce_v3_0_print_status(void *handle)
391{ 402{
403 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
404
392 dev_info(adev->dev, "VCE 3.0 registers\n"); 405 dev_info(adev->dev, "VCE 3.0 registers\n");
393 dev_info(adev->dev, " VCE_STATUS=0x%08X\n", 406 dev_info(adev->dev, " VCE_STATUS=0x%08X\n",
394 RREG32(mmVCE_STATUS)); 407 RREG32(mmVCE_STATUS));
@@ -487,15 +500,14 @@ static int vce_v3_0_process_interrupt(struct amdgpu_device *adev,
487 return 0; 500 return 0;
488} 501}
489 502
490static int vce_v3_0_set_clockgating_state(struct amdgpu_device *adev, 503static int vce_v3_0_set_clockgating_state(void *handle,
491 enum amdgpu_clockgating_state state) 504 enum amd_clockgating_state state)
492{ 505{
493 //TODO
494 return 0; 506 return 0;
495} 507}
496 508
497static int vce_v3_0_set_powergating_state(struct amdgpu_device *adev, 509static int vce_v3_0_set_powergating_state(void *handle,
498 enum amdgpu_powergating_state state) 510 enum amd_powergating_state state)
499{ 511{
500 /* This doesn't actually powergate the VCE block. 512 /* This doesn't actually powergate the VCE block.
501 * That's done in the dpm code via the SMC. This 513 * That's done in the dpm code via the SMC. This
@@ -504,14 +516,16 @@ static int vce_v3_0_set_powergating_state(struct amdgpu_device *adev,
504 * revisit this when there is a cleaner line between 516 * revisit this when there is a cleaner line between
505 * the smc and the hw blocks 517 * the smc and the hw blocks
506 */ 518 */
507 if (state == AMDGPU_PG_STATE_GATE) 519 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
520
521 if (state == AMD_PG_STATE_GATE)
508 /* XXX do we need a vce_v3_0_stop()? */ 522 /* XXX do we need a vce_v3_0_stop()? */
509 return 0; 523 return 0;
510 else 524 else
511 return vce_v3_0_start(adev); 525 return vce_v3_0_start(adev);
512} 526}
513 527
514const struct amdgpu_ip_funcs vce_v3_0_ip_funcs = { 528const struct amd_ip_funcs vce_v3_0_ip_funcs = {
515 .early_init = vce_v3_0_early_init, 529 .early_init = vce_v3_0_early_init,
516 .late_init = NULL, 530 .late_init = NULL,
517 .sw_init = vce_v3_0_sw_init, 531 .sw_init = vce_v3_0_sw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.h b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.h
index f3c2ba92a1f1..b45af65da81f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.h
@@ -24,6 +24,6 @@
24#ifndef __VCE_V3_0_H__ 24#ifndef __VCE_V3_0_H__
25#define __VCE_V3_0_H__ 25#define __VCE_V3_0_H__
26 26
27extern const struct amdgpu_ip_funcs vce_v3_0_ip_funcs; 27extern const struct amd_ip_funcs vce_v3_0_ip_funcs;
28 28
29#endif 29#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 59a073aa42a4..be7c17610696 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -994,42 +994,42 @@ static const struct amdgpu_ip_block_version topaz_ip_blocks[] =
994{ 994{
995 /* ORDER MATTERS! */ 995 /* ORDER MATTERS! */
996 { 996 {
997 .type = AMDGPU_IP_BLOCK_TYPE_COMMON, 997 .type = AMD_IP_BLOCK_TYPE_COMMON,
998 .major = 2, 998 .major = 2,
999 .minor = 0, 999 .minor = 0,
1000 .rev = 0, 1000 .rev = 0,
1001 .funcs = &vi_common_ip_funcs, 1001 .funcs = &vi_common_ip_funcs,
1002 }, 1002 },
1003 { 1003 {
1004 .type = AMDGPU_IP_BLOCK_TYPE_GMC, 1004 .type = AMD_IP_BLOCK_TYPE_GMC,
1005 .major = 8, 1005 .major = 8,
1006 .minor = 0, 1006 .minor = 0,
1007 .rev = 0, 1007 .rev = 0,
1008 .funcs = &gmc_v8_0_ip_funcs, 1008 .funcs = &gmc_v8_0_ip_funcs,
1009 }, 1009 },
1010 { 1010 {
1011 .type = AMDGPU_IP_BLOCK_TYPE_IH, 1011 .type = AMD_IP_BLOCK_TYPE_IH,
1012 .major = 2, 1012 .major = 2,
1013 .minor = 4, 1013 .minor = 4,
1014 .rev = 0, 1014 .rev = 0,
1015 .funcs = &iceland_ih_ip_funcs, 1015 .funcs = &iceland_ih_ip_funcs,
1016 }, 1016 },
1017 { 1017 {
1018 .type = AMDGPU_IP_BLOCK_TYPE_SMC, 1018 .type = AMD_IP_BLOCK_TYPE_SMC,
1019 .major = 7, 1019 .major = 7,
1020 .minor = 1, 1020 .minor = 1,
1021 .rev = 0, 1021 .rev = 0,
1022 .funcs = &iceland_dpm_ip_funcs, 1022 .funcs = &iceland_dpm_ip_funcs,
1023 }, 1023 },
1024 { 1024 {
1025 .type = AMDGPU_IP_BLOCK_TYPE_GFX, 1025 .type = AMD_IP_BLOCK_TYPE_GFX,
1026 .major = 8, 1026 .major = 8,
1027 .minor = 0, 1027 .minor = 0,
1028 .rev = 0, 1028 .rev = 0,
1029 .funcs = &gfx_v8_0_ip_funcs, 1029 .funcs = &gfx_v8_0_ip_funcs,
1030 }, 1030 },
1031 { 1031 {
1032 .type = AMDGPU_IP_BLOCK_TYPE_SDMA, 1032 .type = AMD_IP_BLOCK_TYPE_SDMA,
1033 .major = 2, 1033 .major = 2,
1034 .minor = 4, 1034 .minor = 4,
1035 .rev = 0, 1035 .rev = 0,
@@ -1041,63 +1041,63 @@ static const struct amdgpu_ip_block_version tonga_ip_blocks[] =
1041{ 1041{
1042 /* ORDER MATTERS! */ 1042 /* ORDER MATTERS! */
1043 { 1043 {
1044 .type = AMDGPU_IP_BLOCK_TYPE_COMMON, 1044 .type = AMD_IP_BLOCK_TYPE_COMMON,
1045 .major = 2, 1045 .major = 2,
1046 .minor = 0, 1046 .minor = 0,
1047 .rev = 0, 1047 .rev = 0,
1048 .funcs = &vi_common_ip_funcs, 1048 .funcs = &vi_common_ip_funcs,
1049 }, 1049 },
1050 { 1050 {
1051 .type = AMDGPU_IP_BLOCK_TYPE_GMC, 1051 .type = AMD_IP_BLOCK_TYPE_GMC,
1052 .major = 8, 1052 .major = 8,
1053 .minor = 0, 1053 .minor = 0,
1054 .rev = 0, 1054 .rev = 0,
1055 .funcs = &gmc_v8_0_ip_funcs, 1055 .funcs = &gmc_v8_0_ip_funcs,
1056 }, 1056 },
1057 { 1057 {
1058 .type = AMDGPU_IP_BLOCK_TYPE_IH, 1058 .type = AMD_IP_BLOCK_TYPE_IH,
1059 .major = 3, 1059 .major = 3,
1060 .minor = 0, 1060 .minor = 0,
1061 .rev = 0, 1061 .rev = 0,
1062 .funcs = &tonga_ih_ip_funcs, 1062 .funcs = &tonga_ih_ip_funcs,
1063 }, 1063 },
1064 { 1064 {
1065 .type = AMDGPU_IP_BLOCK_TYPE_SMC, 1065 .type = AMD_IP_BLOCK_TYPE_SMC,
1066 .major = 7, 1066 .major = 7,
1067 .minor = 1, 1067 .minor = 1,
1068 .rev = 0, 1068 .rev = 0,
1069 .funcs = &tonga_dpm_ip_funcs, 1069 .funcs = &tonga_dpm_ip_funcs,
1070 }, 1070 },
1071 { 1071 {
1072 .type = AMDGPU_IP_BLOCK_TYPE_DCE, 1072 .type = AMD_IP_BLOCK_TYPE_DCE,
1073 .major = 10, 1073 .major = 10,
1074 .minor = 0, 1074 .minor = 0,
1075 .rev = 0, 1075 .rev = 0,
1076 .funcs = &dce_v10_0_ip_funcs, 1076 .funcs = &dce_v10_0_ip_funcs,
1077 }, 1077 },
1078 { 1078 {
1079 .type = AMDGPU_IP_BLOCK_TYPE_GFX, 1079 .type = AMD_IP_BLOCK_TYPE_GFX,
1080 .major = 8, 1080 .major = 8,
1081 .minor = 0, 1081 .minor = 0,
1082 .rev = 0, 1082 .rev = 0,
1083 .funcs = &gfx_v8_0_ip_funcs, 1083 .funcs = &gfx_v8_0_ip_funcs,
1084 }, 1084 },
1085 { 1085 {
1086 .type = AMDGPU_IP_BLOCK_TYPE_SDMA, 1086 .type = AMD_IP_BLOCK_TYPE_SDMA,
1087 .major = 3, 1087 .major = 3,
1088 .minor = 0, 1088 .minor = 0,
1089 .rev = 0, 1089 .rev = 0,
1090 .funcs = &sdma_v3_0_ip_funcs, 1090 .funcs = &sdma_v3_0_ip_funcs,
1091 }, 1091 },
1092 { 1092 {
1093 .type = AMDGPU_IP_BLOCK_TYPE_UVD, 1093 .type = AMD_IP_BLOCK_TYPE_UVD,
1094 .major = 5, 1094 .major = 5,
1095 .minor = 0, 1095 .minor = 0,
1096 .rev = 0, 1096 .rev = 0,
1097 .funcs = &uvd_v5_0_ip_funcs, 1097 .funcs = &uvd_v5_0_ip_funcs,
1098 }, 1098 },
1099 { 1099 {
1100 .type = AMDGPU_IP_BLOCK_TYPE_VCE, 1100 .type = AMD_IP_BLOCK_TYPE_VCE,
1101 .major = 3, 1101 .major = 3,
1102 .minor = 0, 1102 .minor = 0,
1103 .rev = 0, 1103 .rev = 0,
@@ -1109,63 +1109,63 @@ static const struct amdgpu_ip_block_version cz_ip_blocks[] =
1109{ 1109{
1110 /* ORDER MATTERS! */ 1110 /* ORDER MATTERS! */
1111 { 1111 {
1112 .type = AMDGPU_IP_BLOCK_TYPE_COMMON, 1112 .type = AMD_IP_BLOCK_TYPE_COMMON,
1113 .major = 2, 1113 .major = 2,
1114 .minor = 0, 1114 .minor = 0,
1115 .rev = 0, 1115 .rev = 0,
1116 .funcs = &vi_common_ip_funcs, 1116 .funcs = &vi_common_ip_funcs,
1117 }, 1117 },
1118 { 1118 {
1119 .type = AMDGPU_IP_BLOCK_TYPE_GMC, 1119 .type = AMD_IP_BLOCK_TYPE_GMC,
1120 .major = 8, 1120 .major = 8,
1121 .minor = 0, 1121 .minor = 0,
1122 .rev = 0, 1122 .rev = 0,
1123 .funcs = &gmc_v8_0_ip_funcs, 1123 .funcs = &gmc_v8_0_ip_funcs,
1124 }, 1124 },
1125 { 1125 {
1126 .type = AMDGPU_IP_BLOCK_TYPE_IH, 1126 .type = AMD_IP_BLOCK_TYPE_IH,
1127 .major = 3, 1127 .major = 3,
1128 .minor = 0, 1128 .minor = 0,
1129 .rev = 0, 1129 .rev = 0,
1130 .funcs = &cz_ih_ip_funcs, 1130 .funcs = &cz_ih_ip_funcs,
1131 }, 1131 },
1132 { 1132 {
1133 .type = AMDGPU_IP_BLOCK_TYPE_SMC, 1133 .type = AMD_IP_BLOCK_TYPE_SMC,
1134 .major = 8, 1134 .major = 8,
1135 .minor = 0, 1135 .minor = 0,
1136 .rev = 0, 1136 .rev = 0,
1137 .funcs = &cz_dpm_ip_funcs, 1137 .funcs = &cz_dpm_ip_funcs,
1138 }, 1138 },
1139 { 1139 {
1140 .type = AMDGPU_IP_BLOCK_TYPE_DCE, 1140 .type = AMD_IP_BLOCK_TYPE_DCE,
1141 .major = 11, 1141 .major = 11,
1142 .minor = 0, 1142 .minor = 0,
1143 .rev = 0, 1143 .rev = 0,
1144 .funcs = &dce_v11_0_ip_funcs, 1144 .funcs = &dce_v11_0_ip_funcs,
1145 }, 1145 },
1146 { 1146 {
1147 .type = AMDGPU_IP_BLOCK_TYPE_GFX, 1147 .type = AMD_IP_BLOCK_TYPE_GFX,
1148 .major = 8, 1148 .major = 8,
1149 .minor = 0, 1149 .minor = 0,
1150 .rev = 0, 1150 .rev = 0,
1151 .funcs = &gfx_v8_0_ip_funcs, 1151 .funcs = &gfx_v8_0_ip_funcs,
1152 }, 1152 },
1153 { 1153 {
1154 .type = AMDGPU_IP_BLOCK_TYPE_SDMA, 1154 .type = AMD_IP_BLOCK_TYPE_SDMA,
1155 .major = 3, 1155 .major = 3,
1156 .minor = 0, 1156 .minor = 0,
1157 .rev = 0, 1157 .rev = 0,
1158 .funcs = &sdma_v3_0_ip_funcs, 1158 .funcs = &sdma_v3_0_ip_funcs,
1159 }, 1159 },
1160 { 1160 {
1161 .type = AMDGPU_IP_BLOCK_TYPE_UVD, 1161 .type = AMD_IP_BLOCK_TYPE_UVD,
1162 .major = 6, 1162 .major = 6,
1163 .minor = 0, 1163 .minor = 0,
1164 .rev = 0, 1164 .rev = 0,
1165 .funcs = &uvd_v6_0_ip_funcs, 1165 .funcs = &uvd_v6_0_ip_funcs,
1166 }, 1166 },
1167 { 1167 {
1168 .type = AMDGPU_IP_BLOCK_TYPE_VCE, 1168 .type = AMD_IP_BLOCK_TYPE_VCE,
1169 .major = 3, 1169 .major = 3,
1170 .minor = 0, 1170 .minor = 0,
1171 .rev = 0, 1171 .rev = 0,
@@ -1225,9 +1225,10 @@ static const struct amdgpu_asic_funcs vi_asic_funcs =
1225 .wait_for_mc_idle = &gmc_v8_0_mc_wait_for_idle, 1225 .wait_for_mc_idle = &gmc_v8_0_mc_wait_for_idle,
1226}; 1226};
1227 1227
1228static int vi_common_early_init(struct amdgpu_device *adev) 1228static int vi_common_early_init(void *handle)
1229{ 1229{
1230 bool smc_enabled = false; 1230 bool smc_enabled = false;
1231 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1231 1232
1232 adev->smc_rreg = &vi_smc_rreg; 1233 adev->smc_rreg = &vi_smc_rreg;
1233 adev->smc_wreg = &vi_smc_wreg; 1234 adev->smc_wreg = &vi_smc_wreg;
@@ -1240,8 +1241,8 @@ static int vi_common_early_init(struct amdgpu_device *adev)
1240 1241
1241 adev->asic_funcs = &vi_asic_funcs; 1242 adev->asic_funcs = &vi_asic_funcs;
1242 1243
1243 if (amdgpu_get_ip_block(adev, AMDGPU_IP_BLOCK_TYPE_SMC) && 1244 if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) &&
1244 (amdgpu_ip_block_mask & (1 << AMDGPU_IP_BLOCK_TYPE_SMC))) 1245 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC)))
1245 smc_enabled = true; 1246 smc_enabled = true;
1246 1247
1247 adev->rev_id = vi_get_rev_id(adev); 1248 adev->rev_id = vi_get_rev_id(adev);
@@ -1279,18 +1280,20 @@ static int vi_common_early_init(struct amdgpu_device *adev)
1279 return 0; 1280 return 0;
1280} 1281}
1281 1282
1282static int vi_common_sw_init(struct amdgpu_device *adev) 1283static int vi_common_sw_init(void *handle)
1283{ 1284{
1284 return 0; 1285 return 0;
1285} 1286}
1286 1287
1287static int vi_common_sw_fini(struct amdgpu_device *adev) 1288static int vi_common_sw_fini(void *handle)
1288{ 1289{
1289 return 0; 1290 return 0;
1290} 1291}
1291 1292
1292static int vi_common_hw_init(struct amdgpu_device *adev) 1293static int vi_common_hw_init(void *handle)
1293{ 1294{
1295 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1296
1294 /* move the golden regs per IP block */ 1297 /* move the golden regs per IP block */
1295 vi_init_golden_registers(adev); 1298 vi_init_golden_registers(adev);
1296 /* enable pcie gen2/3 link */ 1299 /* enable pcie gen2/3 link */
@@ -1303,58 +1306,63 @@ static int vi_common_hw_init(struct amdgpu_device *adev)
1303 return 0; 1306 return 0;
1304} 1307}
1305 1308
1306static int vi_common_hw_fini(struct amdgpu_device *adev) 1309static int vi_common_hw_fini(void *handle)
1307{ 1310{
1311 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1312
1308 /* enable the doorbell aperture */ 1313 /* enable the doorbell aperture */
1309 vi_enable_doorbell_aperture(adev, false); 1314 vi_enable_doorbell_aperture(adev, false);
1310 1315
1311 return 0; 1316 return 0;
1312} 1317}
1313 1318
1314static int vi_common_suspend(struct amdgpu_device *adev) 1319static int vi_common_suspend(void *handle)
1315{ 1320{
1321 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1322
1316 return vi_common_hw_fini(adev); 1323 return vi_common_hw_fini(adev);
1317} 1324}
1318 1325
1319static int vi_common_resume(struct amdgpu_device *adev) 1326static int vi_common_resume(void *handle)
1320{ 1327{
1328 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1329
1321 return vi_common_hw_init(adev); 1330 return vi_common_hw_init(adev);
1322} 1331}
1323 1332
1324static bool vi_common_is_idle(struct amdgpu_device *adev) 1333static bool vi_common_is_idle(void *handle)
1325{ 1334{
1326 return true; 1335 return true;
1327} 1336}
1328 1337
1329static int vi_common_wait_for_idle(struct amdgpu_device *adev) 1338static int vi_common_wait_for_idle(void *handle)
1330{ 1339{
1331 return 0; 1340 return 0;
1332} 1341}
1333 1342
1334static void vi_common_print_status(struct amdgpu_device *adev) 1343static void vi_common_print_status(void *handle)
1335{ 1344{
1336 1345 return;
1337} 1346}
1338 1347
1339static int vi_common_soft_reset(struct amdgpu_device *adev) 1348static int vi_common_soft_reset(void *handle)
1340{ 1349{
1341 /* XXX hard reset?? */
1342 return 0; 1350 return 0;
1343} 1351}
1344 1352
1345static int vi_common_set_clockgating_state(struct amdgpu_device *adev, 1353static int vi_common_set_clockgating_state(void *handle,
1346 enum amdgpu_clockgating_state state) 1354 enum amd_clockgating_state state)
1347{ 1355{
1348 return 0; 1356 return 0;
1349} 1357}
1350 1358
1351static int vi_common_set_powergating_state(struct amdgpu_device *adev, 1359static int vi_common_set_powergating_state(void *handle,
1352 enum amdgpu_powergating_state state) 1360 enum amd_powergating_state state)
1353{ 1361{
1354 return 0; 1362 return 0;
1355} 1363}
1356 1364
1357const struct amdgpu_ip_funcs vi_common_ip_funcs = { 1365const struct amd_ip_funcs vi_common_ip_funcs = {
1358 .early_init = vi_common_early_init, 1366 .early_init = vi_common_early_init,
1359 .late_init = NULL, 1367 .late_init = NULL,
1360 .sw_init = vi_common_sw_init, 1368 .sw_init = vi_common_sw_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.h b/drivers/gpu/drm/amd/amdgpu/vi.h
index d16a5f7e4edd..502094042462 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.h
+++ b/drivers/gpu/drm/amd/amdgpu/vi.h
@@ -24,7 +24,7 @@
24#ifndef __VI_H__ 24#ifndef __VI_H__
25#define __VI_H__ 25#define __VI_H__
26 26
27extern const struct amdgpu_ip_funcs vi_common_ip_funcs; 27extern const struct amd_ip_funcs vi_common_ip_funcs;
28 28
29void vi_srbm_select(struct amdgpu_device *adev, 29void vi_srbm_select(struct amdgpu_device *adev,
30 u32 me, u32 pipe, u32 queue, u32 vmid); 30 u32 me, u32 pipe, u32 queue, u32 vmid);
diff --git a/drivers/gpu/drm/amd/amdgpu/vi_dpm.h b/drivers/gpu/drm/amd/amdgpu/vi_dpm.h
index 11cb1f7eeba5..3b45332f5df4 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/vi_dpm.h
@@ -24,13 +24,13 @@
24#ifndef __VI_DPM_H__ 24#ifndef __VI_DPM_H__
25#define __VI_DPM_H__ 25#define __VI_DPM_H__
26 26
27extern const struct amdgpu_ip_funcs cz_dpm_ip_funcs; 27extern const struct amd_ip_funcs cz_dpm_ip_funcs;
28int cz_smu_init(struct amdgpu_device *adev); 28int cz_smu_init(struct amdgpu_device *adev);
29int cz_smu_start(struct amdgpu_device *adev); 29int cz_smu_start(struct amdgpu_device *adev);
30int cz_smu_fini(struct amdgpu_device *adev); 30int cz_smu_fini(struct amdgpu_device *adev);
31 31
32extern const struct amdgpu_ip_funcs tonga_dpm_ip_funcs; 32extern const struct amd_ip_funcs tonga_dpm_ip_funcs;
33 33
34extern const struct amdgpu_ip_funcs iceland_dpm_ip_funcs; 34extern const struct amd_ip_funcs iceland_dpm_ip_funcs;
35 35
36#endif 36#endif
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
new file mode 100644
index 000000000000..5bdf1b4397a0
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -0,0 +1,81 @@
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __AMD_SHARED_H__
24#define __AMD_SHARED_H__
25
26enum amd_ip_block_type {
27 AMD_IP_BLOCK_TYPE_COMMON,
28 AMD_IP_BLOCK_TYPE_GMC,
29 AMD_IP_BLOCK_TYPE_IH,
30 AMD_IP_BLOCK_TYPE_SMC,
31 AMD_IP_BLOCK_TYPE_DCE,
32 AMD_IP_BLOCK_TYPE_GFX,
33 AMD_IP_BLOCK_TYPE_SDMA,
34 AMD_IP_BLOCK_TYPE_UVD,
35 AMD_IP_BLOCK_TYPE_VCE,
36};
37
38enum amd_clockgating_state {
39 AMD_CG_STATE_GATE = 0,
40 AMD_CG_STATE_UNGATE,
41};
42
43enum amd_powergating_state {
44 AMD_PG_STATE_GATE = 0,
45 AMD_PG_STATE_UNGATE,
46};
47
48struct amd_ip_funcs {
49 /* sets up early driver state (pre sw_init), does not configure hw - Optional */
50 int (*early_init)(void *handle);
51 /* sets up late driver/hw state (post hw_init) - Optional */
52 int (*late_init)(void *handle);
53 /* sets up driver state, does not configure hw */
54 int (*sw_init)(void *handle);
55 /* tears down driver state, does not configure hw */
56 int (*sw_fini)(void *handle);
57 /* sets up the hw state */
58 int (*hw_init)(void *handle);
59 /* tears down the hw state */
60 int (*hw_fini)(void *handle);
61 /* handles IP specific hw/sw changes for suspend */
62 int (*suspend)(void *handle);
63 /* handles IP specific hw/sw changes for resume */
64 int (*resume)(void *handle);
65 /* returns current IP block idle status */
66 bool (*is_idle)(void *handle);
67 /* poll for idle */
68 int (*wait_for_idle)(void *handle);
69 /* soft reset the IP block */
70 int (*soft_reset)(void *handle);
71 /* dump the IP block status registers */
72 void (*print_status)(void *handle);
73 /* enable/disable cg for the IP block */
74 int (*set_clockgating_state)(void *handle,
75 enum amd_clockgating_state state);
76 /* enable/disable pg for the IP block */
77 int (*set_powergating_state)(void *handle,
78 enum amd_powergating_state state);
79};
80
81#endif /* __AMD_SHARED_H__ */
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