diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2016-10-03 21:09:13 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2016-10-03 21:09:13 -0400 |
commit | 5e1b834b27fb2c27cde33a0752425f11d10c0b2d (patch) | |
tree | 055c2c7165dcf0ccd73a273b16ad493ff48823a6 | |
parent | 49deffe0b0e4c2030696c7a6fd680bacf4761069 (diff) | |
parent | b536fd587044af02183b3c02690431b93154f0fa (diff) |
Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull timer updates from Thomas Gleixner:
"A rather smalish set of updates for timers and timekeeping:
- Two core fixes to prevent potential undefinded behaviour about
which gcc is complaining rightfully.
- A fix to prevent stopping the tick on an (soon) offline CPU so it
can complete the shutdown procedure.
- Wait for clocks to stabilize before making decisions, so a not yet
validated clock is not rejected.
- The usual pile of fixes to the various clocksource drivers.
- Core code typo and include fixlets"
* 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
timekeeping: Include the correct header for errno definitions
clocksource/drivers/ti-32k: Prevent ftrace recursion
clocksource/mips-gic-timer: Stop checking cpu_has_counter
clocksource/mips-gic-timer: Print an error if IRQ setup fails
tick/nohz: Prevent stopping the tick on an offline CPU
clocksource/drivers/oxnas: Add OX820 compatible
clocksource/drivers/timer-atmel-pit: Simplify IRQ handler
clocksource/drivers/timer-atmel-pit: Remove uselesss WARN_ON_ONCE
clocksource/drivers/timer-atmel-pit: Drop at91sam926x_pit_common_init
clocksource/drivers/moxart: Replace panic by pr_err
clocksource/drivers/moxart: Replace setup_irq by request_irq
clocksource/drivers/moxart: Add Aspeed support
clocksource/drivers/moxart: Use struct to hold state
clocksource/drivers/moxart: Refactor enable/disable
time: Avoid undefined behaviour in ktime_add_safe()
time: Avoid undefined behaviour in timespec64_add_safe()
timekeeping: Prints the amounts of time spent during suspend
clocksource: Defer override invalidation unless clock is unstable
hrtimer: Spelling fixes
-rw-r--r-- | Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt | 4 | ||||
-rw-r--r-- | Documentation/devicetree/bindings/timer/oxsemi,rps-timer.txt | 2 | ||||
-rw-r--r-- | drivers/clocksource/mips-gic-timer.c | 7 | ||||
-rw-r--r-- | drivers/clocksource/moxart_timer.c | 193 | ||||
-rw-r--r-- | drivers/clocksource/timer-atmel-pit.c | 96 | ||||
-rw-r--r-- | drivers/clocksource/timer-oxnas-rps.c | 2 | ||||
-rw-r--r-- | drivers/clocksource/timer-ti-32k.c | 2 | ||||
-rw-r--r-- | include/linux/ktime.h | 7 | ||||
-rw-r--r-- | include/linux/time64.h | 1 | ||||
-rw-r--r-- | include/linux/timekeeping.h | 2 | ||||
-rw-r--r-- | kernel/time/clocksource.c | 15 | ||||
-rw-r--r-- | kernel/time/hrtimer.c | 6 | ||||
-rw-r--r-- | kernel/time/tick-sched.c | 7 | ||||
-rw-r--r-- | kernel/time/time.c | 2 | ||||
-rw-r--r-- | kernel/time/timekeeping_debug.c | 2 |
15 files changed, 210 insertions, 138 deletions
diff --git a/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt index da2d510cae47..e207c11630af 100644 --- a/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt +++ b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt | |||
@@ -2,7 +2,9 @@ MOXA ART timer | |||
2 | 2 | ||
3 | Required properties: | 3 | Required properties: |
4 | 4 | ||
5 | - compatible : Must be "moxa,moxart-timer" | 5 | - compatible : Must be one of: |
6 | - "moxa,moxart-timer" | ||
7 | - "aspeed,ast2400-timer" | ||
6 | - reg : Should contain registers location and length | 8 | - reg : Should contain registers location and length |
7 | - interrupts : Should contain the timer interrupt number | 9 | - interrupts : Should contain the timer interrupt number |
8 | - clocks : Should contain phandle for the clock that drives the counter | 10 | - clocks : Should contain phandle for the clock that drives the counter |
diff --git a/Documentation/devicetree/bindings/timer/oxsemi,rps-timer.txt b/Documentation/devicetree/bindings/timer/oxsemi,rps-timer.txt index 3ca89cd1caef..d191612539e8 100644 --- a/Documentation/devicetree/bindings/timer/oxsemi,rps-timer.txt +++ b/Documentation/devicetree/bindings/timer/oxsemi,rps-timer.txt | |||
@@ -2,7 +2,7 @@ Oxford Semiconductor OXNAS SoCs Family RPS Timer | |||
2 | ================================================ | 2 | ================================================ |
3 | 3 | ||
4 | Required properties: | 4 | Required properties: |
5 | - compatible: Should be "oxsemi,ox810se-rps-timer" | 5 | - compatible: Should be "oxsemi,ox810se-rps-timer" or "oxsemi,ox820-rps-timer" |
6 | - reg : Specifies base physical address and size of the registers. | 6 | - reg : Specifies base physical address and size of the registers. |
7 | - interrupts : The interrupts of the two timers | 7 | - interrupts : The interrupts of the two timers |
8 | - clocks : The phandle of the timer clock source | 8 | - clocks : The phandle of the timer clock source |
diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c index b4b3ab5a11ad..7a960cd01104 100644 --- a/drivers/clocksource/mips-gic-timer.c +++ b/drivers/clocksource/mips-gic-timer.c | |||
@@ -109,12 +109,15 @@ static int gic_clockevent_init(void) | |||
109 | { | 109 | { |
110 | int ret; | 110 | int ret; |
111 | 111 | ||
112 | if (!cpu_has_counter || !gic_frequency) | 112 | if (!gic_frequency) |
113 | return -ENXIO; | 113 | return -ENXIO; |
114 | 114 | ||
115 | ret = setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction); | 115 | ret = setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction); |
116 | if (ret < 0) | 116 | if (ret < 0) { |
117 | pr_err("GIC timer IRQ %d setup failed: %d\n", | ||
118 | gic_timer_irq, ret); | ||
117 | return ret; | 119 | return ret; |
120 | } | ||
118 | 121 | ||
119 | cpuhp_setup_state(CPUHP_AP_MIPS_GIC_TIMER_STARTING, | 122 | cpuhp_setup_state(CPUHP_AP_MIPS_GIC_TIMER_STARTING, |
120 | "AP_MIPS_GIC_TIMER_STARTING", gic_starting_cpu, | 123 | "AP_MIPS_GIC_TIMER_STARTING", gic_starting_cpu, |
diff --git a/drivers/clocksource/moxart_timer.c b/drivers/clocksource/moxart_timer.c index 841454417acd..2a8f4705c734 100644 --- a/drivers/clocksource/moxart_timer.c +++ b/drivers/clocksource/moxart_timer.c | |||
@@ -21,6 +21,7 @@ | |||
21 | #include <linux/io.h> | 21 | #include <linux/io.h> |
22 | #include <linux/clocksource.h> | 22 | #include <linux/clocksource.h> |
23 | #include <linux/bitops.h> | 23 | #include <linux/bitops.h> |
24 | #include <linux/slab.h> | ||
24 | 25 | ||
25 | #define TIMER1_BASE 0x00 | 26 | #define TIMER1_BASE 0x00 |
26 | #define TIMER2_BASE 0x10 | 27 | #define TIMER2_BASE 0x10 |
@@ -36,75 +37,109 @@ | |||
36 | #define TIMER_INTR_MASK 0x38 | 37 | #define TIMER_INTR_MASK 0x38 |
37 | 38 | ||
38 | /* | 39 | /* |
39 | * TIMER_CR flags: | 40 | * Moxart TIMER_CR flags: |
40 | * | 41 | * |
41 | * TIMEREG_CR_*_CLOCK 0: PCLK, 1: EXT1CLK | 42 | * MOXART_CR_*_CLOCK 0: PCLK, 1: EXT1CLK |
42 | * TIMEREG_CR_*_INT overflow interrupt enable bit | 43 | * MOXART_CR_*_INT overflow interrupt enable bit |
43 | */ | 44 | */ |
44 | #define TIMEREG_CR_1_ENABLE BIT(0) | 45 | #define MOXART_CR_1_ENABLE BIT(0) |
45 | #define TIMEREG_CR_1_CLOCK BIT(1) | 46 | #define MOXART_CR_1_CLOCK BIT(1) |
46 | #define TIMEREG_CR_1_INT BIT(2) | 47 | #define MOXART_CR_1_INT BIT(2) |
47 | #define TIMEREG_CR_2_ENABLE BIT(3) | 48 | #define MOXART_CR_2_ENABLE BIT(3) |
48 | #define TIMEREG_CR_2_CLOCK BIT(4) | 49 | #define MOXART_CR_2_CLOCK BIT(4) |
49 | #define TIMEREG_CR_2_INT BIT(5) | 50 | #define MOXART_CR_2_INT BIT(5) |
50 | #define TIMEREG_CR_3_ENABLE BIT(6) | 51 | #define MOXART_CR_3_ENABLE BIT(6) |
51 | #define TIMEREG_CR_3_CLOCK BIT(7) | 52 | #define MOXART_CR_3_CLOCK BIT(7) |
52 | #define TIMEREG_CR_3_INT BIT(8) | 53 | #define MOXART_CR_3_INT BIT(8) |
53 | #define TIMEREG_CR_COUNT_UP BIT(9) | 54 | #define MOXART_CR_COUNT_UP BIT(9) |
54 | 55 | ||
55 | #define TIMER1_ENABLE (TIMEREG_CR_2_ENABLE | TIMEREG_CR_1_ENABLE) | 56 | #define MOXART_TIMER1_ENABLE (MOXART_CR_2_ENABLE | MOXART_CR_1_ENABLE) |
56 | #define TIMER1_DISABLE (TIMEREG_CR_2_ENABLE) | 57 | #define MOXART_TIMER1_DISABLE (MOXART_CR_2_ENABLE) |
57 | 58 | ||
58 | static void __iomem *base; | 59 | /* |
59 | static unsigned int clock_count_per_tick; | 60 | * The ASpeed variant of the IP block has a different layout |
61 | * for the control register | ||
62 | */ | ||
63 | #define ASPEED_CR_1_ENABLE BIT(0) | ||
64 | #define ASPEED_CR_1_CLOCK BIT(1) | ||
65 | #define ASPEED_CR_1_INT BIT(2) | ||
66 | #define ASPEED_CR_2_ENABLE BIT(4) | ||
67 | #define ASPEED_CR_2_CLOCK BIT(5) | ||
68 | #define ASPEED_CR_2_INT BIT(6) | ||
69 | #define ASPEED_CR_3_ENABLE BIT(8) | ||
70 | #define ASPEED_CR_3_CLOCK BIT(9) | ||
71 | #define ASPEED_CR_3_INT BIT(10) | ||
72 | |||
73 | #define ASPEED_TIMER1_ENABLE (ASPEED_CR_2_ENABLE | ASPEED_CR_1_ENABLE) | ||
74 | #define ASPEED_TIMER1_DISABLE (ASPEED_CR_2_ENABLE) | ||
75 | |||
76 | struct moxart_timer { | ||
77 | void __iomem *base; | ||
78 | unsigned int t1_disable_val; | ||
79 | unsigned int t1_enable_val; | ||
80 | unsigned int count_per_tick; | ||
81 | struct clock_event_device clkevt; | ||
82 | }; | ||
83 | |||
84 | static inline struct moxart_timer *to_moxart(struct clock_event_device *evt) | ||
85 | { | ||
86 | return container_of(evt, struct moxart_timer, clkevt); | ||
87 | } | ||
88 | |||
89 | static inline void moxart_disable(struct clock_event_device *evt) | ||
90 | { | ||
91 | struct moxart_timer *timer = to_moxart(evt); | ||
92 | |||
93 | writel(timer->t1_disable_val, timer->base + TIMER_CR); | ||
94 | } | ||
95 | |||
96 | static inline void moxart_enable(struct clock_event_device *evt) | ||
97 | { | ||
98 | struct moxart_timer *timer = to_moxart(evt); | ||
99 | |||
100 | writel(timer->t1_enable_val, timer->base + TIMER_CR); | ||
101 | } | ||
60 | 102 | ||
61 | static int moxart_shutdown(struct clock_event_device *evt) | 103 | static int moxart_shutdown(struct clock_event_device *evt) |
62 | { | 104 | { |
63 | writel(TIMER1_DISABLE, base + TIMER_CR); | 105 | moxart_disable(evt); |
64 | return 0; | 106 | return 0; |
65 | } | 107 | } |
66 | 108 | ||
67 | static int moxart_set_oneshot(struct clock_event_device *evt) | 109 | static int moxart_set_oneshot(struct clock_event_device *evt) |
68 | { | 110 | { |
69 | writel(TIMER1_DISABLE, base + TIMER_CR); | 111 | moxart_disable(evt); |
70 | writel(~0, base + TIMER1_BASE + REG_LOAD); | 112 | writel(~0, to_moxart(evt)->base + TIMER1_BASE + REG_LOAD); |
71 | return 0; | 113 | return 0; |
72 | } | 114 | } |
73 | 115 | ||
74 | static int moxart_set_periodic(struct clock_event_device *evt) | 116 | static int moxart_set_periodic(struct clock_event_device *evt) |
75 | { | 117 | { |
76 | writel(clock_count_per_tick, base + TIMER1_BASE + REG_LOAD); | 118 | struct moxart_timer *timer = to_moxart(evt); |
77 | writel(TIMER1_ENABLE, base + TIMER_CR); | 119 | |
120 | moxart_disable(evt); | ||
121 | writel(timer->count_per_tick, timer->base + TIMER1_BASE + REG_LOAD); | ||
122 | writel(0, timer->base + TIMER1_BASE + REG_MATCH1); | ||
123 | moxart_enable(evt); | ||
78 | return 0; | 124 | return 0; |
79 | } | 125 | } |
80 | 126 | ||
81 | static int moxart_clkevt_next_event(unsigned long cycles, | 127 | static int moxart_clkevt_next_event(unsigned long cycles, |
82 | struct clock_event_device *unused) | 128 | struct clock_event_device *evt) |
83 | { | 129 | { |
130 | struct moxart_timer *timer = to_moxart(evt); | ||
84 | u32 u; | 131 | u32 u; |
85 | 132 | ||
86 | writel(TIMER1_DISABLE, base + TIMER_CR); | 133 | moxart_disable(evt); |
87 | 134 | ||
88 | u = readl(base + TIMER1_BASE + REG_COUNT) - cycles; | 135 | u = readl(timer->base + TIMER1_BASE + REG_COUNT) - cycles; |
89 | writel(u, base + TIMER1_BASE + REG_MATCH1); | 136 | writel(u, timer->base + TIMER1_BASE + REG_MATCH1); |
90 | 137 | ||
91 | writel(TIMER1_ENABLE, base + TIMER_CR); | 138 | moxart_enable(evt); |
92 | 139 | ||
93 | return 0; | 140 | return 0; |
94 | } | 141 | } |
95 | 142 | ||
96 | static struct clock_event_device moxart_clockevent = { | ||
97 | .name = "moxart_timer", | ||
98 | .rating = 200, | ||
99 | .features = CLOCK_EVT_FEAT_PERIODIC | | ||
100 | CLOCK_EVT_FEAT_ONESHOT, | ||
101 | .set_state_shutdown = moxart_shutdown, | ||
102 | .set_state_periodic = moxart_set_periodic, | ||
103 | .set_state_oneshot = moxart_set_oneshot, | ||
104 | .tick_resume = moxart_set_oneshot, | ||
105 | .set_next_event = moxart_clkevt_next_event, | ||
106 | }; | ||
107 | |||
108 | static irqreturn_t moxart_timer_interrupt(int irq, void *dev_id) | 143 | static irqreturn_t moxart_timer_interrupt(int irq, void *dev_id) |
109 | { | 144 | { |
110 | struct clock_event_device *evt = dev_id; | 145 | struct clock_event_device *evt = dev_id; |
@@ -112,21 +147,19 @@ static irqreturn_t moxart_timer_interrupt(int irq, void *dev_id) | |||
112 | return IRQ_HANDLED; | 147 | return IRQ_HANDLED; |
113 | } | 148 | } |
114 | 149 | ||
115 | static struct irqaction moxart_timer_irq = { | ||
116 | .name = "moxart-timer", | ||
117 | .flags = IRQF_TIMER, | ||
118 | .handler = moxart_timer_interrupt, | ||
119 | .dev_id = &moxart_clockevent, | ||
120 | }; | ||
121 | |||
122 | static int __init moxart_timer_init(struct device_node *node) | 150 | static int __init moxart_timer_init(struct device_node *node) |
123 | { | 151 | { |
124 | int ret, irq; | 152 | int ret, irq; |
125 | unsigned long pclk; | 153 | unsigned long pclk; |
126 | struct clk *clk; | 154 | struct clk *clk; |
155 | struct moxart_timer *timer; | ||
156 | |||
157 | timer = kzalloc(sizeof(*timer), GFP_KERNEL); | ||
158 | if (!timer) | ||
159 | return -ENOMEM; | ||
127 | 160 | ||
128 | base = of_iomap(node, 0); | 161 | timer->base = of_iomap(node, 0); |
129 | if (!base) { | 162 | if (!timer->base) { |
130 | pr_err("%s: of_iomap failed\n", node->full_name); | 163 | pr_err("%s: of_iomap failed\n", node->full_name); |
131 | return -ENXIO; | 164 | return -ENXIO; |
132 | } | 165 | } |
@@ -137,12 +170,6 @@ static int __init moxart_timer_init(struct device_node *node) | |||
137 | return -EINVAL; | 170 | return -EINVAL; |
138 | } | 171 | } |
139 | 172 | ||
140 | ret = setup_irq(irq, &moxart_timer_irq); | ||
141 | if (ret) { | ||
142 | pr_err("%s: setup_irq failed\n", node->full_name); | ||
143 | return ret; | ||
144 | } | ||
145 | |||
146 | clk = of_clk_get(node, 0); | 173 | clk = of_clk_get(node, 0); |
147 | if (IS_ERR(clk)) { | 174 | if (IS_ERR(clk)) { |
148 | pr_err("%s: of_clk_get failed\n", node->full_name); | 175 | pr_err("%s: of_clk_get failed\n", node->full_name); |
@@ -151,7 +178,32 @@ static int __init moxart_timer_init(struct device_node *node) | |||
151 | 178 | ||
152 | pclk = clk_get_rate(clk); | 179 | pclk = clk_get_rate(clk); |
153 | 180 | ||
154 | ret = clocksource_mmio_init(base + TIMER2_BASE + REG_COUNT, | 181 | if (of_device_is_compatible(node, "moxa,moxart-timer")) { |
182 | timer->t1_enable_val = MOXART_TIMER1_ENABLE; | ||
183 | timer->t1_disable_val = MOXART_TIMER1_DISABLE; | ||
184 | } else if (of_device_is_compatible(node, "aspeed,ast2400-timer")) { | ||
185 | timer->t1_enable_val = ASPEED_TIMER1_ENABLE; | ||
186 | timer->t1_disable_val = ASPEED_TIMER1_DISABLE; | ||
187 | } else { | ||
188 | pr_err("%s: unknown platform\n", node->full_name); | ||
189 | return -EINVAL; | ||
190 | } | ||
191 | |||
192 | timer->count_per_tick = DIV_ROUND_CLOSEST(pclk, HZ); | ||
193 | |||
194 | timer->clkevt.name = node->name; | ||
195 | timer->clkevt.rating = 200; | ||
196 | timer->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | | ||
197 | CLOCK_EVT_FEAT_ONESHOT; | ||
198 | timer->clkevt.set_state_shutdown = moxart_shutdown; | ||
199 | timer->clkevt.set_state_periodic = moxart_set_periodic; | ||
200 | timer->clkevt.set_state_oneshot = moxart_set_oneshot; | ||
201 | timer->clkevt.tick_resume = moxart_set_oneshot; | ||
202 | timer->clkevt.set_next_event = moxart_clkevt_next_event; | ||
203 | timer->clkevt.cpumask = cpumask_of(0); | ||
204 | timer->clkevt.irq = irq; | ||
205 | |||
206 | ret = clocksource_mmio_init(timer->base + TIMER2_BASE + REG_COUNT, | ||
155 | "moxart_timer", pclk, 200, 32, | 207 | "moxart_timer", pclk, 200, 32, |
156 | clocksource_mmio_readl_down); | 208 | clocksource_mmio_readl_down); |
157 | if (ret) { | 209 | if (ret) { |
@@ -159,13 +211,26 @@ static int __init moxart_timer_init(struct device_node *node) | |||
159 | return ret; | 211 | return ret; |
160 | } | 212 | } |
161 | 213 | ||
162 | clock_count_per_tick = DIV_ROUND_CLOSEST(pclk, HZ); | 214 | ret = request_irq(irq, moxart_timer_interrupt, IRQF_TIMER, |
215 | node->name, &timer->clkevt); | ||
216 | if (ret) { | ||
217 | pr_err("%s: setup_irq failed\n", node->full_name); | ||
218 | return ret; | ||
219 | } | ||
163 | 220 | ||
164 | writel(~0, base + TIMER2_BASE + REG_LOAD); | 221 | /* Clear match registers */ |
165 | writel(TIMEREG_CR_2_ENABLE, base + TIMER_CR); | 222 | writel(0, timer->base + TIMER1_BASE + REG_MATCH1); |
223 | writel(0, timer->base + TIMER1_BASE + REG_MATCH2); | ||
224 | writel(0, timer->base + TIMER2_BASE + REG_MATCH1); | ||
225 | writel(0, timer->base + TIMER2_BASE + REG_MATCH2); | ||
166 | 226 | ||
167 | moxart_clockevent.cpumask = cpumask_of(0); | 227 | /* |
168 | moxart_clockevent.irq = irq; | 228 | * Start timer 2 rolling as our main wall clock source, keep timer 1 |
229 | * disabled | ||
230 | */ | ||
231 | writel(0, timer->base + TIMER_CR); | ||
232 | writel(~0, timer->base + TIMER2_BASE + REG_LOAD); | ||
233 | writel(timer->t1_disable_val, timer->base + TIMER_CR); | ||
169 | 234 | ||
170 | /* | 235 | /* |
171 | * documentation is not publicly available: | 236 | * documentation is not publicly available: |
@@ -173,9 +238,9 @@ static int __init moxart_timer_init(struct device_node *node) | |||
173 | * max_delta 0xfffffffe should be ok because count | 238 | * max_delta 0xfffffffe should be ok because count |
174 | * register size is u32 | 239 | * register size is u32 |
175 | */ | 240 | */ |
176 | clockevents_config_and_register(&moxart_clockevent, pclk, | 241 | clockevents_config_and_register(&timer->clkevt, pclk, 0x4, 0xfffffffe); |
177 | 0x4, 0xfffffffe); | ||
178 | 242 | ||
179 | return 0; | 243 | return 0; |
180 | } | 244 | } |
181 | CLOCKSOURCE_OF_DECLARE(moxart, "moxa,moxart-timer", moxart_timer_init); | 245 | CLOCKSOURCE_OF_DECLARE(moxart, "moxa,moxart-timer", moxart_timer_init); |
246 | CLOCKSOURCE_OF_DECLARE(aspeed, "aspeed,ast2400-timer", moxart_timer_init); | ||
diff --git a/drivers/clocksource/timer-atmel-pit.c b/drivers/clocksource/timer-atmel-pit.c index 7f0f5b26d8c5..6555821bbdae 100644 --- a/drivers/clocksource/timer-atmel-pit.c +++ b/drivers/clocksource/timer-atmel-pit.c | |||
@@ -149,24 +149,13 @@ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id) | |||
149 | { | 149 | { |
150 | struct pit_data *data = dev_id; | 150 | struct pit_data *data = dev_id; |
151 | 151 | ||
152 | /* | ||
153 | * irqs should be disabled here, but as the irq is shared they are only | ||
154 | * guaranteed to be off if the timer irq is registered first. | ||
155 | */ | ||
156 | WARN_ON_ONCE(!irqs_disabled()); | ||
157 | |||
158 | /* The PIT interrupt may be disabled, and is shared */ | 152 | /* The PIT interrupt may be disabled, and is shared */ |
159 | if (clockevent_state_periodic(&data->clkevt) && | 153 | if (clockevent_state_periodic(&data->clkevt) && |
160 | (pit_read(data->base, AT91_PIT_SR) & AT91_PIT_PITS)) { | 154 | (pit_read(data->base, AT91_PIT_SR) & AT91_PIT_PITS)) { |
161 | unsigned nr_ticks; | ||
162 | |||
163 | /* Get number of ticks performed before irq, and ack it */ | 155 | /* Get number of ticks performed before irq, and ack it */ |
164 | nr_ticks = PIT_PICNT(pit_read(data->base, AT91_PIT_PIVR)); | 156 | data->cnt += data->cycle * PIT_PICNT(pit_read(data->base, |
165 | do { | 157 | AT91_PIT_PIVR)); |
166 | data->cnt += data->cycle; | 158 | data->clkevt.event_handler(&data->clkevt); |
167 | data->clkevt.event_handler(&data->clkevt); | ||
168 | nr_ticks--; | ||
169 | } while (nr_ticks); | ||
170 | 159 | ||
171 | return IRQ_HANDLED; | 160 | return IRQ_HANDLED; |
172 | } | 161 | } |
@@ -177,11 +166,41 @@ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id) | |||
177 | /* | 166 | /* |
178 | * Set up both clocksource and clockevent support. | 167 | * Set up both clocksource and clockevent support. |
179 | */ | 168 | */ |
180 | static int __init at91sam926x_pit_common_init(struct pit_data *data) | 169 | static int __init at91sam926x_pit_dt_init(struct device_node *node) |
181 | { | 170 | { |
182 | unsigned long pit_rate; | 171 | unsigned long pit_rate; |
183 | unsigned bits; | 172 | unsigned bits; |
184 | int ret; | 173 | int ret; |
174 | struct pit_data *data; | ||
175 | |||
176 | data = kzalloc(sizeof(*data), GFP_KERNEL); | ||
177 | if (!data) | ||
178 | return -ENOMEM; | ||
179 | |||
180 | data->base = of_iomap(node, 0); | ||
181 | if (!data->base) { | ||
182 | pr_err("Could not map PIT address\n"); | ||
183 | return -ENXIO; | ||
184 | } | ||
185 | |||
186 | data->mck = of_clk_get(node, 0); | ||
187 | if (IS_ERR(data->mck)) { | ||
188 | pr_err("Unable to get mck clk\n"); | ||
189 | return PTR_ERR(data->mck); | ||
190 | } | ||
191 | |||
192 | ret = clk_prepare_enable(data->mck); | ||
193 | if (ret) { | ||
194 | pr_err("Unable to enable mck\n"); | ||
195 | return ret; | ||
196 | } | ||
197 | |||
198 | /* Get the interrupts property */ | ||
199 | data->irq = irq_of_parse_and_map(node, 0); | ||
200 | if (!data->irq) { | ||
201 | pr_err("Unable to get IRQ from DT\n"); | ||
202 | return -EINVAL; | ||
203 | } | ||
185 | 204 | ||
186 | /* | 205 | /* |
187 | * Use our actual MCK to figure out how many MCK/16 ticks per | 206 | * Use our actual MCK to figure out how many MCK/16 ticks per |
@@ -236,46 +255,5 @@ static int __init at91sam926x_pit_common_init(struct pit_data *data) | |||
236 | 255 | ||
237 | return 0; | 256 | return 0; |
238 | } | 257 | } |
239 | |||
240 | static int __init at91sam926x_pit_dt_init(struct device_node *node) | ||
241 | { | ||
242 | struct pit_data *data; | ||
243 | int ret; | ||
244 | |||
245 | data = kzalloc(sizeof(*data), GFP_KERNEL); | ||
246 | if (!data) | ||
247 | return -ENOMEM; | ||
248 | |||
249 | data->base = of_iomap(node, 0); | ||
250 | if (!data->base) { | ||
251 | pr_err("Could not map PIT address\n"); | ||
252 | return -ENXIO; | ||
253 | } | ||
254 | |||
255 | data->mck = of_clk_get(node, 0); | ||
256 | if (IS_ERR(data->mck)) | ||
257 | /* Fallback on clkdev for !CCF-based boards */ | ||
258 | data->mck = clk_get(NULL, "mck"); | ||
259 | |||
260 | if (IS_ERR(data->mck)) { | ||
261 | pr_err("Unable to get mck clk\n"); | ||
262 | return PTR_ERR(data->mck); | ||
263 | } | ||
264 | |||
265 | ret = clk_prepare_enable(data->mck); | ||
266 | if (ret) { | ||
267 | pr_err("Unable to enable mck\n"); | ||
268 | return ret; | ||
269 | } | ||
270 | |||
271 | /* Get the interrupts property */ | ||
272 | data->irq = irq_of_parse_and_map(node, 0); | ||
273 | if (!data->irq) { | ||
274 | pr_err("Unable to get IRQ from DT\n"); | ||
275 | return -EINVAL; | ||
276 | } | ||
277 | |||
278 | return at91sam926x_pit_common_init(data); | ||
279 | } | ||
280 | CLOCKSOURCE_OF_DECLARE(at91sam926x_pit, "atmel,at91sam9260-pit", | 258 | CLOCKSOURCE_OF_DECLARE(at91sam926x_pit, "atmel,at91sam9260-pit", |
281 | at91sam926x_pit_dt_init); | 259 | at91sam926x_pit_dt_init); |
diff --git a/drivers/clocksource/timer-oxnas-rps.c b/drivers/clocksource/timer-oxnas-rps.c index bd887e2a8cf8..d630bf417773 100644 --- a/drivers/clocksource/timer-oxnas-rps.c +++ b/drivers/clocksource/timer-oxnas-rps.c | |||
@@ -295,3 +295,5 @@ err_alloc: | |||
295 | 295 | ||
296 | CLOCKSOURCE_OF_DECLARE(ox810se_rps, | 296 | CLOCKSOURCE_OF_DECLARE(ox810se_rps, |
297 | "oxsemi,ox810se-rps-timer", oxnas_rps_timer_init); | 297 | "oxsemi,ox810se-rps-timer", oxnas_rps_timer_init); |
298 | CLOCKSOURCE_OF_DECLARE(ox820_rps, | ||
299 | "oxsemi,ox820se-rps-timer", oxnas_rps_timer_init); | ||
diff --git a/drivers/clocksource/timer-ti-32k.c b/drivers/clocksource/timer-ti-32k.c index 92b7e390f6c8..cf5b14e442e4 100644 --- a/drivers/clocksource/timer-ti-32k.c +++ b/drivers/clocksource/timer-ti-32k.c | |||
@@ -65,7 +65,7 @@ static inline struct ti_32k *to_ti_32k(struct clocksource *cs) | |||
65 | return container_of(cs, struct ti_32k, cs); | 65 | return container_of(cs, struct ti_32k, cs); |
66 | } | 66 | } |
67 | 67 | ||
68 | static cycle_t ti_32k_read_cycles(struct clocksource *cs) | 68 | static cycle_t notrace ti_32k_read_cycles(struct clocksource *cs) |
69 | { | 69 | { |
70 | struct ti_32k *ti = to_ti_32k(cs); | 70 | struct ti_32k *ti = to_ti_32k(cs); |
71 | 71 | ||
diff --git a/include/linux/ktime.h b/include/linux/ktime.h index 2b6a204bd8d4..3ffc69ebe967 100644 --- a/include/linux/ktime.h +++ b/include/linux/ktime.h | |||
@@ -64,6 +64,13 @@ static inline ktime_t ktime_set(const s64 secs, const unsigned long nsecs) | |||
64 | ({ (ktime_t){ .tv64 = (lhs).tv64 + (rhs).tv64 }; }) | 64 | ({ (ktime_t){ .tv64 = (lhs).tv64 + (rhs).tv64 }; }) |
65 | 65 | ||
66 | /* | 66 | /* |
67 | * Same as ktime_add(), but avoids undefined behaviour on overflow; however, | ||
68 | * this means that you must check the result for overflow yourself. | ||
69 | */ | ||
70 | #define ktime_add_unsafe(lhs, rhs) \ | ||
71 | ({ (ktime_t){ .tv64 = (u64) (lhs).tv64 + (rhs).tv64 }; }) | ||
72 | |||
73 | /* | ||
67 | * Add a ktime_t variable and a scalar nanosecond value. | 74 | * Add a ktime_t variable and a scalar nanosecond value. |
68 | * res = kt + nsval: | 75 | * res = kt + nsval: |
69 | */ | 76 | */ |
diff --git a/include/linux/time64.h b/include/linux/time64.h index 7e5d2fa9ac46..980c71b3001a 100644 --- a/include/linux/time64.h +++ b/include/linux/time64.h | |||
@@ -5,6 +5,7 @@ | |||
5 | #include <linux/math64.h> | 5 | #include <linux/math64.h> |
6 | 6 | ||
7 | typedef __s64 time64_t; | 7 | typedef __s64 time64_t; |
8 | typedef __u64 timeu64_t; | ||
8 | 9 | ||
9 | /* | 10 | /* |
10 | * This wants to go into uapi/linux/time.h once we agreed about the | 11 | * This wants to go into uapi/linux/time.h once we agreed about the |
diff --git a/include/linux/timekeeping.h b/include/linux/timekeeping.h index 816b7543f81b..09168c52ab64 100644 --- a/include/linux/timekeeping.h +++ b/include/linux/timekeeping.h | |||
@@ -1,7 +1,7 @@ | |||
1 | #ifndef _LINUX_TIMEKEEPING_H | 1 | #ifndef _LINUX_TIMEKEEPING_H |
2 | #define _LINUX_TIMEKEEPING_H | 2 | #define _LINUX_TIMEKEEPING_H |
3 | 3 | ||
4 | #include <asm-generic/errno-base.h> | 4 | #include <linux/errno.h> |
5 | 5 | ||
6 | /* Included from linux/ktime.h */ | 6 | /* Included from linux/ktime.h */ |
7 | 7 | ||
diff --git a/kernel/time/clocksource.c b/kernel/time/clocksource.c index 6a5a310a1a53..7e4fad75acaa 100644 --- a/kernel/time/clocksource.c +++ b/kernel/time/clocksource.c | |||
@@ -600,9 +600,18 @@ static void __clocksource_select(bool skipcur) | |||
600 | */ | 600 | */ |
601 | if (!(cs->flags & CLOCK_SOURCE_VALID_FOR_HRES) && oneshot) { | 601 | if (!(cs->flags & CLOCK_SOURCE_VALID_FOR_HRES) && oneshot) { |
602 | /* Override clocksource cannot be used. */ | 602 | /* Override clocksource cannot be used. */ |
603 | pr_warn("Override clocksource %s is not HRT compatible - cannot switch while in HRT/NOHZ mode\n", | 603 | if (cs->flags & CLOCK_SOURCE_UNSTABLE) { |
604 | cs->name); | 604 | pr_warn("Override clocksource %s is unstable and not HRT compatible - cannot switch while in HRT/NOHZ mode\n", |
605 | override_name[0] = 0; | 605 | cs->name); |
606 | override_name[0] = 0; | ||
607 | } else { | ||
608 | /* | ||
609 | * The override cannot be currently verified. | ||
610 | * Deferring to let the watchdog check. | ||
611 | */ | ||
612 | pr_info("Override clocksource %s is not currently HRT compatible - deferring\n", | ||
613 | cs->name); | ||
614 | } | ||
606 | } else | 615 | } else |
607 | /* Override clocksource can be used. */ | 616 | /* Override clocksource can be used. */ |
608 | best = cs; | 617 | best = cs; |
diff --git a/kernel/time/hrtimer.c b/kernel/time/hrtimer.c index 9ba7c820fc23..bb5ec425dfe0 100644 --- a/kernel/time/hrtimer.c +++ b/kernel/time/hrtimer.c | |||
@@ -307,7 +307,7 @@ EXPORT_SYMBOL_GPL(__ktime_divns); | |||
307 | */ | 307 | */ |
308 | ktime_t ktime_add_safe(const ktime_t lhs, const ktime_t rhs) | 308 | ktime_t ktime_add_safe(const ktime_t lhs, const ktime_t rhs) |
309 | { | 309 | { |
310 | ktime_t res = ktime_add(lhs, rhs); | 310 | ktime_t res = ktime_add_unsafe(lhs, rhs); |
311 | 311 | ||
312 | /* | 312 | /* |
313 | * We use KTIME_SEC_MAX here, the maximum timeout which we can | 313 | * We use KTIME_SEC_MAX here, the maximum timeout which we can |
@@ -703,7 +703,7 @@ static void clock_was_set_work(struct work_struct *work) | |||
703 | static DECLARE_WORK(hrtimer_work, clock_was_set_work); | 703 | static DECLARE_WORK(hrtimer_work, clock_was_set_work); |
704 | 704 | ||
705 | /* | 705 | /* |
706 | * Called from timekeeping and resume code to reprogramm the hrtimer | 706 | * Called from timekeeping and resume code to reprogram the hrtimer |
707 | * interrupt device on all cpus. | 707 | * interrupt device on all cpus. |
708 | */ | 708 | */ |
709 | void clock_was_set_delayed(void) | 709 | void clock_was_set_delayed(void) |
@@ -1241,7 +1241,7 @@ static void __run_hrtimer(struct hrtimer_cpu_base *cpu_base, | |||
1241 | 1241 | ||
1242 | /* | 1242 | /* |
1243 | * Note: We clear the running state after enqueue_hrtimer and | 1243 | * Note: We clear the running state after enqueue_hrtimer and |
1244 | * we do not reprogramm the event hardware. Happens either in | 1244 | * we do not reprogram the event hardware. Happens either in |
1245 | * hrtimer_start_range_ns() or in hrtimer_interrupt() | 1245 | * hrtimer_start_range_ns() or in hrtimer_interrupt() |
1246 | * | 1246 | * |
1247 | * Note: Because we dropped the cpu_base->lock above, | 1247 | * Note: Because we dropped the cpu_base->lock above, |
diff --git a/kernel/time/tick-sched.c b/kernel/time/tick-sched.c index 2ec7c00228f3..3bcb61b52f6c 100644 --- a/kernel/time/tick-sched.c +++ b/kernel/time/tick-sched.c | |||
@@ -186,10 +186,13 @@ static bool check_tick_dependency(atomic_t *dep) | |||
186 | return false; | 186 | return false; |
187 | } | 187 | } |
188 | 188 | ||
189 | static bool can_stop_full_tick(struct tick_sched *ts) | 189 | static bool can_stop_full_tick(int cpu, struct tick_sched *ts) |
190 | { | 190 | { |
191 | WARN_ON_ONCE(!irqs_disabled()); | 191 | WARN_ON_ONCE(!irqs_disabled()); |
192 | 192 | ||
193 | if (unlikely(!cpu_online(cpu))) | ||
194 | return false; | ||
195 | |||
193 | if (check_tick_dependency(&tick_dep_mask)) | 196 | if (check_tick_dependency(&tick_dep_mask)) |
194 | return false; | 197 | return false; |
195 | 198 | ||
@@ -843,7 +846,7 @@ static void tick_nohz_full_update_tick(struct tick_sched *ts) | |||
843 | if (!ts->tick_stopped && ts->nohz_mode == NOHZ_MODE_INACTIVE) | 846 | if (!ts->tick_stopped && ts->nohz_mode == NOHZ_MODE_INACTIVE) |
844 | return; | 847 | return; |
845 | 848 | ||
846 | if (can_stop_full_tick(ts)) | 849 | if (can_stop_full_tick(cpu, ts)) |
847 | tick_nohz_stop_sched_tick(ts, ktime_get(), cpu); | 850 | tick_nohz_stop_sched_tick(ts, ktime_get(), cpu); |
848 | else if (ts->tick_stopped) | 851 | else if (ts->tick_stopped) |
849 | tick_nohz_restart_sched_tick(ts, ktime_get()); | 852 | tick_nohz_restart_sched_tick(ts, ktime_get()); |
diff --git a/kernel/time/time.c b/kernel/time/time.c index 667b9335f5d6..bd62fb8e8e77 100644 --- a/kernel/time/time.c +++ b/kernel/time/time.c | |||
@@ -780,7 +780,7 @@ struct timespec64 timespec64_add_safe(const struct timespec64 lhs, | |||
780 | { | 780 | { |
781 | struct timespec64 res; | 781 | struct timespec64 res; |
782 | 782 | ||
783 | set_normalized_timespec64(&res, lhs.tv_sec + rhs.tv_sec, | 783 | set_normalized_timespec64(&res, (timeu64_t) lhs.tv_sec + rhs.tv_sec, |
784 | lhs.tv_nsec + rhs.tv_nsec); | 784 | lhs.tv_nsec + rhs.tv_nsec); |
785 | 785 | ||
786 | if (unlikely(res.tv_sec < lhs.tv_sec || res.tv_sec < rhs.tv_sec)) { | 786 | if (unlikely(res.tv_sec < lhs.tv_sec || res.tv_sec < rhs.tv_sec)) { |
diff --git a/kernel/time/timekeeping_debug.c b/kernel/time/timekeeping_debug.c index 107310a6f36f..ca9fb800336b 100644 --- a/kernel/time/timekeeping_debug.c +++ b/kernel/time/timekeeping_debug.c | |||
@@ -75,5 +75,7 @@ void tk_debug_account_sleep_time(struct timespec64 *t) | |||
75 | int bin = min(fls(t->tv_sec), NUM_BINS-1); | 75 | int bin = min(fls(t->tv_sec), NUM_BINS-1); |
76 | 76 | ||
77 | sleep_time_bin[bin]++; | 77 | sleep_time_bin[bin]++; |
78 | pr_info("Suspended for %lld.%03lu seconds\n", (s64)t->tv_sec, | ||
79 | t->tv_nsec / NSEC_PER_MSEC); | ||
78 | } | 80 | } |
79 | 81 | ||